Light Emitting Diode

Abstract

A light-emitting diode, comprising: a first conductive semiconductor layer; an active layer arranged on the first conductive semiconductor layer; a second conductive semiconductor layer arranged on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; a second bump pad electrically connected to the second conductive semiconductor layer; a first solder bump arranged on the first bump pad; and a second solder bump arranged on the second bump pad, wherein the first solder bump and the second solder bump have a thickness ranging from 10 times to 80 times the thickness of the first bump pad and the second bump pad, respectively.

Description

[0001] This application is a divisional application with application date of December 26, 2019, application number 201911369944.5, and invention name “Light Emitting Diode”. Technical Field

[0002] The invention relates to a light emitting diode. Background Art

[0003] Generally, nitrides of group III elements such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and direct transition band structures, and therefore have recently attracted much attention as light source materials for visible and ultraviolet light. In particular, blue and green light-emitting diodes using indium gallium nitride (InGaN) are used in a variety of applications such as large-scale natural color flat panel display devices, signal lights, indoor lighting, high-density light sources, high-resolution output systems, and optical communications.

[0004] On the other hand, a distributed Bragg reflector is a reflector having high reflectivity in a specific wavelength band by laminating insulating layers with different refractive indices. The distributed Bragg reflector reflects light in a light emitting diode to reduce light loss, thereby improving the light efficiency of the light emitting diode.

[0005] A DBR formed on a flat surface such as a substrate can form a uniform layer, and the reliability of the reflector is high. In contrast, when a DBR is formed on a structure having side surfaces such as a table, a large number of micro cracks or pinholes may be formed in the DBR, thereby reducing the reliability due to moisture penetration.

[0006] In particular, the more the number of stacked layers increases, the more the reflectivity of the distributed Bragg reflector increases, so a large number of stacked layers is required. In addition, in order to have a high reflectivity in a wide band in the visible area, the thickness of the distributed Bragg reflector is further increased. The increase in the thickness of the distributed Bragg reflector further reduces the reliability of the light-emitting diode and makes the light-emitting diode manufacturing process more difficult.

[0007] On the other hand, light emitting diodes are provided in various chip shapes, and the light emitting diode chip is mounted on a mounting surface of a package, a substrate or a printed circuit board, etc. For example, a light emitting diode in the form of a flip chip includes a bump pad, and the bump pad is mounted on a contact pad of a printed circuit board, etc. through solder paste.

[0008] The mounting process of the prior art generally involves applying solder paste on the connection pads, placing the bump pads of the light emitting diode chip on the solder paste, and then performing a reflow process, whereby the bump pads are soldered to the connection pads by solder.

[0009] However, in order to solder the LED chip, a considerable amount of solder paste needs to be applied to the connection pad. To this end, the solder paste needs to be applied multiple times to one connection pad. Therefore, the more the amount of solder paste applied to the connection pad increases, the more complicated the LED chip mounting process becomes, and the greater the possibility of process defects.

[0010] On the other hand, the bump pad formed on the LED chip is generally relatively thin, and thus does not help to handle the LED chip. As a result, it is difficult to form a white wall for improving the brightness of the LED chip. In addition, since it is difficult to handle the relatively small-sized LED chip, it is difficult to perform a mounting process using solder paste. Summary of the invention

[0011] The problem to be solved by the present invention is to provide a light emitting diode using a distributed Bragg reflector capable of maintaining a relatively high reflectivity and reducing the thickness.

[0012] Another problem to be solved by the present invention is to provide a light emitting diode having high reliability in a high humidity environment.

[0013] Another problem to be solved by the present invention is to provide a light emitting diode chip that can easily perform a soldering process using solder.

[0014] Another problem to be solved by the present invention is to provide a light emitting diode chip that is easy to handle.

[0015] The present invention provides a light-emitting diode, which includes: a first conductive semiconductor layer; an active layer arranged on the first conductive semiconductor layer; a second conductive semiconductor layer arranged on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; a second bump pad electrically connected to the second conductive semiconductor layer; a first solder bump arranged on the first bump pad; and a second solder bump arranged on the second bump pad, wherein the first solder bump and the second solder bump have a thickness ranging from 10 times to 80 times the thickness of the first bump pad and the second bump pad, respectively.

[0016] A light emitting diode according to an embodiment of the present invention comprises: a first conductive semiconductor layer; a table located on the first conductive semiconductor layer and comprising an active layer and a second conductive semiconductor layer; and a lower insulating layer covering the table and at least a portion of the first conductive semiconductor layer exposed around the table, and having a first opening portion for allowing electrical connection with the first conductive semiconductor layer and a second opening portion for allowing electrical connection with the second conductive semiconductor layer, wherein the active layer generates light having a peak wavelength below 500 nm, the lower insulating layer comprises a distributed Bragg reflector, the lower insulating layer has a high reflection band continuously showing a reflectivity of more than 90% within a wavelength range in a visible region, the reflectivity in a first wavelength region including a peak wavelength of light generated in the active layer in the high reflection band is higher than the reflectivity in a second wavelength region within a range of 554 nm to 700 nm, and the first wavelength region is located in a wavelength region shorter than 554 nm.

[0017] A light emitting diode according to another embodiment of the present invention comprises: a first conductive semiconductor layer; a table located on the first conductive semiconductor layer and comprising an active layer and a second conductive semiconductor layer; and a lower insulating layer covering the table and at least a portion of the first conductive semiconductor layer exposed around the table and having a first opening portion for allowing electrical connection with the first conductive semiconductor layer and a second opening portion for allowing electrical connection with the second conductive semiconductor layer, the lower insulating layer comprising a distributed Bragg reflector and a coupling layer arranged on the distributed Bragg reflector, the coupling layer comprising a mixed layer of at least two oxides including SiO2.

[0018] A light emitting diode according to another embodiment of the present invention comprises: a first conductive semiconductor layer; a table located on the first conductive semiconductor layer and comprising an active layer and a second conductive semiconductor layer; a distributed Bragg reflector covering a side surface of the table and at least a portion of the first conductive semiconductor layer exposed around the table; and a protective layer covering the distributed Bragg reflector on the first conductive semiconductor layer, the protective layer comprising a mixed layer of at least two oxides including SiO2.

[0019] A light-emitting diode according to another embodiment of the present invention includes: a first conductive semiconductor layer; an active layer arranged on the first conductive semiconductor layer; a second conductive semiconductor layer arranged on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; a second bump pad electrically connected to the second conductive semiconductor layer; a first solder bump arranged on the first bump pad; and a second solder bump arranged on the second bump pad, wherein the first solder bump and the second solder bump have a thickness ranging from 10 times to 80 times the thickness of the first bump pad and the second bump pad, respectively.

[0020] A light-emitting diode according to another embodiment of the present invention includes: a substrate; a first conductive semiconductor layer arranged on the substrate; an active layer arranged on the first conductive semiconductor layer; a second conductive semiconductor layer arranged on the active layer; an upper insulating layer arranged on the second conductive semiconductor layer and having an opening portion for allowing electrical connection; and a first solder bump and a second solder bump, arranged on the upper insulating layer and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer through the opening portion of the upper insulating layer, respectively, the first solder bump and the second solder bump having a thickness ranging from 10um to 100um, respectively.

[0021] A light-emitting element according to another embodiment of the present invention includes: a mounting surface having a connection pad; and a light-emitting diode mounted on the mounting surface by soldering, the light-emitting diode including: a first conductive semiconductor layer; an active layer arranged on the first conductive semiconductor layer; a second conductive semiconductor layer arranged on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; and a second bump pad electrically connected to the second conductive semiconductor layer, the solder soldering the connection pad and the first bump pad and the second bump pad, the solder having a thickness ranging from 10 times to 80 times the thickness of the first bump pad and the second bump pad.

[0022] A light-emitting diode according to another embodiment of the present invention comprises: a substrate; at least four light-emitting units arranged on the substrate and respectively comprising a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; and at least two solder bumps arranged on the light-emitting units, the at least four light-emitting units comprising at least two light-emitting units arranged near one side edge of the substrate and at least two light-emitting units arranged near another side edge of the substrate, solder bumps are provided on two or more of the at least two light-emitting units arranged near one side edge of the substrate, and solder bumps are provided on two or more of the at least two light-emitting units arranged near another side edge of the substrate.

[0023] According to the embodiments of the present invention, the reflectivity of light generated in the active layer is high and the reflectivity of visible light in a relatively long wavelength region is relatively low, so that the thickness of the distributed Bragg reflector can be reduced, thereby providing a light emitting diode with high reliability.

[0024] In addition, by using a waterproof coupling layer that can prevent moisture penetration to protect the distributed Bragg reflector, a light-emitting diode having high reliability in a high-temperature and high-humidity environment can be provided.

[0025] Furthermore, according to the embodiments of the present invention, the soldering process can be easily performed by providing relatively thick solder bumps on the light emitting diode, so that the light emitting diode chip can be easily handled.

[0026] Other advantages and effects of the present invention will become more apparent from the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic top view of a light emitting diode for explaining an embodiment of the present invention.

[0028] Figure 2 It is along Figure 1 A cross-sectional view taken along the cutting line AA.

[0029] Figure 3 This is a schematic cross-sectional view for explaining an example of a lower insulating layer.

[0030] Figure 4 It is used to illustrate Figure 3 A schematic graph of an example of a distributed Bragg reflector in a lower insulating layer.

[0031] Figure 5 It is used to illustrate the use of Figure 4 A simulated graph of the reflectivity of the lower insulating layer of the distributed Bragg reflector.

[0032] Figure 6 This is a schematic cross-sectional view for explaining another example of the lower insulating layer.

[0033] Figure 7 It is used to illustrate Figure 6 A schematic graph of an example of a distributed Bragg reflector in a lower insulating layer.

[0034] Figure 8 It is used to illustrate the use of Figure 6 The simulated and actually measured reflectivity curves of the lower insulating layer of the distributed Bragg reflector.

[0035] Figure 9a as well as Figure 9b It is a schematic cross-sectional view for explaining a distributed Bragg reflector and a coupling layer.

[0036] Fig.10 It is a schematic cross-sectional view of a light emitting diode for explaining another embodiment of the present invention.

[0037] Fig.11 It is a schematic top view of a light emitting diode for describing another embodiment of the present invention.

[0038] Fig.12 It is used to illustrate Fig.11 A schematic circuit diagram of a light emitting diode.

[0039] Fig.13 It is along Fig.11 A schematic cross-sectional view taken along the cutting line BB of .

[0040] Fig.14 It is along Fig.11 A schematic cross-sectional view taken along the cutting line CC.

[0041] Fig.15 It is a schematic top view of a light emitting diode for explaining an embodiment of the present invention.

[0042] Fig.16 It is along Fig.15 A cross-sectional view taken along the cutting line AA.

[0043] Fig.17 FIG. 1 is a schematic cross-sectional view for explaining a solder bump of a light emitting diode according to an embodiment of the present invention.

[0044] Fig.18 It is a schematic top view of a light emitting diode for explaining an embodiment of the present invention.

[0045] Figures 19a to 19f It is a schematic cross-sectional view for explaining a process for manufacturing a light emitting element according to an embodiment of the present invention.

[0046] Fig. 20 It is a schematic top view of a light emitting diode for describing another embodiment of the present invention.

[0047] Fig.21 It is used to illustrate Fig. 20 A schematic circuit diagram of a light emitting diode.

[0048] Fig. 22 It is along Fig. 20 A schematic cross-sectional view taken along the cutting line BB of .

[0049] Fig.23 It is along Fig. 20 A schematic cross-sectional view taken along the cutting line CC.

[0050] Fig.24It is a schematic cross-sectional view of a light emitting diode for explaining another embodiment of the present invention.

[0051] Fig.25 It is a schematic top view of a light emitting diode for describing another embodiment of the present invention.

[0052] Fig.26 It is an exploded perspective view for explaining a lighting device using a light emitting diode according to an embodiment of the present invention.

[0053] Fig. 27 FIG. 1 is a cross-sectional view for explaining a display device to which a light emitting diode according to another embodiment of the present invention is applied.

[0054] Fig.28 FIG. 1 is a cross-sectional view for explaining a display device to which a light emitting diode according to another embodiment of the present invention is applied.

[0055] Fig.29 This is a cross-sectional view for explaining an example in which a light emitting diode according to another embodiment of the present invention is applied to a headlamp. DETAILED DESCRIPTION

[0056] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments described below are provided as examples so that the concept of the present invention can be fully conveyed to the general technicians in the technical field to which the present invention belongs. Therefore, the present invention is not limited to the embodiments described below, and may also be embodied in other ways. Moreover, in the accompanying drawings, the width, length, thickness, etc. of the constituent elements may also be exaggerated for the sake of convenience. In addition, when it is recorded that a constituent element is "above" or "on" other constituent elements, it not only includes the situation that each part is "directly above" other parts or "directly on" other parts, but also includes the situation that other constituent elements are interposed between each constituent element and other constituent elements. Throughout the entire specification, the same reference numerals represent the same constituent elements.

[0057] A light emitting diode according to an embodiment of the present invention comprises: a first conductive semiconductor layer; a table located on the first conductive semiconductor layer and comprising an active layer and a second conductive semiconductor layer; and a lower insulating layer covering the table and at least a portion of the first conductive semiconductor layer exposed around the table, and having a first opening portion for allowing electrical connection with the first conductive semiconductor layer and a second opening portion for allowing electrical connection with the second conductive semiconductor layer, wherein the active layer generates light having a peak wavelength below 500 nm, the lower insulating layer comprises a distributed Bragg reflector, the lower insulating layer has a high reflection band continuously showing a reflectivity of more than 90% within a wavelength range in a visible region, the reflectivity in a first wavelength region including a peak wavelength of light generated in the active layer in the high reflection band is higher than the reflectivity in a second wavelength region within a range of 554 nm to 700 nm, and the first wavelength region is located in a wavelength region shorter than 554 nm.

[0058] By providing the first wavelength region having a relatively high reflectivity in the high reflection band, the overall thickness of the distributed Bragg reflector can be reduced, thereby providing a light emitting diode capable of improving reliability.

[0059] It may be that the lower insulating layer further includes a coupling layer arranged on the distributed Bragg reflector.

[0060] In some embodiments, the coupling layer may include a mixed layer of at least two oxides including SiO2. Here, the term "mixed layer" means a layer in which two or more oxides are mixed with each other. For example, oxides such as TiO2, SnO2, MgO or ZnO may be mixed in the SiO2 layer. In one embodiment, the coupling layer may include a SiO2-TiO2 mixed layer. The SiO2-TiO2 mixed layer means a layer in which SiO2 and TiO2 are mixed with each other. Considering the DBR (distributed Bragg reflector) design, TiO2 may be randomly mixed in the SiO2-TiO2 mixed layer at about 1 mol% to 5 mol%. The SiO2-TiO2 coupling layer has waterproof properties, and therefore, the reliability of the light-emitting diode in a high temperature and high humidity environment can be improved.

[0061] In one embodiment, the coupling layer may cover the top surface of the distributed Bragg reflector and leave the side surface exposed. In another embodiment, the coupling layer may cover the top surface and the side surface of the distributed Bragg reflector.

[0062] On the other hand, the lower insulating layer may have a reflectivity of 98% or more in a wavelength range of 420 nm to 480 nm, and a reflectivity of 90% or more in a wavelength range of 554 nm to 700 nm.

[0063] In one embodiment, the first wavelength region may be within a range of 420 nm to 480 nm, and the reflectivity in the first wavelength region is higher than the reflectivity in a range of 500 nm to 700 nm.

[0064] It may be that the light-emitting diode further includes: a transparent conductive oxide layer, arranged on the table and electrically connected to the second conductive semiconductor layer; a dielectric layer, covering the conductive oxide layer and having a plurality of openings that expose the conductive oxide layer; and a metal reflective layer, arranged on the dielectric layer and connected to the conductive oxide layer through the openings of the dielectric layer, the lower insulating layer is arranged on the metal reflective layer, the first opening exposes the first conductive semiconductor layer, and the second opening exposes the metal reflective layer.

[0065] Furthermore, the light-emitting diode may further include: a first pad metal layer, arranged on the lower insulating layer and electrically connected to the first conductive semiconductor layer through a first opening portion of the lower insulating layer; and a second pad metal layer, arranged on the lower insulating layer and electrically connected to the second conductive semiconductor layer through a second opening portion of the lower insulating layer.

[0066] In addition, the light emitting diode may further include an upper insulating layer covering the first pad metal layer and the second pad metal layer, and including a first opening portion exposing the first pad metal layer and a second opening portion exposing the second pad metal layer.

[0067] In some embodiments, the upper insulating layer may include a SiO 2 -TiO 2 mixed layer.

[0068] In addition, the upper insulating layer may cover side surfaces of the lower insulating layer.

[0069] It may be that the light emitting diode further includes: a first bump pad; and a second bump pad, the first bump pad and the second bump pad being electrically connected to the first pad metal layer and the second pad metal layer through the first opening and the second opening of the upper insulating layer, respectively.

[0070] In some embodiments, the light-emitting diode may further include: a substrate; and a plurality of light-emitting units arranged on the substrate, the light-emitting units respectively including the first conductive semiconductor layer and a table, the lower insulating layer covers the plurality of light-emitting units, and has a first opening portion and a second opening portion for allowing electrical connection with the first conductive semiconductor layer and the second conductive semiconductor layer of each light-emitting unit.

[0071] In addition, the lower insulating layer may cover the exposed portion of the substrate between the light emitting units.

[0072] In addition, the light-emitting diode may further include: a transparent conductive oxide layer, which is arranged on the table of each light-emitting unit and electrically connected to the second conductive semiconductor layer; a dielectric layer, which covers the conductive oxide layer on each light-emitting unit and has a plurality of openings that expose the conductive oxide layer; and a metal reflective layer, which is arranged on the dielectric layer on each light-emitting unit and connected to the conductive oxide layer through the openings of the dielectric layer, the lower insulating layer is arranged on the metal reflective layer, the first opening exposes the first conductive semiconductor layer, and the second opening exposes the metal reflective layer.

[0073] On the other hand, the dielectric layers may be separated from each other, and each dielectric layer is located in the region above the first conductive type semiconductor layer of each light emitting unit.

[0074] Furthermore, the light-emitting diode may further include: a first pad metal layer, which is arranged on any one of the light-emitting units and is connected to the first conductive semiconductor layer through the first opening; a second pad metal layer, which is arranged on another light-emitting unit of the light-emitting units and is electrically connected to the second conductive semiconductor layer through the second opening; and a connecting metal layer, which electrically connects adjacent light-emitting units.

[0075] A light emitting diode according to another embodiment of the present invention comprises: a first conductive semiconductor layer; a table located on the first conductive semiconductor layer and comprising an active layer and a second conductive semiconductor layer; and a lower insulating layer covering the table and at least a portion of the first conductive semiconductor layer exposed around the table and having a first opening portion for allowing electrical connection with the first conductive semiconductor layer and a second opening portion for allowing electrical connection with the second conductive semiconductor layer, the lower insulating layer comprising a distributed Bragg reflector and a coupling layer arranged on the distributed Bragg reflector, the coupling layer comprising a mixed layer of at least two oxides including SiO2.

[0076] In one embodiment, the mixed layer may be a SiO2-TiO2 mixed layer.

[0077] A light emitting diode according to another embodiment of the present invention comprises: a first conductive semiconductor layer; a table located on the first conductive semiconductor layer and comprising an active layer and a second conductive semiconductor layer; a distributed Bragg reflector covering a side surface of the table and at least a portion of the first conductive semiconductor layer exposed around the table; and a protective layer covering the distributed Bragg reflector on the first conductive semiconductor layer, the protective layer comprising a mixed layer of at least two oxides.

[0078] In one embodiment, the mixed layer may be a SiO2-TiO2 mixed layer.

[0079] The protective layer may cover the entire top surface of the distributed Bragg reflector. For example, the protective layer may be a coupling layer.

[0080] In some embodiments, the protective layer may cover a portion of the top surface and the side surface of the distributed Bragg reflector. For example, the protective layer may be an upper insulating layer.

[0081] A light-emitting diode according to another embodiment of the present invention includes: a first conductive semiconductor layer; an active layer arranged on the first conductive semiconductor layer; a second conductive semiconductor layer arranged on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; a second bump pad electrically connected to the second conductive semiconductor layer; a first solder bump arranged on the first bump pad; and a second solder bump arranged on the second bump pad, wherein the first solder bump and the second solder bump have a thickness ranging from 10 times to 80 times the thickness of the first bump pad and the second bump pad, respectively.

[0082] Furthermore, the first solder bump and the second solder bump may have inclined side surfaces, and an inclination angle of the inclined side surfaces relative to the bottom surface may be in a range of 65 to 75 degrees.

[0083] On the other hand, the distance between the first solder bump and the second solder bump may be greater than or equal to 2 times and less than or equal to 10 times the thickness of the first solder bump or the second solder bump.

[0084] Furthermore, the light emitting diode may further include a substrate arranged under the first conductive semiconductor layer, and the shortest horizontal distance between the first solder bump or the second solder bump and the substrate is the same as or greater than the thickness of the first solder bump and the second solder bump.

[0085] It may be that the light emitting diode also includes an upper insulating layer arranged on the second conductive semiconductor layer, the upper insulating layer has an opening portion for allowing electrical connection, the first bump pad and the second bump pad are arranged on the upper insulating layer and are electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer through the opening portion.

[0086] In one embodiment, the first solder bump and the second solder bump may cover the entire top surfaces of the first bump pad and the second bump pad respectively.

[0087] The distance between the first bump pad and the second bump pad may be greater than or equal to 2 times and less than or equal to 10 times the thickness of the first solder bump or the second solder bump.

[0088] It may be that the light emitting diode further includes a substrate arranged under the first conductive semiconductor layer, and the shortest horizontal distance between the first bump pad or the second bump pad and the edge of the substrate is the same as or greater than the thickness of the first solder bump and the second solder bump.

[0089] It may be that the light-emitting diode also includes: a transparent conductive oxide layer, which is electrically connected to the second conductive semiconductor layer; a dielectric layer, which covers the conductive oxide layer and has a plurality of openings that expose the conductive oxide layer; a metal reflective layer, which is arranged on the dielectric layer and is connected to the conductive oxide layer through the openings of the dielectric layer; a lower insulating layer, which is arranged on the metal reflective layer and includes a first opening that exposes the first conductive semiconductor layer and a second opening that exposes the metal reflective layer; a first pad metal layer, which is arranged on the lower insulating layer and is electrically connected to the first conductive semiconductor layer through the first opening of the lower insulating layer; and a second pad metal layer, which is arranged on the lower insulating layer and is electrically connected to the second conductive semiconductor layer through the second opening of the lower insulating layer, and the openings of the upper insulating layer expose the first pad metal layer and the second pad metal layer.

[0090] In some embodiments, the light emitting diode may further include: a substrate; and a plurality of light emitting units arranged on the substrate, the light emitting units respectively including the first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, the first bump pad being electrically connected to the first conductive semiconductor layer of one of the plurality of light emitting units, and the second bump pad being electrically connected to the second conductive semiconductor layer of another of the plurality of light emitting units.

[0091] In one embodiment, the light emitting diode may further include a dummy bump pad disposed on another light emitting unit among the plurality of light emitting units, and the dummy bump pad is electrically isolated from the light emitting unit.

[0092] In another embodiment, the first bump pad and the second bump pad may be arranged across at least two light emitting units respectively.

[0093] Furthermore, the first bump pad and the second bump pad may include a narrow region between the light emitting units.

[0094] A light-emitting diode according to another embodiment of the present invention includes: a substrate; a first conductive semiconductor layer arranged on the substrate; an active layer arranged on the first conductive semiconductor layer; a second conductive semiconductor layer arranged on the active layer; an upper insulating layer arranged on the second conductive semiconductor layer and having an opening portion for allowing electrical connection; and a first solder bump and a second solder bump, arranged on the upper insulating layer and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer through the opening portion of the upper insulating layer, respectively, the first solder bump and the second solder bump having a thickness ranging from 10um to 100um, respectively.

[0095] In addition, the first solder bump and the second solder bump may have inclined side surfaces, and an inclination angle of the inclined side surfaces relative to the bottom surface is in a range of 65 degrees to 75 degrees.

[0096] Furthermore, the distance between the first solder bump and the second solder bump may be not less than 2 times and not more than 10 times the thickness of the first solder bump or the second solder bump.

[0097] The shortest distance in the horizontal direction between the first solder bump or the second solder bump and the substrate may be greater than 1 / 2 of the distance between the first solder bump and the second solder bump.

[0098] A light-emitting element according to another embodiment of the present invention includes: a mounting surface having a connection pad; and a light-emitting diode mounted on the mounting surface by soldering, the light-emitting diode including: a first conductive semiconductor layer; an active layer arranged on the first conductive semiconductor layer; a second conductive semiconductor layer arranged on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; and a second bump pad electrically connected to the second conductive semiconductor layer, the solder soldering the connection pad and the first bump pad and the second bump pad, the solder having a thickness ranging from 10 times to 80 times the thickness of the first bump pad and the second bump pad.

[0099] In addition, the light emitting diode may further include an upper insulating layer located between the second conductive semiconductor layer and the first bump pad and the second bump pad, and having an opening portion for allowing electrical connection.

[0100] Furthermore, the light-emitting diode may further include: a transparent conductive oxide layer electrically connected to the second conductive semiconductor layer; a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer; a metal reflective layer arranged on the dielectric layer and connected to the conductive oxide layer through the openings of the dielectric layer; a lower insulating layer arranged on the metal reflective layer and including a first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; a first pad metal layer arranged on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the first opening of the lower insulating layer; and a second pad metal layer arranged on the lower insulating layer and electrically connected to the second conductive semiconductor layer through the second opening of the lower insulating layer, the openings of the upper insulating layer exposing the first pad metal layer and the second pad metal layer.

[0101] A light-emitting diode according to another embodiment of the present invention comprises: a substrate; at least four light-emitting units arranged on the substrate and respectively comprising a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; and at least two solder bumps arranged on the light-emitting units, the at least four light-emitting units comprising at least two light-emitting units arranged near one side edge of the substrate and at least two light-emitting units arranged near another side edge of the substrate, solder bumps are provided on two or more of the at least two light-emitting units arranged near one side edge of the substrate, and solder bumps are provided on two or more of the at least two light-emitting units arranged near another side edge of the substrate.

[0102] The solder bumps may be arranged in a symmetrical structure so as to stably mount the light emitting diode.

[0103] On the other hand, the at least two solder bumps may include: a first solder bump electrically connected to one light emitting unit; and a second solder bump electrically connected to another light emitting unit.

[0104] Furthermore, the light-emitting diode may further include: a first bump pad, located between the first solder bump and the light-emitting unit; and a second bump pad, located between the second solder bump and the light-emitting unit, the first solder bump and the second solder bump having a thickness ranging from 10 times to 80 times the thickness of the first bump pad and the second bump pad, respectively.

[0105] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0106] Figure 1 is a schematic top view of a light emitting diode for illustrating an embodiment of the present invention, Figure 2It is along Figure 1 A cross-sectional view taken along the cutting line AA.

[0107] Reference Figure 1 as well as Figure 2 The light emitting diode includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, a conductive oxide layer 28, a dielectric layer 29, a metal reflective layer 31, a lower insulating layer 33, a first pad metal layer 35a, a second pad metal layer 35b and an upper insulating layer 37. Furthermore, the light emitting diode may further include a first bump pad 39a and a second bump pad 39b.

[0108] The substrate 21 is not particularly limited as long as it is a substrate capable of growing a gallium nitride-based semiconductor layer. Examples of the substrate 21 include various substrates such as a sapphire substrate, a gallium nitride substrate, and a SiC substrate, and may be a patterned sapphire substrate. The substrate 21 may be a substrate such as Figure 1 The substrate 21 has a rectangular or square shape as shown in the top view, but is not necessarily limited to this. The size of the substrate 21 is not particularly limited and can be selected in a variety of ways.

[0109] The first conductive semiconductor layer 23 is disposed on the substrate 21. The first conductive semiconductor layer 23 is a layer grown on the substrate 21 and may be a gallium nitride semiconductor layer. The first conductive semiconductor layer 23 may be a gallium nitride semiconductor layer doped with a dopant, such as Si.

[0110] In this embodiment, the edge of the first conductive semiconductor layer 23 is parallel to the edge of the substrate 21. However, the present invention is not limited thereto, and the first conductive semiconductor layer 23 may also be located inside the region surrounded by the edge of the substrate 21. In this case, a portion of the upper surface of the substrate 21 may be exposed along the edge of the first conductive semiconductor layer 23.

[0111] The mesa M is disposed on the first conductive semiconductor layer 23. The mesa M may be defined and exist inside a region surrounded by the first conductive semiconductor layer 23, and thus a region near an edge of the first conductive semiconductor layer 23 may not be covered by the mesa M but exposed to the outside.

[0112] The mesa M includes a second conductive semiconductor layer 27 and an active layer 25. The active layer 25 is between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27. The active layer 25 may have a single quantum well structure or a multi-quantum well structure. In the active layer 25, the composition and thickness of the well layer may determine the wavelength of the generated light. In particular, an active layer that generates ultraviolet light, cyan light, or green light may be provided by adjusting the composition of the well layer. In the present embodiment, the active layer 25 may generate ultraviolet light or cyan light, especially below 500 nm, and may further generate visible light in the range of 400 nm to 470 nm.

[0113] On the other hand, the second conductive semiconductor layer 27 may be a gallium nitride-based semiconductor layer doped with a p-type dopant, such as Mg. The concentration of the p-type dopant in the second conductive semiconductor layer 27 may be, for example, 8×10 18 ~4×10 21 / cm 3 In particular, the p-type doping concentration in the second conductive type semiconductor layer 27 may have a concentration distribution that varies according to the thickness within the range.

[0114] On the other hand, the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 can be a single layer, but are not limited thereto, and can also be multiple layers, or can include a superlattice layer. The first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 can be grown on the substrate 21 in a chamber by a known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0115] On the other hand, Figure 1 As shown, a protrusion 30 extending inwardly toward the mesa M may be formed on the mesa M, and the top surface of the first conductive type semiconductor layer 23 may be exposed through the protrusion 30. The protrusion 30 may be formed long from one side edge of the mesa M toward the other side edge opposite thereto, toward the inside of the mesa M. The length of the protrusion 30 is not particularly limited, and may be 1 / 2 of the length of the mesa M or longer. In addition, Figure 1 Two protrusions 30 are shown, but the number of protrusions 30 may be one or more than three. As the number of protrusions 30 increases, the number of internal contacts 35a2 of the first pad metal layer 35a described later also increases, and the current spreading performance is improved.

[0116] On the other hand, the protrusion 30 has a rounded shape with a widened width at the end portion. By setting the end portion shape of the protrusion 30 in this way, the lower insulating layer 33 can be patterned in a similar shape. In particular, when the lower insulating layer 33 includes a distributed Bragg reflector, if it is not as Figure 1In this way, if the width becomes wider in the end portion, a serious double step is formed on the side wall of the distributed Bragg reflector, and the inclination angle of the side wall becomes larger, so cracks are easily generated in the first pad metal layer 35a. Therefore, by forming the end portion shape of the protrusion 30 and the end portion shape of the first opening portion 33a2 of the lower insulating layer 33 as in this embodiment, the edge of the lower insulating layer 33 can be formed to have a gentle inclination angle, which can improve the yield of the light-emitting diode.

[0117] In the present embodiment, the protrusion 30 is shown and described as being formed in the mesa M, but the mesa M may have at least one via hole penetrating the second conductive type semiconductor layer 27 and the active layer 25 instead of the protrusion 30 .

[0118] On the other hand, the conductive oxide layer 28 is arranged above the mesa M to contact the second conductive type semiconductor layer 27. The conductive oxide layer 28 may be arranged across almost the entire area of ​​the mesa M in the area above the mesa M. For example, the conductive oxide layer 28 may cover more than 80% of the area above the mesa M, and may further cover more than 90%.

[0119] The conductive oxide layer 28 is formed of an oxide layer that allows the light generated in the active layer 25 to pass through. The conductive oxide layer 28 can be formed, for example, of ITO (indium tin oxide) or ZnO. The conductive oxide layer 28 is formed with a thickness sufficient to make ohmic contact with the second conductive semiconductor layer 27, for example, it can be formed in a thickness range of 3nm to 50nm, specifically in a thickness range of 6nm to 30nm. If the thickness of the conductive oxide layer 28 is too thin, sufficient ohmic characteristics cannot be provided, and the forward voltage increases. In addition, if the thickness of the conductive oxide layer 28 is too thick, a loss caused by light absorption occurs, reducing the luminous efficiency.

[0120] On the other hand, the dielectric layer 29 covers the conductive oxide layer 28. Furthermore, the dielectric layer 29 may cover the side surfaces of the second conductive type semiconductor layer 27 and the active layer 25. The edge of the dielectric layer 29 may be covered by the lower insulating layer 33. Therefore, the edge of the dielectric layer 29 is farther away from the edge of the substrate 21 than the edge of the lower insulating layer 33. Thus, as described later, a portion of the lower insulating layer 33 may be in contact with the first conductive type semiconductor layer 23 around the mesa M. Further, the dielectric layer 29 may be limited to the upper region of the second conductive type semiconductor layer 27, and the lower insulating layer 33 may also be in contact with the side surfaces of the second conductive type semiconductor layer 27 and the active layer 25.

[0121] The dielectric layer 29 has an opening 29a that exposes the conductive oxide layer 28. A plurality of openings 29a may be arranged above the conductive oxide layer 28. The openings 29a may be used as a connection path to allow the metal reflective layer 31 to be connected to the conductive oxide layer 28. The dielectric layer 29 also exposes the first conductive semiconductor layer 23 around the mesa M and exposes the first conductive semiconductor layer 23 within the protrusion 30.

[0122] The dielectric layer 29 is formed of an insulating material having a lower refractive index than the second conductive semiconductor layer 27 and the conductive oxide layer 28. The dielectric layer 29 can be formed of SiO2, for example.

[0123] The thickness of the dielectric layer 29 may be in the range of 200 nm to 1000 nm, and specifically, in the range of 300 nm to 800 nm. When the thickness of the dielectric layer 29 is less than 200 nm, the forward voltage is high and the light output is low and undesirable. On the other hand, if the thickness of the dielectric layer 29 exceeds 400 nm, the light output is saturated, showing a trend that the forward voltage increases again. Therefore, it is preferred that the thickness of the dielectric layer 29 does not exceed 1000 nm, and in particular, it may be less than 800 nm.

[0124] On the other hand, the metal reflective layer 31 is arranged on the dielectric layer 29 and is connected to the ohmic contact layer 28 through the opening 29a. The metal reflective layer 31 may include a reflective metal, for example, Ag or Ni / Ag. Furthermore, the metal reflective layer 32 may include a barrier layer for protecting the reflective metal material layer, for example, Ni, and may include an Au layer to prevent oxidation of the metal layer. Furthermore, in order to improve the adhesion of the Au layer, a Ti layer may also be included under the Au layer. The metal reflective layer 31 is connected to the top surface of the dielectric layer 29, and therefore, the thickness of the dielectric layer 29 is the same as the spacing distance between the conductive oxide layer 28 and the metal reflective layer 31.

[0125] The conductive oxide layer 28 forms an ohmic contact, and the metal reflective layer 31 is disposed on the dielectric layer 29, thereby preventing the ohmic resistance from becoming high due to solder, etc. Furthermore, the reflectivity of light can be increased by arranging the conductive oxide layer 28, the dielectric layer 29, and the metal reflective layer 31 on the second conductive semiconductor layer 27, thereby improving the luminous efficiency.

[0126] The lower insulating layer 33 covers the mesa M and the metal reflective layer 31. The lower insulating layer 33 may also cover the first conductive type semiconductor layer 23 along the edge of the mesa M, and may cover the first conductive type semiconductor layer 23 in the protruding portion 30 inside the mesa M. The lower insulating layer 33 particularly covers the side surface of the mesa M. The lower insulating layer 33 may also cover the dielectric layer 29.

[0127] On the other hand, the lower insulating layer 33 has first openings 33a1 and 33a2 for exposing the first conductive semiconductor layer and a second opening 33b for exposing the metal reflective layer 31. The first opening 33a1 exposes the first conductive semiconductor layer 23 along the edge of the mesa M, and the first opening 33a2 exposes the first conductive semiconductor layer 23 in the convex portion 30. When a via is formed instead of the convex portion 30, the first opening 33a2 exposes the first conductive semiconductor layer 23 in the via.

[0128] like Figure 1 As shown, the first opening portion 33a1 and the first opening portion 33a2 may be connected to each other. However, the present invention is not limited thereto, and the first opening portions 33a1 and 33a2 may also be separated from each other.

[0129] In the present embodiment, the first opening 33a1 of the lower insulating layer 33 is formed to expose the peripheral area including the edge of the first conductive semiconductor layer 23. However, the present invention is not limited thereto, and the first opening 33a1 of the lower insulating layer 33 may be formed in a strip shape along the edge of the mesa M. At this time, the edge of the first conductive semiconductor layer 23 may be covered by the lower insulating layer 33 or may be parallel to the edge of the lower insulating layer 33.

[0130] The second opening 33b exposes the metal reflective layer 31. A plurality of second openings 33b may be formed, and these second openings 33b may be arranged near one side edge of the substrate 21 opposite to the protruding portion 30. The position of the second opening 33b will be described again below.

[0131] On the other hand, the lower insulating layer 33 includes a distributed Bragg reflector. The distributed Bragg reflector can be formed by stacking insulating layers with different refractive indices. For example, the distributed Bragg reflector can be formed by alternately and repeatedly stacking silicon nitride films and silicon oxide films. The lower insulating layer 33 may also include a coupling layer. The coupling layer can cover the top surface of the distributed Bragg reflector and function as a protective layer to protect the distributed Bragg reflector. In addition, the coupling layer improves the adhesion of the pad metal layers 35a and 35b arranged on the distributed Bragg reflector. For the specific structure of the lower insulating layer 33, refer to Figures 3 to 8 Explain again.

[0132] On the other hand, the first pad metal layer 35a is arranged on the lower insulating layer 33, and is insulated from the mesa M and the metal reflective layer 31 by the lower insulating layer 33. The first pad metal layer 35a contacts the first conductive type semiconductor layer 23 through the first openings 33a1 and 33a2 of the lower insulating layer 33. The first pad metal layer 35a may include an external contact portion 35a1 that contacts the first conductive type semiconductor layer 23 along the edge of the mesa M and an internal contact portion 35a2 that contacts the first conductive type semiconductor layer 23 in the protrusion 30 or the via hole. The external contact portion 35a1 contacts the first conductive type semiconductor layer 23 near the edge of the substrate 21 along the edge of the mesa M, and the internal contact portion 35a2 contacts the first conductive type semiconductor layer 23 inside the region surrounded by the external contact portion 35a1. The external contact portion 35a1 and the internal contact portion 35a2 may also be connected to each other, but are not limited thereto, and may also be separated from each other. In addition, the external contact portion 35a1 may be in continuous contact with the first conductive type semiconductor layer 23 along the edge of the mesa M, but the present invention is not limited thereto, and a plurality of external contact portions 35a1 may also be arranged spaced apart from each other.

[0133] On the other hand, the second pad metal layer 35b is arranged on the lower insulating layer 33 in the area above the mesa M, and is electrically connected to the metal reflective layer 31 through the second opening 33b of the lower insulating layer 33. The second pad metal layer 35b may be surrounded by the first pad metal layer 35a, and a boundary area 35ab may be formed therebetween. The lower insulating layer 33 is exposed in the boundary area 35ab, and the boundary area 35ab is covered by the upper insulating layer 37 described later.

[0134] The first pad metal layer 35a and the second pad metal layer 35b can be formed together with the same material by the same process. The first pad metal layer 35a and the second pad metal layer 35b may include an ohmic reflective layer such as an Al layer, and the ohmic reflective layer may be formed on an adhesive layer of Ti, Cr or Ni. In addition, a protective layer of a single layer or a composite layer structure of Ni, Cr, Au, etc. may be formed on the ohmic reflective layer. The first pad metal layer 35a and the second pad metal layer 35b may have a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti, for example.

[0135] The upper insulating layer 37 covers the first pad metal layer 35a and the second pad metal layer 35b. In addition, the upper insulating layer 37 can cover the first conductive semiconductor layer 23 along the edge of the mesa M. In this embodiment, the upper insulating layer 37 can expose the first conductive semiconductor layer 23 along the edge of the substrate 21. However, the present invention is not limited to this, and the upper insulating layer 37 can either cover the entire first conductive semiconductor layer 23 or be parallel to the edge of the substrate 21.

[0136] On the other hand, the upper insulating layer 37 has a first opening 37a that exposes the first pad metal layer 35a and a second opening 37b that exposes the second pad metal layer 35b. The first opening 37a and the second opening 37b can be arranged in the area above the mesa M and can be arranged to be opposite to each other. In particular, the first opening 37a and the second opening 37b can be arranged to be close to the two side edges of the mesa M.

[0137] The upper insulating layer 37 may be formed of a single layer of SiO2 or Si3N4, but is not limited thereto, and may also include a SiO2-TiO2 mixed layer or a MgF2 layer. The SiO2-TiO2 mixed layer or the MgF2 layer has excellent waterproof properties and can improve the reliability of the light-emitting diode in a high temperature and high humidity environment. In addition, the upper insulating layer 37 may have a multilayer structure including a silicon nitride film and a silicon oxide film, or may include a distributed Bragg reflector including alternately stacked silicon oxide films and titanium oxide films.

[0138] On the other hand, the first bump pad 39a is electrically connected to the first pad metal layer 35a exposed through the first opening 37a of the upper insulating layer 37, and the second bump pad 39b is electrically connected to the second pad metal layer 35b exposed through the second opening 37b. Figure 1 As shown, the first bump pad 39a may be arranged in the first opening 37a of the upper insulating layer 37, and the second bump pad 39b may be arranged in the second opening 37b of the upper insulating layer 37. However, the present invention is not limited to this, and the first bump pad 39a and the second bump pad 39b may also cover and seal the first opening 37a and the second opening 37b respectively. In addition, the second bump pad 39b may cover the upper area of ​​the second opening 33b of the lower insulating layer 33. The second bump pad 39b may cover the entire second opening 33b of the lower insulating layer 33, but is not limited to this, and a portion of the opening 33b may be located outside the second bump pad 39b.

[0139] In addition, if Figure 1 As shown, the second bump pad 39b may also be limited to the upper region of the second pad metal layer 35a. However, the present invention is not limited thereto, and a portion of the second bump pad 39b may also overlap with the first pad metal layer 35a. However, the upper insulating layer 37 may be arranged between the first pad metal layer 35a and the second bump pad 39b to insulate them.

[0140] According to an embodiment of the present invention, a reflective structure of a conductive oxide layer 28, a dielectric layer 29, and a metal reflective layer 31 is used instead of the conventional ohmic reflective layer. Thus, it is possible to block soldering materials such as solder from penetrating into the contact area, ensure a stable ohmic contact resistance, and improve the reliability of the light-emitting diode. Furthermore, by setting the thickness of the dielectric layer 29 to be greater than 300 nm, high light output and low forward voltage can be achieved.

[0141] Figure 3 is a schematic cross-sectional view for explaining an example of the lower insulating layer 33. Figure 4 It is used to illustrate Figure 3 A schematic diagram of an example of a distributed Bragg reflector in the lower insulating layer of Figure 5 It is used to illustrate the use of Figure 4 A simulated graph of the reflectivity of the lower insulating layer of the distributed Bragg reflector.

[0142] First, refer to Figure 3 The lower insulating layer 33 may include a distributed Bragg reflector 133a and a coupling layer 33c, wherein the distributed Bragg reflector 133a includes a plurality of pairs of a first insulating layer 33a having a first refractive index and a second insulating layer 33b having a second refractive index.

[0143] The first insulating layer 33a may have a lower refractive index than the second insulating layer 33b, and may be formed of, for example, a silicon oxide film (refractive index: about 1.47). The second insulating layer 33b may be formed of, for example, a titanium oxide film (refractive index: about 2.39).

[0144] like Figure 4 As shown, for example, 12 pairs of first insulating layers 33a and second insulating layers 33b may be formed, and the thicknesses of the first insulating layers 33a in the distributed Bragg reflectors are different from each other, and the thicknesses of the second insulating layers 33b may also be different from each other.

[0145] In particular, by adjusting the thicknesses of the first insulating layer 33a and the second insulating layer 33b, a light emitting diode having relatively high light efficiency while reducing the overall thickness of the distributed Bragg reflector can be provided.

[0146] For example, the first and second insulating layers 33a and 33b may be formed to exhibit relatively high reflectivity in a first wavelength region including a peak wavelength of light generated in the active layer 25 and relatively low reflectivity in a long wavelength region longer than the first wavelength region. Figure 4 An example of the optical thickness according to the layer order of the first insulating layer 33a and the second insulating layer 33b is shown. Here, considering the visible region, the central wavelength λ is set to 554 nm.

[0147] like Figure 4As shown, the optical thicknesses of the first insulating layer 33a and the second insulating layer 33b are different from each other. In particular, the layers located in the lower region of the distributed Bragg reflector (e.g., the 1st to 10th layers) have a larger thickness deviation than the layers located in the upper region (e.g., the 11th to 24th layers). For example, the layers located in the lower region include layers having an optical thickness of 0.3λ or more and layers having an optical thickness of 0.25λ or less. In contrast, the layers located in the upper region generally have a thickness of 0.25λ or less.

[0148] In addition, in this embodiment, the layers with an optical thickness of less than 0.25λ may be more than the layers with an optical thickness of more than 0.25λ. Thus, bands with different reflectivities may be formed in the stop band of the distributed Bragg reflector, and a higher reflectivity may be achieved in a relatively short band.

[0149] On the other hand, the coupling layer 33c can be formed of the same material as the first insulating layer 33a, such as a SiO2 layer. However, the coupling layer 33c is not limited to SiO2. The coupling layer 33c can be a mixed layer of at least two oxides including SiO2. Examples of the mixed layer include SiO2-TiO2, SiO2-SnO2, or SiO2-ZnO. In particular, Figure 6 The coupling layer 33d is shown as a SiO2-TiO2 mixed layer or a MgF2 layer, which will be described again later.

[0150] Figure 5 It is used to describe the Figure 4 The simulated curve graph of the reflectivity of the lower insulating layer 33 of the distributed Bragg reflector and the SiO2 coupling layer 33c with an optical thickness of 120 nm is shown here. Here, the simulated curve graph including the lower insulating layer formed to have a high reflectivity in a wide wavelength range of the visible region is shown together with the conventional distributed Bragg reflector with a high reflectivity in the visible region is shown with a dotted line, and the simulated curve graph of the embodiment of the present invention is shown with a solid line. The simulation is performed as follows: the first insulating layer 33a and the second insulating layer 33b are alternately stacked on a glass substrate (n: about 1.52), and finally the SiO2 coupling layer 33c with a thickness of about 120 nm is formed, and then the reflectivity on one side of the glass substrate is shown.

[0151] Reference Figure 5 , including the lower insulating layer of the conventional distributed Bragg reflector, generally exhibits high reflectivity in the stopband region, and several ripples are observed in the stopband, but exhibits a basically constant reflectivity. In contrast, it can be seen that the lower insulating layer 33 of a specific embodiment of the present invention is divided into a first wavelength region that exhibits a relatively high reflectivity in the stopband and a second wavelength region that exhibits a relatively lower reflectivity than the first wavelength region.

[0152] Here, it is difficult to define the stop band in the present invention, so in order to explain the present invention, a "high reflection wavelength band" similar to the stop band is introduced. In this specification, the "high reflection wavelength band" is defined as a wavelength band that continuously exhibits a reflectivity of more than 90%. Therefore, the high reflection wavelength band of the lower insulating layer of the prior art is a region between about 420nm and 750nm, and the high reflection wavelength band of one example of the present invention is a region between about 400nm and 700nm.

[0153] By adjusting the materials and thicknesses of the first insulating layer 33a, the second insulating layer 33b and the coupling layer 33c, the high reflection band can be adjusted to a wide wavelength region including the visible region.

[0154] On the other hand, the conventional lower insulating layer exhibits a reflectivity having a substantially symmetrical shape with respect to the central wavelength in the high reflection band, but the lower insulating layer 33 of the embodiment of the present invention exhibits a reflectivity that is significantly asymmetric with respect to the central wavelength. That is, the lower insulating layer 33 of the embodiment of the present invention includes a first wavelength region exhibiting a relatively high reflectivity compared to other wavelength regions on the short wavelength side shorter than the central wavelength in the high reflection band. Figure 5 The first wavelength region may be a wavelength range of about 420 nm to 480 nm, in which the reflectivity is 98% or more, and a reflectivity is 90% or more in a wavelength range of 500 nm to 700 nm.

[0155] In the present embodiment, the reason for having a relatively high reflectivity in the wavelength range of 420 nm to 480 nm is to ensure high reflectivity of light emitted from the active layer 25 when the peak wavelength of light emitted from the active layer 25 is assumed to be about 450 nm. Therefore, the first wavelength region showing a reflectivity of 98% or more can be changed in consideration of the wavelength of light generated in the active layer 25.

[0156] On the other hand, the wavelength range that does not show a relatively low reflectivity in the high reflection band is also limited to 500nm to 700nm, and can be changed to other wavelength ranges. However, the visible region above the central wavelength, i.e., 554nm, can be set to have a relatively low reflectivity compared to the first wavelength region. In addition, the first wavelength region can be limited to a short wavelength region shorter than the central wavelength, i.e., 554nm.

[0157] In the high reflection band, the first wavelength region has a relatively high reflectivity, and the other regions have a relatively low reflectivity, so that the light loss of the light emitting diode can be prevented while reducing the overall thickness of the distributed Bragg reflector 133a. Furthermore, by reducing the thickness of the distributed Bragg reflector 133a, the thickness of the lower insulating layer 33 in the light emitting diode can be reduced, and the process stability and reliability can be ensured.

[0158] on the other hand, Figure 5 The simulation graph is shown, and the actually measured reflectivity may be slightly different from the simulation. Nevertheless, the lower insulating layer 33 may include a first wavelength region showing a relatively high reflectivity on the short wavelength side shorter than the central wavelength in the high reflection band.

[0159] Figure 6 is a schematic cross-sectional view for explaining another example of the lower insulating layer, Figure 7 It is used to illustrate Figure 6 A schematic diagram of an example of a distributed Bragg reflector in the lower insulating layer of Figure 8 It is used to illustrate the use of Figure 6 The simulated and actually measured reflectivity curves of the lower insulating layer of the distributed Bragg reflector.

[0160] Reference Figure 6 , the lower insulating layer 33′ of this embodiment is Figure 3 The lower insulating layer 33 of FIG. 1 is substantially similar to the lower insulating layer 33 of FIG. 1 , except that the coupling layer 33d is a waterproof coupling layer for preventing moisture from penetrating. The coupling layer 33d may include, for example, a SiO2-TiO2 mixed layer or a MgF2 layer.

[0161] The SiO2-TiO2 mixed layer or the MgF2 layer has a hydrophobic property, thereby preventing moisture from penetrating into the distributed Bragg reflector 133b. When moisture penetrates into the distributed Bragg reflector 133b including the TiO2 layer, since the TiO2 layer is easily affected by moisture, the reflectivity of the distributed Bragg reflector may deteriorate sharply, and then, an electrical short circuit through the lower insulating layer may occur, resulting in component failure. By using the waterproof coupling layer 33d, the distributed Bragg reflector 133b can be protected and the reliability in a high humidity environment can be improved.

[0162] The SiO2-TiO2 mixed layer can be formed by electron beam evaporation technology and using a SiO2 target and a TiO2 target at the same time or using a target of mixed SiO2 oxide and TiO2 oxide. Considering the design of DBR (distributed Bragg reflector), the content of TiO2 in the SiO2-TiO2 mixed layer can be about 1 mol% to 5 mol% relative to the overall mixed layer. The coupling layer 33d can have a thickness of more than 100nm, and can further have a thickness of more than 200nm or more than 300nm. However, the increase in the thickness of the coupling layer 33d leads to an increase in the thickness of the lower insulating layer 33', so the thickness of the coupling layer 33d can be limited to less than about 400nm, for example.

[0163] On the other hand, the distributed Bragg reflector 133b may have the same layer structure as the distributed Bragg reflector 133a, but as the coupling layer 33d is formed of a SiO2-TiO2 mixed layer, the insulating layer directly below the coupling layer 33d may be the first insulating layer 33a, and the thicknesses of the first insulating layer 33a and the second insulating layer 33b may be changed to be suitable for the coupling layer 33d. Figure 7 The optical thickness of each insulating layer 33a, 33b of the distributed Bragg reflector 133b is shown.

[0164] Reference Figure 7 The thickness of the first insulating layer 33a and the second insulating layer 33b is different from that of the reference layer 33a. Figure 4 The values ​​of the thickness described are different, but the overall structure is generally similar. That is, the optical thicknesses of the first insulating layer 33a and the second insulating layer 33b are different from each other, and in particular, the layers of the distributed Bragg reflector 133b located in the lower region (for example, the 1st to 9th layers) have a larger thickness deviation than the layers located in the upper region (for example, the 10th to 23rd layers). For example, the layers located in the lower region include layers with an optical thickness of 0.3λ or more and layers with an optical thickness of 0.25λ or less. In contrast, the layers located in the upper region generally have a thickness of less than 0.25λ. In addition, in the present embodiment, the layers with an optical thickness of less than 0.25λ can be more than the layers with an optical thickness of more than 0.25λ. As a result, wavelength bands with different reflectivities can be formed in the stop band of the distributed Bragg reflector, and a higher reflectivity can be achieved in a relatively short short wavelength region.

[0165] On the other hand, Figure 7 In this case, as the coupling layer 33d is formed on the first insulating layer 33a, one second insulating layer 33b can be omitted from the number of layers of the distributed Bragg reflector 133a to reduce the overall number of layers.

[0166] Figure 8 Shown for illustration includes having Figure 7 The distribution of optical thickness of the Bragg reflector 133b and the reflectivity of the lower insulating layer 33' of the coupling layer 33d formed of a SiO2-TiO2 mixed layer of about 300nm are shown in a simulated curve graph (solid line) and an actually measured curve graph (dashed line).

[0167] The simulation was performed as follows: the first insulating layer 33a and the second insulating layer 33b were alternately stacked on a glass substrate (n: about 1.52) and finally a SiO2-TiO2 mixed layer (n: about 1.51) was formed with a thickness of about 300nm as a coupling layer 33d, and then the reflectivity on the glass substrate side was displayed. The actual measurement was also performed on the glass substrate side after the lower insulating layer 33' was formed on the glass substrate.

[0168] First, the simulation curve graph (solid line) is observed. In the high reflection band with a reflectivity of more than 90%, a relatively high reflectivity is shown in the range of about 405nm to about 485nm, and a relatively low reflectivity is shown in the range of about 500nm to 700nm. The first wavelength region showing high reflectivity is located in a short wavelength region shorter than 554nm, and the wavelength region of 554nm to 700nm shows a relatively low reflectivity compared to the first wavelength region.

[0169] On the other hand, the actual measurement graph (dashed line) shows that the boundary between the high reflectance region and the low reflectance region is blurred compared to the simulation graph, but the high reflectance region and the low reflectance region can be divided similarly to the simulation graph.

[0170] In the actual measurement curve, a relatively high reflectivity is shown in the region of about 420nm to 500nm, and a relatively low reflectivity is shown in the region of about 520nm to 700nm. That is, the reflectivity of the first wavelength region including the peak wavelength (e.g., 450nm) of the light generated in the active layer 25 is higher than the reflectivity of the visible region above the central wavelength of 554nm.

[0171] According to the embodiment of the present invention, the DBRs 133a, 133b exhibit relatively high reflectivity in a specific visible region of a short wavelength region shorter than the central wavelength, so the thickness of the lower insulating layer 33, 33' can be reduced without increasing the overall thickness of the DBR.

[0172] Furthermore, by forming the coupling layer 33d as a SiO2-TiO2 mixed layer or a MgF2 layer, the lower insulating layer 33' can prevent moisture from penetrating, thereby improving the reliability of the light emitting diode in a high temperature and high humidity environment.

[0173] On the other hand, in this embodiment, the lower insulating layer 33' includes a distributed Bragg reflector 133b and a coupling layer 33d, but the reliability of the light-emitting diode in a high temperature and high humidity environment is achieved through the coupling layer 33d, so the coupling layer 33d can also be applied to the previous distributed Bragg reflector.

[0174] Figure 9a as well as Figure 9b It is a schematic cross-sectional view for explaining the distributed Bragg reflector 133 b and the coupling layer 33 d .

[0175] Reference Figure 9aThe coupling layer 33d is located on the distributed Bragg reflector 133b and can cover the entire top surface of the distributed Bragg reflector 133b. The coupling layer 33d can be continuously evaporated after the distributed Bragg reflector 133b is evaporated, and can be patterned together with the distributed Bragg reflector 133b. Thus, the coupling layer 33d exposes the side of the distributed Bragg reflector 133b.

[0176] Reference Figure 9b In this embodiment, the coupling layer 33d covers the top surface and the side surface of the distributed Bragg reflector 133b. After the distributed Bragg reflector 133b is patterned, the coupling layer 33d is formed on the patterned distributed Bragg reflector 133b, so that the following can be provided: Figure 9b Thus, the coupling layer 33d can protect not only the top surface of the distributed Bragg reflector 133b but also the side surface.

[0177] In the embodiment of the present invention, it is described that the coupling layer 33d protects the distributed Bragg reflector 133b, but the upper insulating layer 37 described above may cover the top surface and the side surface of the distributed Bragg reflector 133b to protect the distributed Bragg reflector 133b. Furthermore, the upper insulating layer 37 may be formed of a SiO2-TiO2 mixed layer or a MgF2 layer, and the coupling layer 33d may be omitted.

[0178] Fig.10 It is a schematic cross-sectional view of a light emitting diode for explaining another embodiment of the present invention. Fig.10 It is a cross-sectional view showing an enlarged edge portion of the substrate 21 .

[0179] Reference Fig.10 The light emitting diode of this embodiment is different from the reference Figure 1 as well as Figure 2 The light emitting diode described above is substantially similar, except that the upper insulating layer 37 covers the side surfaces of the lower insulating layer 33 .

[0180] As shown in the figure, the first conductive type semiconductor layer 23 is formed to expose an edge portion of the substrate 21 .

[0181] The lower insulating layer 33 may cover the side of the first conductive semiconductor layer 23, but is not limited thereto, and the edge of the lower insulating layer 33 may also be located on the first conductive semiconductor layer 23. The edge of the lower insulating layer 33 may be located outside the first pad metal layer 35a. As shown in the figure, the external contact portion 35a1 may be located in the opening portion 33a1 of the lower insulating layer 33.

[0182] The upper insulating layer 37 may be in contact with the side surface of the lower insulating layer 33 , and further may be in contact with a portion of the top surface of the lower insulating layer 33 .

[0183] In this embodiment, the lower insulating layer 33 may be Figure 3 or Figure 6 The same as described above, but not limited thereto, may also include the case of a distributed Bragg reflector of the prior art (for example, Figure 5 The reflectivity of the lower insulating layer is shown by the dotted line in FIG.

[0184] On the other hand, when the lower insulating layer 33 includes a DBR of the related art, the upper insulating layer 37 may be formed of a SiO2-TiO2 mixed layer or a MgF2 layer, thereby preventing moisture from penetrating into the DBR.

[0185] Fig.11 is a schematic top view of a light emitting diode for illustrating another embodiment of the present invention, Fig.12 It is used to illustrate Fig.11 The schematic circuit diagram of the light emitting diode, Fig.13 It is along Fig.11 A schematic cross-sectional view taken along the cutting line BB of Fig.14 It is along Fig.11 A schematic cross-sectional view taken along the cutting line CC.

[0186] Reference Figures 11 to 14 The light emitting diode of this embodiment is substantially similar to the embodiment described above, except that a plurality of light emitting units C1, C2, C3, and C4 are arranged on the substrate 21. Fig.12 As shown, the light emitting cells C1, C2, C3, and C4 may be connected in series between the first bump pad 39a and the second bump pad 39b.

[0187] The first light emitting cell C1, the second light emitting cell C2, the third light emitting cell C3, and the fourth light emitting cell C4 are arranged on the substrate 21. The first light emitting cell C1, the second light emitting cell C2, the third light emitting cell C3, and the fourth light emitting cell C4 are separated from each other by separate regions that expose the substrate 21. The top surface of the substrate 21 may be exposed in regions between the light emitting cells.

[0188] In this embodiment, the first light emitting unit C1 and the second light emitting unit C2 are arranged at the bottom, and the third light emitting unit C3 and the fourth light emitting unit C4 are arranged at the top, but the first light emitting unit C1, the second light emitting unit C2, the third light emitting unit C3 and the fourth light emitting unit C4 can be arranged in various ways. In addition, in this embodiment, four light emitting units are shown and described as being arranged on the substrate 21, but the number of light emitting units is not particularly limited. For example, two light emitting units can be arranged on the substrate 21, or seven light emitting units can be arranged.

[0189] Each light emitting unit includes a first conductive semiconductor layer 23 and a mesa M. The first conductive semiconductor layer 23 and the mesa M are similar to those in the previous reference. Figure 1 as well as Figure 2 The situations described are the same, so in order to avoid repetition, detailed description of the same matters will be omitted.

[0190] The mesa M may be defined inside the region surrounded by the first conductive semiconductor layer 23 , and thus, a region near the edge adjacent to the outer side of the first conductive semiconductor layer 23 is not covered by the mesa M but is exposed to the outside.

[0191] In the present embodiment, each mesa M may include a via hole 27 a , and the first conductive type semiconductor layer 23 is exposed in the via hole 27 a .

[0192] On the other hand, a conductive oxide layer 28 is arranged on each mesa M, and a dielectric layer 29 covers the conductive oxide layer 28 on each light emitting unit C1, C2, C3, and C4 and the mesa M. The conductive oxide layer 28 is in ohmic contact with the second conductive type semiconductor layer 27. The conductive oxide layer 28 can be arranged in the area above the mesa M across almost the entire area of ​​the mesa M. However, the conductive oxide layer 28 can be separated from the edge of the mesa M.

[0193] The dielectric layer 29 may cover the area above the mesa M and the side surface, and cover the first conductive type semiconductor layer exposed around the mesa M. The dielectric layer 29 also has an opening 29a that exposes the conductive oxide layer 28. The dielectric layer 29 is located in the area above the first conductive type semiconductor layer 23, so the dielectric layers 29 on different light-emitting units may be separated from each other. However, the present invention is not necessarily limited to this, and the dielectric layers on adjacent light-emitting units may also be connected to each other.

[0194] The metal reflective layer 31 is disposed on the dielectric layer 29 and is connected to the conductive oxide layer 28 through the opening 29a of the dielectric layer 29. The metal reflective layer 31 is disposed in the region above the mesas M of each of the light emitting units C1, C2, C3, and C4.

[0195] The lower insulating layer 33 covers the mesa M and covers the metal reflective layer 31 and the dielectric layer 29. The lower insulating layer 33 also covers the first conductive type semiconductor layer 23 exposed outside the dielectric layer 29 and the substrate 21. When the substrate 21 is a patterned sapphire substrate, the lower insulating layer 33 can be formed along the shape of the protrusion on the substrate 21.

[0196] As shown in the figure, the edge of the lower insulating layer 33 may be located on the first conductive semiconductor layer 23 of each light emitting unit, but is not limited thereto. The lower insulating layer 33 may cover the side of the first conductive semiconductor layer 23 and be located on the substrate 21 .

[0197] The lower insulating layer 33 has a first opening portion 33a in the via hole 27a of each mesa M to expose the first conductive semiconductor layer 23, and also has a second opening portion 33b1 on the first light-emitting unit C1 to expose the metal reflective layer 31, and a second opening portion 33b2 on the second light-emitting unit C2, the third light-emitting unit C3 and the fourth light-emitting unit C4 to expose the metal reflective layer 31.

[0198] In this embodiment, the lower insulating layer 33 does not include an opening portion exposing the first conductive semiconductor layer 23 around the mesa M. However, the present invention is not limited thereto, and the lower insulating layer 33 may also include an opening portion exposing the first conductive semiconductor layer 23 around the mesa.

[0199] The second opening 33b1 is disposed on the first light emitting cell C1, and the second opening 33b2 exposes the metal reflective layer 31 of each light emitting cell near the separation region of the light emitting cell. The second opening 33b2 may have a shape generally long along the separation region, but is not limited thereto and may have various shapes.

[0200] On the other hand, the second opening 33b1 may be located on the first light emitting cell C1 and in the area below the second bump pad 39b. However, in another embodiment, the second opening 33b1 may also be arranged horizontally apart from the second bump pad 39b on the first light emitting cell C1.

[0201] On the other hand, a first pad metal layer 35 a , a second pad metal layer 35 b , and a connection metal layer 35 c are disposed on the lower insulating layer 33 .

[0202] The first pad metal layer 35a is arranged on the fourth light emitting unit C4, and is in ohmic contact with the first conductive semiconductor layer 23 exposed in the via hole 27a of the mesa M. In the present embodiment, an internal contact portion is formed in the via hole 27a, but an external contact portion may also be formed around the mesa M. However, by arranging the first pad metal layer 35a in the upper region of the mesa M, it can be kept away from the edge of the substrate 21, thereby preventing the first pad metal layer 35a from being damaged by moisture entering from the side of the substrate 21.

[0203] The second pad metal layer 35b may be disposed on the first light emitting cell C1 and electrically connected to the metal reflective layer 31 through the second opening 33b1. Thus, the second pad metal layer 35b is electrically connected to the second conductive semiconductor layer 27 of the first light emitting cell C1.

[0204] The second pad metal layer 35b is located on the mesa M and is insulated from the first conductive semiconductor layer 23. Furthermore, the second pad metal layer 35b can be separated from the side of the mesa M on the first light emitting unit C1. Thus, the second pad metal layer 35b can be prevented from being damaged by moisture entering from the side of the substrate 21.

[0205] On the other hand, the connecting metal layer 35c connects adjacent light-emitting units in series. The connecting metal layer 35c can be electrically connected to the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 of the adjacent light-emitting unit through the first opening portion 33a and the second opening portion 33b2 of the lower insulating layer 33. For example, one connecting metal layer 35c can be electrically connected to the first conductive semiconductor layer 23 in the first light-emitting unit C1, and at the same time electrically connected to the metal reflective layer 31 on the second light-emitting unit C2. Thus, the first light-emitting unit C1 and the second light-emitting unit C2 are connected in series with each other through the connecting metal layer 33c. In this way, the second light-emitting unit C2 and the third light-emitting unit C3 can be connected in series through the connecting metal layer 35c, and the third light-emitting unit C3 and the fourth light-emitting unit C4 can be connected in series through the connecting metal layer 35c.

[0206] The connection metal layer 35c is separated from the first pad metal layer 35a and the second pad metal layer 35b. Further, the connection metal layer 35c may be formed to have a narrower width than the mesa M, and thus may be further away from the edge of the substrate 21 than the mesa M.

[0207] The first pad metal layer 35a, the second pad metal layer 35b and the connection metal layer 35c may be formed together by the same process and with the same material. For example, the first pad metal layer 35a, the second pad metal layer 35b and the connection metal layer 35c may include an ohmic reflective layer such as an Al layer, and the ohmic reflective layer may be formed on an adhesive layer of Ti, Cr or Ni. In addition, a protective layer of a single layer or a composite layer structure of Ni, Cr, Au, etc. may be formed on the ohmic reflective layer. The first pad metal layer 35a, the second pad metal layer 35b and the connection metal layer 35c may have, for example, a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti.

[0208] The upper insulating layer 37 is arranged on the first pad metal layer 35a, the second pad metal layer 35b and the connection metal layer 35c, and has a first opening portion 37a that exposes the first pad metal layer 35a and a second opening portion 37b that exposes the second pad metal layer 35b. The upper insulating layer 37 can cover the top surface of the substrate 21 exposed around the light emitting unit 21. As shown in the figure, the upper insulating layer 37 can cover the edge of the substrate 21, but it is not limited thereto, and the edge of the upper insulating layer 37 can be located inside the edge of the substrate 21.

[0209] On the other hand, the first opening portion 37a is arranged in the upper region of the first pad metal layer 35a, and thus is separated from the connection metal layer 35c and the second opening portion 33b2 of the lower insulating layer 33. In addition, the second opening portion 37b is also defined and exists on the second pad metal layer 35b, and is separated from the connection metal layer 35c.

[0210] In this embodiment, the first pad metal layer 35a and the second pad metal layer 35b exposed through the first opening 37a and the second opening 37b of the upper insulating layer 37 can be used as a pad for directly soldering solder. Figure 1 as well as Figure 2 As described above, the first bump pad 39a and the second bump pad 39b can respectively cover the first pad metal layer 35a and the second pad metal layer 35b exposed through the first opening 37a and the second opening 37b of the upper insulating layer 37. The first bump pad 39a and the second bump pad 39b can be arranged across a plurality of light emitting units, respectively, to cover and seal the first opening 37a and the second opening 37b.

[0211] In this embodiment, the lower insulating layer 33 may be a reference Figure 3 The lower insulating layer described herein, but not limited thereto, may also be a reference to Figure 6 The lower insulating layer 33' is described. Figure 9a or Figure 9b Furthermore, the lower insulating layer 33 may be a lower insulating layer including a conventional distributed Bragg reflector, and in this case, the upper insulating layer 37 may include a SiO2-TiO2 mixed layer or a MgF2 layer.

[0212] On the other hand, the coupling layer 33d formed of the SiO2-TiO2 mixed layer and the Figure 7 The lower insulating layer 33' of the distributed Bragg reflector is applied to a light-emitting diode including a plurality of light-emitting units, and reliability tests are performed under high temperature and high humidity environments of 85°C and 85% relative humidity, and 60°C and 90% relative humidity. Figure 5 The lower insulating layer of the prior art is applied to the light emitting diode including the plurality of light emitting units, and a reliability test is performed under the same conditions.

[0213] After 500 hours, most of the light emitting diodes of the conventional technology samples failed and the reliability test was terminated. However, the samples of the embodiments of the present invention did not have a failure rate of more than 5% until 2000 hours under both conditions.

[0214] Therefore, it was confirmed that the reliability in a high-temperature and high-humidity environment was improved by using the SiO 2 -TiO 2 mixed layer.

[0215] Fig.15 is a schematic top view of a light emitting diode 1000 for illustrating an embodiment of the present invention. Fig.16 It is along Fig.15 A cross-sectional view taken along the cutting line AA.

[0216] Reference Fig.15 as well as Fig.16 The light emitting diode may include a substrate 221, a first conductive semiconductor layer 223, an active layer 225, a second conductive semiconductor layer 227, a conductive oxide layer 228, a dielectric layer 229, a metal reflective layer 231, a lower insulating layer 233, a first pad metal layer 235a, a second pad metal layer 235b, an upper insulating layer 237, a first bump pad 239a, a second bump pad 239b, a first solder bump 241a and a second solder bump 241b.

[0217] The substrate 221 is not particularly limited as long as it is a substrate capable of growing a gallium nitride-based semiconductor layer. Examples of the substrate 221 include various substrates such as a sapphire substrate, a gallium nitride substrate, and a SiC substrate, and may be a patterned sapphire substrate. The substrate 221 may be a substrate such as Fig.15 The substrate 221 has a rectangular or square shape as shown in the top view, but is not necessarily limited thereto. The size of the substrate 221 is not particularly limited and can be selected in a variety of ways.

[0218] The first conductive semiconductor layer 223 is disposed on the substrate 221. The first conductive semiconductor layer 223 is a layer grown on the substrate 221, and may be a gallium nitride semiconductor layer. The first conductive semiconductor layer 223 may be a gallium nitride semiconductor layer doped with a dopant, such as Si.

[0219] In this embodiment, the edge of the first conductive semiconductor layer 223 may be located inside the region surrounded by the edge of the substrate 221. Thus, a portion of the upper surface of the substrate 221 may be exposed along the edge of the first conductive semiconductor layer 223. However, the present invention is not limited thereto, and the edge of the first conductive semiconductor layer 223 may also be side by side with the edge of the substrate 221.

[0220] The mesa M may be disposed on the first conductive semiconductor layer 223. The mesa M may be defined and exist inside a region surrounded by the first conductive semiconductor layer 223, and thus a region near an edge of the first conductive semiconductor layer 223 may not be covered by the mesa M but exposed to the outside.

[0221] The mesa M includes a second conductive semiconductor layer 227 and an active layer 225. Although not shown, the mesa M may also include a portion of the thickness of the first conductive semiconductor layer 223. The active layer 225 is between the first conductive semiconductor layer 223 and the second conductive semiconductor layer 227. The active layer 225 may have a single quantum well structure or a multi-quantum well structure. In the active layer 225, the composition and thickness of the well layer determine the wavelength of the generated light. In particular, an active layer that generates ultraviolet light, cyan light, or green light can be provided by adjusting the composition of the well layer.

[0222] On the other hand, the second conductive semiconductor layer 227 may be a gallium nitride-based semiconductor layer doped with p-type dopant, such as Mg. The p-type doping concentration in the second conductive semiconductor layer 227 may have a concentration distribution that varies according to the thickness within the range.

[0223] On the other hand, the first conductive semiconductor layer 223 and the second conductive semiconductor layer 227 can be a single layer, but are not limited thereto, and can also be a multi-layer, or can include a superlattice layer. The first conductive semiconductor layer 223, the active layer 225, and the second conductive semiconductor layer 227 can be grown on the substrate 221 in a chamber using a well-known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0224] On the other hand, Fig.15 As shown, the mesa M may have a via hole 227a for exposing the first conductive type semiconductor layer 223. The via hole 227a may be surrounded by the second conductive type semiconductor layer 227 and the active layer 225. Fig.15 As shown, the via hole 227a may have a long shape passing through the center of the light emitting diode. As shown, the via hole 227a may be arranged to pass through the center of the mesa M and be inclined toward one side edge. The length of the via hole 227a is not particularly limited and may be 1 / 2 of the length of the mesa M or longer.

[0225] On the other hand, as shown in the figure, the ends of the via hole 227a may be relatively wide and circular. By setting the end shape of the via hole 227a in this way, the dielectric layer 229 and the lower insulating layer 233 may be patterned in a similar shape. In particular, when the lower insulating layer 233 includes a distributed Bragg reflector, if it is not as shown in FIG. Fig.15In this way, the width at the end of the via hole 227a becomes wider, a serious double step is formed on the side wall of the distributed Bragg reflector, and the inclination angle of the side wall becomes larger, so cracks are easily generated in the first pad metal layer 235a. Therefore, by forming the shape of the end of the via hole 227a and the shape of the end of the first opening 233a2 of the lower insulating layer 233 as in this embodiment, the edge of the lower insulating layer 233 can have a gentle inclination angle, which can improve the yield of the light-emitting diode.

[0226] Although it is shown and described that the mesa M has a single via 227a, the present invention is not limited thereto. For example, a plurality of vias may be arranged inside the mesa M. The more the number of vias 227a increases, the more the current dispersion performance of the light-emitting diode can be improved. In addition, a protrusion extending into the inside of the mesa M may be formed at the edge of the mesa M instead of the via 227a. The protrusion may be formed long from one side edge of the mesa M toward the other side edge opposite thereto, toward the inside of the mesa M.

[0227] On the other hand, the conductive oxide layer 228 is arranged above the mesa M to contact the second conductive type semiconductor layer 227. The conductive oxide layer 228 may be arranged across almost the entire area of ​​the mesa M in the area above the mesa M. For example, the conductive oxide layer 228 may cover more than 80% of the area above the mesa M, and further more than 90%.

[0228] The conductive oxide layer 228 is formed of an oxide layer that allows the light generated in the active layer 225 to pass through. The conductive oxide layer 228 can be formed, for example, of ITO (indium tin oxide) or ZnO. The conductive oxide layer 228 is formed with a thickness sufficient to make ohmic contact with the second conductive semiconductor layer 227, for example, it can be formed in a thickness range of 3nm to 50nm, specifically in a thickness range of 6nm to 30nm. If the thickness of the conductive oxide layer 228 is too thin, sufficient ohmic characteristics cannot be provided, and the forward voltage increases. In addition, if the thickness of the conductive oxide layer 228 is too thick, losses caused by light absorption occur, reducing the luminous efficiency.

[0229] On the other hand, the dielectric layer 229 covers the conductive oxide layer 228. Furthermore, the dielectric layer 229 may cover the side surfaces of the second conductive semiconductor layer 227 and the active layer 225. The edge of the dielectric layer 229 may be covered by the lower insulating layer 233. Therefore, the edge of the dielectric layer 229 is farther away from the edge of the substrate 221 than the edge of the lower insulating layer 233. Thus, as described later, a portion of the lower insulating layer 233 may be in contact with the first conductive semiconductor layer 223 around the mesa M. Further, the dielectric layer 229 may be limited to the upper region of the second conductive semiconductor layer 227, and the lower insulating layer 233 may also be in contact with the side surfaces of the second conductive semiconductor layer 227 and the active layer 225.

[0230] The dielectric layer 229 has an opening 229a that exposes the conductive oxide layer 228. A plurality of openings 229a may be arranged above the conductive oxide layer 228. The openings 229a may serve as a connection path so that the metal reflective layer 231 can be connected to the conductive oxide layer 228. The dielectric layer 229 may further have an opening 229b that exposes the first conductive semiconductor layer 223 around the mesa M and exposes the first conductive semiconductor layer 223 in the via hole 227a.

[0231] The dielectric layer 229 is formed of an insulating material having a lower refractive index than the second conductive semiconductor layer 227 and the conductive oxide layer 228. The dielectric layer 229 may be formed of SiO2, for example.

[0232] The thickness of the dielectric layer 229 may be in the range of 200 nm to 1000 nm, and may be specifically in the range of 300 nm to 800 nm. When the thickness of the dielectric layer 229 is less than 200 nm, the forward voltage is high and the light output is low and undesirable. On the other hand, if the thickness of the dielectric layer 229 exceeds 400 nm, the light output is saturated, showing a trend that the forward voltage increases again. Therefore, it is preferred that the thickness of the dielectric layer 229 does not exceed 1000 nm, and may be in particular less than 800 nm.

[0233] On the other hand, the metal reflective layer 231 is arranged on the dielectric layer 229 and is connected to the ohmic contact layer 228 through the opening 229a. The metal reflective layer 231 may include a reflective metal, for example, Ag or Ni / Ag. Furthermore, the metal reflective layer 232 may include a barrier layer for protecting the reflective metal material layer, for example, Ni, and may include an Au layer to prevent oxidation of the metal layer. Furthermore, in order to improve the adhesion of the Au layer, a Ti layer may also be included under the Au layer. The metal reflective layer 231 is in contact with the top surface of the dielectric layer 229, and therefore, the thickness of the dielectric layer 229 is the same as the spacing distance between the conductive oxide layer 228 and the metal reflective layer 231.

[0234] The conductive oxide layer 228 forms an ohmic contact, and the metal reflective layer 231 is disposed on the dielectric layer 229, thereby preventing the ohmic resistance from becoming high due to solder, etc. Furthermore, the reflectivity of light can be increased by arranging the conductive oxide layer 228, the dielectric layer 229, and the metal reflective layer 231 on the second conductive semiconductor layer 227, thereby improving the luminous efficiency.

[0235] The lower insulating layer 233 covers the mesa M and the metal reflective layer 231. The lower insulating layer 233 may also cover the first conductive type semiconductor layer 223 along the edge of the mesa M, and may cover the first conductive type semiconductor layer 223 in the via hole 227a inside the mesa M. The lower insulating layer 233 particularly covers the side surface of the mesa M. The lower insulating layer 233 may also cover the dielectric layer 229.

[0236] On the other hand, the lower insulating layer 233 has first openings 233a1 and 233a2 for exposing the first conductive semiconductor layer and a second opening 233b for exposing the metal reflective layer 231. The first opening 233a1 exposes the first conductive semiconductor layer 223 along the edge of the mesa M, and the first opening 233a2 exposes the first conductive semiconductor layer 223 in the via hole 227a.

[0237] like Fig.15 As shown, a plurality of first openings 233a1 may be arranged along the edge of the mesa M, but the present invention is not limited thereto. For example, a single first opening 233a1 may also be formed along the edge of the mesa M.

[0238] In the present embodiment, the first opening 233a1 of the lower insulating layer 233 is shown and described as being arranged along the edge of the mesa M, but the lower insulating layer 233 may also be formed to expose its peripheral area including the edge of the first conductive semiconductor layer 223. That is, in the present embodiment, the edge of the lower insulating layer 233 is shown to be side by side with the edge of the substrate 221, but the edge of the lower insulating layer 233 may be located on the first conductive semiconductor layer 223.

[0239] The second opening portion 233b exposes the metal reflective layer 231. A plurality of second opening portions 233b may be formed, and the second opening portions 233b may be arranged near a central region of the mesa M.

[0240] On the other hand, the lower insulating layer 233 may be formed of a single layer of SiO2 or Si3N4, but is not limited thereto, and may also be formed of multiple layers. Furthermore, the lower insulating layer 233 may include a distributed Bragg reflector. The distributed Bragg reflector may be formed by stacking insulating layers having different refractive indices. For example, the distributed Bragg reflector may be formed by alternately and repeatedly stacking silicon oxide films and titanium oxide films. The lower insulating layer 233 may also include a coupling layer. The coupling layer may cover the top surface of the distributed Bragg reflector and function as a protective layer to protect the distributed Bragg reflector. In addition, the coupling layer improves the adhesion of the pad metal layers 235a and 235b arranged on the distributed Bragg reflector. The coupling layer may be formed of SiO2, but is not limited thereto, and may also be formed of a SiO2-TiO2 mixed layer or a MgF2 layer. The SiO2-TiO2 mixed layer or the MgF2 layer has a waterproof property, thereby improving the reliability of the light-emitting diode in a high temperature and high humidity environment.

[0241] On the other hand, the first pad metal layer 235a is arranged on the lower insulating layer 233, and is insulated from the mesa M and the metal reflective layer 231 by the lower insulating layer 233. The first pad metal layer 235a contacts the first conductive type semiconductor layer 223 through the first openings 233a1 and 233a2 of the lower insulating layer 233. The first pad metal layer 235a may contact the first conductive type semiconductor layer 223 through the first opening 233a1 along the edge of the mesa M, and may contact the first conductive type semiconductor layer 223 in the via hole 227a through the second opening 233a2.

[0242] On the other hand, the second pad metal layer 235b is arranged on the lower insulating layer 233 in the area above the mesa M, and is electrically connected to the metal reflective layer 231 through the second opening 233b of the lower insulating layer 233. The second pad metal layer 235b may be surrounded by the first pad metal layer 235a, and a boundary area may be formed therebetween. Fig.15 As shown, the boundary region may be formed in a ring shape. The lower insulating layer 233 is exposed in the boundary region, and the boundary region is covered by an upper insulating layer 237 described later.

[0243] The first pad metal layer 235a and the second pad metal layer 235b can be formed together with the same material by the same process. The first pad metal layer 235a and the second pad metal layer 235b may include an ohmic reflective layer such as an Al layer, and the ohmic reflective layer may be formed on an adhesive layer of Ti, Cr or Ni. In addition, a protective layer of a single layer or a composite layer structure of Ni, Cr, Au, etc. may be formed on the ohmic reflective layer. The first pad metal layer 235a and the second pad metal layer 235b may have a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti, for example.

[0244] The upper insulating layer 237 covers the first pad metal layer 235a and the second pad metal layer 235b. In addition, the upper insulating layer 237 can cover the first conductive semiconductor layer 223 along the edge of the mesa M. In this embodiment, the upper insulating layer 237 is side by side with the edge of the substrate 221. However, the present invention is not limited to this, and the edge of the upper insulating layer 237 can also be located inside the area surrounded by the edge of the substrate 221, so that the upper insulating layer 237 exposes the edge area of ​​the substrate 221.

[0245] On the other hand, the upper insulating layer 237 has a first opening 237a for exposing the first pad metal layer 235a and a second opening 237b for exposing the second pad metal layer 235b. The first opening 237a and the second opening 237b can be arranged in the area above the table M and can be arranged to be opposite to each other. In particular, the first opening 237a and the second opening 237b can be arranged to be close to the two side edges of the table M. In addition, as shown in the figure, the second opening 237b of the upper insulating layer 237 can be laterally separated from the second opening 233b of the lower insulating layer 233. By separating the second opening 233b of the lower insulating layer 233 and the second opening 237b of the upper insulating layer 237 laterally, it is possible to prevent the solder from causing damage to the metal reflective layer 231 and the conductive oxide layer 228.

[0246] The upper insulating layer 237 may be formed of a single layer of SiO2 or Si3N4, but is not limited thereto, and may also include a SiO2-TiO2 mixed layer or a MgF2 layer. The SiO2-TiO2 mixed layer or the MgF2 layer has excellent waterproof properties and can improve the reliability of the light-emitting diode in a high temperature and high humidity environment. In addition, the upper insulating layer 237 may have a multilayer structure including a silicon nitride film and a silicon oxide film, or may include a distributed Bragg reflector including alternately stacked silicon oxide films and titanium oxide films.

[0247] On the other hand, the first bump pad 239a is electrically connected to the first pad metal layer 235a exposed through the first opening 237a of the upper insulating layer 237, and the second bump pad 239b is electrically connected to the second pad metal layer 235b exposed through the second opening 237b. Fig.15 As shown, the first bump pad 239a and the second bump pad 239b can respectively cover and seal the first opening 237a and the second opening 237b of the upper insulating layer 237. However, the present invention is not limited thereto, and the first bump pad 239a can be arranged in the first opening 237a of the upper insulating layer 237, and the second bump pad 239b can be arranged in the second opening 237b of the upper insulating layer 237.

[0248] In addition, if Fig.15As shown, the second bump pad 239b may be defined and exist in the upper region of the second pad metal layer 235a. However, the present invention is not limited thereto, and a portion of the second bump pad 239b may also overlap with the first pad metal layer 235a. However, the upper insulating layer 237 may be arranged between the first pad metal layer 235a and the second bump pad 239b to insulate them.

[0249] The first bump pad 239a and the second bump pad 239b may be formed of a metal layer, which may include a plurality of layers. In particular, the first bump pad 239a and the second bump pad 239b may include Au or Pt.

[0250] The first solder bump 241a is disposed on the first bump pad 239a, and the second solder bump 241b is disposed on the second bump pad 239b. The first solder bump 241a and the second solder bump 241b may include, for example, AgCuSn.

[0251] The first solder bump 241a and the second solder bump 241b can be formed as follows: after placing solder paste including solder powder and flux on the first bump pad 239a and the second bump pad 239b, the flux is removed by a reflow process. Thus, the first solder bump 241a and the second solder bump 241b can have the same bottom area as the first bump pad 239a and the second bump pad 239b.

[0252] On the other hand, the first solder bump 241a and the second solder bump 241b are relatively thicker than the first bump pad 239a and the second bump pad 239b. For example, the thickness T2 of the first solder bump 241a or the second solder bump 241b may be 10 to 80 times the thickness T1 of the first bump pad 239a or the second bump pad 239b. Specifically, the first bump pad 239a and the second bump pad 239b have a thickness of approximately 1um, whereas the first solder bump 241a and the second solder bump 241b may have a thickness of 10um to 100um.

[0253] In addition, the first solder bump 241a and the second solder bump 241b may have inclined side surfaces and may have a substantially trapezoidal cross-sectional shape. Fig.17 As shown, the inclination angle θ of the side surface of the first solder bump 241a and the second solder bump 241b relative to the bottom surface can be in the range of about 65 degrees to 75 degrees. When the inclination angle θ is within the above range, the solder bumps 241a and 241b can be easily formed, and then the light emitting diode 1000 can be easily transferred.

[0254] On the other hand, Fig.18As shown, it is necessary to control the interval s1 between the first solder bump 241a and the second solder bump 241b, and the intervals s2 and s3 between the first solder bump 241a and the second solder bump 241b and the edge of the substrate 221. For example, the interval s1 is more than twice the thickness of the first solder bump 241a and the second solder bump 241b. The upper limit of the interval s1 is not particularly limited, but in order to ensure sufficient area for the solder bumps 241a and the solder bumps 241b, it may not exceed 10 times.

[0255] On the other hand, the intervals s2 and s3 may be greater than 1 / 2 of the interval s1. Furthermore, the intervals s2 and s3 may be equal to or greater than the thickness T2 of the first solder bump 241a and the second solder bump 241b. By controlling the intervals s1, s2, and s3, the first solder bump 241a and the second solder bump 241b may be easily formed using screen printing technology, and electrical short circuits between the solder bumps may be prevented.

[0256] According to an embodiment of the present invention, a reflective structure of a conductive oxide layer 228, a dielectric layer 229, and a metal reflective layer 231 is used instead of the conventional ohmic reflective layer. Thus, soldering materials such as solder can be blocked from entering the contact area, and a stable ohmic contact resistance can be ensured, thereby improving the reliability of the light-emitting diode. Furthermore, by setting the thickness of the dielectric layer 229 to be greater than 300 nm, high light output and low forward voltage can be achieved.

[0257] Furthermore, by forming the first solder bump 241 a and the second solder bump 241 b on the first bump pad 239 a and the second bump pad 239 b , the amount of solder paste used in the LED mounting process can be reduced, and the LED mounting process can be simplified.

[0258] In addition, by arranging the solder bumps 241a and 241b having a thickness 10 times or more than that of the first bump pad 239a and the second bump pad 239b, the handling of the light emitting diode can be easily performed.

[0259] Figures 19a to 19f This is a schematic cross-sectional view for explaining a process of manufacturing a light emitting element according to an embodiment of the present invention. Here, a process of forming solder bumps 241a and 241b by screen printing technology and using them to mount the light emitting element on a mounting surface is explained.

[0260] First, refer to Fig.19a , prepare a substrate 221 having bump pads 239a and 239b. Although not shown, a substrate 221 may be formed as shown in FIG. Fig.15 as well as Fig.16As described above, the first conductive semiconductor layer 223, the active layer 225, the second conductive semiconductor layer 227, the conductive oxide layer 228, the dielectric layer 229, the metal reflective layer 231, the lower insulating layer 233, the first pad metal layer 235a, the second pad metal layer 235b and the upper insulating layer 237. The first bump pad 239a and the second bump pad 239b may be arranged on the upper insulating layer 237.

[0261] A plurality of light emitting diode regions may be arranged on the substrate 221 , and a first bump pad 239 a and a second bump pad 239 b may be formed in each region.

[0262] Reference Fig.19b , a mask 210 is arranged on the substrate 221. The mask 210 has an opening portion that exposes the bump pads 239a and 239b, and the mask 210 is arranged so that the opening portion is aligned with the bump pads 239a and 239b. The height of the opening portion may be greater than about 20um and less than about 300um.

[0263] Next, the openings of the mask 210 are filled with solder paste 240. The solder paste 240 may be applied using, for example, a squeeze printing technique, so that the solder paste 240 having a thickness substantially corresponding to the height of the openings is disposed on the bump pads.

[0264] Reference Fig.19c , remove the mask 210, and reflow the solder paste through a reflow process. As a result, the solder paste condenses to form a solder bump 240a with an inclined side and a bulging top surface. In the reflow process, most of the flux in the solder paste can be removed.

[0265] In order to remove the mask 210, the intervals between the solder pastes 240 need to be set to be larger than the thickness of the solder pastes 240. If the intervals between the solder pastes 240 are too narrow, the solder pastes 240 may be connected to each other, making it difficult to remove the mask 210.

[0266] On the other hand, during the reflow process, the first bump pad 239a and the second bump pad 239b and the solder may diffuse and mix with each other. As a result, the boundary between the first bump pad 239a and the second bump pad 239b and the solder bump 240a may be unclear. However, when the first bump pad 239a and the second bump pad 239b are formed by multiple metal layers, a part of them may be mixed with the solder and a part of them may remain.

[0267] Reference Fig.19dA portion of the thickness of the solder bump 240a is removed to form a first solder bump 241a and a second solder bump 241b. The solder bump 240a may be cut by a cutting process such as a flying cut technique.

[0268] In particular, the solder bump 240a may be cut by more than 50%. Thus, the first solder bump 241a and the second solder bump 241b may be formed with a thickness less than 1 / 2 of the height of the opening of the mask 210. If the solder bump 240a is cut by less than 50%, when transferring the light-emitting diode, process defects may easily occur due to poor adhesion of the solder bumps 241a and 241b.

[0269] Reference Fig.19e , individual light emitting diodes 1000 are completed by dividing the substrate 221. A process of grinding the bottom surface of the substrate 221 to reduce the thickness may be added before dividing the substrate 221. The process of reducing the thickness of the substrate 221 may also be performed before printing the solder paste.

[0270] On the other hand, although two light emitting diodes 1000 are shown in the figure, several hundred or several thousand light emitting diodes 1000 may be formed on one substrate 221 .

[0271] Reference Fig.19f The light emitting diode 1000 is soldered to the base substrate 251 having the connection pads 251a and 251b. The solder bumps 241a and 241b of the light emitting diode 1000 are aligned on the connection pads 251a and 251b, and the light emitting diode 1000 can be soldered to the base substrate 251 by using the soldering technology of the reflow process.

[0272] At this time, solder paste may be applied to the contact pads 251a and 251b in advance. However, as the solder bumps 241a and 241b are arranged on the light emitting diode 1000, the amount of solder paste applied to the contact pads 251a and 251b may be greatly reduced compared to the prior art.

[0273] Thus, a light emitting element is provided in which the contact pads 251a and 251b and the first bump pad 241a and the second bump pad 241b are soldered to each other through the solders 241a' and 241b'.

[0274] Here, although it is described that the light emitting diode 1000 is mounted on the base substrate 251 , a printed circuit board may be used instead of the base substrate 251 , or a package having leads may be used.

[0275] Thus, various light-emitting elements such as a light-emitting diode package or a light-emitting module in which the light-emitting diode 1000 is mounted can be provided.

[0276] Fig. 20 FIG. 2 is a schematic top view of a light emitting diode 2000 for illustrating another embodiment of the present invention. Fig.21 It is used to illustrate Fig. 20 The schematic circuit diagram of the light emitting diode, Fig. 22 It is along Fig. 20 A schematic cross-sectional view taken along the cutting line BB of Fig.23 It is along Fig. 20 A schematic cross-sectional view taken along the cutting line CC.

[0277] Reference Figure 20 to Figure 23 The light emitting diode of this embodiment is the same as that of the previous reference Fig.15 The embodiment described is generally similar, except that a plurality of light emitting units C1, C2, C3, and C4 are arranged on the substrate 221. Fig.21 As shown, the light emitting cells C1, C2, C3, and C4 may be connected in series between the first bump pad 239a and the second bump pad 239b.

[0278] The first light emitting cell C1, the second light emitting cell C2, the third light emitting cell C3 and the fourth light emitting cell C4 are arranged on the substrate 221. The first light emitting cell C1, the second light emitting cell C2, the third light emitting cell C3 and the fourth light emitting cell C4 are separated from each other by exposing the separation area of ​​the substrate 221. The top surface of the substrate 221 may be exposed in the area between the light emitting cells.

[0279] In this embodiment, the first light emitting unit C1 and the second light emitting unit C2 are arranged on the lower side, and the third light emitting unit C3 and the fourth light emitting unit C4 are arranged on the upper side, but the first light emitting unit C1, the second light emitting unit C2, the third light emitting unit C3 and the fourth light emitting unit C4 can be arranged in various ways. In addition, in this embodiment, four light emitting units are shown and described as being arranged on the substrate 221, but the number of light emitting units is not particularly limited. For example, two light emitting units or seven light emitting units can be arranged on the substrate 221.

[0280] Each light emitting unit includes a first conductive semiconductor layer 223 and a mesa M. The first conductive semiconductor layer 223 and the mesa M are similar to those in the previous reference. Fig.15 as well as Fig.16 The situations described are the same, so in order to avoid repetition, detailed description of the same matters will be omitted.

[0281] The mesa M may be defined and exist inside the region surrounded by the first conductive semiconductor layer 223 , and thus, a region near the edge adjacent to the outer side of the first conductive semiconductor layer 223 is not covered by the mesa M but exposed to the outside.

[0282] In the present embodiment, each mesa M may include a via hole 227 a , and the first conductive type semiconductor layer 223 is exposed in each via hole 227 a .

[0283] On the other hand, a conductive oxide layer 228 is arranged on each mesa M, and a dielectric layer 229 covers the conductive oxide layer 228 on each light emitting unit C1, C2, C3, and C4 and the mesa M. The conductive oxide layer 228 is in ohmic contact with the second conductive type semiconductor layer 227. The conductive oxide layer 228 can be arranged in the area above the mesa M across almost the entire area of ​​the mesa M. However, the conductive oxide layer 228 can be separated from the edge of the mesa M.

[0284] The dielectric layer 229 may cover the area above the mesa M and the side surface, and cover the first conductive semiconductor layer exposed around the mesa M. The dielectric layer 229 also has an opening 229a that exposes the conductive oxide layer 228. The dielectric layer 229 is located in the area above the first conductive semiconductor layer 223, so the dielectric layers 229 on different light-emitting units may be separated from each other. However, the present invention is not necessarily limited to this, and the dielectric layers on adjacent light-emitting units may also be connected to each other.

[0285] The metal reflective layer 231 is disposed on the dielectric layer 229 and is connected to the conductive oxide layer 228 through the opening 229a of the dielectric layer 229. The metal reflective layer 231 is disposed in the region above the mesas M of each of the light emitting units C1, C2, C3, and C4.

[0286] The lower insulating layer 233 covers the mesa M and covers the metal reflective layer 231 and the dielectric layer 229. The lower insulating layer 233 also covers the first conductive type semiconductor layer 223 exposed outside the dielectric layer 229 and the substrate 221. When the substrate 221 is a patterned sapphire substrate, the lower insulating layer 233 can be formed along the shape of the protrusion on the substrate 221.

[0287] As shown in the figure, the edge of the lower insulating layer 233 may be located on the first conductive semiconductor layer 223 of each light emitting unit, but is not limited thereto. The lower insulating layer 233 may also cover the side of the first conductive semiconductor layer 223 and be located on the substrate 221 .

[0288] The lower insulating layer 233 has a first opening portion 233a in the via hole 227a of each mesa M to expose the first conductive semiconductor layer 223, and also has a second opening portion 233b1 on the first light-emitting unit C1 to expose the metal reflective layer 231, and a second opening portion 233b2 on the second light-emitting unit C2, the third light-emitting unit C3 and the fourth light-emitting unit C4 to expose the metal reflective layer 231.

[0289] In this embodiment, the lower insulating layer 233 does not include an opening portion exposing the first conductive semiconductor layer 223 around the mesa M. However, the present invention is not limited thereto, and the lower insulating layer 233 may also include an opening portion exposing the first conductive semiconductor layer 223 around the mesa.

[0290] The second opening 233b1 is disposed on the first light emitting cell C1, and the second opening 233b2 exposes the metal reflective layer 231 of each light emitting cell near the separation region of the light emitting cell. The second opening 233b2 may have a shape substantially long along the separation region, but is not limited thereto and may have various shapes.

[0291] On the other hand, the second opening 233b1 may be located on the first light emitting cell C1 and in the area below the second bump pad 239b. However, in another embodiment, the second opening 233b1 may also be arranged horizontally apart from the second bump pad 239b on the first light emitting cell C1.

[0292] As reference Fig.15 as well as Fig.16 As described above, the lower insulating layer 233 may be formed as a single layer or multiple layers, or may include a distributed Bragg reflector. In addition, the lower insulating layer 233 may further include a coupling layer covering the distributed Bragg reflector.

[0293] On the other hand, a first pad metal layer 235 a , a second pad metal layer 235 b , and a connection metal layer 235 c are disposed on the lower insulating layer 233 .

[0294] The first pad metal layer 235a is arranged on the fourth light emitting unit C4, and is in ohmic contact with the first conductive semiconductor layer 223 in the via hole 227a exposed in the mesa M. In the present embodiment, it is shown that the first pad metal layer 235a is in contact with the first conductive semiconductor layer 223 in the via hole 227a, but it can also be in contact with the first conductive semiconductor layer 223 around the mesa M. However, by arranging the first pad metal layer 235a in the upper region of the mesa M, it can be far away from the edge of the substrate 221, thereby preventing the first pad metal layer 235a from being damaged by moisture entering from the side of the substrate 221.

[0295] The second pad metal layer 235b may be disposed on the first light emitting cell C1 and electrically connected to the metal reflective layer 231 through the second opening 233b1. Thus, the second pad metal layer 235b is electrically connected to the second conductive semiconductor layer 227 of the first light emitting cell C1.

[0296] The second pad metal layer 235b is located on the mesa M and is insulated from the first conductive semiconductor layer 223. Furthermore, the second pad metal layer 235b can be separated from the side of the mesa M on the first light emitting unit C1. Thus, the second pad metal layer 235b can be prevented from being damaged by moisture entering from the side of the substrate 221.

[0297] On the other hand, the connecting metal layer 235c connects adjacent light-emitting units in series. The connecting metal layer 235c can be electrically connected to the first conductive semiconductor layer 223 and the second conductive semiconductor layer 227 of the adjacent light-emitting unit through the first opening 233a and the second opening 233b2 of the lower insulating layer 233. For example, one connecting metal layer 235c can be electrically connected to the first conductive semiconductor layer 223 in the first light-emitting unit C1, and at the same time electrically connected to the metal reflective layer 231 on the second light-emitting unit C2. Thus, the first light-emitting unit C1 and the second light-emitting unit C2 are connected in series with each other through the connecting metal layer 233c. In this way, the second light-emitting unit C2 and the third light-emitting unit C3 can be connected in series through the connecting metal layer 235c, and the third light-emitting unit C3 and the fourth light-emitting unit C4 can be connected in series through the connecting metal layer 235c.

[0298] The connection metal layer 235c is spaced apart from the first pad metal layer 235a and the second pad metal layer 235b. Further, the connection metal layer 235c may be formed to have a narrower width than the mesa M, and thus may be further away from the edge of the substrate 221 than the mesa M.

[0299] The first pad metal layer 235a, the second pad metal layer 235b and the connection metal layer 235c can be formed together with the same material by the same process. For example, the first pad metal layer 235a, the second pad metal layer 235b and the connection metal layer 235c may include an ohmic reflective layer such as an Al layer, and the ohmic reflective layer may be formed on an adhesive layer of Ti, Cr or Ni. In addition, a protective layer of a single layer or a composite layer structure of Ni, Cr, Au, etc. may be formed on the ohmic reflective layer. The first pad metal layer 235a, the second pad metal layer 235b and the connection metal layer 235c may have a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti, for example.

[0300] The upper insulating layer 237 is arranged on the first pad metal layer 235a, the second pad metal layer 235b and the connection metal layer 235c, and has a first opening portion 237a that exposes the first pad metal layer 235a and a second opening portion 237b that exposes the second pad metal layer 235b. The upper insulating layer 237 can cover the top surface of the substrate 221 exposed around the light emitting unit 221. As shown in the figure, the upper insulating layer 237 can cover the edge of the substrate 221, but it is not limited thereto, and the edge of the upper insulating layer 237 can also be located inside the edge of the substrate 221.

[0301] On the other hand, the first opening portion 237a is arranged in the upper region of the first pad metal layer 235a, and thus is separated from the connection metal layer 235c and the second opening portion 233b2 of the lower insulating layer 233. In addition, the second opening portion 237b is defined and exists on the second pad metal layer 235b, and is separated from the connection metal layer 235c.

[0302] In this embodiment, the first pad metal layer 235a and the second pad metal layer 235b exposed through the first opening 237a and the second opening 237b of the upper insulating layer 237 can be used as bump pads on which solder bumps 241a and 241b are formed. Fig.15 as well as Fig.16 As described above, the first bump pad 239a and the second bump pad 239b may respectively cover the first pad metal layer 235a and the second pad metal layer 235b exposed through the first opening 237a and the second opening 237b of the upper insulating layer 237. The first bump pad 239a and the second bump pad 239b may be arranged across a plurality of light emitting units, respectively, and may cover and seal the first opening 237a and the second opening 237b.

[0303] The first solder bump 241a and the second solder bump 241b are arranged on the first bump pad 239a and the second bump pad 239b, respectively. The first solder bump 241a and the second solder bump 241b may have a bottom surface of the same shape as the first bump pad 239a and the second bump pad 239b. On the other hand, the thickness of the first solder bump 241a and the second solder bump 241b, the interval between them, and the interval between them and the edge of the substrate 221 are similar to the reference Fig.17 as well as Fig.18 The situations described are the same, so in order to avoid repetition, detailed descriptions are omitted.

[0304] Fig.24 as well as Fig.25 It is a schematic top view of light emitting diodes 200a and 200b for explaining another embodiment of the present invention.

[0305] Reference Fig.24 The light emitting diode 200a of this embodiment is different from the reference Figure 20 to Figure 23 The light emitting diodes described above are generally similar, except that the shapes of the first bump pad 239a and the second bump pad 239b are different, and thus the shapes of the first solder bump 241a and the second solder bump 241b are different.

[0306] That is, in the light emitting diode 2000, the first bump pad 239a and the second bump pad 239b have a substantially long rectangular shape and are arranged across a plurality of light emitting units, respectively. In contrast, in the light emitting diode 200a, the first bump pad 239a and the second bump pad 239b are arranged across a plurality of light emitting units, respectively, but the area between the light emitting units includes an area with a narrow width.

[0307] The first solder bump 241 a and the second solder bump 241 b may cover the first bump pad 239 a and the second bump pad 239 a and be formed in the same shape as the first bump pad 239 a and the second bump pad 239 b .

[0308] Reference Fig.25 The light emitting diode 200b of this embodiment is different from the reference Figure 20 to Figure 23 The light emitting diode 2000 described above is substantially similar, except that the first bump pad 239a and the second bump pad 239b are respectively arranged on a single light emitting unit C4, C1 and a dummy bump pad 239c is arranged on the other light emitting units C2, C3.

[0309] The dummy bump pad 239c is formed on the upper insulating layer 237 together with the first bump pad 239a and the second bump pad 239b in the same process. However, the dummy bump pad 239c is electrically isolated from the first light emitting cell C1, the second light emitting cell C2, the third light emitting cell C3 and the fourth light emitting cell C4 by the upper insulating layer 237.

[0310] On the other hand, the first solder bump 241a and the second solder bump 241b may be arranged on the first bump pad 239a and the second bump pad 239b respectively, and the dummy solder bump 241c may be arranged on the dummy bump pad 239c. The dummy solder bump 241c may also be omitted, thereby saving the amount of solder paste used to form the solder bumps.

[0311] In the present embodiment, a light-emitting diode including four light-emitting units is described as an example, but the light-emitting diode may include more light-emitting units than four. At this time, the solder bumps may be arranged so as to stably carry out the installation process of the light-emitting diode. For example, the first solder bump may be arranged across at least two light-emitting units arranged near one side edge of the substrate, and the second solder bump may be arranged across at least two light-emitting units arranged near the other side edge of the substrate. Alternatively, a virtual solder bump may be arranged on at least one of the at least two light-emitting units arranged near one side edge of the substrate, and the first solder bump may be arranged on at least one of the other light-emitting units. In addition, a virtual solder bump may be arranged on at least one of the at least two light-emitting units arranged near the other side edge of the substrate, and the second solder bump may be arranged on at least one of the other light-emitting units.

[0312] Fig.26 It is an exploded perspective view for explaining a lighting device using a light emitting diode according to an embodiment of the present invention.

[0313] Reference Fig.26 The lighting device of this embodiment includes a diffusion cover 1010, a light emitting element module 1020 and a main body 1030. The main body 1030 can accommodate the light emitting element module 1020, and the diffusion cover 1010 can be arranged on the main body 1030 so as to cover the upper part of the light emitting element module 1020.

[0314] The main body 1030 is not limited as long as it can accommodate and support the light emitting element module 1020 and supply power to the light emitting element module 1020. For example, as shown in the figure, the main body 1030 may include a main body housing 1031, a power supply device 1033, a power supply housing 1035, and a power connection portion 1037.

[0315] The power supply device 1033 can be accommodated in the power supply housing 1035 and electrically connected to the light emitting element module 1020, and includes at least one IC chip. The IC chip can adjust, convert or control the characteristics of the power supplied to the light emitting element module 1020. The power supply housing 1035 can accommodate and support the power supply device 1033, and the power supply housing 1035 in which the power supply device 1033 is fixed can be located inside the main body housing 1031. The power supply connection part 115 can be arranged at the lower end of the power supply housing 1035 and combined with the power supply housing 1035. Thus, the power supply connection part 1037 is electrically connected to the power supply device 1033 inside the power supply housing 1035, and can play the role of a channel that enables external power to be supplied to the power supply device 1033.

[0316] The light emitting element module 1020 includes a substrate 1023 and a light emitting element 1021 disposed on the substrate 1023. The light emitting element module 1020 may be disposed above the main housing 1031 and electrically connected to the power supply device 1033.

[0317] The substrate 1023 is not limited as long as it is a substrate capable of supporting the light emitting element 1021, and may be, for example, a printed circuit substrate including wiring. The substrate 1023 may have a shape corresponding to the fixing portion above the main housing 1031 so as to be stably fixed to the main housing 1031. The light emitting element 1021 may include at least one of the light emitting diodes of the above-mentioned embodiments of the present invention.

[0318] The diffusion cover 1010 may be arranged on the light emitting element 1021 and fixed to the main body housing 1031 to cover the light emitting element 1021. The diffusion cover 1010 may have a light-transmitting material, and the light directivity characteristics of the lighting device may be adjusted by adjusting the shape and light transmittance of the diffusion cover 1010. Therefore, the diffusion cover 1010 may be changed into various forms according to the purpose of use and the applicable form of the lighting device.

[0319] Fig. 27 FIG. 1 is a cross-sectional view for explaining a display device to which a light emitting diode according to another embodiment of the present invention is applied.

[0320] The display device of this embodiment includes: a display panel 2110 ; a backlight unit that provides light to the display panel 2110 ; and a panel guide that supports a lower edge of the display panel 2110 .

[0321] The display panel 2110 is not particularly limited, and may be, for example, a liquid crystal display panel including a liquid crystal layer. A gate drive PCB (printed circuit board) supplied with a drive signal by the gate line may be further provided at the edge of the display panel 2110. Here, the gate drive PCB may also be formed on a thin film transistor substrate instead of being formed on a separate PCB.

[0322] The backlight unit includes a light source module including at least one substrate and a plurality of light emitting elements 2160. Furthermore, the backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusion plate 2131 and an optical sheet 2130.

[0323] The bottom cover 2180 may be opened upward to accommodate the substrate, the light emitting element 2160, the reflective sheet 2170, the diffuser 2131, and the optical sheet 2130. In addition, the bottom cover 2180 may be combined with the panel guide. The substrate may be located below the reflective sheet 2170 and arranged to be surrounded by the reflective sheet 2170. However, it is not limited to this, and when a reflective material is coated on the surface, it may also be located on the reflective sheet 2170. In addition, the substrate may be formed in a plurality and arranged in a form in which a plurality of substrates are arranged side by side, but it is not limited to this, and it may be formed as a single substrate.

[0324] The light emitting element 2160 may include the light emitting diode of the embodiment of the present invention described above. The light emitting element 2160 may be regularly arranged in a certain pattern on the substrate. In addition, the lens 2210 is arranged on each light emitting element 2160 to improve the uniformity of the light emitted from the plurality of light emitting elements 2160.

[0325] The diffusion plate 2131 and the optical sheet 2130 are located on the light emitting element 2160. Light emitted from the light emitting element 2160 may be supplied to the display panel 2110 in the form of a surface light source through the diffusion plate 2131 and the optical sheet 2130.

[0326] Thus, the light emitting element according to the embodiment of the present invention can be applied to a direct-type display device like the one in this embodiment.

[0327] Fig.28 FIG. 1 is a cross-sectional view for explaining a display device to which a light emitting diode according to another embodiment of the present invention is applied.

[0328] The display device having the backlight unit of this embodiment includes: a display panel 3210 for displaying an image; a backlight unit arranged on the back of the display panel 3210 for irradiating light. Furthermore, the display device includes: a frame 3240 for supporting the display panel 3210 and accommodating the backlight unit; and covers 3270 and 3280 for wrapping the display panel 3210.

[0329] The display panel 3210 is not particularly limited, for example, it can be a liquid crystal display panel including a liquid crystal layer. A gate drive PCB for supplying a drive signal to the gate line can also be provided at the edge of the display panel 3210. Here, the gate drive PCB can also be formed on a thin film transistor substrate instead of being formed on a separate PCB. The display panel 3210 can be fixed by cover covers 3270 and 3280 located above and below it, and the cover cover 3270 located below can be combined with a backlight unit.

[0330] The backlight unit for providing light to the display panel 3210 includes: a lower cover 3270, a portion of the top surface of which is open; a light source module, which is arranged on one side of the inner part of the lower cover 3270; and a light guide plate 3250, which is arranged side by side with the light source module to convert point light into surface light. In addition, the backlight unit of this embodiment may also include: an optical sheet 3230, which is located on the light guide plate 3250 to diffuse and focus light; and a reflective sheet 3260, which is arranged below the light guide plate 3250 to reflect light traveling in the direction below the light guide plate 3250 toward the display panel 3210.

[0331] The light source module includes: a substrate 3220; and a plurality of light-emitting elements 3110, which are arranged at a certain interval on one side of the substrate 3220. The substrate 3220 is not limited as long as it supports the light-emitting element 3110 and is electrically connected to the light-emitting element 3110. For example, it can be a printed circuit substrate. The light-emitting element 3110 may include at least one light-emitting diode of the above-mentioned embodiment of the present invention. The light emitted from the light source module is incident on the light guide plate 3250 and is supplied to the display panel 3210 through the optical sheet 3230. The point light source emitted from the light-emitting element 3110 can be converted into a surface light source through the light guide plate 3250 and the optical sheet 3230.

[0332] Thus, the light emitting element according to the embodiment of the present invention can be applied to an edge type display device like the one in this embodiment.

[0333] Fig.29 This is a cross-sectional view for explaining an example in which a light emitting diode according to another embodiment of the present invention is applied to a headlamp.

[0334] Reference Fig.29 The headlamp includes a lamp body 4070 , a substrate 4020 , a light emitting element 4010 , and a cover lens 4050 . Furthermore, the headlamp may further include a heat dissipation portion 4030 , a support rib 4060 , and a connection member 4040 .

[0335] The substrate 4020 is fixed by the support ribs 4060 and is arranged on the lamp body 4070 in a spaced manner. The substrate 4020 is not limited as long as it can support the light emitting element 4010. For example, it can be a substrate having a conductive pattern such as a printed circuit substrate. The light emitting element 4010 can be located on the substrate 4020 and supported and fixed by the substrate 4020. In addition, the light emitting element 4010 can be electrically connected to an external power source through the conductive pattern of the substrate 4020. In addition, the light emitting element 4010 can include at least one light emitting diode according to the above-mentioned embodiment of the present invention.

[0336] The cover lens 4050 is located on the path along which the light emitted from the light emitting element 4010 moves. For example, as shown in the figure, the cover lens 4050 can be arranged to be separated from the light emitting element 4010 by the connecting component 4040, and can be arranged in the direction in which the light emitted from the light emitting element 4010 is to be provided. The direction angle and / or color of the light emitted from the headlight to the outside can be adjusted by the cover lens 4050. On the other hand, the connecting component 4040 can also be arranged to surround the light emitting element 4010 while fixing the cover lens 4050 to the substrate 4020 to play a light-guiding role of providing a light path 4045. At this time, the connecting component 4040 can be formed of a light-reflective material, or coated with a light-reflective material. On the other hand, the heat dissipation portion 4030 can include a heat sink 4031 and / or a heat dissipation fan 4033, which can discharge the heat generated when the light emitting element 4010 is driven to the outside.

[0337] Thus, the light emitting element according to the embodiment of the present invention can be applied to a headlamp like the present embodiment, and can be particularly applied to a headlamp for an automobile.

[0338] Although various embodiments of the present invention have been described above, the present invention is not limited to these embodiments. In addition, the content or constituent elements described in one embodiment may also be applied to other embodiments as long as they do not depart from the technical concept of the present invention.

Claims

1. A light emitting diode, comprising: a first conductive type semiconductor layer; An active layer, arranged on the first conductive type semiconductor layer; A second conductive semiconductor layer is arranged on the active layer; a transparent conductive oxide layer electrically connected to the second conductive type semiconductor layer; a dielectric layer covering the conductive oxide layer and having a plurality of openings for exposing the conductive oxide layer; a metal reflective layer, arranged on the dielectric layer and connected to the conductive oxide layer through an opening of the dielectric layer; a lower insulating layer, arranged on the metal reflective layer, and comprising a first opening portion for exposing the first conductive type semiconductor layer and a second opening portion for exposing the metal reflective layer; a first pad metal layer, arranged on the lower insulating layer and electrically connected to the first conductive type semiconductor layer through a first opening of the lower insulating layer; a second pad metal layer, arranged on the lower insulating layer and electrically connected to the second conductive type semiconductor layer through a second opening of the lower insulating layer; an upper insulating layer, disposed on the first pad metal layer and the second pad metal layer, and having an opening portion exposing the first pad metal layer and the second pad metal layer; a first bump pad electrically connected to the first pad metal layer through an opening of the upper insulating layer; a second bump pad electrically connected to the second pad metal layer through the opening of the upper insulating layer; A first solder bump is arranged on the first bump pad; and A second solder bump is arranged on the second bump pad, The first solder bump has a thickness ranging from 10 times to 80 times the thickness of the first bump pad and the second bump pad, and the second solder bump has a thickness ranging from 10 times to 80 times the thickness of the first bump pad and the second bump pad.

2. The light emitting diode according to claim 1, wherein: The first solder bump and the second solder bump have inclined side surfaces, and an inclination angle of the inclined side surfaces relative to a bottom surface is in a range of 65 degrees to 75 degrees.

3. The light emitting diode according to claim 1, wherein: The distance between the first solder bump and the second solder bump is greater than or equal to 2 times and less than or equal to 10 times the thickness of the first solder bump or the second solder bump.

4. The light emitting diode according to claim 3, wherein: The light emitting diode further includes a substrate arranged below the first conductive type semiconductor layer. The shortest distance in the horizontal direction between the first solder bump or the second solder bump and the edge of the substrate is the same as or greater than the thickness of the first solder bump and the second solder bump.

5. The light emitting diode according to claim 1, wherein: The first bump pad and the second bump pad have a flat top surface.

6. The light emitting diode according to claim 1, wherein: The first solder bump and the second solder bump cover the entire top surfaces of the first bump pad and the second bump pad respectively.

7. The light emitting diode according to claim 1, wherein: A distance between the first bump pad and the second bump pad is greater than or equal to 2 times and less than or equal to 10 times the thickness of the first solder bump or the second solder bump.

8. The light emitting diode according to claim 1, wherein: The light emitting diode further includes a substrate arranged below the first conductive type semiconductor layer. The shortest distance in the horizontal direction between the first bump pad or the second bump pad and the edge of the substrate is the same as or greater than the thickness of the first solder bump and the second solder bump.

9. The light emitting diode according to claim 1, wherein: The light emitting diode further comprises: substrate; and A plurality of light emitting units are arranged on the substrate, The light emitting units respectively include the first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, The first bump pad is electrically connected to the first conductive semiconductor layer of one of the plurality of light emitting units. The second bump pad is electrically connected to the second conductive type semiconductor layer of another light emitting unit among the plurality of light emitting units.

10. The light emitting diode according to claim 9, wherein: The light emitting diode further includes a dummy bump pad disposed on other light emitting units among the plurality of light emitting units, The dummy bump pad is electrically isolated from the light emitting unit.

11. The light emitting diode according to claim 9, wherein: The first bump pad and the second bump pad are respectively arranged across at least two light emitting units.

12. The light emitting diode according to claim 11, wherein: Regions of the first bump pad and the second bump pad between the light emitting units include regions with narrow widths.

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