Magnetic storage device

Abstract

A magnetic storage device includes an array of memory cells including magnetic memory cells, a voltage generator configured to generate a gate voltage, a row decoder including word line drivers configured to be driven by the gate voltage generated from the voltage generator, the row decoder connected to the array of memory cells by word lines, a column decoder connected to the array of memory cells by a plurality of bit lines and a plurality of source lines, and a write driver configured to deliver a write voltage to a bit line selected by the column decoder from the plurality of bit lines, the write driver driven by the gate voltage generated from the voltage generator.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0038142, filed with the Korean Intellectual Property Office on April 2, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to magnetic storage devices. Background Technology

[0004] Non-volatile memory devices using resistive materials include phase-change random access memory (PRAM), resistive RAM (RRAM), and magnetic RAM (MRAM). Dynamic RAM (DRAM) and flash memory use electrical charge to store data. Meanwhile, non-volatile memory devices using resistive materials store data using phase-change state changes of materials such as chalcogenide alloys (PRAM), resistance changes of variable-resistance materials (RRAM), and resistance changes of MTJ (magnetic tunnel junction) thin films that depend on the magnetization state of ferromagnetic materials (MRAM).

[0005] MRAM (Magnetic Random Access Memory) devices have attracted attention due to their high read / write speeds, high durability, non-volatility, and low power consumption during operation. MRAM devices can use magnetic materials as the information storage medium to store information. Summary of the Invention

[0006] Various aspects of the present invention provide magnetic storage devices with improved product reliability.

[0007] However, the aspects of the inventive concept are not limited to those set forth herein. These and other aspects of the inventive concept will become more apparent to those skilled in the art from the detailed description of some exemplary embodiments given below.

[0008] According to an exemplary embodiment of the present invention, a magnetic storage device may include: a memory cell array comprising magnetic memory cells; a voltage generator configured to generate a gate voltage; a row decoder including a word line driver driven by the gate voltage generated from the voltage generator, the row decoder being connected to the memory cell array via word lines; a column decoder connected to the memory cell array via multiple bit lines and multiple source lines; and a write driver configured to deliver a write voltage to a bit line selected by the column decoder from the multiple bit lines, the write driver being driven by the gate voltage generated from the voltage generator.

[0009] According to an exemplary embodiment of the present invention, a magnetic storage device may include: a magnetic storage cell including a variable resistance element and a selection transistor; a word line driver connected to the gate of the selection transistor; a write driver that transmits a write voltage to the selection transistor; and a voltage generator configured to apply a gate voltage to the word line driver and the write driver.

[0010] According to an exemplary embodiment of the present invention, a magnetic storage device may include: a memory cell array comprising magnetic memory cells; word lines, bit lines, and source lines connected to the memory cell array; a write driver connected to the bit lines and the source lines, the write driver being configured to receive a gate voltage; a word line driver connected to the word lines, the word line driver being configured to receive the gate voltage; and a voltage generator configured to transfer the gate voltage to the word line driver and the write driver. The voltage generator may include: a first transistor; a second transistor, the first transistor having a first gate connected to the write driver, and the second transistor having a second gate connected to the word line driver; a switching block connected between the first transistor and the second transistor; and a charge pump configured to transfer the gate voltage to the first gate of the first transistor and the second gate of the second transistor. Attached Figure Description

[0011] The above and other aspects and features of the inventive concept will become more apparent from a detailed description of some exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating a magnetic storage device according to an example embodiment;

[0013] Figure 2 This is a block diagram illustrating another magnetic storage device according to an example embodiment;

[0014] Figure 3 This is a diagram illustrating a memory cell array of a magnetic storage device according to an example embodiment;

[0015] Figure 4 This is a diagram illustrating the memory cells of a memory cell array according to an example embodiment;

[0016] Figure 5 This is a diagram illustrating a write operation of a magnetic storage device according to an example embodiment;

[0017] Figure 6 This is another diagram illustrating the write operation of a magnetic storage device according to an example embodiment;

[0018] Figure 7 This is a diagram illustrating a voltage generator according to an example embodiment;

[0019] Figure 8 This is another diagram illustrating a voltage generator according to an example embodiment;

[0020] Figure 9 This is another diagram illustrating a voltage generator according to an example embodiment;

[0021] Figure 10 This is another diagram illustrating a voltage generator according to an example embodiment;

[0022] Figure 11 This is a diagram illustrating a variable resistor according to an example embodiment;

[0023] Figure 12 This is a diagram illustrating another variable resistor according to an example embodiment; and

[0024] Figure 13 This is a block diagram illustrating a system including a magnetic storage device according to an example embodiment. Detailed Implementation

[0025] Figure 1 This is a block diagram illustrating a magnetic storage device according to an example embodiment. Figure 2 This is a block diagram illustrating another magnetic storage device according to an example embodiment.

[0026] Reference Figure 1 The magnetic storage device 100 includes a memory cell array 110, a row decoder 120, a column decoder 130, a write driver 140, a data buffer 150, and control logic 160. Furthermore, the row decoder 120 may include a word line driver 180, and the control logic 160 may include a voltage generator 170.

[0027] Row decoder 120 can control the voltage of word line WL according to control logic 160. For example, row decoder 120 can apply a selection voltage for reading or writing to a selected word line, and can apply a non-selection voltage (one or more non-selection voltages) for disabling reading or writing to other unselected word lines. Row decoder 120 can be connected to memory cell array 110 (e.g., memory cells in memory cell array 110) via word line WL.

[0028] Column decoder 130 can be connected to the source lines and bit lines in the memory cell array 110. Column decoder 130 can be connected to a write driver. Column decoder 130 can, under the control of control logic 160, electrically connect selected source lines and selected bit lines to the write driver.

[0029] The column decoder 130 may, under the control of the control logic 160, apply a bias voltage to the remaining unselected source lines and bit lines. The bias voltage may be defined as not affecting write or read operations to selected memory cells connected to the selected word lines, some selected bit lines, and some selected source lines, and the bias voltage may include, for example, a ground voltage.

[0030] The voltage generator 170 included in the control logic 160 can generate a gate voltage VG. The gate voltage VG can be applied to the word line driver 180 in the row decoder 120 to drive the row decoder 120. In addition, the gate voltage VG can be applied to the write driver 140 to drive the write driver 140.

[0031] Voltage generator 170 includes one charge pump or a group of charge pumps. That is, the charge pump associated with the operation of row decoder 120 and the charge pump associated with the operation of column decoder 130 may not be provided separately. In other words, one charge pump or a group of charge pumps may be provided in voltage generator 170 and associated with the operation of row decoder 120 and column decoder 130. The number of charge pumps is not limited to one. Therefore, by configuring one charge pump or a group of multiple charge pumps associated with the operation of row decoder 120 and column decoder 130, the area occupied by the charge pumps in magnetic storage device 100 can be reduced. In addition, the standby power consumption during standby time generated during write operations can be reduced.

[0032] When the state of a particular memory cell is the same as the state indicated by the data to be written to that particular memory cell, the write driver associated with that particular memory cell can maintain the state of that particular memory cell without changing it. When maintaining the data of a particular memory cell that does not need to be changed, the write driver associated with that particular memory cell can transmit a write inhibit voltage (e.g., ground voltage) to the source line and bit line associated with that particular memory cell.

[0033] During a write operation, the write driver 140 can receive and be driven by the gate voltage VG generated from the voltage generator 170, the write activation signal from the control logic 160, and the inverted write activation signal. The write driver can output a write voltage in response to the gate voltage VG, the write activation signal, and the inverted write activation signal.

[0034] For example, write driver 140 can deliver a write voltage to a selected bit line or a selected source line. For example, during a write operation that transitions the state of a memory cell from a first state (e.g., a low-resistance state or a high-resistance state) to a second state (e.g., a high-resistance state or a low-resistance state), write driver 140 can deliver a write voltage to a selected bit line selected by column decoder 130.

[0035] For example, during a write operation that changes the state of a memory cell from a second state to a first state, the write driver 140 can transmit the write voltage to the source line.

[0036] Data buffer 150 can be connected to the write driver via data line DL. Data buffer 150 can exchange data with an external device (e.g., a memory controller) under the control of control logic 160. For example, during a write operation, data buffer 150 can transfer data received from an external device to write driver 140. During a read operation, data buffer 150 can output data transferred from a sense amplifier (not shown) in write driver 140 to an external device.

[0037] Control logic 160 can receive control signals and addresses from an external device (e.g., a memory controller). In response to the control signals and addresses, the control logic can control the row decoder, column decoder, write driver, and data buffer to perform write and / or read operations.

[0038] Control logic 160 can provide a write activation signal and an inverted write activation signal to the write driver. The write activation signal and the inverted write activation signal can be complementary signals, but are not limited to them. When a write operation is performed, control logic 160 can control the write activation signal to a high level and the inverted write activation signal to a low level.

[0039] Control logic 160 may include voltage generator 170. Voltage generator 170 can generate a gate voltage VG during a write operation. Gate voltage VG can be transmitted to write driver 140 and word line driver 180. Gate voltage VG can be used by the write driver to generate a write voltage. In addition, gate voltage VG drives word line driver and can be used by row decoder 120 to select word lines. The level of gate voltage VG can be higher than the level of write voltage or the level of power supply voltage of magnetic storage device 100.

[0040] The write driver 140 can use the gate voltage VG to generate a write voltage with the same level. Because the gate voltage VG is higher than the write voltage or the supply voltage, the write driver 140 can generate a write voltage with a level approximately equal to the supply voltage.

[0041] Reference Figure 2 The example embodiments shown are similar to those described above. Figure 1 Unlike the example embodiment shown, voltage generator 170 may exist outside of control logic 160. (Not provided) Figure 1 Instead of repeating descriptions, the main focus will be on describing the differences.

[0042] During a write operation, voltage generator 170 can receive an operation signal from control logic 160 and generate a gate voltage VG. The gate voltage VG can be transmitted to word line driver 180 and write driver 140.

[0043] The voltage generator 170 includes one charge pump or a group of charge pumps. That is, the charge pumps associated with the operation of the row decoder 120 and the column decoder 130 may not be provided separately. In other words, one charge pump or a group of charge pumps associated with the operation of the row decoder 120 and the column decoder 130 can be provided in the voltage generator 170. The number of charge pumps is not limited to one. Therefore, by configuring one charge pump or a group of multiple charge pumps associated with the operation of the row decoder 120 and the column decoder 130, the area occupied by the charge pumps in the magnetic storage device 100 can be reduced. In addition, the standby power consumption during standby time generated during write operations can be reduced.

[0044] Figure 3 This is a diagram illustrating a storage cell array of a magnetic storage device according to an example embodiment. Figure 4 This is a diagram illustrating the storage cells of a storage cell array according to an example embodiment.

[0045] Reference Figure 1 , Figure 3 and Figure 4 The storage cell array 110 includes storage cells MC.

[0046] The memory cell MC can be connected to the source lines (SL1 to SLn) (n is a positive integer), bit lines (BL1 to BLn), and word lines (WL1 to WLm) (m is a positive integer). The memory cells MC can be arranged in rows and columns. The rows of the memory cells MC can be connected to the word lines (WL1 to WLm). The columns of the memory cells MC can be connected to the source lines (SL1 to SLn) and bit lines (BL1 to BLn). The voltage of the word lines (WL1 to WLm) can be controlled by the row decoder 120 under the control of the control logic 160. The bit lines (BL1 to BLn) and source lines (SL1 to SLn) can be connected to the column decoder 130.

[0047] A memory cell MC may include a selection transistor ST and a variable resistor element VR.

[0048] The select transistor ST includes: a first node connected to each source line (SL1 to SLn), a second node connected to each bit line (BL1 to BLn) via a variable resistor element VR, and a gate connected between the first node and the second node to each word line (WL1 to WLm).

[0049] For example, the gate of the select transistor ST can be connected to the first word line WL1. One electrode of the select transistor ST can be connected to the first bit line BL1 via a variable resistor element VR. Furthermore, the other electrode of the select transistor ST can be connected to the first source line SL1.

[0050] The variable resistive element VR comprises a pinned layer PL, a tunneling layer TL, and a free layer FL. The pinned layer PL may have a magnetization direction. The free layer FL may have a magnetization direction that changes according to the voltage (or current) applied to the variable resistive element VR.

[0051] The resistance of the variable resistor element VR can be changed based on whether the magnetization direction of the free layer FL is the same as or different from that of the pinned layer PL, or based on the magnitude of the difference between the magnetization directions of the free layer FL and the pinned layer PL. The variable resistor element VR can store data in the form of its resistance value. This will be explained later. Figure 5 and / or Figure 6 To describe the details of the write operation.

[0052] Figure 5 This is a diagram illustrating a write operation of a magnetic storage device according to an example embodiment.

[0053] Reference Figure 1 , Figure 3 and Figure 5 The write driver 140, bit line control circuit 155 and memory cell MC can be connected through the first bit line BL1 and the first source line SL1.

[0054] Bit line control circuitry 155 may be included in memory cell array 110 or write driver 140, but is not limited thereto.

[0055] The memory cell MC can be connected to the first bit line BL1, the first source line SL1, and the first word line WL1. The same operation can be applied equivalently to memory cells connected to other bit lines (e.g., the second bit lines to the nth bit lines) and other word lines (e.g., the second word lines to the mth word lines).

[0056] When the first word line WL1 is activated, the selection transistor ST is also activated, allowing the first bit line BL1 and the first source line SL1 to be connected via the memory cell MC. At this time, a cell current CC can be generated flowing to the memory cell MC. In the case of a write operation, data can be recorded using the cell current CC, and in the case of a read operation, data can be read by sensing the cell current CC. However, the invention is not limited to this.

[0057] Bit line control circuit 155 may include a first bit line switch 155-1 and a second bit line switch 155-2. The first bit line switch 155-1 and the second bit line switch 155-2 control each bit line (BL1 to BLn) and each source line (SL1 to SLn) according to the bit line control signal BLA.

[0058] For example, because the first bit line switch 155-1 and the second bit line switch 155-2 are turned on, the bit line control circuit 155 can activate the first bit line BL1 and the first source line SL1 based on the bit line control signal BLA input from the control logic 160. In the following description of the write operation of the memory cell MC, it is assumed that the first bit line switch 155-1 and the second bit line switch 155-2 of the bit line control circuit 155 are turned on.

[0059] The write driver 140 can be connected to the memory cell MC via the first bit line BL1 and the first source line SL1. The memory cell MC can store data 0 or 1 according to the control of the write driver 140.

[0060] The write driver 140 can use a first gate voltage VG1 and / or a second gate voltage VG2 input from the voltage generator 170 and a first write control signal WR1 and / or a second write control signal WR2 input from the control logic 160 to record data 0 or 1 on the memory cell MC.

[0061] The write driver 140 may include a first write controller 142, a second write controller 143, and write switches 141-1 to 141-4. The first write controller 142 and / or the second write controller 143 are shown as transistors, but the inventive concept is not limited thereto. The write switches 141-1 to 141-4 are shown as switches, but the inventive concept is not limited thereto.

[0062] The first write switch 141-1 and the fourth write switch 141-4 can be controlled by the first write control signal WR1. The second write switch 141-2 and the third write switch 141-3 can be controlled by the second write control signal WR2. For example, the first write control signal WR1 can be a signal applied when recording data 1, and the second write control signal WR2 can be a signal applied when recording data 0.

[0063] When one of the first write control signal WR1 and the second write control signal WR2 is applied, the other may not be applied. For example, when the second write control signal WR2 is applied, the first write control signal WR1 is not applied, and the cell current CC can flow from the first source line BL1 to the first source line SL1. On the other hand, when the first write control signal WR1 is applied, the second write control signal WR2 is not applied, and the cell current CC can flow from the first source line SL1 to the first source line BL1. However, the write operation according to the present invention is not limited to this.

[0064] When the first gate voltage VG1 and the first write control signal WR1 are applied to the write driver 140, one end of the first write controller 142 can be connected to the first drive voltage VDD, and the other end can be connected to the first source line SL1. Furthermore, the second drive voltage VSS can be connected to the first bit line BL1. At this time, the first write controller 142 can be controlled by the control logic 160 to adjust the cell current CC.

[0065] When the second gate voltage VG2 and the second write control signal WR2 are applied to the write driver 140, one end of the second write controller 143 can be connected to the first drive voltage VDD, and the other end can be connected to the first bit line BL1. Furthermore, the second drive voltage VSS can be connected to the first source line SL1. At this time, the second write controller 143 can be controlled by the control logic 160 to adjust the cell current CC.

[0066] Figure 6 This is another diagram illustrating a write operation of a magnetic storage device according to an example embodiment. For reference, it will not be provided. Figure 5 Instead of repeating descriptions, the main focus will be on describing the differences.

[0067] Reference Figure 1 , Figure 3 and Figure 6 The bit line control circuit 155 may include a third bit line switch 155-3 and a fourth bit line switch 155-4. The third bit line switch 155-3 and the fourth bit line switch 155-4 control each bit line (BL1 to BLn) and each source line (SL1 to SLn) according to the bit line control signals BLA and / BLA.

[0068] The third bit line switch 155-3 and the fourth bit line switch 155-4 can both be constructed from CMOS transmission gates, but are not limited to this.

[0069] For example, when the third bit line switch 155-3 and the fourth bit line switch 155-4 are in the ON state, the bit line control circuit 155 can activate the first bit line BL1 and the first source line SL1 based on the bit line control signals BLA and / BLA input from the control logic 160. In the following description, the write operation of the memory cell MC is described by assuming that the third bit line switch 155-3 and the fourth bit line switch 155-4 of the bit line control circuit 155 are in the ON state.

[0070] The write driver 140 can be connected to the memory cell MC via the first bit line BL1 and the first source line SL1. The memory cell MC can store data 0 or 1 according to the control of the write driver 140.

[0071] The write driver 140 can record data 0 or 1 on the memory cell MC using a first gate voltage VG1 and / or a second gate voltage VG2 input from the voltage generator 170 and a third write control signal WR3 and / or a fourth write control signal WR4 and / or a fourth write control signal input from the control logic 160.

[0072] The write driver 140 may include a first write controller 142, a second write controller 143, and write switches 141-5 to 141-8. The first write controller 142 and / or the second write controller 143 are shown as transistors, but the inventive concept is not limited thereto. The write switches 141-5 to 141-8 are shown as CMOS transmission gates, but the inventive concept is not limited thereto.

[0073] The fifth write switch 141-5 and the eighth write switch 141-8 can be controlled by the third write control signals WR3 and / WR3. The sixth write switch 141-6 and the seventh write switch 141-7 can be controlled by the fourth write control signals WR4 and / WR4. For example, the third write control signals WR3 and / WR3 can be signals applied when recording data 1, and the fourth write control signals WR4 and / WR4 can be signals applied when recording data 0.

[0074] At this point, in order to turn on write switches 141-5 to 141-8, it is desirable to turn on the gates of the NMOS and PMOS that constitute each write switch 141-5 to 141-8. To turn on the gates of the NMOS and PMOS that constitute each write switch 141-5 to 141-8, the write control signals entering the gates of the NMOS and PMOS can have different polarities. However, the absolute magnitudes of the write control signals entering the gates of the NMOS and PMOS may be different.

[0075] When one set of the third write control signals WR3 and / WR3 and the fourth write control signals WR4 and / WR4 is applied, the other set may not be applied. For example, when the third write control signals WR3 and / WR3 are applied, the fourth write control signals WR4 and / WR4 may not be applied, and the cell current CC can flow from the first source line BL1 to the first source line SL1. On the other hand, when the fourth write control signals WR4 and / WR4 are applied, the third write control signals WR3 and / WR3 may not be applied, and the cell current CC can flow from the first source line SL1 to the first source line BL1. However, the write operation according to the present invention is not limited to this.

[0076] When the first gate voltage VG1 and the third write control signals WR3 and / WR3 are applied to the write driver 140, one end of the first write controller 142 can be connected to the first drive voltage VDD, and the other end can be connected to the first source line SL1. Furthermore, the second drive voltage VSS can be connected to the first bit line BL1. At this time, the first write controller 142 can be controlled by the control logic 160 to adjust the cell current CC.

[0077] When the second gate voltage VG2 and the fourth write control signals WR4 and / WR4 are applied to the write driver 140, one end of the second write controller 143 can be connected to the first drive voltage VDD, and the other end can be connected to the first bit line BL1. Furthermore, the second drive voltage VSS can be connected to the first source line SL1. At this time, the second write controller 143 can be controlled by the control logic 160 to adjust the cell current CC.

[0078] Figure 7 This is a diagram illustrating a voltage generator according to an example embodiment. Figure 8 This is another diagram illustrating a voltage generator according to an example embodiment. Figure 9 This is another diagram illustrating a voltage generator according to an example embodiment. Figure 10 This is another diagram illustrating a voltage generator according to an example embodiment.

[0079] Reference Figure 7The voltage generator 170 may include a first transistor T1, a second transistor T2, a comparator 176, a clock (CK) generator 177, a reference voltage (VREF) generator 175, a charge pump 179, a switching block 190, and a variable resistor 192.

[0080] In the following text, refer to Figure 6 The write operation will assume that the first gate voltage VG1 and the third write control signals WR3 and / WR3 are applied to the write driver 140. That is, it will assume that one end of the first write controller 142 is connected to the first drive voltage VDD, and the other end is connected to the first source line SL1, and the first drive voltage VDD is connected to the first source line SL1.

[0081] Refer again Figure 7 The voltage generator 170 can be connected to the word line driver 180 and the write driver 140.

[0082] For example, the gate of the first transistor T1 of the voltage generator 170 can be connected to the gate of the first write controller 142 in the write driver. Furthermore, the gate of the second transistor T2 of the voltage generator 170 can be connected to the word line driver 180. That is, the second transistor T2 of the voltage generator 170 can be connected to the gate of the selection transistor ST of the memory cell MC via the word line driver 180.

[0083] The first transistor T1 includes a first terminal connected to a first drive voltage VDD, a second terminal connected to a switching block 190, and a gate connected to a gate node NG. The first transistor T1 can operate by receiving a gate voltage VG from a charge pump 179. Here, the gate voltage VG can be a second gate voltage VG2.

[0084] The first transistor T1 can be an NMOS transistor. That is, the first transistor T1 can form a source follower of the gate voltage VG. Therefore, even without components such as capacitors that occupy a large area, the first transistor T1 can have relatively low output impedance, relatively high controllability, and / or relatively fast recovery speed.

[0085] The second transistor T2 includes a first terminal connected to the switching block 190, a second terminal connected to the variable resistor 192, and a gate connected to the gate node NG. The second transistor T2 can be operated by receiving a gate voltage VG from the charge pump 179.

[0086] The variable resistor 192 can be connected between the comparator node NC and the second drive voltage VSS. For example, it can be as follows: Figure 11 and Figure 12The variable resistor 192 is configured as shown, and during a write operation, the resistance value can be adjusted to have the minimum resistance value of the variable resistor element VR in the memory cell MC. For example, the second drive voltage VSS can be ground voltage. However, the inventive concept is not limited thereto. Like the variable resistor element VR, the variable resistor 192 can include a tunneling magnetoresistive element having a pinned layer PL, a tunneling layer TL, and a free layer FL.

[0087] Reference voltage generator 175 can output a reference voltage VREF. Reference voltage generator 175 can also adjust the level of the reference voltage VREF. The reference voltage VREF can be fed to the positive input of comparator 176.

[0088] Comparator 176 can compare the voltage of the comparison node NC with the reference voltage VREF. For example, when the voltage of the comparison node NC is equal to or higher than the reference voltage VREF, comparator 176 can control the activation signal EN to a low level. When the voltage of the comparison node NC becomes lower than the reference voltage VREF, comparator 176 can control the activation signal EN to a high level.

[0089] Clock generator 177 can receive an external clock signal ECK from an external device (e.g., a memory controller). For example, it can receive the external clock signal ECK by including it in a control signal. That is, clock generator 177 can generate a clock signal CK in response to an activation signal EN and the external clock signal ECK.

[0090] For example, when the external clock signal ECK is transmitted to the clock generator 177 and the activation signal EN is input from the comparator 176, the clock generator 177 can generate the clock signal CK and transmit it to the charge pump 179. Conversely, if the external clock signal ECK or the activation signal EN is not transmitted to the clock generator 177, the clock generator 177 may not output the clock signal CK.

[0091] The charge pump 179 can be configured to generate a gate voltage VG. For example, the charge pump 179 can receive a clock signal CK to adjust the level of the gate voltage VG. For example, when the activation signal EN goes high, the charge pump 179 can increase the level of the gate voltage VG by pumping. When the activation signal EN goes low, the charge pump 179 can stop pumping and maintain the level of the gate voltage VG in its original state.

[0092] When a write operation is performed on a specific memory cell MC, the switch block 190 may include elements present in the current path from the first drive voltage to the second drive voltage via the memory cell MC. For example, the switch block 190 may include a switch or parasitic resistor present between the write driver and the memory cell MC, and a switch or parasitic resistor present between the memory cell MC and the second drive voltage.

[0093] For example, the first write controller 142 can receive an applied gate voltage VG to output a voltage minus a threshold voltage of the first write controller 142. This subtracted voltage can be transmitted to the memory cell MC via voltage distribution. A switch block 190 can be connected between the first transistor T1 and the second transistor T2 to reflect the aforementioned features in the voltage generator 170. Figure 5 As shown, the switch block 190 may include a first switch 141-1, a second switch 141-2, a third switch 141-3, a fourth switch 141-4, a bit line switch 155-1, and a source line switch 155-2. Therefore, the gate voltage VG that needs to be supplied to the word line driver 180 and the write driver 140 can be regulated by the charge pump 179 in the voltage generator 170.

[0094] Reference Figure 8 The voltage generator 170 can contain two charge pumps 179. That is, the voltage generator 170 can include a first charge pump 179a and a second charge pump 179b.

[0095] The first charge pump 179a can receive a first clock signal CK1 from the clock generator 177. The first charge pump 179a can pump the gate voltage VG in response to the first clock signal CK1. The second charge pump 179b can receive a second clock signal CK2 from the clock generator 177. The second charge pump 179b can pump the gate voltage VG in response to the second clock signal CK2. If the first clock signal CK1 and / or the second clock signal CK2 are not transmitted to the first charge pump 179a and / or the second charge pump 179b, then the first charge pump 179a and / or the second charge pump 179b can stop pumping. The pumping capability of each of the first charge pump 179a and / or the second charge pump 179b can be adjusted.

[0096] Reference Figure 9 The voltage controller 178 and the pumping transistor PT can also be included. Figure 7 In voltage generator 170. For reference, the number of charge pumps and pumping transistors are not limited to this. Not provided. Figure 7 Instead of repeating descriptions, the main focus will be on describing the differences.

[0097] The first terminal of the pumping transistor PT is connected to the charge pump 179, the second terminal is connected to the clock generator 177, and the gate of the pumping transistor PT can be connected to the voltage controller 178.

[0098] Voltage controller 178 can be configured to regulate the amount of pumping by charge pump 179. Voltage controller 178 can receive a voltage clock signal VECK. For example, during a write operation, voltage controller 178 can receive a command including the voltage clock signal VECK from an external device (e.g., a memory controller) and apply a voltage to the gate of pumping transistor PT to turn on pumping transistor PT.

[0099] Voltage controller 178 can transmit a first activation signal EN1 to reference voltage generator 175 based on information stored in an external device (e.g., a memory controller or other components in control logic) or internal memory (or alternatively, information received from an external device or internal memory). That is, voltage controller 178 can adjust the first activation signal EN1 to adjust the reference voltage VREF generated from reference voltage generator 175.

[0100] The voltage controller 178 can transmit an operation signal to the clock generator 177 to control the clock signal CK generated by the clock generator 177.

[0101] Clock generator 177 can receive an external clock signal ECK from an external device (e.g., a memory controller). For example, it can receive the external clock signal ECK by including it in a control signal. That is, clock generator 177 can generate a clock signal CK in response to an activation signal EN, the external clock signal ECK, and an operation signal received from voltage controller 178. The generated clock signal CK can be input to pump transistor PT, and the clock signal CK can be transmitted to charge pump 179 via pump transistor PT.

[0102] Reference Figure 10 The voltage controller 178, the first pumping transistor PT1, and the second pumping transistor PT2 may also be included. Figure 8 In voltage generator 170. For reference, the number of charge pumps and pumping transistors are not limited to this. Not provided. Figure 8 and Figure 9 Instead of repeating descriptions, the main focus will be on describing the differences.

[0103] The first terminal of the first pumping transistor PT1 is connected to the first charge pump 179a, and the second terminal is connected to the clock generator 177. The gate of the first pumping transistor PT1 can be connected to the voltage controller 178. The first terminal of the second pumping transistor PT2 is connected to the second charge pump 179b, and the second terminal is connected to the clock generator 177. The gate of the second pumping transistor PT2 can be connected to the voltage controller 178.

[0104] The voltage controller 178 can receive a voltage clock signal VECK. For example, during a write operation, the voltage controller 178 can receive a command including the voltage clock signal VECK from an external device (e.g., a memory controller) and can apply a voltage to the gate of the first pump transistor PT1 and / or the gate of the second pump transistor PT2 to turn on the first pump transistor PT1 and / or the second pump transistor PT2.

[0105] Clock generator 177 can receive an external clock signal ECK from an external device (e.g., a memory controller). For example, it can receive the external clock signal ECK by including it in a control signal. That is, clock generator 177 can generate a first clock signal CK1 and / or a second clock signal CK2 in response to an activation signal EN, the external clock signal ECK, and an operation signal received from voltage controller 178. The generated first clock signal CK1 and / or second clock signal CK2 can be input to a first pumping transistor PT1 and / or a second pumping transistor PT2. The first clock signal CK1 and / or second clock signal CK2 can be transmitted to a first charge pump 179a and / or a second charge pump 179b via the first pumping transistor PT1 and / or the second pumping transistor PT2.

[0106] Example embodiments of the present invention (e.g., Figures 7 to 10 In this configuration, no separate charge pump is provided for the word line driver and the write driver. That is, a single charge pump or a group of charge pumps can be provided as a single charge pump block included in a single voltage generator to apply gate voltages to both the word line driver and the write driver. In other words, the charge pump block can include one charge pump or a group of multiple charge pumps, thereby reducing the area occupied by the charge pump in the magnetic storage device and / or reducing standby power consumption during standby time generated during write operations.

[0107] Figure 11 This is a diagram illustrating a variable resistor according to an example embodiment.

[0108] Reference Figure 7 and Figure 11In the variable resistor 192, the switch is configured to turn on / off according to a first to a third signal (Sa to Sc) having different values ​​from each other, and a first to a third resistor (Ra to Rc) connected in parallel to each of the first to third signals (Sa to Sc) can be connected between the comparator node NC and the second drive voltage VSS. However, the inventive concept is not limited thereto, and the configuration and number of resistors can be modified differently.

[0109] Figure 12 This is a diagram illustrating another variable resistor according to an example embodiment.

[0110] Reference Figure 7 and Figure 12 The variable resistor 192 may include a plurality of transistors (MN11 to MN16). In this case, the variable resistor 192 may include an on-resistance formed by the conduction of one or more of the transistors (MN11 to MN16).

[0111] For example, the eleventh transistor MN11 can be driven by the fourth signal Se, the twelfth transistor MN12 and the thirteenth transistor MN13 can be driven by the fifth signal Sp, and the fourteenth transistor MN14, the fifteenth transistor MN15 and the sixteenth transistor MN16 can be driven by the sixth signal Sg.

[0112] Figure 13 This is a block diagram illustrating a system including a magnetic storage device according to an example embodiment.

[0113] Reference Figure 13 System 200 includes a processor 211 that controls the overall operation of magnetic storage device 213. Magnetic storage device 213 may be... Figure 1 The magnetic storage device 100 shown is shown.

[0114] The magnetic storage device 213 and the processor 211 can be encapsulated in a package 210. The package 210 can be mounted on a system board (not shown).

[0115] The processor 211 may include a memory controller 215 for controlling the operation of the magnetic storage device 213.

[0116] System 200 may include memory 240, which can be used as operating memory for processor 211. A host connected to the system can send data to and receive data from magnetic storage device 213 via processor 211 and host interface (I / F) 230. At this time, memory controller 215 can perform the functions of memory interface. System 200 may also include error correction code (ECC) block 220.

[0117] The ECC block 220, which operates under the control of the processor 211, can detect and correct errors in the data read from the magnetic storage device 213 by the memory controller 215.

[0118] The processor 211 can control the data exchange between the ECC block 220, the host interface 230 and the memory 240 via the bus 201.

[0119] System 200 can be implemented as a Universal Serial Bus (USB) storage drive or memory stick.

[0120] The row decoder 120, column decoder 130, control logic 160, processor 211, and / or memory controller MC 215, including word line driver 180, described herein can be implemented using hardware and combinations of software and hardware. For example, the hardware may include microcontrollers, memory modules, sensors, amplifiers, bandpass filters, analog-to-digital converters, and processing devices. The processing device can be implemented using one or more hardware devices configured to execute and / or run program code by performing arithmetic, logical, and input / output operations. The processing device may include a controller and arithmetic logic unit, digital signal processor, microcomputer, field-programmable array, programmable logic unit, microprocessor, or any other device capable of responding to and executing instructions in a defined manner. The processing device may run an operating system (OS) and one or more software applications running on the OS. The processing device may also access, store, manipulate, process, and create data in response to the execution of software. For simplicity, the description of the processing device is used in the singular; however, those skilled in the art will understand that the processing device may include multiple processing elements and various types of processing elements. For example, the processing device may include multiple processors or one processor and one controller. In addition, different processing configurations are possible, such as parallel processors, multi-core processors, distributed processing, etc.

[0121] Software can include computer programs, code, instructions, or combinations thereof to independently or collectively instruct and / or configure a processing device to operate in a desired manner, thereby transforming the processing device into a dedicated processor. Software and data can be permanently or temporarily implemented in any type of machine, component, physical or virtual device, and / or computer storage medium or apparatus. Software can also be distributed across networked computer systems, thus being stored and executed in a distributed manner. Software and data can be stored on one or more computer-readable recording media.

[0122] In closing, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments disclosed herein without substantially departing from the principles of the inventive concept. Therefore, the exemplary embodiments of the inventive concept disclosed herein are used only in a general and descriptive sense and not for limiting purposes.

[0123] While the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope of the inventive concept as defined by the appended claims. Therefore, it is intended that these exemplary embodiments be considered illustrative rather than restrictive in all respects, and that the scope of the inventive concept be indicated by reference to the appended claims rather than the foregoing description.

Claims

1. A magnetic storage device comprising: an array of storage cells including magnetic storage cells; a voltage generator configured to generate a gate voltage; a row decoder including word line drivers configured to be driven by the gate voltage generated from the voltage generator, the row decoder connected to the array of storage cells by word lines; a column decoder connected to the array of storage cells by a plurality of bit lines and a plurality of source lines; and a write driver configured to deliver a write voltage to a bit line selected by the column decoder from the plurality of bit lines, the write driver driven by the gate voltage generated from the voltage generator, wherein the voltage generator includes a first transistor and a second transistor, a first gate of the first transistor and a second gate of the second transistor are configured to receive the gate voltage, the first gate of the first transistor is connected to the write driver, and the second gate of the second transistor is connected to the word line drivers. the voltage generator includes a charge pump configured to generate the gate voltage.

2. The magnetic memory device of claim 1, wherein, the voltage generator includes a voltage controller configured to adjust an amount of pumping of the charge pump.

3. The magnetic storage device of claim 2, wherein, 4. The magnetic storage device of claim 1, further comprising: a variable resistance between the second transistor and ground.

5. The magnetic storage device of claim 4, wherein the variable resistance includes a plurality of sub-variable resistances, and the plurality of sub-variable resistances are configured to be operated by corresponding ones of a plurality of switches connected in parallel to the plurality of sub-variable resistances.

6. The magnetic storage device of claim 4, wherein the variable resistance includes a plurality of transistors, and one or more of the plurality of transistors are turned on to adjust a total resistance of the variable resistance. the write driver includes:

7. The magnetic memory device of claim 1 wherein, a first switch and a second switch configured to be controlled by a first write control signal; and a third switch and a fourth switch configured to be controlled by a second write control signal.

8. The magnetic storage device of claim 7, further comprising: a bit line switch configured to be controlled by a switch signal, the bit line switch connected to the bit line, the bit line switch connected to the second switch and the third switch, and a source line switch configured to be controlled by the switch signal, the source line switch connected to the source line, the source line switch connected to the first switch and the fourth switch.

9. The magnetic storage device of claim 8, wherein ​ The voltage generator further includes a switch block between the first transistor and the second transistor, the switch block including the first switch, the second switch, the third switch, the fourth switch, the bit line switch, and the source line switch.

10. A magnetic storage device, comprising: a magnetic storage cell including a variable resistance element and a select transistor; a word line driver connected to a gate of the select transistor; a write driver configured to transmit a write voltage to the select transistor; and a voltage generator configured to apply a gate voltage to the word line driver and the write driver, wherein the voltage generator includes a first transistor and a second transistor, and a first gate of the first transistor and a second gate of the second transistor are configured to receive the gate voltage, the first gate of the first transistor connected to the write driver, the second gate of the second transistor connected to the word line driver.

11. The magnetic memory device of claim 10 wherein, the voltage generator includes a charge pump configured to generate the gate voltage.

12. The magnetic memory device of claim 11 wherein, the voltage generator includes a voltage controller configured to adjust an amount of pumping of the charge pump.

13. The magnetic storage device of claim 10, further comprising: a switch block between the first transistor and the second transistor, the switch block including at least one switch connected between the write driver and the magnetic storage cell and at least one switch between the magnetic storage cell and ground.

14. The magnetic storage device of claim 13, further comprising: a variable resistance between the second transistor and the ground.

15. A magnetic storage device, comprising: an array of storage cells including a magnetic storage cell; a word line, a bit line, and a source line connected to the array of storage cells; a write driver connected to the bit line and the source line, the write driver configured to receive a gate voltage; a word line driver connected to the word line, the word line driver configured to receive the gate voltage; and a voltage generator configured to transmit the gate voltage to the word line driver and the write driver, the voltage generator including: a first transistor and a second transistor, a first gate of the first transistor connected to the write driver, a second gate of the second transistor connected to the word line driver, a switch block connected between the first transistor and the second transistor, and a charge pump configured to transmit the gate voltage to the first gate of the first transistor and the second gate of the second transistor.

16. The magnetic storage device of claim 15, further comprising: a variable resistance between the second transistor and ground.

17. The magnetic memory device of claim 16, wherein, the voltage generator includes: a comparator; a reference voltage generator configured to transmit a reference voltage to the comparator; and a clock generator configured to receive an activation signal from the comparator and transmit a clock signal to the charge pump, wherein the comparator is configured to compare the reference voltage to a voltage of a node to which the second transistor and the variable resistance are connected.

18. The magnetic storage device of claim 17, further comprising: a voltage controller configured to adjust an amount of pumping of the charge pump.

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