Command / address channel error detection

Abstract

The memory component and the controller transmit commands and data to each other. The commands to activate and then access the data, and the data itself, are transmitted between the controller and the memory component at different times. The controller and the memory component each calculate a corresponding error detection code (EDC) value for the activation command information (e.g., the memory bank address and the row address), and store the error detection code value indexed by the memory bank address. When the memory component is accessed, the retrieved EDC value is combined with the EDC value calculated based on the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for inspection.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure 1 is a block diagram of the memory system.

[0002] Figure 2 is a block diagram of the memory system.

[0003] Figure 3A is a flow chart illustrating a read operation.

[0004] Figure 3B is a flow chart illustrating a write operation.

[0005] Figure 4 is a diagram illustrating controller actions performed for a read operation.

[0006] Figure 5 is a diagram illustrating memory component actions performed for a read operation.

[0007] Figure 6 is a diagram illustrating controller actions performed for a write operation.

[0008] Figure 7 is a diagram illustrating the actions of memory components performed for a write operation.

[0009] Figure 8 is a diagram illustrating controller actions performed for a write operation to a memory component that checks an error detection code.

[0010] Fig. 9 2 is a diagram illustrating the actions of a memory component performed for a write operation and a check on an error detection code.

[0011] Fig.10 is a diagram illustrating a memory system that checks an error detection code applied to command / address communications.

[0012] Fig.11 is a flow diagram illustrating memory component access.

[0013] Fig.12 is a flow chart illustrating a method of accessing a memory component.

[0014] Fig.13 is a flow chart illustrating a method of determining whether an error occurs.

[0015] Fig.14 is a flow chart illustrating a method of providing error detection information.

[0016] Fig.15 is a flow chart illustrating a method of transmitting error detection information to a controller.

[0017] Fig.16 is a flow chart illustrating a method of receiving error detection information from a memory component.

[0018] Fig.17 It is a block diagram of the processing system. DETAILED DESCRIPTION

[0019] A memory component (e.g., a dynamic random access memory-DRAM integrated circuit system) receives command and address information for activating row and access column operations (e.g., to read and / or write data). The command to activate and then access the data, as well as the data itself, are transmitted between the controller and the memory component at different times. The controller calculates an error detection code (EDC) value for the activation command information (e.g., a bank address and a row address), and stores the error detection code value indexed by the bank address. Similarly, upon receiving an activation command, the memory component calculates an EDC value based on the received activation command information, and stores the EDC value indexed by the bank address.

[0020] When an access command is received by the memory component, the received bank address is used to retrieve the stored EDC value. The retrieved EDC value is then combined with the EDC value calculated based on the access command information, and the EDC value calculated from the data itself. Similar operations are performed by the controller to generate an expected EDC value, which is compared to the EDC value calculated by the memory component.

[0021] In one embodiment, the combined EDC value may be transmitted to a controller for checking. In another embodiment, the combined EDC value may be checked against an EDC value received from a controller.

[0022] In one embodiment, the individual EDC values ​​calculated for the activation and access command information may be communicated to the controller separately for examination (i.e., without first being combined with other EDC values ​​into a "combined" EDC value). These individual EDC values ​​may be communicated to the controller by "modulating" the EDC value for the data using an invertible function, the invertible function taking the data EDC value and the command EDC value as inputs. The controller "demodulates" the data EDC value and the command EDC value using the expected EDC value calculated by the controller for the corresponding command (as input to the inverse of the invertible function). In one embodiment, the invertible function may be an exclusive-OR (XOR) operation between one or more bits of the data EDC value and the command EDC value.

[0023] Figure 1 is a block diagram of the memory system. Figure 1 , the memory system 100 includes a controller 110 and a memory component 120. The controller 110 includes an error detection code calculation circuit system 112, an error detection code combination circuit system 113, an error detection code comparison circuit system 114, an error indicator 119, a command / address (CA) interface 131a, a data (DQ) interface 132a, and an error detection code (EDC) interface 133a. The controller 110 also generates and / or processes activation commands and information 115a, access commands and information 115b, and data 115c. The memory component 120 includes an error detection code calculation circuit system 122, an error detection code combination circuit system 123, a memory core (e.g., a memory cell array) 126, a CA interface 131b, a DQ interface 132b, and an EDC interface 133b. The memory component 120 also receives, responds to, and / or processes the received activation commands and information 125a, the received access commands and information 125b, and the data 125c.

[0024] Controller 110 and memory component 120 may be integrated circuit type devices (e.g., often referred to as "chips"). A memory controller, such as controller 120, manages the flow of data to and from memory devices and / or memory modules. Memory component 120 (also referred to as memory 120) may be a stand-alone device or may be a component of a memory module. The memory controller may be a separate stand-alone chip or may be integrated into another chip. For example, the memory controller may be included on a single die with a microprocessor or as part of a more complex integrated circuit system (e.g., a system on a chip (SOC)).

[0025] The controller 110 is operably coupled to the memory component 120 via a CA interface 131a, which is coupled to a CA signal line 131. The CA signal line 131 (and the corresponding CA interface 131a on the controller 110 and the CA interface 131b on the memory component 120) includes X number of signal lines. In one embodiment, X=11. In one embodiment, the CA signal line 131 may include one or more (e.g., 1) data bus inversion (DBI) signal lines. The controller 110 is operably coupled to the memory component 120 to send commands and associated information (e.g., addresses) to the memory 120 via the CA signal line 131. The memory component 120 receives these commands (and associated information - e.g., addresses) via a CA interface 131b, which is also coupled to the CA signal line 131.

[0026] The controller 110 is operably coupled to the memory 120 via a DQ interface 132a, which is coupled to a DQ signal line 132. The DQ signal line 132 (and the corresponding DQ interface 132a on the controller 110 and the DQ interface 132b on the memory component 120) may include a number of signal lines Y. In one embodiment, Y=18. In one embodiment, the DQ signal line 132 may include one or more (e.g., 2) DBI signal lines. The controller 110 and the memory component 120 are operably coupled via the DQ signal line 132 to bidirectionally transmit data (e.g., data 115c and / or data 125c). The memory component 120 may store (e.g., in the memory core 126) and retrieve (e.g., from the memory core 126) data transmitted via the DQ interface 132b and the DQ signal line 132.

[0027] The memory 120 is operably coupled to the controller 110 via an EDC interface 133b, which is coupled to an EDC signal line 133. The EDC signal line 133 (and the corresponding EDC interface 133a on the controller 110 and the EDC interface 133b on the memory component 120) may include a Z number of signal lines. In one embodiment, Z=2. In one embodiment, the EDC signal line 133 may include one or more (e.g., 1) DBI signal lines. The memory 120 is operably coupled to the controller 110 to send error detection code information (e.g., EDC code bits) to the controller 110 via the EDC interface 133b and the EDC signal line 133. The controller 110 receives these EDC bits via the EDC interface 133a and the EDC signal line 133.

[0028] In one embodiment, the controller 110 sends an activation command 115a to the memory component 120 via the CA signal line 131. The activation command 115a includes an associated bank address (BA) value and a row address (R or ROW) value. The memory component 120 receives the transmitted command and the associated address information. However, during the transmission and / or reception of the activation command 115a, errors may occur such that one or more bits of the received command and / or the associated address information are different from the transmitted activation command 115a. This may cause the memory component 120 to receive the activation command 115a. Figure 1 1 is illustrated by activation command 125a—activation command 125a may have the same (ie, correct) or incorrect (ie, corrupted) command and / or associated address information as activation command 115a. The received activation command 125a is provided to the EDC computing circuitry 122.

[0029] The controller 110 also sends an access command 115b to the memory component 120 via the CA signal line 131. The access command 115b can be a read or write command that reads data from the memory core 126 or stores data to the memory core 126, respectively. The access command 115b includes an associated bank address (BA) value and a column address (C or COL) value. The memory component 120 receives the sent command and the associated address information. However, during the transmission and / or reception of the access command 115b, an error may occur such that one or more bits of the received command and / or the associated address information are different from the sent access command 115b. This may occur in the event of a malfunction. Figure 1 Received access command 125b is provided to EDC computing circuitry 122. This is illustrated in FIG. 1 by access command 125b—access command 125b may have the same (ie, correct) or incorrect (ie, corrupted) command and / or associated address information as access command 115b.

[0030] If the access command 115b is a write, the controller 110 also sends data 115c to the memory component 120 via the DQ signal line 132. The memory component 120 receives the sent data. However, during the transmission and / or reception of the data 115c, errors may occur, causing one or more bits of the received data to differ from the sent data. This may occur in the case of Figure 1 Received data 125c is provided to EDC calculation circuitry 122. In one embodiment, EDC calculation circuitry 122 calculates a CRC-8 type error detection code.

[0031] If the access command 115b is a read, the memory component 120 retrieves (from the memory core 126) the data 125c and sends the data 125c to the controller 110 via the DQ signal line 132. The controller 110 receives the sent data. However, during the storage (by the memory 126), transmission and / or reception of the data 125c, errors may occur such that one or more bits of the received data are different from the data sent. This may occur during the storage (by the memory 126), transmission and / or reception of the data 125c. Figure 1 Received data 115c is provided to EDC calculation circuitry 112. In one embodiment, EDC calculation circuitry 112 calculates a CRC-8 type error detection code.

[0032] Memory 120 provides the received activation command 125a, the received access command 125b, and data 125c (which are received from controller 110 or retrieved from memory core 126 as appropriate) to EDC calculation circuit system 122. In one embodiment, activation command 125a, access command 125b, and data 125c may be provided to EDC calculation circuit system 122 at different points in time. Thus, EDC calculation circuit system 122 calculates three EDC values. These three EDC values ​​are combined by EDC combining circuit system 123 into a single cyclic redundancy check (CRC) value 128. CRC value 128 is sent to controller 110 via EDC signal line 133.

[0033] Controller 110 provides activation command 115a, access command 115b, and data 115c to EDC calculation circuitry 112. In one embodiment, activation command 115a, access command 115b, and data 115c may be provided to EDC calculation circuitry 112 at different points in time. Thus, EDC calculation circuitry 112 calculates three EDC values. The three EDC values ​​are combined into a single cyclic redundancy check (CRC) value 118 by EDC combining circuitry 113. EDC combining circuitry 113 provides CRC value 118 to EDC comparison circuitry 114.

[0034] EDC comparison circuitry 114 compares CRC value 118 generated by controller 110 with CRC value 128 received from memory 120. If the two CRC values ​​are equivalent (e.g., equal), error indicator 119 is set to indicate that an error has not been detected. If the two CRC values ​​are not equivalent (e.g., not equal), error indicator 119 is set to indicate that an error has been detected.

[0035] In one embodiment, EDC calculation circuitry 113 and EDC calculation circuitry 123 generate error detection codes having an XOR value relative to The operation is linear in nature. In other words, the functions used to generate CRC 118 and CRC 128 satisfy the following conditions: Thus, EDC combination circuitry 113 and EDC combination circuitry 114 may include a bitwise exclusive OR (XOR) of the three EDC values ​​received from EDC calculation circuitry 113 and EDC calculation circuitry 114, respectively.

[0036] It should be understood from the foregoing that since the activation command 115a, the access command 115b and the data 115c are all inputs for calculating the controller CRC value 118, and since the received activation command 125a, the received access command 125b and the data 125c are all inputs for calculating the memory CRC value 128, and since the memory CRC value 128 is transmitted to the controller 110, certain errors (e.g., errors with less than a given number of corrupted bits) may be detected when transmitting, receiving and / or storing the activation command 115a, the access command 115b, the data 115c, the data 125c and / or the CRC value 128.

[0037] Figure 2 is a block diagram of the memory system. Figure 2 , the memory system 200 includes a controller 210 and a memory component 220. The controller 210 includes an activation command information synchronizer 211a, an access command information synchronizer 211b, a data synchronizer 211c, an error detection code (EDC) calculation circuit system 212, an error detection code combination circuit system 213, an error detection code comparison circuit system 214, an error indicator 219, a command / address (CA) interface 231a, a data (DQ) interface 232a, and an EDC interface 233a. The controller 210 generates and / or processes activation command information 215a, access command information 215b, and data 215c.

[0038] The memory component 220 (also referred to as memory 220) includes an activation command information synchronizer 221a, an access command information synchronizer 221b, a data synchronizer 221c, an error detection code calculation circuit system 222, an error detection code combination circuit system 223, a memory core (e.g., a memory cell array) 226, a CA interface 231b, a DQ interface 232b, and an EDC interface 233b. The memory component 220 receives, responds to, and / or processes received activation command information 225a, received access command information 225b, and data 225c. The controller 210 and the memory component 220 may be integrated circuit type devices.

[0039] The controller 210 is operably coupled to the memory 220 via a CA interface 231a, which is coupled to a CA signal line 231. The CA signal line 231 (and the corresponding CA interface 231a on the controller 210 and the CA interface 231b on the memory component 220) may include X number of signal lines. In one embodiment, X=11. In one embodiment, the CA signal line 231 may include one or more (e.g., 1) data bus inversion (DBI) signal lines. The controller 210 is operably coupled to the memory 220 to send commands and associated information (e.g., addresses) to the memory 220 via the CA signal line 231. The memory 220 receives these commands (and associated information - e.g., addresses) via a CA interface 231b, which is also coupled to the CA signal line 231.

[0040] The controller 210 is operably coupled to the memory 220 via a DQ interface 232a, which is coupled to a DQ signal line 232. The DQ signal line 232 (and the corresponding DQ interface 232a on the controller 210 and the DQ interface 232b on the memory component 120) may include a number of signal lines Y. In one embodiment, Y=18. In one embodiment, the DQ signal line 232 may include one or more (e.g., 2) DBI signal lines. The controller 210 and the memory component 220 are operably coupled via the DQ signal line 232 to bidirectionally transmit data (e.g., data 215c and / or data 225c). The memory 220 may store (e.g., in the memory core 226) and retrieve (e.g., from the memory core 226) data transmitted via the DQ interface 232b and the DQ signal line 232.

[0041] The memory 220 is operably coupled to the controller 210 via an EDC interface 233b, which is coupled to an EDC signal line 233. The EDC signal line 233 (and the corresponding EDC interface 233a on the controller 210 and the EDC interface 233b on the memory component 220) may include a Z number of signal lines. In one embodiment, Z=2. In one embodiment, the EDC signal line 233 may include one or more (e.g., 1) DBI signal lines. The memory 220 is operably coupled to the controller 210 to send error detection code information (e.g., EDC code bits) to the controller 210 via the EDC interface 233b and the EDC signal line 233. The controller 210 receives these EDC bits via the EDC interface 233a and the EDC signal line 233.

[0042] In one embodiment, the controller 210 sends activation command information 215a to the memory component 220 via the CA signal line 231. The activation command information 215a includes, but is not limited to, a bank address (BA) value and a row address (R or ROW) value. The memory component 220 receives the sent activation command information. However, during the transmission and / or reception of the activation command information 215a, errors may occur, causing one or more bits of the received activation command information 225a to be different from the sent activation command information 215a. The received activation command information 225a is provided to the EDC calculation circuit system 222. The received activation command information 225a is provided to the EDC calculation circuit system 222 at a first point in time (e.g., a clock cycle, etc.). This Figure 2 T ACT 222a. The EDC calculation result based on the activation command information 225a (activation command information EDC code value 226a) is provided to the activation command information synchronizer 221a. In one embodiment, the EDC calculation circuit system 222 calculates a CRC-8 type error detection code.

[0043] The activation command information synchronizer 221a stores the activation command information EDC code value 226a until other inputs are ready to be combined with the activation command information EDC code value 226a. The activation command information synchronizer 221a may be a memory. In one embodiment, the activation command information synchronizer 221a may be a register file that is indexed by a memory bank address value from the received activation command information 225a. This allows the activation command information EDC code value 226a to be retrieved from the activation command information synchronizer 221a using a memory bank address value from a second (e.g., access) command that is received at a later point in time.

[0044] At a second point in time, after the activation command information 215a has been sent to the memory 220, the controller 210 transmits access command information 215b to the memory component 220 via the CA signal line 231. The access command information 215b can be associated with a read or write command, which reads data from the memory core 126 or stores data to the memory core 126, respectively. The access command information 215b includes, but is not limited to, a bank address (BA) value and a column address (C or COL) value. The memory component 220 receives the transmitted access command information. However, during the transmission and / or reception of the access command information 215b, errors may occur, causing one or more bits of the received access command information 225b to be different from the sent access command information 215b. The received access command information 225b is provided to the EDC calculation circuit system 222. The received access command information 225b is provided to the EDC calculation circuit system 222 at a second point in time (e.g., a clock cycle, etc.). This Figure 2 T ACC The EDC calculation result based on the access command information 225b (access command information EDC code value 226b) is provided to the access command information synchronizer 221b.

[0045] The access command information synchronizer 221b stores the access command information EDC code value 226b until other inputs are ready to be combined with the access command information EDC code value 226b. The activation command information synchronizer 221b may be a memory. In one embodiment, the activation command information synchronizer 221a may be a register.

[0046] If the access command information 215b is associated with a write command, the controller 210 transmits the data 215c to the memory component 220 via the DQ signal line 232. The memory component 220 receives the transmitted data. However, during the transmission and / or reception of the data 215c, an error may occur, causing one or more bits of the received data 225c to be different from the transmitted data 215c. The received data 225c is provided to the EDC calculation circuit system 222. The received data 225c is provided to the EDC calculation circuit system 222 at a third point in time (e.g., clock cycle, etc.). This Figure 2 T DAT The EDC calculation result based on the received data 225c (data EDC code value 226c) is provided to the data synchronizer 221c.

[0047] If the access command information 215b is associated with a read command, the memory component 220 retrieves the data 225c (from the memory core 226) and transmits the retrieved data 225c to the controller 210 via the DQ signal line 232. The retrieved data 225c is provided to the EDC calculation circuit system 222. The retrieved data 225c is provided to the EDC calculation circuit system 222 at a third point in time (e.g., clock cycle, etc.). This Figure 2 T DAT The EDC calculation result based on the retrieved data 225c (data EDC code value 226c) is provided to the data synchronizer 221c.

[0048] The data synchronizer 221c stores the data EDC code value 226c until other inputs are ready to be combined with the data EDC code value 226c. The data synchronizer 221c may be a memory. The data synchronizer 221c may be a register or a buffer memory.

[0049] The activation command information synchronizer 221a, the access command information synchronizer 221b and the data synchronizer 221c provide the activation command information EDC code value 226a, the access command information EDC code value 226b and the data EDC code value 226c to the EDC combination circuit system 223 respectively. In one embodiment, the activation command information synchronizer 221a, the access command information synchronizer 221b and the data synchronizer 221c can be controlled to provide an EDC value for combination, and the EDC value corresponds to the storage body, row and column accessed by the access command. In one embodiment, the activation command information synchronizer 221a, the access command information synchronizer 221b and the data synchronizer 221c can be controlled to provide an EDC value for combination, and the EDC value corresponds to one or more of different storage bodies, rows and / or columns. The EDC value is combined into a single cyclic redundancy check (CRC) value 228 by the EDC combination circuit system 223. The CRC value 228 is transmitted to the controller 210 via the EDC signal line 233.

[0050] Controller 210 provides activation command information 215a, access command information 215b, and data 215c to EDC computing circuit system 212. In one embodiment, activation command 215a, access command 215b, and data 215c may be provided to EDC computing circuit system 212 at different points in time. Figure 2 T ACT 212a, T ACC 212b and T DAT212c. The respective results of these EDC calculations are provided to the corresponding activation command information synchronizer 211a, access command information synchronizer 211b or data synchronizer 211c. In one embodiment, the EDC calculation circuitry 212 calculates a CRC-8 type error detection code.

[0051] The activation command information synchronizer 211a, the access command information synchronizer 211b, and the data synchronizer 211c provide the activation command information EDC code value 216a, the access command information EDC code value 216b, and the data EDC code value 216c to the EDC combination circuit system 213, respectively. In one embodiment, the activation command information synchronizer 211a, the access command information synchronizer 211b, and the data synchronizer 211c can be controlled to provide an EDC value for combination, which corresponds to the storage body, row, and column accessed by the access command. In one embodiment, the activation command information synchronizer 211a, the access command information synchronizer 211b, and the data synchronizer 211c can be controlled to provide an EDC value for combination, which corresponds to one or more of different storage bodies, rows, and / or columns. The EDC value is combined into a single cyclic redundancy check (CRC) value 218 by the EDC combination circuit system 213. The EDC combination circuit system 213 provides the CRC value 218 to the EDC comparison circuit system 214.

[0052] EDC comparison circuitry 214 compares CRC value 218 generated by controller 210 with CRC value 228 received from memory 220. If the two CRC values ​​are equal (e.g., identical), error indicator 219 is set to indicate that an error has not been detected. If the two CRC values ​​are not equal (e.g., not identical), error indicator 219 is set to indicate that an error has been detected.

[0053] In one embodiment, EDC calculation circuitry 213 and EDC calculation circuitry 223 generate error detection codes having a relative XOR The operation is linear in nature. In other words, the function used to generate CRC 218 and CRC 228 satisfies the following: Thus, EDC combining circuitry 213 and EDC combining circuitry 214 may include a bitwise exclusive OR (XOR) of three EDC values ​​received from synchronizers 211a-211c and synchronizers 221a-221c, respectively.

[0054] It should be understood from the foregoing that since the activation command information 215a, the access command information 215b and the data 215c are all inputs for the calculation of the controller CRC value 218, and since the received activation command information 225a, the received access command information 225b and the data 225c are all inputs for the calculation of the memory CRC value 228, and since the memory CRC value 228 is transmitted to the controller 210, certain errors (for example, errors with less than a given number of corrupted bits) may be detected in the transmission, reception and / or storage of the activation command information 215a, the access command information 215b, the data 215c, the data 225c and / or the CRC value 228.

[0055] Figure 3A 2 is a flow chart illustrating a read operation. The controller 210 issues an activation command. The activation command information ACT is transmitted to the memory 220 through the CA interface 231a. The controller 210 also couples ACT to the EDC calculation circuit system 222. The activation command information received through the CA interface 231b of the memory 220 may be damaged during transmission. Therefore, the activation command information received by the memory 220 is Figure 3A Memory 220 couples ACT' from CA interface 231b to EDC calculation circuitry 222.

[0056] After the activation command, the controller 210 issues a read command. The read command information RD is transmitted to the memory 220 through the CA interface 231a. The controller 210 also couples RD to the EDC calculation circuit system 222. The read command information received through the CA interface 231b of the memory 220 may be damaged during transmission. Therefore, the read command information received by the memory 220 is not received by the memory 220. Figure 3A Memory 220 couples RD′ from CA interface 231 b to EDC calculation circuitry 222 .

[0057] The EDC calculation circuitry 212 of the controller 210 calculates a first cyclic redundancy check (CRC) value based on ACT and calculates a second CRC value based on RD. Figure 3A Similarly, the EDC calculation circuit system 222 of the memory 220 calculates the third CRC value based on ACT' and calculates the fourth CRC value based on RD'. These are respectively shown in Figure 3A CRC(ACT') and CRC(RD') are shown in FIG. CRC(ACT) and CRC(RD) are coupled to EDC combining circuit system 213 through controller 210. CRC(ACT') and CRC(RD') are coupled to EDC combining circuit system 223 through memory 220.

[0058] Because the memory 220 performs a read operation, the memory 220 retrieves data DQ' from the memory core. The data retrieved by the memory 220 may be damaged. Therefore, the data retrieved by the memory 220 is Figure 3A The memory 220 couples DQ' to the DQ interface 232b and the EDC calculation circuit system 222. The EDC calculation circuit system 222 of the memory 220 calculates the fifth CRC value based on DQ'. Figure 3A The EDC combining circuit system 223 calculates a sixth CRC value based on CRC(ACT'), CRC(RD') and CRC(DQ'). Figure 3A It is illustrated as CRC (ACT', RD', DQ').

[0059] The memory 220 couples the CRC (ACT', RD', DQ') to the EDC interface 233b. The EDC interface 233b transmits the CRC (ACT', RD', DQ') to the controller 210. The CRC information received by the CA interface 231a of the controller 210 may be damaged during the transmission. Therefore, the CRC information received by the controller 210 is Figure 3A Controller 210 couples CRC'(ACT', RD', DQ') from EDC interface 233a to EDC comparison circuitry 214.

[0060] The DQ interface 232b transmits DQ' to the controller 210. The data received by the CA interface 231a of the controller 210 may be damaged during the transmission. Figure 3A The controller 210 couples DQ' from the CA interface 231a to the EDC calculation circuit system 212. The EDC calculation circuit system 212 of the controller 210 calculates the seventh CRC value based on DQ'. Figure 3A The EDC combining circuit system 213 calculates an eighth CRC value based on CRC(ACT), CRC(RD) and CRC(DQ"). This is shown in Figure 3A It is illustrated as CRC(ACT, RD, DQ”).

[0061] The EDC comparison circuit system 214 compares CRC'(ACT', RD', DQ') and CRC(ACT, RD, DQ") to determine whether the transmission or storage of data described herein is damaged, and signals the result to other circuit systems in the controller 210. In other words, if CRC'(ACT', RD', DQ') is equal to CRC(ACT, RD, DQ"), the EDC comparison circuit system 214 indicates to the controller 210 that no error has occurred. If CRC'(ACT', RD', DQ') is not equal to CRC(ACT, RD, DQ"), the EDC comparison circuit system 214 indicates to the controller 210 that an error has occurred.

[0062] Figure 3B 2 is a flowchart illustrating a write operation. The controller 210 issues an activation command. The activation command information ACT is transmitted to the memory 220 through the CA interface 231a. The controller 210 also couples ACT to the EDC calculation circuit system 222. The activation command information received through the CA interface 231b of the memory 220 may be damaged during transmission. Therefore, the activation command information received by the memory 220 is not received by the memory 220. Figure 3B Memory 220 couples ACT' from CA interface 231b to EDC calculation circuitry 222.

[0063] After the activation command, the controller 210 issues a write command. The write command information WR is transmitted to the memory 220 through the CA interface 231a. The controller 210 also couples WR to the EDC calculation circuit system 222. The write command information received through the CA interface 231b of the memory 220 may be damaged during the transmission. Therefore, the write command information received by the memory 220 is not received by the memory 220. Figure 3B Memory 220 couples WR′ from CA interface 231 b to EDC computation circuitry 222 .

[0064] The EDC calculation circuitry 212 of the controller 210 calculates a first cyclic redundancy check (CRC) value based on ACT and a second CRC value based on WR. Figure 3B Similarly, the EDC calculation circuit system 222 of the memory 220 calculates the third CRC value based on ACT' and calculates the fourth CRC value based on WR'. Figure 3B CRC(ACT') and CRC(WR') are respectively illustrated as CRC(ACT') and CRC(WR'). CRC(ACT) and CRC(WR') are coupled to EDC combining circuit system 213 through controller 210. CRC(ACT') and CRC(WR') are coupled to EDC combining circuit system 223 through memory 220.

[0065] Because the memory 220 performs a write operation, the controller 210 transmits the write data DQ to the memory 220 via the DQ interface 232a. The data received by the memory 220 may be damaged. Figure 3B 20 is illustrated as DQ'. The memory 220 couples DQ' to the EDC calculation circuit system 222. The EDC calculation circuit system 222 of the memory 220 calculates the fifth CRC value based on DQ'. Figure 3B The EDC combining circuit system 223 calculates a sixth CRC value based on CRC(ACT'), CRC(WR') and CRC(DQ'). Figure 3B It is illustrated as CRC (ACT', WR', DQ').

[0066] The memory 210 couples the CRC (ACT', WR', DQ') to the EDC interface 233b. The EDC interface 233b transmits the CRC (ACT', WR', DQ') to the controller 210. The CRC information received by the CA interface 231a of the controller 210 may be damaged during transmission. Therefore, the CRC information received by the controller 210 is Figure 3B Controller 210 couples CRC'(ACT', WR', DQ') from EDC interface 233a to EDC comparison circuitry 214.

[0067] The EDC calculation circuitry 212 of the controller 210 calculates a sixth CRC value based on DQ. Figure 3B EDC combining circuitry 213 calculates a seventh CRC value based on CRC(ACT), CRC(WR), and CRC(DQ). Figure 3B It is illustrated as CRC (ACT, WR, DQ).

[0068] EDC comparison circuitry 214 compares CRC'(ACT', WR', DQ') to CRC(ACT, WR, DQ) to determine whether the transmission or storage of data described herein is corrupted, and signals the result to other circuitry in controller 210. In other words, if CRC'(ACT', WR', DQ') is equal to CRC(ACT, WR, DQ), then EDC comparison circuitry 214 indicates to controller 210 that no error has occurred. If CRC'(ACT', WR', DQ') is not equal to CRC(ACT, WR, DQ), then EDC comparison circuitry 214 indicates to controller 210 that an error has occurred.

[0069] Figure 4 is a diagram illustrating controller actions performed for a read operation. Figure 4 , the controller 400 includes a register file (also referred to as a storage element) 411, an error detection code (EDC) calculation circuit system 412, an exclusive OR (XOR) 413, and an XOR 414. The register file 411 has a storage location corresponding to each memory bank address value, so that the register file 411 can read / write entries using a memory bank address and an index (also referred to as an address).

[0070] The controller 400 generates an activation command message 410. The activation command message 410 includes a bank address (BA) value 410a and a row address value (ROW) 410b. The activation command message 410 is transmitted to the memory component.

[0071] Arrow 451 illustrates that BA value 410a is provided to EDC calculation circuitry 412. Arrow 452 illustrates that row address value 410b is provided to EDC calculation circuitry 412. Based on BA value 410a and ROW value 410b, EDC calculation circuitry 412 generates a first CRC value CRC(0,0,0,BA,ROW). Arrow 453 illustrates that CRC(0,0,0,BA,ROW) is provided to and stored in register file 411 at a location determined (indexed) by bank address value 410a (as illustrated by arrow 451a).

[0072] Controller 400 generates read command information 420. Read command information 420 includes a bank address (BA) value 420a and a column address value (COL) 420b. Arrow 454 illustrates that BA value 420a is provided to EDC calculation circuitry 412. Arrow 455 illustrates that column address value 420b is provided to EDC calculation circuitry 412. Read command information 420 is transmitted to the memory component.

[0073] exist Figure 4 4, BA value 420a is equal to BA value 410a, so that BA value 420a can be used to retrieve CRC (0, 0, 0, BA, ROW) from position BA of register file 411. This is illustrated by arrow 454a, which is indexed to the same position in register file 411 as arrow 451a. Arrow 456 illustrates that the result of reading position BA from register file 411 (i.e., the stored value CRC (0, 0, 0, BA, ROW)) is provided to XOR 413.

[0074] Based on BA value 420 a and column address value 420 b , EDC calculation circuitry 412 generates a second CRC value CRC(0, BA, COL, 0, 0). Arrow 457 illustrates that CRC(0, BA, COL, 0, 0) is provided to XOR 413 .

[0075] Controller 400 receives data (DQ) in response to read command information 420 that has been transmitted to the memory component. Arrow 458 illustrates that the read data DQ is provided to EDC calculation circuit system 412. Based on the read data DQ, EDC calculation circuit system 412 generates a third CRC value CRC (DQ, 0, 0, 0, 0). Arrow 459 illustrates that CRC (DQ, 0, 0, 0, 0) is provided to XOR 413.

[0076] XOR 413 calculation Because the EDC calculation circuitry 412 generates an error detection code that has a relative The operation is linear in nature, so CRC(DQ, BA, COL, BA, ROW) is the expected CRC value, which will be equal to the memory calculated CRC value, CRC(DQ', BA', COL', BA', ROW') when no errors occur.

[0077] In response to the read command information 420 transmitted to the memory component, the controller 400 receives the memory calculated CRC value CRC(DQ', BA", COL', BA', ROW'). Arrow 470 illustrates that the memory calculated CRC value is provided to XOR414. The expected CRC value CRC(DQ, BA, COL, BA, ROW) is bitwise XORed with CRC(DQ', BA", COL', BA', ROW') by XOR 414. This XOR operation effectively performs a bitwise comparison of the two CRC values.

[0078] If the expected CRC value CRC(DQ, BA, COL, BA, ROW) is equal to the memory calculated CRC value CRC(DQ', BA", COL', BA', ROW'), then the output of XOR 414 indicates to the controller 410 that no error has occurred. If the expected CRC value CRC(DQ, BA, COL, BA, ROW) is not equal to the memory calculated CRC value CRC(DQ', BA", COL', BA', ROW'), then the output of XOR 414 indicates to the controller 410 that an error has occurred. This is Figure 4 This is illustrated by arrow 480 .

[0079] Figure 5 is a diagram illustrating memory component actions performed for a read operation. Figure 5 , the memory component 500 includes a register file (also referred to as a memory element) 511, an error detection code (EDC) calculation circuit system 512, an exclusive OR (XOR) 513, and a memory core 526. The register file 511 has a storage location corresponding to each memory bank address value, so that the register file 511 can read / write entries using a memory bank address and an index (also referred to as an address).

[0080] The memory component 500 receives an activate command message 510. The activate command message 510 may be received from, for example, the controller 400. The activate command message 510 includes a received bank address (BA') value 510a and a received row address (ROW') value 510b.

[0081] Arrow 551 illustrates that received BA' value 510a is provided to EDC calculation circuitry 512. Arrow 552 illustrates that received ROW' value 510b is provided to EDC calculation circuitry 512. Based on received BA' value 510a and received ROW' value 510b, EDC calculation circuitry 512 generates a first CRC value CRC(0,0,0,BA',ROW'). Arrow 553 illustrates that CRC(0,0,0,BA',ROW') is provided to and stored in register file 511 at a location determined (indexed) by received BA' value 510a (as illustrated by arrow 551a).

[0082] The memory component 500 receives read command information 520. The read command information 520 may be received from, for example, the controller 400. The read command information 520 includes a received second bank address (BA") value 520a and a received column address (COL') value 520b. Arrow 554 illustrates that the received BA' value 520a is provided to the EDC calculation circuit system 512. Arrow 555 illustrates that the received COL' value 520b is provided to the EDC calculation circuit system 512.

[0083] exist Figure 5 , BA" value 520a is equal to BA' value 510a, so that BA" value 520a can be used to retrieve CRC(0,0,0,BA',ROW') from position BA' of register file 511. This is illustrated by arrow 554a, which is indexed to the same position in register file 511 as arrow 551a. Arrow 556 illustrates that the result of reading position BA' from register file 511 (i.e., the stored value CRC(0,0,0,BA',ROW')) is provided to XOR 513.

[0084] Based on BA” value 520a and COL′ value 520b , EDC calculation circuitry 512 generates a second CRC value CRC(0, BA”, COL′, 0, 0). Arrow 557 illustrates that CRC(0, BA”, COL′, 0, 0) is provided to XOR 413 .

[0085] In response to the read command information 520 received by the memory component 500, the memory component 500 retrieves the read data from the memory core 526. Arrow 558 illustrates that the read data DQ' is provided to the EDC calculation circuit system 512. The read data DQ' is also transmitted to the controller (e.g., the controller 400). Figure 5 Based on the read data DQ′, the EDC calculation circuitry 512 generates a third CRC value CRC(DQ′, 0, 0, 0, 0). Arrow 559 illustrates that the CRC(DQ′, 0, 0, 0, 0) is provided to the XOR 513.

[0086] XOR 513 calculation Because the EDC calculation circuitry 512 generates an error detection code that has a relative The operation is linear in nature, so CRC(DQ', BA", COL', BA', ROW') is a CRC value that will be equal to the CRC value CRC(DQ, BA, COL, BA, ROW) calculated by the controller when no error occurs. The memory component 500 transmits the CRC value CRC(DQ', BA", COL', BA', ROW') calculated by the memory. This Figure 5 This is illustrated by arrow 570 .

[0087] Figure 6 is a diagram illustrating controller actions performed for a write operation. Figure 6 , the controller 600 includes a register file (also referred to as a memory element) 611, an error detection code (EDC) calculation circuit system 612, an exclusive OR (XOR) 613, and an XOR 614. The register file 611 has a storage location corresponding to each memory bank address value, so that the register file 611 can read / write entries using a memory bank address and an index (also referred to as an address).

[0088] The controller 600 generates an activation command message 610. The activation command message 610 includes a bank address (BA) value 610a and a row address value (ROW) 610b. The activation command message 610 is transmitted to the memory component.

[0089] Arrow 651 illustrates that BA value 610a is provided to EDC calculation circuitry 612. Arrow 652 illustrates that row address value 610b is provided to EDC calculation circuitry 612. Based on BA value 610a and ROW value 610b, EDC calculation circuitry 612 generates a first CRC value CRC(0,0,0,BA,ROW). Arrow 653 illustrates that CRC(0,0,0,BA,ROW) is provided to and stored in register file 611 at a location determined (indexed) by bank address value 610a (as illustrated by arrow 651a).

[0090] Controller 600 generates write command information 620. Write command information 620 includes a bank address (BA) value 620a and a column address value (COL) 620b. Arrow 654 illustrates that BA value 620a is provided to EDC calculation circuitry 612. Arrow 655 illustrates that column address value 620b is provided to EDC calculation circuitry 612. Write command information 620 is transmitted to the memory component.

[0091] exist Figure 6 , BA value 620a is equal to BA value 610a, so that BA value 620a can be used to retrieve CRC (0, 0, 0, BA, ROW) from position BA of register file 611. This is illustrated by arrow 654a, which is indexed to the same position in register file 611 as arrow 651a. Arrow 656 illustrates that the result of reading position BA from register file 611 (i.e., the stored value CRC (0, 0, 0, BA, ROW)) is provided to XOR 613.

[0092] Based on BA value 620 a and column address value 620 b , EDC calculation circuitry 612 generates a second CRC value CRC(0, BA, COL, 0, 0). Arrow 657 illustrates that CRC(0, BA, COL, 0, 0) is provided to XOR 613 .

[0093] As the controller 600 performs a write operation, the controller 600 provides write data (DQ) 658 (illustrated by arrow 658b) that is transmitted to the memory component. Arrow 658a illustrates that the write data DQ is provided to the EDC calculation circuit system 612. Based on the write data DQ, the EDC calculation circuit system 612 generates a third CRC value CRC (DQ, 0, 0, 0, 0). Arrow 659 illustrates that CRC (DQ, 0, 0, 0, 0) is provided to XOR 613.

[0094] XOR 613 calculation Because the EDC calculation circuit system 612 generates an error detection code, the error detection code has a relative The operation is linear in nature, so CRC(DQ, BA, COL, BA, ROW) is the expected CRC value, which will be equal to the memory calculated CRC value CRC(DQ', BA", COL', BA', ROW') when no error occurs.

[0095] In response to the write command information 620 and the data 658 transmitted to the memory component, the controller 600 receives the memory calculated CRC value CRC(DQ', BA", COL', BA', ROW'). Arrow 670 illustrates that the memory calculated CRC value is provided to XOR 614. The expected CRC value CRC(DQ, BA, COL, BA, ROW) is bitwise XORed with CRC(DQ', BA", COL', BA', ROW') by XOR 614. The XOR operation effectively performs a bitwise comparison of the two CRC values.

[0096] If the expected CRC value CRC(DQ, BA, COL, BA, ROW) is equal to the memory calculated CRC value CRC(DQ', BA", COL', BA', ROW'), then XOR 614 indicates to the controller 600 that no error has occurred. If the expected CRC value CRC(DQ, BA, COL, BA, ROW) is not equal to the memory calculated CRC value CRC CRC(DQ', BA", COL', BA', ROW'), then XOR 614 indicates to the controller 600 that an error has occurred. This is Figure 6 This is illustrated by arrow 680.

[0097] Figure 7 is a diagram illustrating the actions of memory components performed for a write operation. Figure 7 , the memory component 700 includes a register file (also referred to as a memory element) 711, an error detection code (EDC) calculation circuit system 712, an exclusive OR (XOR) 713, and a memory core 726. The register file 711 has a storage location corresponding to each memory bank address value, so that the register file 711 can read / write entries using a memory bank address and an index (also referred to as an address).

[0098] The memory component 700 receives an activate command message 710. The activate command message 710 may be received from, for example, the controller 600. The activate command message 710 includes a received bank address (BA') value 710a and a received row address (ROW') value 710b.

[0099] Arrow 751 illustrates that received BA' value 710a is provided to EDC calculation circuitry 712. Arrow 752 illustrates that received ROW' value 710b is provided to EDC calculation circuitry 712. Based on received BA' value 710a and received ROW' value 710b, EDC calculation circuitry 712 generates a first CRC value CRC(0,0,0,BA',ROW'). Arrow 753 illustrates that CRC(0,0,0,BA',ROW') is provided to and stored in register file 711 at a location determined (indexed) by received BA' value 710a (as illustrated by arrow 751a).

[0100] The memory component 700 receives write command information 720. The write command information 720 may be received from, for example, the controller 600. The write command information 720 includes a received second bank address (BA") value 720a and a received column address (COL') value 720b. Arrow 754 illustrates that the received BA" value 720a is provided to the EDC calculation circuit system 712. Arrow 755 illustrates that the received COL' value 720b is provided to the EDC calculation circuit system 712.

[0101] exist Figure 7 , BA" value 720a is equal to BA' value 710a so that BA" value 720a can be used to retrieve CRC(0,0,0,BA',ROW') from position BA' of register file 711. This is illustrated by arrow 754a, which is indexed to the same position in register file 711 as arrow 751a. Arrow 756 illustrates that the result of reading position BA' from register file 711 (i.e., the stored value CRC(0,0,0,BA',ROW')) is provided to XOR 713.

[0102] Based on BA” value 720a and COL′ value 720b , EDC calculation circuitry 712 generates a second CRC value CRC(0, BA”, COL’, 0, 0). Arrow 757 illustrates that CRC(0, BA”, COL’, 0, 0) is provided to XOR 713 .

[0103] Because the memory component 700 is controlled to perform a write operation, the memory component receives the write data DQ'. The memory component 700 stores the received write data DQ' in the memory core 726. Arrow 758 illustrates that the received write data DQ' is provided to the EDC calculation circuit system 712. Based on the received write data DQ', the EDC calculation circuit system 712 generates a third CRC value CRC (DQ', 0, 0, 0, 0). Arrow 759 illustrates that CRC (DQ', 0, 0, 0, 0) is provided to XOR713.

[0104] XOR 713 calculation Because the EDC calculation circuit system 712 generates an error detection code, the error detection code has a relative The operation is linear in nature, so CRC(DQ', BA", COL', BA', ROW') is a CRC value. When an error does not occur, the CRC value will be equal to the CRC value CRC(DQ, BA, COL, BA, ROW) calculated by the controller. The memory component 700 transmits the CRC value CRC(DQ', BA", COL', BA', ROW') calculated by the memory. This Figure 7 This is illustrated by arrow 770.

[0105] Figure 8 FIG. 1 is a diagram illustrating controller actions performed for a write operation to a memory component that checks an error detection code. Figure 8 , the controller 800 includes a register file (also referred to as a memory element) 811, an error detection code (EDC) calculation circuit system 812, an exclusive OR (XOR) 813, an XOR 814, an EDC transmitter 835, and an EDC receiver 836. The register file 811 has a storage location corresponding to each memory bank address value, so that the register file 811 can read / write entries using a memory bank address and an index (also referred to as an address).

[0106] The controller 800 generates an activation command message 810. The activation command message 810 includes a bank address (BA) value 810a and a row address value (ROW) 810b. The activation command message 810 is transmitted to the memory component.

[0107] Arrow 851 illustrates that BA value 810a is provided to EDC calculation circuitry 812. Arrow 852 illustrates that row address value 810b is provided to EDC calculation circuitry 812. Based on BA value 810a and ROW value 810b, EDC calculation circuitry 812 generates a first CRC value CRC(0,0,0,BA,ROW). Arrow 853 illustrates that CRC(0,0,0,BA,ROW) is provided to and stored in register file 811 at a location determined (indexed) by bank address value 810a (as illustrated by arrow 851a).

[0108] Controller 800 generates write command information 820. Write command information 820 includes a bank address (BA) value 820a and a column address value (COL) 820b. Arrow 854 illustrates that BA value 820a is provided to EDC calculation circuitry 812. Arrow 855 illustrates that column address value 820b is provided to EDC calculation circuitry 812. Write command information 820 is transmitted to the memory component.

[0109] exist Figure 8 8, BA value 820a is equal to BA value 810a, so that BA value 820a can be used to retrieve CRC (0, 0, 0, BA, ROW) from position BA of register file 811. This is illustrated by arrow 854a, which is indexed to the same position in register file 811 as arrow 851a. Arrow 856 illustrates that the result of reading position BA from register file 811 (i.e., the stored value CRC (0, 0, 0, BA, ROW)) is provided to XOR 813.

[0110] Based on BA value 820 a and column address value 820 b , EDC calculation circuitry 812 generates a second CRC value CRC(0, BA, COL, 0, 0). Arrow 857 illustrates that CRC(0, BA, COL, 0, 0) is provided to XOR 813 .

[0111] As the controller 800 performs a write operation, the controller 800 provides write data (DQ) 858, which is transmitted to the memory component (illustrated by arrow 858b). Arrow 858a illustrates that the write data DQ is provided to the EDC calculation circuit system 812. Based on the write data DQ, the EDC calculation circuit system 812 generates a third CRC value CRC (DQ, 0, 0, 0, 0). Arrow 859 illustrates that CRC (DQ, 0, 0, 0, 0) is provided to XOR 813.

[0112] XOR 813 calculation Since the EDC calculation circuit system 812 generates an error detection code, the error detection code has a relative The operation is linear in nature, so CRC(DQ, BA, COL, BA, ROW) is the expected CRC value, which will be equal to the memory calculated CRC value CRC(DQ', BA', COL', BA', ROW') when no error occurs.

[0113] The controller 800 uses a transmitter 835 to transmit a CRC value CRC(DQ, BA, COL, BA, ROW) calculated by the controller. Arrow 870 illustrates that the CRC value calculated by the controller is transmitted to the memory component. The controller 800 can receive a signal (e.g., ERR_WR) from the memory component that indicates whether the memory component has detected that an error has occurred. It should be understood that for a read operation, the controller 800 can receive a CRC value CRC(DQ', BA", COL', BA', ROW') calculated by the memory via a receiver 836.

[0114] Fig. 9 FIG. 1 is a diagram illustrating the actions of a memory component performed for a write operation and a check for an error detection code. Fig. 9 , the memory component 900 includes a register file (also referred to as a memory element) 911, an error detection code (EDC) calculation circuit system 912, an exclusive OR (XOR) 913, a memory core 926, a transmitter 935, and a receiver 936. The register file 911 has a storage location corresponding to each memory bank address value, so that the register file 911 can read / write entries using a memory bank address and an index (also referred to as an address).

[0115] The memory component 900 receives an activate command message 910. The activate command message 910 may be received from, for example, the controller 800. The activate command message 910 includes a received bank address (BA') value 910a and a received row address (ROW') value 910b.

[0116] Arrow 951 illustrates that received BA' value 910a is provided to EDC calculation circuitry 912. Arrow 952 illustrates that received ROW' value 910b is provided to EDC calculation circuitry 912. Based on received BA' value 910a and received ROW' value 910b, EDC calculation circuitry 912 generates a first CRC value CRC(0,0,0,BA',ROW'). Arrow 953 illustrates that CRC(0,0,0,BA',ROW') is provided to and stored in register file 911 at a location determined (indexed) by received BA' value 910a (as illustrated by arrow 951a).

[0117] The memory component 900 receives write command information 920. The write command information 920 may be received from, for example, the controller 800. The write command information 920 includes a received second bank address (BA") value 920a and a received column address (COL') value 920b. Arrow 954 illustrates that the received BA" value 920a is provided to the EDC calculation circuit system 912. Arrow 955 illustrates that the received COL' value 920b is provided to the EDC calculation circuit system 912.

[0118] exist Fig. 9 , BA" value 920a is equal to BA' value 910a, so that BA" value 920a can be used to retrieve CRC(0,0,0,BA',ROW') from position BA' of register file 911. This is illustrated by arrow 954a, which is indexed to the same position in register file 911 as arrow 951a. Arrow 956 illustrates that the result of reading position BA' from register file 911 (i.e., the stored value CRC(0,0,0,BA',ROW')) is provided to XOR 913.

[0119] Based on BA” value 920a and COL′ value 920b , EDC calculation circuitry 912 generates a second CRC value CRC(0, BA”, COL’, 0, 0). Arrow 957 illustrates that CRC(0, BA”, COL’, 0, 0) is provided to XOR 913 .

[0120] Because the memory component 900 is controlled to perform a write operation, the memory component receives the write data DQ'. The memory component 900 stores the received write data DQ' in the memory core 926. Arrow 958 illustrates that the received write data DQ' is provided to the EDC calculation circuit system 912. Based on the received write data DQ', the EDC calculation circuit system 912 generates a third CRC value CRC (DQ', 0, 0, 0, 0). Arrow 959 illustrates that CRC (DQ', 0, 0, 0, 0) is provided to XOR913.

[0121] XOR 913 calculation Because the EDC calculation circuit system 912 generates an error detection code, the error detection code has a relative The operation is linear in nature, so CRC(DQ', BA", COL', BA', ROW') is a CRC value that will be equal to the CRC value CRC(DQ, BA, COL, BA, ROW) calculated by the controller when no error occurs.

[0122] In response to the write command information 920 transmitted to the memory component, the memory component 900 receives the CRC value CRC(DQ, BA, COL, BA, ROW) calculated by the controller. Arrow 960 illustrates that the CRC value calculated by the controller is provided to the XOR 914 via the receiver 936. The received CRC value CRC(DQ, BA, COL, BA, ROW) is bitwise XORed with the expected CRC(DQ', BA", COL', BA', ROW') by the XOR 914. This XOR operation effectively performs a bitwise comparison of the two CRC values.

[0123] If the received CRC value CRC(DQ, BA, COL, BA, ROW) is equal to the expected calculated CRC value CRC(DQ', BA", COL', BA', ROW'), then XOR 914 indicates to the memory component 900 that no error has occurred. If the received CRC value CRC(DQ, BA, COL, BA, ROW) is not equal to the memory calculated CRC value CRC(DQ', BA", COL', BA', ROW'), then XOR 914 indicates to the memory component 900 that an error has occurred. This is Fig. 9 This is illustrated in the diagram by the signal ERR_WR. An indicator of whether an error has occurred can be sent to the controller. Fig. 9 This is illustrated by arrow 975.

[0124] In one embodiment, if XOR 914 indicates that an error has occurred, the memory component 900 aborts the write operation (i.e., does not store the write data to the memory core 926). By not performing a write operation when an error has been detected, the memory component avoids the possibility of writing (and thereby overwriting) data in a bank of the memory core 926 at an unintended (i.e., erroneous / corrupted) location.

[0125] Fig.10 is a diagram illustrating a memory system that checks an error detection code applied to command / address communications. Fig.10 , the memory system 1000 includes a controller 1010 and a memory component 1020. The controller 1010 includes a first-in-first-out (FIFO) buffer 1011, an error detection code (EDC) calculation circuit system 1012a, an EDC calculation circuit system 1012b, an exclusive OR (XOR) 1013, a selector (multiplexer-MUX) 1017, an error indicator 1019, a command / address (CA) interface 1031a, a data (DQ) interface 1032a, and a modulated error detection code (MEDC) interface 1033a.

[0126] The memory component 1020 includes an EDC calculation circuitry 1022a, an EDC calculation circuitry 1022b, an XOR 1023, a selector (MUX) 1027, a memory core (eg, a memory cell array) 1026, a CA interface 1031b, a DQ interface 1032b, and a MEDC interface 1033b.

[0127] The controller 1010 is operably coupled to the memory 1020 via a CA interface 1031a, which is coupled to a CA signal line 1031. The CA signal line 1031 (and the corresponding interface 1031a on the controller 1010 and the CA interface 1031b on the memory component 1020) may include X number of signal lines. In one embodiment, X=11. In one embodiment, the CA signal line 1031 may include one or more (e.g., 1) data bus inversion (DBI) signal lines. The controller 1010 is operably coupled to the memory 1020 to send commands and associated information (e.g., addresses) to the memory 1020 via the CA signal line 1031. The memory 1020 receives these commands (and associated information - such as addresses) via a CA interface 1031b, which is also coupled to the CA signal line 1031.

[0128] The controller 1010 is operably coupled to the memory 1020 via a DQ interface 1032a, which is coupled to a DQ signal line 1032. The DQ signal line 1032 (and the corresponding DQ interface 1032a on the controller 1010 and the DQ interface 1032b on the memory component 1020) may include a number of signal lines Y. In one embodiment, Y=18. In one embodiment, the DQ signal line 1032 may include one or more (e.g., 2) DBI signal lines. The controller 1010 and the memory component 1020 are operably coupled via the DQ signal line 1032 to transfer data bidirectionally. The memory 1020 may store (e.g., in the memory core 1026) and retrieve (e.g., from the memory core 1026) data transferred via the DQ interface 1032b and the DQ signal line 1032.

[0129] The memory 1020 is operably coupled to the controller 1010 via the MEDC interface 1033b, which is coupled to the MEDC signal line 1033. The MEDC signal line 1033 (and the corresponding MEDC interface 1033a on the controller 1010 and the EDC interface 1033b on the memory component 1020) may include a Z number of signal lines. In one embodiment, Z=2. In one embodiment, the EDC signal line 1033 may include one or more (e.g., 1) DBI signal lines. The memory 1020 is operably coupled to the controller 1010 to send error detection code information (e.g., EDC code bits) to the controller 1010 via the MEDC interface 1033b and the MEDC signal line 1033. The controller 1010 receives these MEDC bits via the MEDC interface 1033a and the MEDC signal line 1033.

[0130] In one embodiment, the controller 1010 sends command / address information (CA) 1015a via CA signal line 1031. The command / address information 1015a is also provided to the EDC calculation circuitry 1022a. The EDC calculation circuitry 1022a calculates a first error detection code value, which is stored in the FIFO buffer 1011. The FIFO buffer 1011 allows the controller 1010 to synchronize the first error detection code value with the receipt of a second error detection code value from the memory 1020 (e.g., through the interface 1033a).

[0131] The memory 1020 receives command / address information (CA') 1025a via CA signal line 1031. Typically, the received command / address information 1025a should be the same as the transmitted command / address information 1015a. However, the transmitted command / address information 1015a may have been corrupted when it is received by the memory 1020 as the received command / address information 1025a. The received command / address information 1025a is also provided to the EDC calculation circuit system 1022a. The EDC calculation circuit system 1022a calculates a second error detection code value. The second EDC value is provided to the XOR 1023.

[0132] Simultaneously with sending the command / address information 1015a, the controller 1010 may send or receive data 1015c via the DQ interface 1032a. The controller 1010 provides the data 1015c to the EDC calculation circuit system 1012b. The EDC calculation circuit system 1012b provides the third EDC value to the selector 1017. The selector 1017 selects between the output of the data EDC calculation circuit system 1012b and the held value 1015b. The output of the selector 1017 is provided to the XOR 1013. The output of the XOR 1013 is the error indicator 1019.

[0133] Similarly, simultaneously with receiving command / address information 1025a, memory 1020 may send or receive data 1025c via DQ interface 1032b. Memory 1020 provides data 1025c to EDC calculation circuit system 1022b. EDC calculation circuit system 1022b provides a fourth EDC value to selector 1027. Selector 1027 selects between the output of EDC calculation circuit system 1022b and hold value 1025b. The output of selector 1027 is provided to XOR 1023. The output of XOR 1023 is provided to MEDC interface 1033a.

[0134] The EDC calculation circuit system 1012a calculates the expected EDC code value (e.g., parity or CRC) based on the CA information 1015a sent to the memory 1020. The controller 1010 writes the expected EDC code value into the FIFO (queue) 1011. The FIFO 1011 has a depth that compensates for the round-trip delay of the controller 1010, the CA interface 1031a, the CA signal line 1031, the CA interface 1031b, the EDC calculation circuit system 1022a, the XOR 1023, the MEDC interface 1033b, the MEDC signal line 1033, and the MEDC interface 1033a.

[0135] The EDC calculation circuit system 1022a calculates the memory calculated EDC code value based on the received CA information 1025a. When data is not transferred via the DQ signal line 1032, the selector 1027 couples the hold pattern 1025b to the XOR 1023. When data is transferred via the DQ signal line 1032, the selector 1027 couples the data EDC code value calculated by the EDC calculation circuit system 1022b to the XOR 1023. Therefore, the CA information EDC code value calculated by the EDC calculation circuit system 1022a (through the operation of the XOR 1023) conditionally inverts (conditionally inverts) one or more bits of the output from the selector 1027 (i.e., the hold pattern 1025b or the data EDC value). The conditionally inverted (also referred to as modulated) output from the selector 1027 is transmitted by the memory 1020 to the controller 1010 via the MEDC signal line 1033. Because there is typically a delay between the receipt of CA information and the transmission of the corresponding data and data EDC value associated with the CA information, the CA information EDC code value modulates the data EDC value associated with the different CA information. In other words, the data EDC value associated with the first command / address is modulated by the CA information EDC code value associated with the second (and different) command.

[0136] When data is not transferred via DQ signal line 1032, selector 1017 couples hold pattern 1015b to XOR 1013. When data is transferred via DQ signal line 1032, selector 1017 couples the output of data EDC calculation circuit system 1012b to XOR 1013. Thus, the CA information EDC code value from FIFO 1011 effectively inverts one or more bits (by the operation of XOR 1013) of the output from selector 1017 (i.e., hold pattern 1025b or data EDC value from EDC calculation circuit system 1012b). If the CA information EDC code value from FIFO 1011 matches the corresponding CA information EDC code value calculated by EDC calculation circuit system 1022a, then XOR 1013 selectively inverts the output from selector 1017 in the same manner as XOR 1023 selectively inverts the bits from selector 1027. Thus, XOR 1013 compares the valid modulated bits with the modulated EDC value received from memory 1020. A mis-compare (non-zero) output from XOR 1013 indicates that an error has occurred in the command / address information transfer or the data transfer. When an error has occurred in the command / address information transfer or the data transfer, controller 1010 may take remedial action (e.g., retry one or more commands and / or retry one or more data / information transfers).

[0137] In one embodiment, CA interface 1031b receives command and address information from controller 1010. The command and address information includes a received first command. Data is transmitted to controller 1010 via DQ interface 1032b. The data transmitted to controller 1010 via DQ interface 1032b may be associated with a received second command. Error detection code (EDC) calculation circuit system 1022a calculates a first EDC value based on the received first command. EDC calculation circuit system 1022b calculates a second EDC value based on the data transmitted via DQ interface 1032b.

[0138] XOR 1023 calculates the EDC transfer value using a reversible function (ie, XOR) based on the first EDC value and the value selected by MUX 1027. MUX 1027 selects between the EDC value calculated by EDC calculation circuitry 1022b and held value 1025b. The EDC transfer value is transmitted to controller 1010 via MEDC interface 1033b.

[0139] In one embodiment, the received first command and the received second command transmit data via the DQ interface 1032b during different time allocations. The XOR 1023 may perform a bitwise exclusive OR of at least one, part, or all of the first EDC values ​​with the corresponding at least one, part, or all of the selected values. The hold value 1025b may be from a register. The MUX 1027 may select the hold value 1025b for commands that are not associated with transmitting data via the DQ interface 1032b.

[0140] In one embodiment, CA interface 1031a transmits command and address information to memory component 1020. The command and address information includes a first command. Data associated with a second command is transmitted via DQ interface 1032a. Error detection code (EDC) calculation circuit system 1012a calculates a first EDC value, the first EDC value being based on the command and address information. Error detection code (EDC) calculation circuit system 1012b calculates a second EDC value based on data associated with the second command transmitted via DQ interface 1032a. FIFO 1011 is used to store the first EDC value.

[0141] XOR 1013 calculates an expected EDC value using a reversible function (i.e., XOR) based on the first EDC value received from FIFO 1011 and the value selected by MUX 1017. MUX 1027 selects between the EDC value calculated by EDC calculation circuitry 1012b and the held value 1015b. MEDC interface 1033a receives the EDC transfer value calculated by memory component 1020. Based on the expected EDC value and the received EDC transfer value calculated by memory component 1020, XOR 1013 determines whether an error has occurred.

[0142] In one embodiment, the first command and the second command transmit data via the DQ interface 1032a during different time allocations. The XOR 1013 may perform a bitwise exclusive OR of at least one, some, or all of the expected EDC values ​​with the corresponding at least one, some, or all selected values. The hold value 1015b may originate from a register. The MUX 1017 may select the hold value 1015b for commands that are not associated with transmitting data via the DQ interface 1032a.

[0143] It should be appreciated that the selective application of a reversible function in generating an EDC transfer value is used to communicate information from the memory component 1020 to the controller 1010. Fig.10, at least some of the information communicated is a first EDC value (or parity) calculated by the memory component. When additional bits are available for "modulation" utilizing a reversible function (e.g., when some of the bits among all bits transmitted via MEDC interface 1033 are subjected to "modulation"), additional information may be communicated using these additional bits. For example, Figure 8 The ERR_WR signal 870 and / or Fig. 9 The ERR_WR signal 970 may be communicated by selectively applying a reversible function to one or more bits of a CRC value transmitted by the controller 800 and / or the memory component 900 .

[0144] Fig.11 is a flow diagram illustrating memory component access. Fig.11 The steps shown may be performed by one or more elements of memory system 100, memory system 200, memory component 500, memory component 700, memory component 900, and / or memory system 1000. An activate command and associated bank address and row address are received from a controller 1102. For example, memory component 500 may receive an activate command 510 (e.g., from controller 400) that includes a bank address BA' 510a and a row address ROW' 510b.

[0145] The memory bank address is associated with the stored activation command information (1104). For example, the memory component 500 may store in the register file 511 a CRC value calculated based on at least the BA' value 510a and the ROW' value 510b. The CRC value (e.g., CRC (BA', ROW')) may be stored in the entry corresponding to (e.g., indexed by) the memory bank address BA' value 510a in the register file 511. In this manner, the CRC value is associated with the BA' value 510a by virtue of the location at which the CRC value is stored in the register file 511. In another example, in the register file 511, the memory component 500 may store the ROW' value 510b in the entry corresponding to (e.g., indexed by) the memory bank address BA' value 510a in the register file 511. In another example, in register file 511, memory component 500 may store both BA' value 510a and ROW' value 510b in an entry in register file 511 that corresponds to (e.g., indexed by) bank address BA' value 510a. In the latter two examples, a CRC value (e.g., CRC(BA', ROW')) may be calculated based on the content stored at the location corresponding to BA' value 510a in register file 511.

[0146] An access command and associated bank address and column address are received from the controller (1106). For example, the memory component 500 may receive (e.g., from the controller 400) a read command 520 that includes a bank address BA' value 520a and a column address COL' value 520b. Data associated with the access command is transmitted to the controller (1108). For example, the memory component 500 may transmit data read from the memory core 526 to the controller 400. In another example, the memory component 500 may receive data to be stored in the memory core 526 from the controller 400.

[0147] A first EDC value based on the bank address and the row address is calculated (1110). For example, the EDC calculation circuitry 512 may calculate CRC (0, 0, 0, BA', ROW'). The EDC calculation circuitry 512 may calculate CRC (0, 0, 0, BA', ROW') based on BA' value 510a and / or ROW' value 510b received from the register file 511. The EDC calculation circuitry 512 may calculate CRC (0, 0, 0, BA', ROW') based on BA' value 510a and / or ROW' value 510b received from the controller 400. The memory component 500 may store the CRC (0, 0, 0, BA', ROW') in the register file 511, indexed by the BA' value 510a.

[0148] A second EDC value based on the bank address and the column address is calculated (1112). For example, the EDC calculation circuit system 512 can calculate CRC(0,BA", COL', 0,0) based on the BA" value 520a and the COL' value 520b received from the controller 400. A third EDC value is calculated based on the data transmitted with the controller (1114). For example, the EDC calculation circuit system 512 can calculate CRC(DQ', 0,0,0,0).

[0149] A fourth EDC value based on the first EDC value, the second EDC value, and the third EDC value is calculated (1116). For example, XOR 513 may calculate The fourth EDC value is transmitted to the controller (1118). For example, the memory component 500 may transmit the memory calculated CRC value CRC(DQ′, BA″, COL′, BA′, ROW′) to the controller 400.

[0150] Fig.12 is a flow chart illustrating a method of accessing a memory component. Fig.12The steps shown may be performed by one or more elements of the memory system 100, the memory system 200, the controller 400, the controller 600, the controller 800, and / or the memory system 1000. An activate command and associated bank address and row address are transmitted to a memory component 1202. For example, the controller 400 may transmit (e.g., to the memory component 500) an activate command 410 including a bank address BA 410a and a row address ROW 410b.

[0151] The memory bank address is associated with the stored activation command information (1204). For example, the controller 400 may store a CRC value calculated based on at least the BA value 410a and the ROW value 410b in the register file 411. The CRC value (e.g., CRC (BA, ROW)) may be stored in an entry in the register file 411 corresponding to (e.g., by its index) the memory bank address BA value 410a. In this way, the CRC value is associated with the BA value 410a by virtue of the location where the CRC value is stored in the register file 411. In another example, in the register file 411, the controller 400 may store the ROW value 410b in an entry in the register file 411 corresponding to (e.g., by its index) the memory bank address BA value 410a. In another example, in the register file 411, the controller 400 may store both the BA value 410a and the ROW value 410b in an entry in the register file 411 corresponding to (e.g., by its index) the memory bank address BA value 410a. In the latter two examples, a CRC value (eg, CRC(BA, ROW)) may be calculated based on the stored content at the location corresponding to BA value 410 a in register file 411 .

[0152] The access command and the associated bank address and column address are transmitted to the memory component (1206). For example, the controller 400 may transmit (e.g., to the memory component 500) a read command 420 that includes a bank address BA value 420a and a column address COL value 420b. Data associated with the access command is transmitted to the memory component (1208). For example, the memory component 500 may transmit data read from a memory core 526 of the memory component 500 to the controller 400. In another example, the controller 400 may provide the data to the memory component 500 for storage in the memory core 526.

[0153] A first EDC value based on the bank address and the row address is calculated (1210). For example, EDC calculation circuitry 412 may calculate CRC (0, 0, 0, BA, ROW). EDC calculation circuitry 412 may calculate CRC (0, 0, 0, BA, ROW) based on BA value 410a and / or ROW value 410b received from register file 411. EDC calculation circuitry 412 may calculate CRC (0, 0, 0, BA, ROW) based on BA value 410a and / or ROW value 410b received from other circuitry of controller 400. Controller 400 may store CRC (0, 0, 0, BA, ROW) in register file 411, indexed by BA value 410a.

[0154] A second EDC value based on the bank address and the column address is calculated (1212). For example, EDC calculation circuitry 412 may calculate CRC(0, BA, COL, 0, 0) based on BA value 420a and COL value 420b received from other circuitry of controller 400. A third EDC value is calculated (1214) based on data transmitted with the controller. For example, EDC calculation circuitry 412 may calculate CRC(DQ, 0, 0, 0, 0).

[0155] A fourth EDC value based on the first EDC value, the second EDC value, and the third EDC value is calculated (1216). For example, XOR 413 may calculate

[0156]

[0157] From the memory component, EDC information is received (1218). For example, the controller 400 may receive an EDC value CRC(DQ', BA", COL', BA', ROW') from the memory component 500. Based on the EDC information and the fourth EDC value, it is determined whether an error occurs (1220). For example, XOR 413 may compare the EDC value CRC(DQ', BA", COL', BA', ROW') received from the memory component 500 with the EDC value CRC(DQ, BA, COL, BA, ROW) calculated by the controller 400. If there is a difference between the CRC (DQ', BA", COL', BA', ROW') received from the memory component 500 and the EDC value CRC (DQ, BA, COL, BA, ROW) calculated by the controller 400, it indicates that an error has occurred. If there is no difference between the CRC (DQ', BA", COL', BA', ROW') received from the memory component 500 and the EDC value CRC (DQ, BA, COL, BA, ROW) calculated by the controller 400, it indicates that no (multiple) errors have occurred.

[0158] Fig.13 is a flow chart illustrating a method of determining whether an error occurs. Fig.13 The steps shown may be performed by one or more elements of memory system 100, memory system 200, memory component 500, memory component 700, memory component 900, and / or memory system 1000. An activate command and associated bank address and row address are received from a controller 1302. For example, memory component 900 may receive an activate command 910 (e.g., from controller 800) that includes a bank address BA' 910a and a row address ROW' 910b.

[0159] The memory bank address is associated with the stored activation command information (1304). For example, the memory component 900 may store a CRC value calculated based on at least the BA' value 910a and the ROW' 910b in the register file 911. The CRC value (e.g., CRC (BA', ROW')) may be stored in the entry in the register file 911 that corresponds to (e.g., indexed by) the memory bank address BA' value 910a. In this manner, the CRC value is associated with the BA' value 910a by virtue of the location at which the CRC value is stored in the register file 911. In another example, in the register file 911, the memory component 900 may store the ROW' value 910b in the entry in the register file 911 that corresponds to (e.g., indexed by) the memory bank address BA' value 910a. In another example, the memory component 900 may store both the BA' value 910a and the ROW' value 910b in an entry corresponding to (e.g., indexed by) the bank address BA' value 910a in the register file 911. In the latter two examples, a CRC value (e.g., CRC(BA', ROW')) may be calculated based on the content stored at the location corresponding to the BA' value 910a in the register file 911.

[0160] An access command and associated bank address and column address are received from the controller (1306). For example, the memory component 900 may receive a write command 920 (e.g., from the controller 800), the write command 920 including a bank address BA" value 920a and a column address COL' value 920b. Data associated with the access command is transmitted to the controller (1308). For example, the controller 800 may transmit data to be written to the memory core 926 to the memory component 900.

[0161] A first EDC value based on the bank address and the row address is calculated (1310). For example, the EDC calculation circuitry 912 may calculate CRC (0, 0, 0, BA', ROW'). The EDC calculation circuitry 912 may calculate CRC (0, 0, 0, BA', ROW') based on BA' value 910a and / or ROW' value 910b received from the register file 911. The EDC calculation circuitry 912 may calculate CRC (0, 0, 0, BA', ROW') based on BA' value 910a and / or ROW' value 910b received from the controller 800. The memory component 900 may store the CRC (0, 0, 0, BA', ROW') in the register file 911, indexed by the BA' value 910a.

[0162] A second EDC value based on the bank address and the column address is calculated (1312). For example, the EDC calculation circuit system 912 can calculate CRC (0, BA", COL', 0, 0) based on the BA" value 920a and the COL' value 920b received from the controller 800. A third EDC value is calculated (1314) based on the data transmitted with the controller. For example, the EDC calculation circuit system 912 can calculate CRC (DQ', 0, 0, 0, 0).

[0163] A fourth EDC value based on the first EDC value, the second EDC value, and the third EDC value is calculated (1316). For example, XOR 913 may be calculated

[0164] From the memory component, EDC information is received (1318). For example, the memory component 900 may receive an EDC value CRC(DQ, BA, COL, BA, ROW) from the controller 800. Based on the EDC information and the fourth EDC value, it is determined whether an error has occurred (1320). For example, XOR 913 may compare the EDC value CRC(DQ, BA, COL, BA, ROW) received from the controller 800 with the EDC value CRC(DQ', BA", COL', BA', ROW') calculated by the memory component 900. If there is a difference between the CRC(DQ, BA, COL, BA, ROW) received from the controller 800 and the EDC value CRC(DQ', BA", COL', BA', ROW') calculated by the memory component 900, it indicates that an error has occurred. If there is no difference between the CRC(DQ, BA, COL, BA, ROW) received from the controller 800 and the EDC value CRC(DQ', BA", COL', BA', ROW') calculated by the memory component 900, it indicates that no error(s) have occurred.

[0165] If an error is detected, the memory component 900 may abort the write command 920 and not write the received data to the memory core 926. If an error is detected, the memory component 900 may also signal the controller 800 that an error has occurred. If an error is detected, the memory component 900 may signal the controller 800 that the write command 920 is aborted. In response, the controller 800 may perform a remedial action. The remedial action may include retrying the write command 920.

[0166] Fig.14 is a flow chart illustrating a method of accessing a memory component. Fig.14 The steps shown may be performed by one or more elements of the memory system 100, the memory system 200, the controller 400, the controller 600, the controller 800, and / or the memory system 1000. An activate command and associated bank address and row address are transmitted to a memory component 1402. For example, the controller 800 may transmit (e.g., to the memory component 900) an activate command 810 including a bank address BA 810a and a row address ROW 810b.

[0167] The memory bank address is associated with the stored activation command information (1404). For example, the controller 800 may store a CRC value calculated based on at least the BA value 810a and the ROW value 810b in the register file 811. The CRC value (e.g., CRC (BA, ROW)) may be stored in the entry corresponding to (e.g., by its index) the memory bank address BA value 810a in the register file 811. In this way, the CRC value is associated with the BA value 810a by virtue of the location where the CRC value is stored in the register file 811. In another example, in the register file 811, the controller 800 may store the ROW value 810b in the entry corresponding to (e.g., by its index) the memory bank address BA value 810a in the register file 811. In another example, in the register file 811, the controller 800 may store both the BA value 810a and the ROW value 810b in the entry corresponding to (e.g., by its index) the memory bank address BA value 810a in the register file 811. In the latter two examples, a CRC value (eg, CRC(BA, ROW)) may be calculated based on the content stored at the location corresponding to BA value 810 a in register file 811 .

[0168] The access command and the associated bank address and column address are transmitted to the memory component (1406). For example, the controller 800 may transmit (e.g., to the memory component 900) a write command 820 that includes a bank address BA value 820a and a column address COL value 820b. Data associated with the access command is transmitted to the memory component (1408). For example, the controller 800 may transmit data to be written to the memory core 926 of the memory component 900 to the memory component 900.

[0169] A first EDC value based on the bank address and the row address is calculated (1410). For example, the EDC calculation circuitry 812 may calculate CRC (0, 0, 0, BA, ROW). The EDC calculation circuitry 812 may calculate CRC (0, 0, 0, BA, ROW) based on the BA value 810a and / or the ROW value 810b received from the register file 811. The EDC calculation circuitry 812 may calculate CRC (0, 0, 0, BA, ROW) based on the BA value 810a and / or the ROW value 810b received from other circuitry of the controller 800. The controller 800 may store the CRC (0, 0, 0, BA, ROW) in the register file 811, indexed by the BA value 810a.

[0170] A second EDC value based on the bank address and the column address is calculated (1412). For example, EDC calculation circuitry 812 may calculate CRC(0, BA, COL, 0, 0) based on BA value 820a and COL value 820b received from other circuitry of controller 800. A third EDC value is calculated (1414) based on data transmitted with the controller. For example, EDC calculation circuitry 812 may calculate CRC(DQ, 0, 0, 0, 0).

[0171] A fourth EDC value based on the first EDC value, the second EDC value, and the third EDC value is calculated (1416). For example, XOR 813 may calculate

[0172] The fourth EDC value is transmitted to the memory component ( 1418 ). For example, the controller 800 may transmit the CRC value CRC(DQ, BA, COL, BA, ROW) calculated by the controller to the memory component 900 .

[0173] Fig.15 is a flow chart illustrating a method of transmitting error detection information to a controller. Fig.15The steps shown may be performed by one or more elements of memory system 100, memory system 200, memory component 500, memory component 700, memory component 900, and / or memory system 1000. Command and address information including a received first command is received from a controller 1502. For example, memory component 1020 may receive the first command and associated address information via CA interface 1031b.

[0174] Data associated with the received second command is communicated to the controller (1504). For example, data 1025c associated with the second command (e.g., prior to the first command) may be communicated to the memory component 1020 via the DQ interface 1032b. A first EDC value is calculated based on address information associated with the received first command (1506). For example, a bank address, a row address, and / or a column address associated with the received first command may be input to the EDC calculation circuitry 1022a to calculate a parity or CRC value (a first EDC value).

[0175] The second EDC value is calculated based on the data associated with the received second command (1508). For example, data 1025c transmitted to / from the memory component 1020 via the DQ interface 1032b can be input to the EDC calculation circuit system 1022b to calculate a parity or CRC value (the second EDC value). The EDC transfer value is calculated using a reversible function that uses the first EDC value and a selected value as input, the selected EDC value provided from a set of sources, which can include providing the second EDC value (1510). For example, the MUX 1027 can select between the value provided by the EDC calculation circuit system 1022b and the held value 1025b.

[0176] In one embodiment, the reversible function comprises a bitwise XOR of one or more bits of the first EDC value with the corresponding one or more bits of the second EDC value. Other reversible functions are contemplated. A reversible function has an inverse function. An inverse function is a function that "reverses" another function: if function f applied to input x gives result y, then its inverse g applied to y will give result x, and vice versa. Many types of functions are reversible.

[0177] The EDC transfer value is transmitted to the controller (1512). For example, the memory component 1020 may transmit the EDC transfer value to the controller 1010 via the MEDC interface 1033b, the EDC transfer value having been "modulated" by the XOR 1023.

[0178] Fig.16is a flow chart illustrating a method of receiving error detection information from a memory component. Fig.16 The steps shown may be performed by one or more elements of memory system 100, memory system 200, controller 400, controller 600, controller 800, and / or memory system 1000. Command and address information including a received first command is transmitted to a memory component (1602). For example, controller 1010 may transmit the first command and associated address information via CA interface 1031a.

[0179] Data associated with the second command is transmitted to the memory component (1604). For example, data 1015c associated with the second command (e.g., before the first command) can be transmitted to / from the controller 1010 via the DQ interface 1032a. A first EDC value is calculated (1606) based on address information associated with the first command. For example, a bank address, a row address, and / or a column address associated with the first command can be input to the EDC calculation circuit system 1012a to calculate a parity or CRC value (a first EDC value).

[0180] The second EDC value is calculated based on the data associated with the received second command (1608). For example, data 1015c transmitted to / from the controller 1010 via the DQ interface 1032a can be input to the EDC calculation circuit system 1012b to calculate a parity or CRC value (the second EDC value). The expected EDC transmission value is calculated using a reversible function that uses as input the first EDC value and a selected value, the selected EDC value being provided from a set of sources that can include providing the second EDC value (1610). For example, the MUX 1017 can select between the value provided by the EDC calculation circuit system 1012b and the held value 1015b and provide the value to the XOR 1013, which will "modulate" the selected EDC value using the reversible function that uses as input the EDC value from the FIFO 1011.

[0181] From the memory component, the received EDC value is received (1612). For example, the controller 1010 may receive a "modulated" EDC value from the memory component 1020 via the MEDC interface 1033a. Based on the expected EDC value and the received EDC value, it is determined whether an error has occurred (1620). For example, the XOR 1013 may compare the received EDC value with the "modulated" EDC value to determine whether an error has occurred.

[0182] The above methods, systems and devices can be implemented in a computer system or stored by a computer system. The above methods can also be stored on a non-transitory computer-readable medium. The devices, circuit systems and systems described herein can be implemented using computer-aided design tools available in the art, and the devices, circuit systems and systems described herein can be embodied by computer-readable files containing software descriptions of such circuit systems. This includes but is not limited to one or more elements and components of the memory system 100, the memory system 200, the controller 400, the memory component 500, the controller 600, the memory component 700, the controller 800, the memory component 900 and / or the memory system 1000. These software descriptions can be: descriptions of behavior, register transfer, logic components, transistors and layout geometry levels. In addition, the software description can be stored on a storage medium or transmitted via a carrier wave.

[0183] Data formats that can implement such descriptions include, but are not limited to, formats that support behavioral languages ​​(e.g., C), formats that support register transfer level (RTL) languages ​​(e.g., Verilog and VHDL), formats that support geometric description languages ​​(e.g., GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfer of such files on machine-readable media can be performed electronically through various media on the Internet or, for example, via email. Please note that the physical file can be implemented on a machine-readable medium (e.g., 4 mm tape, 8 mm tape, 3-1 / 2 inch floppy disk media, CD, DVD, etc.).

[0184] Fig.17 17 is a block diagram illustrating one embodiment of a processing system 1700 for including, processing, or generating representations of circuit components 1720. Processing system 1700 includes one or more processors 1702, memory 1704, and one or more communication devices 1706. Processor 1702, memory 1704, and communication devices 1706 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1708.

[0185] Processor 1702 executes instructions of one or more processes 1712 stored in memory 1704 to process and / or generate circuit components 1720 in response to user input 1714 and parameters 1716. Process 1712 can be any suitable electronic design automation (EDA) tool or part thereof for designing, simulating, analyzing and / or verifying electronic circuit systems and / or generating photomasks for electronic circuit systems. Representation 1720 includes data describing all or part of memory system 100, memory system 200, controller 400, memory component 500, controller 600, memory component 700, controller 800, memory component 900, and / or memory system 1000 and their components as shown.

[0186] The representation 1720 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry level descriptions. In addition, the representation 1720 may be stored on a storage medium or transmitted via a carrier wave.

[0187] The data formats in which the representation 1720 may be implemented include, but are not limited to, formats supporting behavioral languages ​​(e.g., C), formats supporting register transfer level (RTL) languages ​​(e.g., Verilog and VHDL), formats supporting geometric description languages ​​(e.g., GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. In addition, data transfer of such files on machine-readable media may be accomplished electronically (e.g., via email) via a variety of media on the Internet.

[0188] User input 1714 may include input parameters from a keyboard, mouse, voice recognition interface, microphone and speaker, graphic display, touch screen, or other type of user interface device. The user interface may be distributed among multiple interface devices. Parameters 1716 may include specifications and / or characteristics that are input to help define representation 1720. For example, parameters 1716 may include information defining device type (e.g., NFET, PFET, etc.), topology (e.g., block diagram, circuit description, schematic, etc.), and / or device description (e.g., device properties, device size, supply voltage, simulation temperature, simulation model, etc.).

[0189] Memory 1704 includes any suitable type, number, and / or configuration of non-transitory computer-readable storage media that stores processes 1712 , user inputs 1714 , parameters 1716 , and circuit components 1720 .

[0190] The communication device 1706 includes any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from the processing system 1700 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, the communication device 1706 can transmit the circuit component 1720 to another system. The communication device 1706 can receive the process 1712, the user input 1714, the parameter 1716, and / or the circuit component 1720 and cause the process 1712, the user input 1714, the parameter 1716, and / or the circuit component 1720 to be stored in the memory 1704.

[0191] The foregoing description of the present invention has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed, and other modifications and variations are possible in light of the above teachings. The embodiments are selected and described in order to best explain the principles of the present invention and its practical application, so that other technical personnel in the field can best utilize the present invention in various embodiments and in various modifications suitable for conceivable specific uses. Unless limited by the prior art, it is intended that the attached claims be interpreted as including other alternative embodiments of the present invention.

Claims

1. A memory component, comprising: a first interface for receiving an activation command, an access command, and associated address information from a controller, wherein the activation command is associated with a first memory bank address value and a row address value, and the access command is associated with a second memory bank address value and a column address value, a second interface for transmitting data associated with the access command to the controller; an error detection code calculation circuit system for calculating a first error detection code value based on the first memory bank address value and the row address value, for calculating a second error detection code value based on the second memory bank address value and the column address value, and for calculating a third error detection code value based on data transmitted via the second interface; circuitry for associating the second bank address value with stored active command information, the stored active command information being based on the row address; code combining circuitry to calculate a fourth error detection code value based on the first error detection code value, the second error detection code value, and the third error detection code value; The third interface is used to transmit error detection information, and the error detection information includes the fourth error detection code value.

2. The memory component of claim 1, wherein the stored activate command information includes the first error detection code value. 3 . The memory component of claim 1 , wherein the stored active command information includes the row address value.

4. The memory component of claim 1 , wherein the error detection information will include the fourth error detection code value based at least in part on the memory component being in a first mode, and the error detection information will include the third error detection code value based at least in part on the memory component being in a second mode.

5. The memory component of claim 1, wherein the access command corresponds to a read operation and the data transferred via the second interface is to be retrieved from a memory bank of the memory component and to be communicated to the controller.

6. The memory component of claim 1, wherein the access command corresponds to a write operation and the data transmitted via the second interface is to be received from the controller and stored in a memory bank of the memory component.

7. The memory component of claim 1, wherein the error detection code calculation circuitry generates the error detection code value based on an error detection code encoding scheme, the error detection code encoding scheme being a linear function.

8. A memory component comprising: a first interface for receiving an activation command, a write command, and associated address information from a controller, wherein the activation command is associated with a first memory bank address value and a row address value, and the write command is associated with a second memory bank address value and a column address value, a second interface for receiving data associated with the write command from the controller; an error detection code calculation circuitry to calculate a first error detection code value based on the first bank address value and the row address value, and to calculate a second error detection code value based on the second bank address value and the column address value, and to calculate a third error detection code value based on the data associated with the write command; circuitry for associating the second bank address value with stored active command information, the stored active command information being based on the row address value; code combining circuitry to calculate a fourth error detection code value based on the first error detection code value, the second error detection code value, and the third error detection code value; a third interface, for receiving error detection information corresponding to the write command from the controller; as well as The error detection circuit system is used to determine whether an error has occurred based on the fourth error detection code value and the error detection information received from the controller.

9. The memory component of claim 8, wherein the stored activate command information includes the first error detection code value.

10. The memory component of claim 8, wherein the stored active command information includes the row address value.

11. The memory component of claim 8 , wherein based at least in part on the memory component being in a first mode, the third interface will receive the error detection information corresponding to the write command from the controller, and based at least in part on the memory component being in a second mode, the third interface will transmit error detection information calculated by the memory component, the error detection information calculated by the memory component will include the third error detection code value.

12. The memory component of claim 8, further comprising: The fourth interface is used to transmit an indicator of whether the error has occurred to the controller.

13. The memory component of claim 8, wherein if the error detection circuitry determines that an error has occurred, the data associated with the write command is not stored in a memory bank of the memory component.

14. The memory assembly of claim 8, further comprising: a fourth interface for transmitting an indicator that an error has occurred to the controller; Circuitry to prevent the data associated with the write command from being stored in a memory bank of the memory component in response to at least determining that the error has occurred.

15. The memory component of claim 8, further comprising: A storage element is used to store error information if the error detection circuit system determines that an error has occurred, the error information including at least one of the following: the second memory bank address, the row address, and the column address.

16. A memory component comprising: A first interface, for receiving a first command, a second command and associated address information from a controller; a second interface for transmitting data associated with the received second command to the controller; an error detection code calculation circuit system for calculating a first error detection code value based on the first command and calculating a second error detection code value based on data transmitted via the second interface; code modulation circuitry to calculate an error detection code transmission value using a reversible function based on the first error detection code value and a selected value to be provided by a source from a group of sources including the error detection code calculation circuitry that provides the second error detection code value; The third interface is used to transmit the error detection code transmission value to the controller.

17. The memory component of claim 16, wherein the first command and the second command transmit data via the second interface during different time allocations.

18. The memory component of claim 16, wherein the reversible function comprises a bitwise exclusive-OR of at least one bit of the first error detection code value and at least one bit of the selected value.

19. The memory component of claim 16, wherein the set of sources includes registers that provide held values.

20. The memory component of claim 19, wherein the retained value is selected for a command that is not associated with data being transmitted via the second interface.

Images