Display device

Abstract

A display device is disclosed. The display device includes: a substrate including a display area and a non-display area surrounding the display area; a transistor located on the substrate; an insulating layer located on the transistor; a power supply voltage line located on the insulating layer and transmitting a power supply voltage; a data line located on the insulating layer and transmitting a data voltage; and auxiliary wiring located in the display area between the substrate and the power supply voltage line. The auxiliary wiring includes portions overlapping the power supply voltage line and portions overlapping the data line, and is electrically connected to the power supply voltage line.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0055880, filed on May 13, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device. Background Technology

[0003] Light-emitting diode (LED) displays have attracted widespread attention as display devices. Unlike liquid crystal displays (LCDs), LED displays are self-emissive, eliminating the need for a light source. Therefore, LED displays can be manufactured to be thinner and lighter than LCD displays. Furthermore, LED displays possess many advantageous characteristics that contribute to high quality (such as low power consumption, high brightness, and high response speed).

[0004] Typically, a light-emitting diode (LED) display device includes transistors and light-emitting elements. The transistors and light-emitting elements can be connected to power supply lines used to transmit power supply voltages (such as drive voltage or common voltage) to receive drive voltage or common voltage. Depending on the area of ​​the display device, the level of the power supply voltage supplied to the display device and the resulting voltage drop may be uneven due to the resistance of the power supply lines. Therefore, display quality, such as brightness uniformity, may be degraded, and power consumption may increase.

[0005] It should be understood that this background section of the technical section is intended to provide useful context for understanding the technology. However, this background section of the technical section may also include ideas, concepts, or understandings that were not part of what is known or understood by a person skilled in the art prior to the corresponding valid filing date of the subject matter disclosed herein. Summary of the Invention

[0006] The embodiment provides a display device that can reduce wiring resistance and voltage drop.

[0007] An embodiment provides a display device comprising: a substrate including a display area and a non-display area surrounding the display area; a transistor disposed on the substrate; an insulating layer disposed on the transistor; a power supply voltage line disposed on the insulating layer and transmitting a power supply voltage; a data line disposed on the insulating layer and transmitting a data voltage; and auxiliary wiring disposed in the display area between the substrate and the power supply voltage line. The auxiliary wiring includes portions overlapping the power supply voltage line and portions overlapping the data line, and is electrically connected to the power supply voltage line.

[0008] The portions of auxiliary wiring that overlap with power supply voltage lines and the portions of auxiliary wiring that overlap with data lines can be overlapped in the plan view.

[0009] The power supply voltage line can be a drive voltage line that transmits the drive voltage or a common voltage line that transmits the common voltage.

[0010] The insulating layer can have multiple contact holes.

[0011] The display device may also include a buffer layer disposed on a substrate, wherein the buffer layer may include a plurality of contact holes.

[0012] The driving voltage line can be connected to the source or drain region of the transistor through a contact hole formed in the insulating layer, and can be connected to the auxiliary wiring through another contact hole formed in the insulating layer.

[0013] The display device may also include pixel electrodes electrically connected to transistors, and auxiliary wiring may include portions superimposed on the pixel electrodes in a plan view.

[0014] Auxiliary wiring may include portions that overlap with the drive voltage lines and portions that overlap with the common voltage lines in the plan view.

[0015] The power supply voltage line can be a drive voltage line, which is connected to the auxiliary wiring through contact holes formed in at least an insulating layer.

[0016] The auxiliary wiring can be placed on the same layer as the gate electrode of the transistor.

[0017] The display device may also include a connection pattern disposed between the insulating layer and the transistor, the connection pattern being electrically connected to the power supply voltage line and the source or drain region of the transistor, and auxiliary wiring being disposed on the same layer as the connection pattern.

[0018] Auxiliary wiring can be placed between the substrate and the transistor.

[0019] The display device may also include a lower pattern superimposed on the active pattern of the transistor, and auxiliary wiring may be disposed on the same layer as the lower pattern.

[0020] The lower pattern can be superimposed on the transistor's channel region between the transistor's channel region and the substrate.

[0021] The active pattern can be offset from the edge of the lower pattern.

[0022] The lower pattern can be electrically connected to the source or drain region of the transistor.

[0023] Power supply lines may include copper.

[0024] The display device may also include an upper contact member that can cover the power supply voltage line.

[0025] The display device may also include a buffer layer disposed between the transistor and the auxiliary wiring, and the buffer layer may be a multilayer comprising at least two layers.

[0026] Power supply voltage lines can be connected to auxiliary wiring through contact holes formed in the insulation and buffer layers.

[0027] An embodiment provides a display device comprising: a substrate including a display area and a non-display area surrounding the display area; a transistor disposed on the substrate; a power supply voltage line disposed on the transistor and transmitting a power supply voltage; a data line disposed on the transistor and transmitting a data voltage; an insulating layer disposed on the power supply voltage line; auxiliary wiring disposed on the insulating layer in the display area, including portions overlapping with the power supply voltage line and portions overlapping with the data line, and connected to the power supply voltage line through contact holes formed in the insulating layer; and a pixel electrode disposed on the auxiliary wiring and electrically connected to the transistor.

[0028] The portions of auxiliary wiring that overlap with power supply voltage lines and the portions of auxiliary wiring that overlap with data lines can be overlapped in the plan view.

[0029] The display device may further include: capacitor electrodes disposed on the same layer as the power supply voltage lines and electrically connected to the transistors; and contact members disposed between the capacitor electrodes and the pixel electrodes, and connected to the capacitor electrodes through contact holes formed in the insulating layer. Auxiliary wiring may be disposed on the same layer as the contact members.

[0030] The power supply voltage line can be a drive voltage line that transmits the drive voltage or a common voltage line that transmits the common voltage.

[0031] The display device may further include: a first contact member disposed on a common voltage line and connected to the common voltage line through a contact hole formed in an insulating layer; and a common electrode disposed on the first contact member and electrically connected to the first contact member. Auxiliary wiring may be disposed on the same layer as the first contact member.

[0032] The display device may further include a second contact member disposed between the first contact member and the common electrode and electrically connected to the first contact member and the common electrode.

[0033] Auxiliary wiring may include portions that overlap with pixel electrodes, portions that overlap with driving voltage lines, and portions that overlap with common voltage lines in a plan view.

[0034] The auxiliary wiring may include a first portion superimposed on the common voltage line and a second portion superimposed on the drive voltage line and pixel electrode in the plan view, and the first portion and the second portion may be separate from each other.

[0035] An embodiment provides a method for manufacturing a display device, the method comprising the steps of: forming a substrate; forming a first conductive layer on the substrate; forming an insulating layer on the first conductive layer; forming a transistor on the first conductive layer; forming an insulating layer on the transistor; and forming a second conductive layer on the insulating layer, the second conductive layer including auxiliary wiring formed in the same process as a scan line or a horizontal initialization voltage line or a horizontal drive voltage line or a gate electrode or a drive gate electrode.

[0036] An embodiment provides a display device comprising: a substrate including a display area and a non-display area surrounding the display area; a transistor disposed on the substrate; an insulating layer disposed on the transistor; driving voltage lines disposed on the insulating layer; and auxiliary wiring disposed in the display area between the substrate and the driving voltage lines, wherein each of the driving voltage lines is connected to a corresponding one of the auxiliary wirings through a contact hole in the insulating layer.

[0037] According to embodiments, the resistance of wiring (e.g., power supply voltage lines such as drive voltage lines and common voltage lines) and the voltage drop of the power supply voltage transmitted through the power supply voltage lines can be reduced. This can improve display quality and reduce power supply voltage margin, thereby reducing power consumption. It can also reduce delays in signals such as data signals. Attached Figure Description

[0038] An additional understanding of the embodiments of the invention will become clearer by referring to the accompanying drawings, which describe the embodiments in detail, wherein:

[0039] Figure 1 A layout diagram of a display device according to an embodiment is shown;

[0040] Figure 2 A circuit diagram of pixels of a display device according to an embodiment is shown;

[0041] Figure 3 A layout diagram of the pixel region of a display device according to an embodiment is shown;

[0042] Figure 4 The following is shown according to the embodiment. Figure 3 A schematic cross-sectional view taken by line A-A';

[0043] Figure 5 The following is shown according to the embodiment. Figure 3 A schematic cross-sectional view taken by line B-B';

[0044] Figure 6 and Figure 7 Each shows the path along according to the embodiment Figure 3 A schematic cross-sectional view taken by line C-C';

[0045] Figure 8 and Figure 9 Each shows the path along according to the embodiment Figure 3 A schematic cross-sectional view taken by line A-A';

[0046] Figure 10 A layout diagram of the pixel region of a display device according to an embodiment is shown;

[0047] Figure 11 The following is shown according to the embodiment. Figure 10 A schematic cross-sectional view taken by line D-D';

[0048] Figure 12 The following is shown according to the embodiment. Figure 10 A schematic cross-sectional view taken by line E-E';

[0049] Figure 13 A layout diagram of the pixel region of a display device according to an embodiment is shown;

[0050] Figure 14 A layout diagram of the pixel region of a display device according to an embodiment is shown;

[0051] Figure 15 The following is shown according to the embodiment. Figure 14 A schematic cross-sectional view taken by line F-F';

[0052] Figure 16 A layout diagram of the pixel region of a display device according to an embodiment is shown;

[0053] Figure 17 The following is shown according to the embodiment. Figure 16 A schematic cross-sectional view taken along line G-G'; and

[0054] Figure 18 A layout diagram of the pixel region of a display device according to an embodiment is shown. Detailed Implementation

[0055] Embodiments of the invention will be described below with reference to the accompanying drawings.

[0056] Although the invention may be modified in various ways and has additional embodiments, the embodiments are shown in the accompanying drawings and will be described primarily in the specification. However, the scope of the invention is not limited to the embodiments shown in the drawings and specification, and should be construed as including all changes, equivalents, and substitutions included within the spirit and scope of the invention.

[0057] In order to describe embodiments of the invention, some parts that are not related to the description may be omitted, and the same reference numerals denote the same elements throughout the specification.

[0058] In the accompanying drawings, the dimensions and thicknesses of the elements shown may be enlarged for clarity and ease of description. However, the invention is not limited to the dimensions and thicknesses illustrated. The thicknesses of layers, films, panels, regions, and other elements may be exaggerated in the accompanying drawings for clarity. The thicknesses of some layers and regions may be exaggerated in the accompanying drawings for better understanding and ease of description.

[0059] Furthermore, in the instruction manual, the phrase "in a plan view" refers to the view of the target portion from above, while the phrase "in a sectional view" refers to the view of the target portion as a section taken by vertically cutting it from the side.

[0060] When a layer, film, region, substrate, or area is referred to as being "on" another layer, film, region, substrate, or area, the layer, film, region, substrate, or area may be directly on the other layer, film, region, substrate, or area, or an intermediate layer, film, region, substrate, or area may exist between them. Conversely, when a layer, film, region, substrate, or area is referred to as being "directly on" another layer, film, region, substrate, or area, an intermediate layer, film, region, substrate, or area may not exist between them. Furthermore, when a layer, film, region, substrate, or area is referred to as being "below" another layer, film, region, substrate, or area, the layer, film, region, substrate, or area may be directly below the other layer, film, region, substrate, or area, or an intermediate layer, film, region, substrate, or area may exist between them. Conversely, when a layer, film, region, substrate, or area is referred to as being "directly below" another layer, film, region, substrate, or area, an intermediate layer, film, region, substrate, or area may not exist between them. Furthermore, "above" or "on" can include being positioned on or below a target and does not necessarily imply a direction based on gravity.

[0061] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or component and another element or component as shown in the figures. It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device shown in the figures is flipped, a device positioned “below” or “under” another device may be placed “above” said other device. Therefore, the exemplary term “below” can include both an upper and lower position. The device may also be positioned in other orientations, and thus, spatial relative terms may be interpreted differently depending on the orientation.

[0062] Throughout this specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to the other element or “electrically connected” to the other element, with one or more intermediate elements inserted between them. It will also be understood that when the terms “comprising,” “including,” and / or variations thereof are used in this specification, they or may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combinations thereof.

[0063] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another for ease of description and interpretation. For example, without departing from this teaching, when discussing a “first element” in a description, it may be named a “second element” or a “third element,” and “second element” and “third element” may be named in a similar manner.

[0064] As used herein, “about” or “approximately” includes the stated value and means: within an acceptable deviation of the stated value, taking into account the measurement mentioned and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system), as determined by a person of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±5% of the stated value.

[0065] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms (such as those defined in a general dictionary) should be interpreted as having the same meaning as they have in the context of the relevant field and will not be interpreted in an idealized or overly formalized sense unless clearly defined in the specification. In the accompanying drawings, the reference numeral x for indicating direction is a first direction, y is a second direction perpendicular to the first direction, and z is a third direction perpendicular to both the first and second directions. The first direction x, the second direction y, and the third direction z may correspond to the horizontal, vertical, and thickness directions of the display device, respectively. It should be noted that these first, second, and third directions may be substantially horizontal, vertical, and thickness directions.

[0066] In the following description, a display device (a light-emitting display device as an example) according to an embodiment will be described with reference to the accompanying drawings.

[0067] Figure 1 A layout diagram of a display device according to an embodiment is shown.

[0068] The display device 1 may include a display panel 10, a flexible printed circuit film 20, a printed circuit board (PCB) 40, etc.

[0069] The display panel 10 may include a display area DA and a non-display area NA corresponding to the screen on which the image is displayed. Wiring and / or circuitry for generating and / or transmitting various signals and voltages applied to the display area DA may be disposed in the non-display area NA. The non-display area NA may surround the display area DA.

[0070] Pixels PX can be arranged in a matrix, for example, within the display area DA of the display panel 10. Data lines 171 for transmitting data signals, drive voltage lines 172 for transmitting drive voltage ELVDD, common voltage lines 170 for transmitting common voltage ELVSS, and initialization voltage lines 173 and 153 for transmitting initialization voltages can be provided. Each pixel PX can receive data signals, drive voltage ELVDD, common voltage ELVSS, and initialization voltage from these respective wirings. Here, drive voltage ELVDD and common voltage ELVSS are power supply voltages applied to the corresponding pixel PX, and drive voltage lines 172 and common voltage lines 170 for transmitting voltages are referred to as power supply voltage lines. Drive voltage ELVDD can be a voltage with a potential higher than that of common voltage ELVSS.

[0071] A gate driver (not shown) can be disposed on the opposite side of the display area DA in the non-display area NA of the display panel 10. Pixel PX can receive scan signals generated by the gate driver and receive data signals according to a predetermined timing sequence.

[0072] The drive voltage transmission line DVL connected to the drive voltage line 172 and the common voltage transmission line CVL connected to the common voltage line 170 can be disposed in the non-display area NA of the display panel 10. Each of the drive voltage transmission line DVL and the common voltage transmission line CVL may include a portion extending substantially in the second direction y and a portion extending substantially in the first direction x.

[0073] As used herein, the term "part" may include a portion or partial area of ​​a whole region of an element, a segment or fragment of an element, or a predetermined quantity of an element, or any other definition as will be understood and appreciated by one of ordinary skill in the art.

[0074] The flexible printed circuit film 20 may have a first end bonded to the display panel 10 and a second end bonded to the printed circuit board 40. A data driver 30 for applying data voltage to the data line 171 may be disposed in the flexible printed circuit film 20 and may be configured as an integrated circuit chip.

[0075] A power supply module 50 that generates power supply voltages such as drive voltage ELVDD or common voltage ELVSS can be disposed in a printed circuit board 40. The power supply module 50 can be configured as an integrated circuit chip. A signal controller for controlling the data driver 30 and the gate driver can be disposed in the printed circuit board 40.

[0076] The construction of the display device according to the embodiments has now been described. The display device according to the embodiments will now be described in more detail.

[0077] Figure 2 A schematic diagram of the equivalent circuit of a pixel of a display device according to an embodiment is shown.

[0078] Reference Figure 2 A pixel PX may include transistors T1, T2 and T3, capacitor Cst and light-emitting diode ED.

[0079] Transistors T1, T2, and T3 may include a first transistor T1, a second transistor T2, and a third transistor T3. The source and drain electrodes, described later, are used to distinguish two electrodes located on opposite sides of the channel in each of transistors T1, T2, and T3, and they are interchangeable.

[0080] The first transistor T1 may include a gate electrode G1, a source electrode S1, and a drain electrode D1. The gate electrode G1 may be connected to the first electrode C1 of the capacitor Cst, the source electrode S1 may be connected to the drive voltage line 172 for receiving the drive voltage ELVDD, and the drain electrode D1 may be connected to the anode of the light-emitting diode ED and the second electrode C2 of the capacitor Cst. The first transistor T1 can receive the data voltage DAT according to the switching operation of the second transistor T2, store the data voltage DAT in the capacitor Cst, and supply drive current to the light-emitting diode ED according to the stored voltage.

[0081] The second transistor T2 may include a gate electrode G2, a source electrode S2, and a drain electrode D2. The gate electrode G2 may be connected to a first scan line for transmitting the first scan signal SC, the source electrode S2 may be connected to a data line 171 capable of transmitting the data voltage DAT or a reference voltage, and the drain electrode D2 may be connected to the gate electrode G1 and the first electrode C1 of the capacitor Cst. The second transistor T2 may be turned on according to the first scan signal SC to transmit the reference voltage or data voltage DAT to the gate electrode G1 and the first electrode C1 of the capacitor Cst.

[0082] The third transistor T3 may include a gate electrode G3, a source electrode S3, and a drain electrode D3. The gate electrode G3 may be connected to a second scan line for transmitting the second scan signal SS. The source electrode S3 may be connected to the second electrode C2 of capacitor Cst, the drain electrode D1, and the anode. The drain electrode D3 may be connected to an initialization voltage line 173 carrying the initialization voltage INIT. The third transistor T3 may be turned on in response to the second scan signal SS to initialize the anode voltage by transmitting the initialization voltage INIT to the anode and the second electrode C2 of capacitor Cst.

[0083] The first electrode C1 of capacitor Cst can be connected to the gate electrode G1 of the first transistor T1, and the second electrode C2 of capacitor Cst can be connected to the source electrode S3 and the anode. The cathode of light-emitting diode ED can be connected to the common voltage line 170 used to transmit the common voltage ELVSS.

[0084] A light-emitting diode (ED) can emit light with a brightness (grayscale) that depends on the drive current generated by the first transistor T1.

[0085] For operations within a single frame, we will use an example where transistors T1, T2, and T3 are all N-channel transistors. Figure 2 An example of the operation of the circuit is shown in the figure.

[0086] At the start of a frame, a high-level first scan signal SC and a high-level second scan signal SS are supplied during the initialization period, and the second transistor T2 and the third transistor T3 are turned on. The reference voltage from data line 171 is supplied to the gate electrode G1 and the first electrode C1 of capacitor Cst through the turned-on second transistor T2, and the initialization voltage INIT is supplied to the drain electrode D1 and the anode through the turned-on third transistor T3. During the initialization period, the drain electrode D1 and the anode are initialized to the initialization voltage INIT. The voltage difference between the reference voltage and the initialization voltage INIT is stored in capacitor Cst.

[0087] When the second scan signal SS is changed to a low level while the first scan signal SC is held at a high level during the sensing period, the second transistor T2 remains on and the third transistor T3 is off. The gate electrode G1 and the first electrode C1 of capacitor Cst maintain the reference voltage through the on-state second transistor T2, while the drain electrode D1 and anode are disconnected from the initialization voltage INIT through the off-state third transistor T3. When the voltage at the gate electrode G1 becomes "reference voltage -V",... th Simultaneously, when current flows from the source electrode S1 to the drain electrode D1, the first transistor T1 is turned off. thThis represents the threshold voltage of the first transistor T1. The voltage difference between the gate electrode G1 and the drain electrode D1 is stored in the capacitor Cst, and this constitutes the threshold voltage (V) of the first transistor T1. th The sensing of the first transistor T1 may have different characteristics for each pixel PX. The deviation can be compensated by generating a data signal, which reflects the characteristic information sensed during the sensing period.

[0088] When a high-level first scan signal SC and a low-level second scan signal SS are supplied during the data input period, the second transistor T2 is turned on and the third transistor T3 is turned off. The data voltage DAT from data line 171 is supplied to the gate electrode G1 and the first electrode C1 of capacitor Cst through the turned-on second transistor T2. The drain electrode D1 and anode can be maintained at approximately the same potential as the potential during the sensing period through the turned-off first transistor T1.

[0089] During the light-emitting period, the first transistor T1, which is turned on by the data voltage DAT transmitted to the gate electrode G1, generates a drive current according to the data voltage DAT, and the drive current allows the light-emitting diode ED to emit light.

[0090] In the following text, reference will be made to Figures 3 to 6 The detailed structure of the display device according to the embodiment is described.

[0091] Figure 3 A layout diagram of the pixel region of a display device according to an embodiment is shown. Figure 4 It is according to the embodiment along Figure 3 A schematic cross-sectional view taken by line A-A'. Figure 5 The following is shown according to the embodiment. Figure 3 A schematic cross-sectional view taken by line B-B'. Figure 6 The following is shown according to the embodiment. Figure 3 A schematic cross-sectional view taken by line C-C'. Figure 3 The planar structure of three adjacent pixels PX1, PX2, and PX3 is shown. Each of pixels PX1, PX2, and PX3 may include a corresponding constituent element; therefore, the reference numerals for the constituent element of one of pixels PX1, PX2, and PX3 can be similarly applied to the corresponding constituent elements of the remaining pixels.

[0092] The display device 1 according to an embodiment includes a substrate 110. The substrate 110 may be made of an insulating material such as glass or plastic, or other suitable insulating material.

[0093] A first conductive layer, including a lower pattern 111, may be disposed on the substrate 110. The lower pattern may also be referred to as a conductive pattern. The first conductive layer may comprise a conductive material such as a metal or metal alloy. The thickness of the lower pattern 111 may range from about several hundred angstroms to about several thousand angstroms.

[0094] A buffer layer 120, which can serve as an insulating layer, may be disposed on the first conductive layer. As described later, the buffer layer 120 may include a first layer 120a and a second layer 120b. The first layer 120a and / or the second layer 120b may include organic insulating materials or inorganic insulating materials.

[0095] An active layer including active patterns 130a, 130b, and 130c can be disposed on buffer layer 120. A first conductive layer can be disposed between substrate 110 and the active layer. The active patterns 130a, 130b, and 130c disposed at each of pixels PX1, PX2, and PX3 can include channel regions 134a, 134b, and 134c forming respective channels of transistors T1, T2, and T3, and conductive regions connected to channel regions 134a, 134b, and 134c. The conductive regions of active patterns 130a, 130b, and 130c can respectively include source regions 133a, 133b, and 133c of transistors T1, T2, and T3, and drain regions 135a, 135b, and 135c.

[0096] In each of pixels PX1, PX2, and PX3, active patterns 130a and 130c can be connected to or separated from each other. Figure 3 An example is shown in which active patterns 130a and 130c are connected to each other. The drain region 135a of active pattern 130a can be the source region 133c of active pattern 130c.

[0097] The active layer may include, for example, semiconductor materials such as oxide semiconductors, polycrystalline silicon, and amorphous silicon. The thickness of the active layer may be smaller than the thickness of the underlying pattern 111, and may be approximately several hundred angstroms.

[0098] Insulating patterns 144 and 145, serving as the first insulating layer, can be disposed on the active layer. Insulating pattern 144 can be superimposed on the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c, and can be disposed on the channel regions 134a, 134b, and 134c. Insulating pattern 144 may not substantially superimpose on the conductive regions of the active patterns 130a, 130b, and 130c. Insulating pattern 145 can be superimposed on auxiliary wirings ALa, ALb, and ALc.

[0099] The term “overlay” can include stacking, overlapping, facing or confronting, extending over, covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. When an element is described as “not overlaying” another element or “not overlapping” another element, this can include elements separated from each other, offset from each other, or separated from each other, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art.

[0100] The second conductive layer can be disposed on the first insulating layer. The second conductive layer may include a first scan line 151 capable of transmitting the first scan signal SC, a second scan line 152 capable of transmitting the second scan signal SS, a horizontal initialization voltage line 153 capable of transmitting the initialization voltage INIT, a horizontal drive voltage line 172h capable of transmitting the drive voltage ELVDD, a drive gate electrode 155, a second gate electrode 154b, a third gate electrode 154c, and auxiliary wiring ALa, ALb, and ALc. Figure 3 In the diagram, the shaded areas correspond to the regions where auxiliary wiring ALa, ALb, and ALc can be formed. The constituent components included in the second conductive layer can be formed in the same layer using the same process. Therefore, manufacturing costs can be reduced. Figure 2 In the circuit diagram, gate electrodes G1, G2, and G3 can correspond to the first gate electrode 154a, the second gate electrode 154b, and the third gate electrode 154c included in the driving gate electrode 155.

[0101] Each of the first scan line 151, the second scan line 152, the horizontal initialization voltage line 153, and the horizontal drive voltage line 172h can extend substantially in the first direction x.

[0102] The driving gate electrode 155 can be disposed between the first scan line 151 and the second scan line 152.

[0103] The second gate electrode 154b may be separated from the first scan line 151 and may extend substantially in the second direction y. The second gate electrode 154b may be directly connected to the first scan line 151.

[0104] The third gate electrode 154c can be separated from the second scan line 152 and can extend substantially in the second direction y. The third gate electrode 154c can be directly connected to the second scan line 152.

[0105] The driving gate electrode 155 disposed in each of pixels PX1, PX2 and PX3 may include an upwardly projecting protrusion 155a and a downwardly projecting first gate electrode 154a that extends substantially in the second direction y.

[0106] The first gate electrode 154a intersects with the active pattern 130a and is superimposed on the channel region 134a of the active pattern 130a. The second gate electrode 154b intersects with the active pattern 130b and is superimposed on the channel region 134b of the active pattern 130b. The third gate electrode 154c intersects with the active pattern 130c and is superimposed on the channel region 134c of the active pattern 130c.

[0107] The auxiliary wirings ALa, ALb, and ALc can be disposed in areas of the second conductive layer where no other constituent elements (i.e., the first scan line 151, the second scan line 152, the horizontal initialization voltage line 153, the horizontal drive voltage line 172h, the drive gate electrode 155, the second gate electrode 154b, and the third gate electrode 154c) are formed. The auxiliary wirings ALa, ALb, and ALc can be electrically connected to power supply voltage lines such as drive voltage lines 172a, 172b, and 172c, and the common voltage line 170, thereby reducing the resistance of the power supply voltage lines.

[0108] Each of the auxiliary wirings ALa, ALb, and ALc may extend substantially in the second direction y. Each of the auxiliary wirings ALa, ALb, and ALc may include a portion superimposed on pixel electrodes 191a, 191b, and 191c in pixels PX1, PX2, and PX3. Each of the auxiliary wirings ALa, ALb, and ALc may include a portion superimposed on drive voltage lines 172a, 172b, and 172c, common voltage line 170, and / or data lines 171a, 171b, and 171c. In the embodiment shown, auxiliary wiring ALa is superimposed on drive voltage line 172a and common voltage line 170, auxiliary wiring ALb is superimposed on drive voltage line 172b and data line 171a, and auxiliary wiring ALc is superimposed on drive voltage line 172c and data line 171b. Auxiliary wirings ALa, ALb, and ALc may not be superimposed on active patterns 130a, 130b, and 130c.

[0109] The second insulating layer 160 may be disposed on the second conductive layer. The second insulating layer 160 may cover transistors T1, T2, and T3. The buffer layer 120 and / or the second insulating layer 160 may include contact holes 24, 26, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, and 60'. As described later, the second insulating layer 160 may be formed of a multilayer comprising at least a first layer 160a and a second layer 160b, wherein the first layer 160a and / or the second layer 160b may comprise organic or inorganic insulating materials.

[0110] The third conductive layer may be disposed on the second insulating layer 160. The third conductive layer may include data lines 171a, 171b and 171c, drive voltage lines 172a, 172b and 172c, common voltage line 170, initialization voltage line 173, capacitor electrode 175, and connecting members 174, 176, 177 and 178.

[0111] Each of the data lines 171a, 171b and 171c, the drive voltage lines 172a, 172b and 172c, the common voltage line 170 and the initialization voltage line 173 may extend substantially in the second direction y and may intersect with the first scan line 151 and the second scan line 152.

[0112] Figure 3 The set of pixels PX1, PX2, and PX3 shown can be arranged substantially adjacent to each other in the first direction x, and can be repeatedly arranged in the first direction x and the second direction y. For example, common voltage lines 170 can be provided to the left and right of the set of pixels PX1, PX2, and PX3. When the three pixels PX1, PX2, and PX3 are repeatedly included in a set, three data lines 171a, 171b, and 171c, three drive voltage lines 172a, 172b, and 172c, and at least one initialization voltage line 173 can be provided between two common voltage lines 170, which can be substantially adjacent in the first direction x.

[0113] Each of the data cables 171a, 171b and 171c can be connected to the source region 133b of the active pattern 130b through the contact hole 64 of the second insulating layer 160.

[0114] Driving voltage lines 172a, 172b, and 172c can be disposed in pixels PX1, PX2, and PX3, respectively. Each of the driving voltage lines 172a, 172b, and 172c can extend substantially in the second direction y.

[0115] Drive voltage lines 172a, 172b, and 172c can be connected to the source region 133a of the active pattern 130a through contact holes 61 of the second insulating layer 160. Drive voltage lines 172a, 172b, and 172c can be connected to the horizontal drive voltage line 172h through contact holes 60 of the second insulating layer 160. The horizontal drive voltage line 172h can transmit the drive voltage ELVDD together with the drive voltage lines 172a, 172b, and 172c. The horizontal drive voltage line 172h and the drive voltage lines 172a, 172b, and 172c can be connected in a grid pattern throughout the display device 1.

[0116] The driving voltage lines 172a, 172b, and 172c can be connected to their respective auxiliary wirings ALa, ALb, and ALc through the contact holes 60' of the second insulating layer 160. In other words, each of the driving voltage lines 172a, 172b, and 172c can be connected to a corresponding auxiliary wiring ALa, ALb, and ALc through a corresponding contact hole 60' in the second insulating layer 160. For example, Figure 5 A drive voltage line 172a is shown connected to the auxiliary wiring ALa via a contact hole 60' in the second insulating layer 160. The resistance of drive voltage lines 172a, 172b, and 172c can be reduced, and the voltage drop of the drive voltage ELVDD transmitted through drive voltage lines 172a, 172b, and 172c can be reduced. The auxiliary wiring ALa can be stacked with the common voltage line 170 as shown, but it can also be de-stacked. The common voltage line 170 can be connected to the auxiliary wiring ALa via a contact hole formed in the second insulating layer 160.

[0117] Initialization voltage line 173 can be connected to horizontal initialization voltage line 153 through contact hole 69 of second insulating layer 160. Horizontal initialization voltage line 153 can transmit initialization voltage INIT together with initialization voltage line 173. Even when one initialization voltage line 173 is set for each of three pixels PX1, PX2, and PX3, initialization voltage INIT can be transmitted to all three pixels PX1, PX2, and PX3 through horizontal initialization voltage line 153. The three pixels PX1, PX2, and PX3 can simultaneously receive initialization voltage INIT through horizontal initialization voltage line 153 and can form a pixel group.

[0118] A capacitor electrode 175 can be provided for each of pixels PX1, PX2, and PX3. The capacitor electrode 175 can be stacked with a corresponding drive gate electrode 155, and a second insulating layer 160 is located between them to form a capacitor Cst. Figure 2 The first electrode C1 and the second electrode C2 of the capacitor Cst can correspond to the driving gate electrode 155 and the capacitor electrode 175, respectively.

[0119] The capacitor electrode 175 may include a downwardly extending protrusion 175a. The protrusion 175a can be connected, for example, through a contact hole 62 in the second insulating layer 160. Figure 4 The drain region 135a of the active pattern 130a or the source region 133c of the active pattern 130c are shown in the diagram. The capacitor electrode 175 can be, for example, as shown in the diagram. Figure 4 The contact hole 68 shown in the diagram, through the buffer layer 120 and the second insulating layer 160, connects to the lower pattern 111. The lower pattern 111 can be electrically connected to the drain region 135a or the source region 133c.

[0120] The connecting member 174 can be electrically connected to the second scan line 152 and the third gate electrode 154c through the contact hole 24 of the second insulating layer 160, so as to electrically connect the second scan line 152 and the third gate electrode 154c.

[0121] The connecting member 176 can be electrically connected to the first scan line 151 and the second gate electrode 154b through the contact hole 26 of the second insulating layer 160.

[0122] The connecting member 177 can be connected to the drain region 135c of the active pattern 130c through contact holes 63 in each of pixels PX1, PX2, and PX3 of the second insulating layer 160, and to the horizontal initialization voltage line 153 through contact holes 67 of the second insulating layer 160. The drain region 135c of the active pattern 130c can be electrically connected to the horizontal initialization voltage line 153.

[0123] The horizontal initialization voltage line 153 may extend substantially in the first direction x, intersecting with three pixels PX1, PX2, and PX3. The horizontal initialization voltage line 153 may be positioned between two adjacent common voltage lines 170, and may not intersect with the two common voltage lines 170. The horizontal initialization voltage line 153 may intersect with three adjacent data lines 171a, 171b, and 171c, and may extend only to the initialization voltage line 173. As another example, the horizontal initialization voltage line 153 may intersect with three adjacent data lines 171a, 171b, and 171c, and may only extend to the initialization voltage line 173.

[0124] The connecting member 178 can be connected to the drain region 135b of the active pattern 130b through contact holes 65 in each of pixels PX1, PX2, and PX3 of the second insulating layer 160, and can be connected to the protrusion 155a of the drive gate electrode 155 through contact holes 66 of the second insulating layer 160. The connecting member 178 can electrically connect the drain region 135b of the active pattern 130b to the protrusion 155a of the drive gate electrode 155.

[0125] Each of the first, second, and third conductive layers may comprise a metal or alloy thereof such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta). Each of the first, second, and third conductive layers may have a single-layer or multi-layer structure as understood by those skilled in the art.

[0126] The first transistor T1 includes a channel region 134a, a source region 133a, a drain region 135a, and a first gate electrode 154a. Since the source region 133a of the first transistor T1 is electrically connected to the drive voltage lines 172a, 172b, and 172c, a drive voltage ELVDD can be applied to it.

[0127] For example, such as Figure 4 As shown, the lower pattern 111 corresponding to the first transistor T1 can be formed to overlap the channel region 134a of the first transistor T1 between the channel region 134a and the substrate 110, thereby blocking external light from entering the channel region 134a and reducing the leakage current and characteristic degradation of the first transistor T1. The lower pattern 111 can be electrically connected to the drain region 135a of the first transistor T1 through the capacitor electrode 175.

[0128] For example, Figure 4 As shown, the lower pattern 111 can be completely superimposed on the active pattern 130a, and can be superimposed on all of the source region 133a, channel region 134a, and drain region 135a of the first transistor T1. The region forming the active pattern 130a can be located in the region forming the lower pattern 111. Since the active pattern 130a does not intersect with the edge of the lower pattern 111, defects such as breaks in the active pattern 130a near the edge of the lower pattern 111 can be prevented. As those skilled in the art will understand and appreciate, the active pattern 130a near the edge of the lower pattern 111 may be thicker than the active pattern 130a and may form relatively large steps. This improves the layout efficiency near the lower pattern 111 and the active pattern 130a.

[0129] The lower pattern 111 can be electrically connected to the pixel electrodes 191a, 191b, and 191c via capacitor electrodes 175 to overlap with the channel region 134a of the first transistor T1. This reduces the rate of change of current in the saturation region of the voltage-current characteristic curve, thus expanding the range of regions where the output current of the first transistor T1 can remain constant. Even when the source-drain voltage (V) of the first transistor T1... ds Even when the output current of the first transistor T1 changes, it can remain constant, thereby improving output saturation characteristics. This can reduce the brightness deviation between pixels depending on the output current of the first transistor T1, thus improving image quality.

[0130] The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 can be electrically connected to data lines 171a, 171b, and 171c to receive a data voltage DAT or a reference voltage. The drain region 135b of the second transistor T2 can be electrically connected to the first gate electrode 154a via a drive gate electrode 155.

[0131] The third transistor T3 includes a channel region 134c, a source region 133c, a drain region 135c, and a third gate electrode 154c. The drain region 135c of the third transistor T3 can receive the initialization voltage INIT from the horizontal initialization voltage line 153.

[0132] The third insulating layer 181 may be disposed on the second insulating layer 160 and the third conductive layer. The third insulating layer 181 may include, for example, Figure 5 The contact hole 83a, which is superimposed on the capacitor electrode 175, is shown in the figure. Figure 3 The contact hole 81 is shown overlapping with the common voltage line 170.

[0133] A fourth conductive layer, including contact members 190a, 190b, 190c and 190d, may be disposed on the third insulating layer 181.

[0134] Contact members 190a, 190b and 190c can be disposed in pixels PX1, PX2 and PX3 respectively, and can contact and be electrically connected to capacitor electrode 175 through contact hole 83a.

[0135] like Figure 6 As shown, for example, contact member 190d can contact and be electrically connected to common voltage line 170 through contact hole 81.

[0136] Contact members 190a, 190b, 190c, and 190d can improve the adhesion between the capacitor electrode 175 of the third conductive layer and the common voltage line 170 and other conductive layers, and can prevent oxidation of the third conductive layer. For example, when the upper layer of the third conductive layer contains copper, oxidation of the copper can be prevented. The fourth conductive layer can contain a conductive material capable of preventing corrosion of the upper layer of the third conductive layer. For example, when the upper layer of the third conductive layer contains copper, the fourth conductive layer can contain a conductive material that can prevent copper corrosion by covering the upper layer of the third conductive layer. The fourth conductive layer can include conductive materials such as metal oxides, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or other suitable materials as will be appreciated and understood by those skilled in the art.

[0137] A fourth insulating layer 182 may be disposed on the third insulating layer 181 and the fourth conductive layer. The fourth insulating layer 182 may be disposed on contact members 190a, 190b, 190c, and 190d, and may have a contact hole 83b overlapping with the contact hole 83a. For example, Figure 5 A fourth insulating layer 182 is shown disposed on the contact member 190a and having a contact hole 83b overlapping with the contact hole 83a.

[0138] At least one of the buffer layer 120, the first insulating layer, the second insulating layer 160, the third insulating layer 181, and the fourth insulating layer 182 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x Inorganic insulating materials such as silicon oxynitride (SiON) and / or organic insulating materials. For example, the fourth insulating layer 182 may include inorganic insulating materials and / or organic insulating materials such as polyimide, acrylic polymers, siloxane polymers, etc., and may have a substantially flat upper surface.

[0139] The pixel electrode layer 191, including pixel electrodes 191a, 191b, and 191c, can be disposed as a fifth conductive layer on the fourth insulating layer 182. Pixel electrodes 191a, 191b, and 191c can be disposed in the respective pixels PX1, PX2, and PX3. The pixel electrodes 191a, 191b, and 191c disposed at the three pixels PX1, PX2, and PX3 can differ in size and shape. Pixel PX1 can represent red, pixel PX2 can represent green, and pixel PX3 can represent blue. Pixels PX1, PX2, and PX3 are not limited to the aforementioned colors and can be any of red, green, and blue. The area emitting light from each of pixels PX1, PX2, and PX3 can be substantially smaller than the area of ​​pixel electrodes 191a, 191b, and 191c. Each of pixel electrodes 191a, 191b, and 191c may include a portion superimposed with auxiliary wirings ALa, ALb, and ALc.

[0140] Pixel electrodes 191a, 191b, and 191c can contact corresponding contact members 190a, 190b, and 190c respectively through contact holes 83b in the fourth insulating layer 182, and can be electrically connected to capacitor electrode 175 through contact members 190a, 190b, and 190c. Each of pixel electrodes 191a, 191b, and 191c can be electrically connected to the drain region 135a of the first transistor T1 to receive voltage from the first transistor T1.

[0141] The pixel electrode layer 191 may include a transmissive-reflective conductive material or a reflective conductive material. The transmissive-reflective conductive material or the reflective conductive material may include any such material as will be understood and appreciated by those skilled in the art.

[0142] The fifth insulating layer 350 may be disposed on the fourth insulating layer 182. The fifth insulating layer 350 may have openings 355 disposed on the pixel electrodes 191a, 191b, and 191c. The fifth insulating layer 350 may comprise an organic insulating material such as a polyacrylic resin or a polyimide resin.

[0143] The light-emitting layer 370 can be disposed on the fifth insulating layer 350 and the pixel electrode layer 191. The light-emitting layer 370 may include components disposed on, for example, such as... Figure 4 The portion of the fifth insulating layer 350 shown is within the opening 355. The light-emitting layer 370 may comprise an organic or inorganic emitting material. At least a portion of the fifth insulating layer 350 may not be, for example, as... Figure 4 The light-emitting layer 370 shown in the figure covers the area.

[0144] For example, Figure 6 As shown, the fifth insulating layer 350 and the light-emitting layer 370 may include contact holes 82 stacked with the contact member 190d.

[0145] The common electrode 270 can be disposed on the light-emitting layer 370. The common electrode 270 can be formed continuously across pixels PX1, PX2, and PX3. For example... Figure 6 As shown, the common electrode 270 can contact the contact member 190d through the contact hole 82 to be electrically connected to the common voltage line 170 to receive the common voltage ELVSS.

[0146] The common electrode 270 may include a conductive transparent material.

[0147] The pixel electrodes 191a, 191b, and 191c of each pixel PX1, PX2, and PX3, the light-emitting layer 370, and the common electrode 270 together constitute a light-emitting diode (ED). One of the pixel electrodes 191a, 191b, and 191c and the common electrode 270 serves as the anode, and the other serves as the cathode.

[0148] A sealing substrate (not shown) for sealing the light-emitting diode ED can be disposed on the common electrode 270, and a color filter (not shown) corresponding to each of the pixels PX1, PX2 and PX3 can be disposed in the sealing substrate.

[0149] Reference Figure 7 The display device according to the embodiments described above is illustrated in the accompanying drawings.

[0150] Figure 7 The following is shown according to the embodiment. Figure 3 A schematic cross-sectional view taken by line C-C'.

[0151] In addition to the fourth insulating layer 182 including a contact hole 81a located on the contact member 190d, and the pixel electrode layer 191 including a contact member 191d that contacts the contact member 190d through the contact hole 81a, Figure 7The embodiments described above are mostly similar. The fifth insulating layer 350 and the light-emitting layer 370 may include contact holes 82a stacked with the contact member 191d. The common electrode 270 can contact the contact member 191d through the contact holes 82a to be electrically connected to the common voltage line 170 to receive the common voltage ELVSS.

[0152] Reference Figure 8 and Figure 9 The display device according to the embodiments described above is illustrated in the accompanying drawings.

[0153] Figure 8 and Figure 9 Each shows the path along according to the embodiment Figure 3 A schematic cross-sectional view taken by line A-A'.

[0154] Apart from Figure 8 The embodiments may include a sixth insulating layer 122 disposed on the second conductive layer and an outer layer of the sixth conductive layer disposed between the sixth insulating layer 122 and the second insulating layer 160. Figure 8 The embodiments are mostly similar to those described above.

[0155] The sixth insulating layer 122 can contact the upper surface of the conductive areas of the active patterns 130a, 130b and 130c. The sixth insulating layer 122 may include a contact hole 61a corresponding to and overlapping the contact hole 61 of the second insulating layer 160, and may include contact holes 62a and 68a.

[0156] exist Figure 8 In some embodiments, a capacitor electrode 157 disposed in the sixth conductive layer may be included instead of the capacitor electrode 175 described above. The capacitor electrode 157 may be connected to the lower pattern 111 via a contact hole 68a, and may be connected to the drain region 135a of the active pattern 130a via a contact hole 62a.

[0157] The capacitor electrode 157 may have a planar shape similar to that of the capacitor electrode 175 described above. The capacitor electrode 157 may be stacked with the corresponding drive gate electrode 155, and the sixth insulating layer 122 is located between them to form the capacitor Cst.

[0158] The sixth conductive layer may include a connection pattern 163. The connection pattern 163 may contact the source region 133a of the active pattern 130a through the contact hole 61a of the sixth insulating layer 122. The drive voltage line 172a may contact the connection pattern 163 through the contact hole 61 of the second insulating layer 160 and be electrically connected to the connection pattern 163, thereby electrically connecting to the source region 133a of the active pattern 130a.

[0159] exist Figure 8In some embodiments, the sixth conductive layer may include auxiliary wirings ALa, ALb, and ALc that may be included in the second conductive layer described above. For example, the auxiliary wirings ALa, ALb, and ALc may be disposed in areas of the sixth conductive layer where no other constituent elements (i.e., capacitor electrode 157 and connection pattern 163) are formed besides the auxiliary wirings ALa, ALb, and ALc. At least one of the auxiliary wirings ALa, ALb, and ALc may be connected to the connection pattern 163 to be formed continuously with the connection pattern 163. The capacitor electrode 157, the connection pattern 163, and the auxiliary wirings ALa, ALb, and ALc, as constituent elements included in the sixth conductive layer, may be formed in the same layer using the same process.

[0160] Apart from Figure 9 The embodiments may include a seventh insulating layer 180 disposed between the third conductive layer and the third insulating layer 181, and a seventh conductive layer disposed outside the seventh insulating layer 180 and the third insulating layer 181. Figure 9 The embodiments are mostly similar to those described above.

[0161] The seventh conductive layer may include conductive patterns extending parallel to and electrically connected to the data lines 171a, 171b, and 171c, drive voltage lines 172a, 172b, and 172c, common voltage line 170, initialization voltage line 173, etc., of the third conductive layer. For example, the seventh conductive layer may include conductive patterns 183 and 185 electrically connected to the drive voltage line 172a and the common voltage line 170, respectively, through contact holes in the seventh insulating layer 180. Conductive patterns 183 and 185 can transmit the same voltage as the constituent elements of the third conductive layer connected thereto, thereby reducing voltage drop.

[0162] When the display device 1 includes a seventh conductive layer, the third conductive layer may include some of the data lines 171a, 171b and 171c, driving voltage lines 172a, 172b and 172c, common voltage line 170, initialization voltage line 173, capacitor electrode 175 and connecting members 174, 176, 177 and 178 that may be included in the third conductive layer in the above embodiments. The seventh conductive layer may include other of the above-mentioned elements, such as conductive patterns 183 and 185.

[0163] In the following description, the display device according to some embodiments will be described mainly with respect to the differences from the embodiments described above.

[0164] Figure 10 A layout diagram of the pixel region of a display device according to an embodiment is shown. Figure 11 The following is shown according to the embodiment. Figure 10 A schematic cross-sectional view taken by line D-D'. Figure 12The following is shown according to the embodiment. Figure 10 A schematic cross-sectional view taken from line E-E'.

[0165] Reference Figure 10 , Figure 11 and Figure 12 The fourth conductive layer may include auxiliary wiring AL together with contact members 190a, 190b, 190c, and 190d. Figure 10 In the diagram, the shaded area corresponds to the area where auxiliary wiring AL can be formed. Auxiliary wiring AL can be provided separately from contact members 190a, 190b, 190c, and 190d in areas where contact members 190a, 190b, 190c, and 190d are not formed, for example, Figure 12 An auxiliary wiring AL is shown, disposed separately from contact member 190d in an area where no contact member 190d is formed. The auxiliary wiring AL can be separate from contact members 190a, 190b, 190c, and 190d. The auxiliary wiring AL can be formed in the same layer using the same process as that used for contact members 190a, 190b, 190c, and 190d.

[0166] The auxiliary wiring AL can be formed continuously across multiple groups of pixels PX1, PX2, and PX3. The auxiliary wiring AL can be formed individually for each group of pixels PX1, PX2, and PX3, or for each of pixels PX1, PX2, and PX3. The auxiliary wiring AL may include portions overlapping with data lines 171a, 171b, and 171c, and as well as... Figure 11 The portion shown overlaps with the common voltage line 170 and with the drive voltage lines 172a, 172b, and 172c. The auxiliary wiring AL can be connected to the drive voltage lines 172a, 172b, and 172c through the contact hole 80' of the third insulating layer 181. Figure 11 An auxiliary wiring AL is shown connected to the drive voltage line 172a through a contact hole 80' formed in the third insulating layer 181. Although not shown, the auxiliary wiring AL can be connected to the common voltage line 170 through a contact hole formed in the third insulating layer 181. In the region of a set of pixels PX1, PX2, and PX3, the auxiliary wiring AL is divided into at least two parts, wherein a first part can be electrically connected to the drive voltage lines (e.g., 172b and 172c), and a second part can be electrically connected to the common voltage line 170. As described above, the auxiliary wiring AL can be electrically connected to power supply voltage lines (such as drive voltage lines 172a, 172b, and 172c and the common voltage line 170) to reduce the resistance of the power supply voltage lines and the voltage drop of the power supply voltage transmitted through the power supply voltage lines.

[0167] Reference Figure 13The auxiliary wiring AL can be formed not to overlap with at least a portion of the first scan line 151 to reduce the capacitance that may form between the auxiliary wiring AL and the first scan line 151. For similar reasons, the auxiliary wiring AL can be formed not to overlap with at least a portion of the second scan line 152. The auxiliary wiring AL can have an opening OP1 overlapping with the first scan line 151 and / or an opening OP2 overlapping with the second scan line 152.

[0168] Figure 14 A layout diagram of the pixel region of a display device according to an embodiment is shown. Figure 15 The following is shown according to the embodiment. Figure 14 A schematic cross-sectional view taken by line F-F'.

[0169] Reference Figure 14 and Figure 15 ,and Figures 10 to 12 Similar to the embodiments, in which the fourth conductive layer includes auxiliary wiring AL together with contact members 190a, 190b, 190c, and 190d. Figure 14 In the diagram, the shaded area corresponds to the auxiliary wiring AL. The auxiliary wiring AL can be separate and isolated from contact members 190a, 190b, and 190c, but it can be connected to and continuously formed with contact member 190d. Since contact member 190d is connected to the common voltage line 170 through contact hole 81, the auxiliary wiring AL can be electrically connected to the common voltage line 170. Because the auxiliary wiring AL can transmit the common voltage ELVSS together with the common voltage line 170, the voltage drop of the common voltage ELVSS can be reduced.

[0170] The auxiliary wiring AL can be formed continuously across multiple groups of pixels PX1, PX2 and PX3, but the auxiliary wiring AL can be formed individually for each group of pixels PX1, PX2 and PX3 or for each of pixels PX1, PX2 and PX3.

[0171] The auxiliary wiring AL can be connected to the drive voltage lines 172a, 172b, and 172c through the contact hole 80' of the third insulating layer 181. For example... Figure 15 As shown, the auxiliary wiring AL can be connected to the common voltage line 170 through contact holes 81 formed in the third insulating layer 181. In the region of a set of pixels PX1, PX2 and PX3, the auxiliary wiring AL can be divided into at least two parts, wherein the first part can be electrically connected to the common voltage line 170 and the second part can be electrically connected to the drive voltage lines (e.g. 172b and 172c).

[0172] Figure 16 A layout diagram of the pixel region of a display device according to an embodiment is shown. Figure 17 The following is shown according to the embodiment. Figure 16 A schematic cross-sectional view taken by line G-G'.

[0173] Reference Figure 16 and Figure 17 The display device 1 may include auxiliary wiring AL disposed between the substrate 110 and the buffer layer 120. For example, the first conductive layer may include auxiliary wiring AL together with the lower pattern 111, and the auxiliary wiring AL may be formed in the same layer using the same process as the lower pattern 111. Figure 16 In the diagram, the shaded areas correspond to the areas where auxiliary wiring (AL) can be formed.

[0174] like Figure 17 As shown, the auxiliary wiring AL can be separated from and isolated from the lower pattern 111. Since the lower pattern 111 is superimposed on the active pattern 130a, the auxiliary wiring AL is not superimposed on the active pattern 130a. The auxiliary wiring AL may not be superimposed on the active patterns 130b and 130c as well as the active pattern 130a to prevent reverse bias effects.

[0175] The drive voltage lines 172a, 172b, and 172c can be connected to the auxiliary wiring AL through contact holes 602 formed in the second insulating layer 160 and the buffer layer 120. Therefore, the auxiliary wiring AL can reduce the resistance of the wiring used to transmit the drive voltage ELVDD and the voltage drop of the drive voltage ELVDD.

[0176] like Figure 17 As shown, the common voltage line 170 can be connected to the auxiliary wiring AL through contact holes 601 formed in the second insulating layer 160 and the buffer layer 120. Figure 18 As shown, the auxiliary wiring AL can be divided into at least two parts, AL1 and AL2, such that the common voltage line 170 can be connected to the first part AL1 through contact holes 601 formed in the second insulating layer 160 and the buffer layer 120, and the driving voltage lines 172a, 172b, and 172c can be connected to the second part AL2 through contact holes 602 formed in the second insulating layer 160 and the buffer layer 120. Figure 18 In the diagram, the shaded areas correspond to the areas where auxiliary wiring (AL) can be formed.

[0177] The auxiliary wiring AL can be formed to occupy a wide portion of the pixel region, potentially creating an undesirable capacitor between the auxiliary wiring AL and another wiring. A thicker insulating layer can be formed on the auxiliary wiring AL to reduce the capacitance of such a capacitor. For this purpose, the buffer layer 120 can be formed from multiple layers including at least a first layer 120a and a second layer 120b. The first layer 120a and / or the second layer 120b can comprise organic or inorganic insulating materials. Similarly, the second insulating layer 160 can be formed from multiple layers including at least a first layer 160a and a second layer 160b, which can comprise organic or inorganic insulating materials. Increasing the thickness of the insulating layer in this way to reduce the capacitance between the auxiliary wiring AL and other wirings can be equivalently applied to the other embodiments described above.

[0178] In the above embodiments, auxiliary wiring AL, ALa, ALb, and ALc can be connected to Figure 1 The diagram shows the drive voltage transmission lines (DVL) and / or common voltage transmission lines (CVL) in the non-display area NA. Although the auxiliary wirings AL, ALa, ALb, and ALc are described as electrically connected to power supply voltage lines such as drive voltage lines 172a, 172b, and 172c or common voltage line 170, the auxiliary wirings AL, ALa, ALb, and ALc can be electrically connected to wirings other than power supply voltage lines. For example, some of the auxiliary wirings AL, ALa, ALb, and ALc can be electrically connected to data lines 171a, 171b, and 171c, thereby helping to reduce the delay of the data signal DAT.

[0179] Although the invention has been shown and described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A display device, the display device comprising: The substrate includes a display area and a non-display area surrounding the display area; Transistors are disposed on the substrate; An insulating layer is disposed on the transistor; A power supply voltage line is disposed on the insulating layer, and the power supply voltage line transmits the power supply voltage. A data line is disposed on the insulating layer, and the data line transmits data voltage; An auxiliary wiring is disposed in the display area between the substrate and the power supply voltage line. The auxiliary wiring includes a portion overlapping the power supply voltage line and a portion overlapping the data line in a plan view, and the auxiliary wiring is electrically connected to the power supply voltage line. as well as The lower pattern is superimposed on the active pattern of the transistor. The auxiliary wiring is disposed on the same layer as the lower pattern, and the auxiliary wiring is electrically separated from the lower pattern.

2. The display device according to claim 1, wherein, The power supply voltage line is either a driving voltage line that transmits driving voltage or a common voltage line that transmits common voltage.

3. The display device according to claim 2, wherein, The driving voltage line is connected to the source or drain region of the transistor through a contact hole formed in the insulating layer, and is connected to the auxiliary wiring through another contact hole formed in the insulating layer.

4. The display device according to claim 2, further comprising a pixel electrode electrically connected to the transistor, wherein, The auxiliary wiring includes the portion that overlaps with the pixel electrode in the plan view.

5. The display device according to claim 4, wherein, The auxiliary wiring includes portions that overlap with the driving voltage lines and portions that overlap with the common voltage lines in the plan view.

6. The display device according to claim 2, wherein, The power supply voltage line is the driving voltage line, which is connected to the auxiliary wiring through contact holes formed in at least the insulating layer.

7. The display device according to claim 1, wherein, The auxiliary wiring is disposed between the substrate and the transistor.

8. The display device according to claim 1, wherein, The lower pattern is electrically connected to the source or drain region of the transistor.

9. The display device according to claim 7, further comprising a buffer layer disposed between the transistor and the auxiliary wiring. in, The buffer layer is a multilayer structure comprising at least two layers.

10. The display device according to claim 9, wherein, The power supply voltage line is connected to the auxiliary wiring through contact holes formed in the insulation layer and the buffer layer.

11. A display device, the display device comprising: The substrate includes a display area and a non-display area surrounding the display area; Transistors are disposed on the substrate; An insulating layer is disposed on the transistor; A power supply voltage line is disposed on the insulating layer, and the power supply voltage line transmits the power supply voltage. A data line is disposed on the insulating layer, and the data line transmits data voltage; as well as An auxiliary wiring is disposed in the display area between the substrate and the power supply voltage line. The auxiliary wiring includes portions overlapping the power supply voltage line and portions overlapping the data line in a plan view, and the auxiliary wiring is electrically connected to the power supply voltage line. The auxiliary wiring is disposed on the same layer as the gate electrode of the transistor.

12. A display device, the display device comprising: The substrate includes a display area and a non-display area surrounding the display area; Transistors are disposed on the substrate; An insulating layer is disposed on the transistor; A power supply voltage line is disposed on the insulating layer, and the power supply voltage line transmits the power supply voltage. A data line is disposed on the insulating layer, and the data line transmits data voltage; An auxiliary wiring is disposed in the display area between the substrate and the power supply voltage line. The auxiliary wiring includes a portion overlapping the power supply voltage line and a portion overlapping the data line in a plan view, and the auxiliary wiring is electrically connected to the power supply voltage line. as well as A connection pattern is disposed between the insulating layer and the transistor. The connection pattern is electrically connected to the power supply voltage line and the source or drain region of the transistor, and The auxiliary wiring is located on the same layer as the connection pattern.

13. A display device, the display device comprising: The substrate includes a display area and a non-display area surrounding the display area; Transistors are disposed on the substrate; A power supply voltage line is disposed on the transistor, and the power supply voltage line transmits the power supply voltage. A data line is disposed on the transistor, and the data line transmits data voltage; An insulating layer is disposed on the power supply voltage line; An auxiliary wiring is disposed on the insulating layer in the display area. The auxiliary wiring includes portions overlapping the power voltage line and the data line in a plan view, and the auxiliary wiring is connected to the power voltage line through contact holes formed in the insulating layer. A pixel electrode is disposed on the auxiliary wiring, and the pixel electrode is electrically connected to the transistor; The capacitor electrodes are disposed on the same layer as the power supply voltage line, and the capacitor electrodes are electrically connected to the transistor; as well as A contact member is disposed between the capacitor electrode and the pixel electrode, and the contact member is connected to the capacitor electrode through a contact hole formed in the insulating layer. The auxiliary wiring and the contact member are disposed on the same layer.

14. The display device according to claim 13, wherein, The power supply voltage line is either a driving voltage line that transmits driving voltage or a common voltage line that transmits common voltage.

15. The display device according to claim 14, wherein, The auxiliary wiring includes portions that overlap with the driving voltage lines and portions that overlap with the common voltage lines in the plan view.

16. The display device according to claim 14, wherein, The auxiliary wiring includes a first portion superimposed on the common voltage line in the plan view and a second portion superimposed on the driving voltage line and the pixel electrode, and The first part and the second part are separate from each other.

17. A display device, the display device comprising: The substrate includes a display area and a non-display area surrounding the display area; Transistors are disposed on the substrate; A common voltage line is disposed on the transistor, and the common voltage line transmits a common voltage. A data line is disposed on the transistor, and the data line transmits data voltage; An insulating layer is disposed on the common voltage line; An auxiliary wiring is disposed on the insulating layer in the display area. The auxiliary wiring includes a portion overlapping the common voltage line and a portion overlapping the data line in a plan view, and the auxiliary wiring is connected to the common voltage line through contact holes formed in the insulating layer. A pixel electrode is disposed on the auxiliary wiring, and the pixel electrode is electrically connected to the transistor; A first contact member is disposed on the common voltage line, and the first contact member is connected to the common voltage line through a contact hole formed in the insulating layer; as well as A common electrode is disposed on the first contact member, and the common electrode is electrically connected to the first contact member. The auxiliary wiring is disposed on the same layer as the first contact member.

18. The display device according to claim 17, further comprising a second contact member disposed between the first contact member and the common electrode, the second contact member being electrically connected to the first contact member and the common electrode.

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