Display Devices

Abstract

A display device includes a display portion having a substantially rectangular area with rounded edges, in which a plurality of data lines are arranged. The display portion includes a first area corresponding to the rounded edge portion and a second area corresponding to the straight edge portion and adjacent to the first area. A data driving circuit includes a plurality of output channels configured to output data voltages. The odd-numbered output channels output data voltages according to the arrangement order of the data lines in the second area. The even-numbered output channels output data voltages according to the reverse arrangement order of the data lines in the first area.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device having data lines at rounded side portions and straight side portions. Background Art

[0002] Modern display products are provided with smaller size and lighter weight. These display products can provide better performance than traditional display products in addition. For example, modern display products can have higher resolution, brighter display, higher contrast, faster response time and various other desirable attributes. Traditional cathode ray tube (CRT) televisions have been widely used in display devices due to many advantages in performance and price. However, compared with CRT displays, known modern display devices have a relatively thin flat panel structure in which the display device is thinner. Examples of flat panel display types include plasma display devices, liquid crystal display devices and organic light emitting diode (OLED) display devices. Compared with CRT displays, each of these flat panel display types provides a thinner and lighter structure that consumes less power.

[0003] Typically, a flat panel display device includes a display portion for displaying an image and a peripheral portion as a non-display area at least partially surrounding the display portion. The non-display area of ​​the display device is typically hidden behind a frame, such as a frame around the active area of ​​the display device. It is typically preferred to keep the frame as thin as possible in order to improve the aesthetic quality of the display device and to make the display device easier to integrate into smaller-sized portable electronic devices. Summary of the invention

[0004] According to an exemplary embodiment of the present disclosure, a display device includes a display portion having a substantially rectangular area with at least one rounded edge, in which a plurality of data lines are arranged. The display portion includes a first area corresponding to the rounded edge portion and a second area corresponding to the straight edge portion and adjacent to the first area. A data driving circuit includes a plurality of output channels configured to output data voltages. Odd-numbered output channels of the plurality of output channels output data voltages according to an arrangement order of data lines arranged in the second area, and even-numbered output channels of the plurality of output channels output data voltages according to an inverse arrangement order of data lines arranged in the first area.

[0005] In an exemplary embodiment of the present disclosure, the display device may further include a plurality of fan-out lines arranged in the fan-out region between the data driving circuit and the second region. The plurality of fan-out lines may be electrically connected to the plurality of output channels.

[0006] In an exemplary embodiment of the present disclosure, the display device may further include a plurality of bypass lines arranged in the first area and the second area. Each of the plurality of bypass lines may include: a first straight line portion disposed between the data lines arranged in the second area and including an end electrically connected to the fan-out line; a crossing portion crossing the data line; and a second straight line portion disposed between the data lines arranged in the first area and including an end electrically connected to the data line arranged in the first area.

[0007] In an exemplary embodiment of the present disclosure, odd-numbered fan-out lines of the plurality of fan-out lines can electrically connect odd-numbered output channels to data lines arranged in the second region, and even-numbered fan-out lines of the plurality of fan-out lines can electrically connect even-numbered output channels to bypass lines arranged in the second region.

[0008] In an exemplary embodiment of the present disclosure, the display portion may further include a third area adjacent to the second area and corresponding to a straight line side portion of the display portion.

[0009] In an exemplary embodiment of the present disclosure, the data driving circuit may further include: a plurality of output channels configured to output the data voltages according to an arrangement order of the data lines arranged in the third area.

[0010] In an exemplary embodiment of the present disclosure, a display device includes a display portion having a substantially rectangular area with at least one rounded edge, in which a plurality of data lines are arranged. The display device includes a first area corresponding to the rounded edge portion and a second area corresponding to the straight edge portion and adjacent to the first area. The data driving circuit includes: an n-multiplexer configured to output a data voltage for each group formed by binding every n output channels; and a plurality of output channels configured to output a plurality of data voltages. The output channels of the odd-numbered groups can output data voltages according to the arrangement order of the data lines arranged in the second area, and the output channels of the even-numbered groups can output data voltages according to the reverse arrangement order of the data lines arranged in the first area.

[0011] In an exemplary embodiment of the present disclosure, the display device may further include: a plurality of fan-out lines arranged in the fan-out region between the data driving circuit and the second region and electrically connected to the plurality of output channels.

[0012] In an exemplary embodiment of the present disclosure, the display device may further include: a plurality of bypass lines arranged in the first region and the second region. Each of the plurality of bypass lines may include: a first straight line portion disposed between the data lines disposed in the second region and including an end electrically connected to the fan-out line; a crossing portion crossing the data line; and a second straight line portion disposed between the data lines disposed in the first region and including an end electrically connected to the data line disposed in the first region.

[0013] In an exemplary embodiment of the present disclosure, when the data driving circuit includes a 2-multiplexer, the 4N-3rd fan-out line electrically connected to the 4N-3rd output channel may be electrically connected to the first data line arranged in the second region. The 4N-2nd fan-out line electrically connected to the 4N-2nd output channel may be electrically connected to the second data line arranged in the second region. The 4N-1st fan-out line electrically connected to the 4N-1st output channel may be electrically connected to the first straight line portion of the first bypass line between the first data line and the second data line arranged in the second region. The 4N fan-out line electrically connected to the 4N output channel may be electrically connected to the first straight line portion of the second bypass line between the second data line and the third data line arranged in the second region. Here, N is a positive integer.

[0014] In an exemplary embodiment of the present disclosure, when the data driving circuit includes a 4-way demultiplexer, the 8N-7th fan-out line electrically connected to the 8N-7th output channel may be electrically connected to the first data line arranged in the second area. The 8N-6th fan-out line electrically connected to the 8N-6th output channel may be electrically connected to the second data line arranged in the second area. The 8N-5th fan-out line electrically connected to the 8N-5th output channel may be electrically connected to the third data line arranged in the second area. The 8N-4th fan-out line electrically connected to the 8N-4th output channel may be electrically connected to the fourth data line arranged in the second area. The 8N-3rd fan-out line electrically connected to the 8N-3rd output channel may be electrically connected to the first straight line portion of the first bypass line between the first data line and the second data line arranged in the second area. The 8N-2nd fan-out line electrically connected to the 8N-2nd output channel may be electrically connected to the first straight line portion of the second bypass line between the second data line and the third data line arranged in the second area. The 8N-1th fan-out line electrically connected to the 8N-1th output channel may be electrically connected to a first straight line portion of a third bypass line between a third data line and a fourth data line arranged in the second region. The 8Nth fan-out line electrically connected to the 8Nth output channel may be electrically connected to a first straight line portion of a fourth bypass line between a fourth data line and a fifth data line arranged in the second region. Here, N is a positive integer.

[0015] In an exemplary embodiment of the present disclosure, the display portion may further include a third area adjacent to the second area and corresponding to the straight line side portion.

[0016] In an exemplary embodiment of the present disclosure, the data driving circuit may further include: a plurality of output channels configured to output the data voltages according to an arrangement order of the data lines arranged in the third area.

[0017] According to an exemplary embodiment of the present disclosure, a display device includes a display portion having a substantially rectangular area with at least one rounded edge, in which a plurality of data lines are arranged. The display portion includes a first area corresponding to the rounded edge portion and a second area corresponding to the straight edge portion and adjacent to the first area. The data drive circuit includes: an n-multiplexer configured to output a data voltage for each group formed by binding every n output lines; and a plurality of output channels electrically connected to the plurality of output lines of the n-multiplexer. Odd-numbered output channels of the plurality of output channels output data voltages according to the arrangement order of the data lines arranged in the second area. Even-numbered output channels of the plurality of output channels output data voltages according to the reverse arrangement order of the data lines arranged in the first area.

[0018] In an exemplary embodiment of the present disclosure, the display device may further include: a plurality of fan-out lines arranged in the fan-out region between the data driving circuit and the second region and electrically connected to the plurality of output channels.

[0019] In an exemplary embodiment of the present disclosure, the display device may further include: a plurality of bypass lines arranged in the first region and the second region. Each of the plurality of bypass lines may include: a first straight line portion disposed between the data lines disposed in the second region and including an end electrically connected to the fan-out line; a crossing portion crossing the data line; and a second straight line portion disposed between the data lines disposed in the first region and including an end electrically connected to the data line disposed in the first region.

[0020] In an exemplary embodiment of the present disclosure, when the data driving circuit includes a 2-way demultiplexer, the 4N-3 output line may be electrically connected to the 4N-3 output channel. The 4N-2 output line may be electrically connected to the 4N-1 output channel. The 4N-1 output line may be electrically connected to the 4N-2 output channel. The 4N output line may be electrically connected to the 4N output channel. Here, N is a positive integer.

[0021] In an exemplary embodiment of the present disclosure, when the data driving circuit includes a 4-multiplexer, the 8N-7th output line may be electrically connected to the 8N-7th output channel. The 8N-6th output line may be electrically connected to the 8N-5th output channel. The 8N-5th output line may be electrically connected to the 8N-3rd output channel. The 8N-4th output line may be electrically connected to the 8N-1st output channel. The 8N-3rd output line may be electrically connected to the 8N-6th output channel. The 8N-2th output line may be electrically connected to the 8N-4th output channel. The 8N-1st output line may be electrically connected to the 8N-2nd output channel. The 8N output line may be electrically connected to the 8N-1st output channel. Here, N is a positive integer.

[0022] In an exemplary embodiment of the present disclosure, the display portion may further include a third area adjacent to the second area and corresponding to the straight line side portion.

[0023] In an exemplary embodiment of the present disclosure, the data driving circuit may further include: a plurality of output channels configured to output the data voltages according to an arrangement order of the data lines arranged in the third area.

[0024] Therefore, the display device according to the exemplary embodiment of the present disclosure can simplify the arrangement of the fan-out lines by changing the order of the data voltages output from the plurality of output channels of the data driving circuit. Therefore, the display device can reduce the non-display area of ​​the display device and the line resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] As the present disclosure becomes better understood, a more complete appreciation of the present disclosure and its many attendant aspects will be readily obtained by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 2 Is a description and Figure 1 A plan view of an output channel of a driver circuit electrically connected to the fan-out lines shown in FIG.

[0028] Figure 3 is along Figure 2 A cross-sectional view taken along line I-I';

[0029] Figure 4 is a plan view illustrating an output channel of a driving circuit electrically connected to a fan-out line of a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 5 is a plan view illustrating an output channel of a driving circuit electrically connected to a fan-out line of a display device according to an exemplary embodiment of the present disclosure;

[0031] Figure 6 is a conceptual diagram describing an output channel of a driving circuit electrically connected to a fan-out line according to an exemplary embodiment of the present disclosure;

[0032] Figure 7 is a conceptual diagram describing an output channel of a driving circuit electrically connected to a fan-out line according to an exemplary embodiment of the present disclosure;

[0033] Figure 8 is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure; and

[0034] Fig. 9 Is a description and Figure 8 The fan-out lines shown in FIG. 1 are electrically connected to a plan view of the output channels of a driving circuit. DETAILED DESCRIPTION

[0035] Illustrative, non-limiting exemplary embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0036] Figure 1 is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure.

[0037] refer to Figure 1 , the display device 1000 may include a display portion (eg, display area) DA configured to display an image and a peripheral portion (eg, peripheral area) PA adjacent to the display portion DA and at least partially surrounding the display portion DA.

[0038] The display portion DA may have a substantially rectangular shape having rounded sides defined in a first direction D1 and a second direction D2 perpendicular to the first direction D1 when viewed in a plan view. Therefore, the shape of the display portion DA may be referred to herein as a rounded rectangle.

[0039] The display portion DA may include a first side area LA and a second side area RA that are laterally symmetrical (e.g., mirror-symmetrical) with respect to a center line CT extending mainly in the first direction D1. Each of the first side area LA and the second side area RA may include a first area A1 and a second area A2. The first area A1 may be an area corresponding to a rounded side of the display portion DA (e.g., the areas A1 may each be in a semi-stadium shape), and the second area A2 may be an area adjacent to the first area A1 and corresponding to a straight side of the display portion DA (e.g., the areas A2 may each be in a rectangular shape).

[0040] The display part DA may include a plurality of pixels arranged in various forms (eg, matrix form, etc.) and including thin film transistors for displaying images and a plurality of data lines DL1 to DLM electrically connected to the pixels. In addition, the display part DA may include a plurality of gate lines crossing the data lines DL1 to DLM.

[0041] The data lines DL1 to DLM may extend mainly in the first direction D1 and may be arranged in the second direction D2. The gate lines may extend mainly in the second direction D2 and may be arranged in the first direction D1.

[0042] In addition, the first to m-th data lines DL1 to DLm may be arranged in the first side area LA, and the (m+1)-th to (M)-th data lines DLm+1 to DLM may be arranged in the second side area RA.

[0043] In addition, 1st to kth data lines DL1 to DLk among 1st to mth data lines DL1 to DLm may be arranged in the first area A1 of the first side area LA, and k+1th to mth data lines DLk+1 to DLm may be arranged in the second area A2 of the first side area LA.

[0044] In addition, the m+1th to qth data lines DLm+1 to DLqth among the m+1th to Mth data lines DLM may be arranged in the second area A2 of the second side area RA, and the q+1th to Mth data lines DLq+1 to DLM may be arranged in the first area A1 of the second side area RA, where k, m, q, and M are positive integers (k <m<q<M)。

[0045] The display portion DA may include a bypass line area CLA in which a plurality of bypass lines CL1 to CLk and CLq+1 to CLM are arranged. Each of the bypass lines CL1 to CLk and CLq+1 to CLM may include a first straight line portion disposed between the data lines, a second straight line portion facing the first straight line portion, and a crossing portion crossing the data lines and electrically connecting the first straight line portion to the second straight line portion.

[0046] The first to k-th bypass lines CL1 to CLk may be electrically connected to the first to k-th data lines DL1 to DLk arranged in the first area A1 of the first side area LA.

[0047] In addition, the q+1th to Mth bypass lines CLq+1 to CLM may be electrically connected to the q+1th to Mth data lines DLq+1 to DLM disposed in the first area A1 of the second side area RA.

[0048] The peripheral portion PA may include a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 may be an area extending mainly in the first direction D1 from a straight side portion corresponding to the second area A2 of the display portion DA. The first non-display area NDA1 may not exist in a rounded side portion corresponding to the first area A1 of the display portion DA.

[0049] The first non-display area NDA1 may include a pad area PDA and a fan-out area FOA. The pad area PDA refers to an area in which the data driving circuit 200 and a plurality of pads are mounted. In the pad area PDA, a plurality of pads contact output channels of the data driving circuit 200.

[0050] A plurality of fan-out lines FL may be arranged in the fan-out area FOA The fan-out lines FL may electrically connect output channels of the data driving circuit 200 to the data lines DL1 to DLM and the bypass lines CL1 to CLk and CLq+1 to CLM.

[0051] In an exemplary embodiment of the present disclosure, the fan-out area FOA may include a bending area BA. The bending area BA may be an area of ​​the first non-display area NDA1 that is bent toward the rear side of the display device 1000 during a module assembling process.

[0052] The second non-display area NDA2 may at least partially surround an outer circumference of the display portion DA.

[0053] A plurality of contact portions electrically connecting the data lines DL1 to DLM to the bypass lines CL1 to CLk and CLq+1 to CLM may be disposed in the second non-display area NDA2 corresponding to the rounded side portion. In addition, a plurality of contact portions electrically connecting the fan-out lines FL to the data lines DL1 to DLM may be disposed in the second non-display area NDA2 corresponding to the straight side portion. In addition, a gate driving circuit generating a plurality of gate signals to drive the gate lines may be integrated in the second non-display area NDA2.

[0054] Figure 2 Is a description and Figure 1 The fan-out lines shown in FIG. 1 are electrically connected to a plan view of the output channels of a driving circuit.

[0055] In an exemplary embodiment of the present disclosure, the display device 1000 may include 1st to 2880th data lines, and the data driving circuit 200 may include 1st to 2880th output channels configured to output data voltages corresponding to the 1st to 2880th data lines.

[0056] refer to Figure 1 and Figure 2, the first side area LA and the second side area RA of the display portion DA may be laterally symmetrical (eg, mirror-symmetrical) with respect to the center line CT of the display portion DA.

[0057] Hereinafter, the structural relationship and interconnection relationship between the 1st data line DL1 to the 1440th data line DL1440 arranged in the first side area LA of the display part DA, the 1st bypass line CL1 to the 720th bypass line CL720, the 1st fan-out line FL1 to the 1440th fan-out line FL1440 arranged in the fan-out area FOA, and the 1st output channel CH1 to the 1440th output channel CH1440 of the data driving circuit 200 will be described.

[0058] The 1st to 1440th data lines DL1440 may be sequentially arranged along a first side direction (e.g., a forward direction D21) of the second direction D2. The 1st to 720th data lines DL720 may be sequentially arranged in the first area A1 along the forward direction D21. The 721st to 1440th data lines DL1440 may be sequentially arranged in the second area A2 along the forward direction D21.

[0059] 1st to 1440th fan-out lines FL1 to FL1440 may be sequentially arranged along the advancing direction D21. Odd-numbered fan-out lines FL1, FL3, ..., and FL1439 among the 1st to 1440th fan-out lines FL1 to FL1440 may be electrically connected to 721st to 1440th data lines DL721 to DL1440 arranged in the second area A2.

[0060] Even-numbered fan-out lines FL2 , FL4 , . . . , and FL1440 of the 1st to 1440th fan-out lines FL1 to FL1440 may be electrically connected to the 1st to 720th bypass lines CL1 to CL720 .

[0061] The 1st to 720th bypass lines CL1 to CL720 may include a first straight line portion L1 arranged between the 721st to 1440th data lines DL721 to DL1440 in the second area A2, a second straight line portion L2 arranged between the 1st to 720th data lines DL720 in the first area A1, and an intersection portion L3 intersecting the 1st to 1440th data lines DL1440 arranged in the first and second areas A1 and A2.

[0062] For example, the first straight line portion L1 of the first bypass line CL1 may be electrically connected to the end of the 1440th fan-out line FL1440 , and the second straight line portion L2 of the first bypass line CL1 may be electrically connected to the end of the 1st data line DL1 .

[0063] The first straight line portion L1 of the 720th bypass line CL720 may be electrically connected to the end of the 2nd fan-out line FL2 , and the second straight line portion L2 of the 720th bypass line CL720 may be electrically connected to the end of the 720th data line DL720 .

[0064] The data driving circuit 200 may include a plurality of output channels CH1 to CH1440 .

[0065] The 1st to 1440th output channels CH1 to CH1440 may be arranged along the forward direction D21 and may be electrically connected to the fan-out lines FL1 to FL1440 arranged in the forward direction D21.

[0066] Odd-numbered output channels CH1 , CH3 , . . . , and CH1439 among the 1st to 1440th output channels CH1 to CH1440 may output data voltages according to an arrangement order of the 721st to 1440th data lines DL721 to DL1440 arranged in the second area A2 .

[0067] Even-numbered output channels CH2, CH4, . . . , and CH1440 among the 1st to 1440th output channels CH1 to CH1440 may output data voltages according to a reverse arrangement order of the 1st to 720th data lines DL1 to DL720 arranged in the first area A1.

[0068] As described above, the odd (or even) numbered output channels CH1, CH3, ..., and CH1439 among the output channels CH1 to CH1440 of the data driving circuit 200 may be directly electrically connected to the data lines DL721 to DL1440, and the even (or odd) numbered output channels CH2, CH4, ..., and CH1440 of the output channels CH1 to CH1440 may be electrically connected to the data lines DL1 to DL720 through the bypass lines CL1 to CL720. The odd (or even) numbered output channels CH1, CH3, ..., and CH1439 of the data driving circuit 200 may output data voltages according to the arrangement order of the data lines DL721 to DL1440 arranged in the second area A2, and the even (or odd) numbered output channels CH2, CH4, ..., and CH1440 of the data driving circuit 200 may output data voltages according to the reverse arrangement order of the data lines DL1 to DL720 arranged in the first area A1. It should be understood that the words "odd (or even)" and "even (or odd)" are intended to mean "odd" and "even" or "even" and "odd", rather than "odd" and "odd" or "even" and "even". Therefore, it should be understood that, as used herein, the alternative forms listed in brackets are all part of the alternative embodiments, and the original forms not in brackets are all part of the main embodiment.

[0069] Therefore, the order of the data voltages output from the plurality of output channels CH1 to CH1440 of the data driving circuit 200 can be changed, and thus the arrangement of the fan-out lines FL1 to FL1440 can be simplified. As a result, the non-display area (or referred to as an invalid space) of the display device 1000 can be reduced, and the line resistance can be reduced.

[0070] Figure 3 It is along Figure 2 A cross-sectional view taken along line II'.

[0071] refer to Figure 2 and Figure 3 , the display device 1000 may include a display portion DA and a first non-display area NDA1.

[0072] The display device 1000 may include a base substrate 100. A thin film transistor TFT and an organic light emitting diode (OLED) 180 electrically connected to the thin film transistor TFT may be disposed in a display portion DA of the base substrate 100.

[0073] The base substrate 100 may be formed of a transparent or opaque material. For example, the base substrate 100 may include quartz, synthetic quartz, calcium fluoride, fluorine-doped (F-doped) quartz, soda-lime glass, and alkali-free glass, etc. In some exemplary embodiments of the present disclosure, the base substrate 100 may be formed of a flexible transparent resin. Examples of transparent resins that can be used for the base substrate 100 may include polyimide. In this case, the polyimide substrate may include a first polyimide layer, a barrier film layer, and a second polyimide layer, etc. For example, the polyimide substrate may be configured such that the first polyimide layer, the barrier film layer, and the second polyimide layer are laminated on a hard glass substrate.

[0074] The buffer layer 110 can prevent metal atoms or impurities from diffusing from the base substrate 100, and can obtain a substantially uniform active pattern ACT by adjusting a heat transfer rate during a crystallization process to form an active pattern ACT to be described later. In addition, when the surface of the base substrate 100 is uneven, the buffer layer 110 can be used to increase the flatness of the surface of the base substrate 100. The buffer layer 110 can be formed by using a silicon compound such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), and / or silicon carbonitride (SiCxNy).

[0075] In an exemplary embodiment of the present disclosure, the active pattern ACT may be disposed on the buffer layer 110. The active pattern ACT may include amorphous silicon or polycrystalline silicon. In an exemplary embodiment of the present disclosure, the active pattern ACT may include an oxide semiconductor including indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and / or zinc (Zn).

[0076] The active pattern ACT may be included in a thin film transistor TFT provided in the display portion DA to form a pixel structure. The active pattern ACT may include a drain region and a source region each doped with impurities and a channel region between the drain region and the source region.

[0077] The first insulating layer 120 may be disposed on the active pattern ACT. The first insulating layer 120 may include an inorganic insulating material. For example, the first insulating layer 120 may be formed using a silicon compound such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), and / or silicon carbonitride (SiCxNy).

[0078] The first gate pattern may be disposed on the first insulating layer 120. The first gate pattern may be formed of a first gate metal layer. The first gate pattern may include a gate line formed in the display portion DA, a gate electrode GE electrically connected to the gate line, and a first storage electrode E1, and may further include a plurality of fan-out lines FL1 to FL1439 formed in the non-display area NDA1.

[0079] The first gate pattern may be formed by using metal, alloy, metal nitride, conductive metal oxide, or transparent conductive material, etc. For example, the first gate pattern may include a conductive metal such as copper and / or aluminum.

[0080] The second insulating layer 130 may be disposed on the first insulating layer 120 on which the first gate pattern is disposed. The second insulating layer 130 may include an inorganic insulating material. For example, the second insulating layer 130 may be formed using a silicon compound such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), and / or silicon carbonitride (SiCxNy).

[0081] The second gate pattern may be disposed on the second insulating layer 130. The second gate pattern may be formed of a second gate metal layer. The second gate pattern may include a second storage electrode E2 formed in the display portion DA, and may include a plurality of fan-out lines FL2 to FL1438 formed in the first non-display area NDA1.

[0082] The second gate pattern may be formed by using metal, alloy, metal nitride, conductive metal oxide, or transparent conductive material, etc. For example, the second gate pattern may include a conductive metal such as copper and / or aluminum.

[0083] The third insulating layer 140 may be disposed on the second insulating layer 130 on which the second gate pattern is disposed. The third insulating layer 140 may include an inorganic insulating material. For example, the third insulating layer 140 may be formed using a silicon compound such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), and / or silicon carbonitride (SiCxNy).

[0084] The first source pattern may be disposed on the third insulating layer 140. The first source pattern may be formed of a first source metal layer. The first source pattern may include data lines DL721, DL722, . . . , and DL1440, a source electrode SE, and a drain electrode DE formed in the display portion DA, and may include a power supply voltage line VL formed in the first non-display area NDA1.

[0085] The first source pattern may have a multi-layered structure. For example, the first source pattern may include a titanium layer, an aluminum layer on the titanium layer, and another titanium layer on the aluminum layer.

[0086] The fourth insulating layer 150 may be disposed on the third insulating layer 140 on which the first source pattern is disposed. For example, the fourth insulating layer 150 may be formed by using a silicon compound such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy) and / or silicon carbonitride (SiCxNy). Alternatively, the fourth insulating layer 150 may be formed by using a photoresist, a polyacryl-based resin, a polyimide-based resin, an acryl-based resin, or the like.

[0087] The second source pattern may be disposed on the fourth insulating layer 150. The second source pattern may be formed of a second source metal layer. The second source pattern may include bypass lines CL1, CL2, . . . , and CL720 formed in the display portion DA and a connection electrode CE electrically connected to the drain electrode DE. .

[0088] The second source pattern may have a multi-layered structure. For example, the second source pattern may include a titanium layer, an aluminum layer disposed on the titanium layer, and another titanium layer disposed on the aluminum layer.

[0089] The fifth insulating layer 160 may be disposed on the fourth insulating layer 150 on which the second source pattern is disposed. For example, the fifth insulating layer 160 may be formed by using a silicon compound such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy) and / or silicon carbonitride (SiCxNy). Alternatively, the fifth insulating layer 160 may be formed by using a photoresist, a polyacryl resin, a polyimide resin, an acryl resin, or the like.

[0090] The organic light emitting diode 180 may be disposed on the fifth insulating layer 160 .

[0091] The organic light emitting diode 180 may include a first electrode 181 , a light emitting layer 182 , and a second electrode 183 .

[0092] The first electrode 181 may be disposed on the fifth insulating layer 160. The first electrode 181 may be formed by using a reflective material or a light-transmitting material according to a light emission mode of the display device. In an exemplary embodiment of the present disclosure, the first electrode 181 may be formed by a single-layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive material film.

[0093] The pixel defining layer PDL may be disposed on the fifth insulating layer 160 on which the first electrode 181 is disposed. The pixel defining layer PDL may be formed by using an organic material or an inorganic material, etc. For example, the pixel defining layer PDL may be formed by using a photoresist, a polyacryl resin, a polyimide resin, an acryl resin, or a silicon compound, etc. In an exemplary embodiment of the present disclosure, an opening partially exposing the first electrode 181 may be formed by etching the pixel defining layer PDL. The light emitting area and the non-light emitting area of ​​the display device 1000 may be defined by the opening of the pixel defining layer PDL. For example, the portion where the opening of the pixel defining layer PDL is located may correspond to the light emitting area, and the portion adjacent to the opening of the pixel defining layer PDL may correspond to the non-light emitting area.

[0094] The light emitting layer 182 may be disposed on the first electrode 181 exposed through the opening of the pixel defining layer PDL. In addition, the light emitting layer 182 may extend to the sidewall of the opening of the pixel defining layer PDL. In an exemplary embodiment of the present disclosure, the light emitting layer 182 may have a multilayer structure including an organic light emitting layer (EL), a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment of the present disclosure, in addition to the organic light emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like may be formed together to correspond to a plurality of pixels. The organic light emitting layer of the light emitting layer 182 may be formed by using a light emitting material that can generate light of different colors such as red light, green light, and blue light according to each pixel of the display device. In some exemplary embodiments of the present disclosure, the organic light emitting layer of the light emitting layer 182 may have a structure in which a plurality of light emitting materials capable of realizing light of different colors such as red light, green light, and blue light are laminated to emit white light. The light emitting structures may be collectively formed to correspond to pixels, and each pixel may be distinguished by a color filter layer.

[0095] The second electrode 183 may be disposed on the pixel defining layer PDL and the light emitting layer 182. The second electrode 183 may include a light-transmitting material or a reflective material according to the light emission mode of the display device. In an exemplary embodiment of the present disclosure, the second electrode 183 may also be formed by a single-layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive material film.

[0096] The thin film encapsulation layer TFE may be disposed on the second electrode 183. The thin film encapsulation layer TFE may prevent the penetration of external moisture and oxygen. The thin film encapsulation layer TFE may have at least one organic layer and at least one inorganic layer. At least one organic layer and at least one inorganic layer may be alternately laminated. For example, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer between the two inorganic layers, but the present invention is not limited thereto. In some exemplary embodiments of the present disclosure, a sealing substrate configured to prevent external air and moisture from penetrating into the display device 1000 may be provided instead of the thin film encapsulation layer TFE.

[0097] According to the present embodiment, a portion of the fan-out lines FL1 to FL1440 arranged in the non-display area may be formed by the first gate metal layer, and the remaining portion may be formed by the second gate metal layer. In addition, the bypass lines CL1 to CL720 crossing the fan-out lines FL1 to FL1440 may be formed by the second source metal layer. Therefore, the arrangement gap between the fan-out lines FL1 to FL1440 may be reduced, and thus the non-display area may be reduced.

[0098] In the following, the same components as the previous embodiment will be described using the same reference numerals, and in the case where some elements are not described in detail, it can be assumed that these elements are at least similar to corresponding elements that have already been described.

[0099] Figure 4 is a plan view illustrating an output channel of a driving circuit electrically connected to a fan-out line of a display device according to an exemplary embodiment of the present disclosure.

[0100] refer to Figure 1 and Figure 4 , the structural relationship and interconnection relationship between the 1st data line DL1 to the 1440th data line DL1440 arranged in the first side area LA of the display part DA, the 1st bypass line CL1 to the 720th bypass line CL720, the 1st fan-out line FL1 to the 1440th fan-out line FL1440 arranged in the fan-out area FOA, and the 1st output channel CH1 to the 1440th output channel CH1440 of the data driving circuit 210 will be described.

[0101] The data driving circuit 210 may include a 2-way demultiplexer 211 and a plurality of output channels CH1 to CH1440 .

[0102] The 2-demultiplexer 211 may output a data voltage for each output group formed by binding every two output lines. The 2-demultiplexer 211 may include a plurality of first switches SW1 and a plurality of second switches SW2.

[0103] The first switch SW1 may be electrically connected to odd-numbered output channels CH1, CH3, ..., CH1437, and CH1439 of, for example, output channels CH1 to CH1440. The first switch SW1 may be turned on in response to a first turn-on control signal, and each of the odd-numbered output channels CH1, CH3, ..., CH1437, and CH1439 may output a corresponding data voltage.

[0104] The second switch SW2 may be electrically connected to, for example, even-numbered output channels CH2, CH4, ..., CH1438, and CH1440 of the output channels CH1 to CH1440. The second switch SW2 may be turned on in response to a second turn-on control signal, and each of the even-numbered output channels CH2, CH4, ..., CH1438, and CH1440 may output a corresponding data voltage.

[0105] The 2-demultiplexer 211 may output a data voltage corresponding to one horizontal line to the output channels CH1 to CH1440 based on a first turn-on control signal and a second turn-on control signal obtained by dividing one horizontal segment of the frame segment into two segments.

[0106] According to driving of the 2-demultiplexer 211 , the output channels CH1 , CH2 , . . . , CH1439 , and CH1440 may be divided into a plurality of output groups GP1 , GP2 , GP3 , . . . , GP719 , and GP720 formed by binding every two output channels.

[0107] The 1st to 1440th fan-out lines FL1 to FL1440 may be electrically connected to the output channels CH1 to CH1440 in response to driving of the 2-demultiplexer 211 of the data driving circuit 210 .

[0108] The first fan-out line FL1 may electrically connect the first output channel CH1 to the 721st data line DL721 .

[0109] The 2nd fan-out line FL2 may cross the 3rd fan-out line FL3 and may electrically connect the 2nd output channel CH2 to the 722nd data line DL722.

[0110] The 3rd fan-out line FL3 may cross the 2nd fan-out line FL2 and may electrically connect the 3rd output channel CH3 to the 720th bypass line CL720 disposed between the 721st data line DL721 and the 722nd data line DL722 .

[0111] The 4th fan-out line FL4 may electrically connect the 4th output channel CH4 to the 719th bypass line CL719 disposed between the 722nd data line DL722 and the 723rd data line DL723 .

[0112] In addition, the 1437th fan-out line FL1437 may electrically connect the 1437th output channel CH1437 to the 1439th data line DL1439.

[0113] The 1438th fan-out line FL1438 may cross the 1439th fan-out line FL1439 and may electrically connect the 1438th output channel CH1438 to the 1440th data line DL1440.

[0114] The 1439th fan-out line FL1439 may cross the 1438th fan-out line FL1438 and may electrically connect the 1439th output channel CH1439 to the second bypass line CL2 disposed between the 1439th data line DL1439 and the 1440th data line DL1440 .

[0115] The 1440th fan-out line FL1440 may electrically connect the 1440th output channel CH1440 to the first bypass line CL1 disposed between the 1440th data line DL1440 and the 1441st data line DL1441 .

[0116] The first output group GP1 of the data driving circuit 210 may include a 1st output channel CH1 and a 2nd output channel CH2, and the second output group GP2 of the data driving circuit 210 may include a 3rd output channel CH3 and a 4th output channel CH4. In addition, the 719th output group GP719 of the data driving circuit 210 may include a 1437th output channel CH1437 and a 1438th output channel CH1438, and the 720th output group GP720 of the data driving circuit 210 may include a 1439th output channel CH1439 and a 1440th output channel CH1440.

[0117] Therefore, the output groups GP1, GP2, GP3, ..., GP719 and GP720 may include odd-numbered output groups GP1, GP3, ..., and GP719 and even-numbered output groups GP2, GP4, ..., and GP720.

[0118] Output channels CH1 , CH2 , . . . , CH1437 , and CH1438 included in odd-numbered output groups GP1 , GP3 , . . . , and GP719 may be sequentially electrically connected to 721st to 1440th data lines DL721 to DL1440 arranged in the second area A2 .

[0119] Output channels CH1, CH2, . . . , CH1437, and CH1438 included in odd-numbered output groups GP1, GP3, . . . , and GP719 may output data voltages according to an arrangement order of 721st to 1440th data lines DL721 to DL1440 arranged in the second area A2.

[0120] Output channels CH3, CH4, . . . , CH1439 and CH1440 included in even-numbered output groups GP2, GP4, . . . , and GP720 may be electrically connected to 1st to 720th data lines DL1 to DL720 arranged in the first area A1 according to a reverse arrangement order through 1st to 720th bypass lines CL1 to CL720.

[0121] Output channels CH3, CH4, . . . , CH1439 and CH1440 included in even-numbered output groups GP2, GP4, . . . , and GP720 may output data voltages according to the reverse arrangement order of the 1st to 720th data lines DL1 to DL720 arranged in the first area A1.

[0122] For example, a first pixel P1 electrically connected to the 719th data line DL719 and a second pixel P2 electrically connected to the 720th data line DL720 may be arranged in the first area A1, and a third pixel P3 electrically connected to the 721st data line DL721 and a fourth pixel P4 electrically connected to the 722nd data line DL722 may be arranged in the second area A2.

[0123] According to driving of the 2-demultiplexer 211 , the first switch SW1 may be turned on in a first segment in one horizontal segment, and the second switch SW2 may be turned on in a second segment in one horizontal segment.

[0124] During the first segment, the 1st output channel CH1 of the first output group GP1 may output a data voltage corresponding to the third pixel P3 of the second area A2, and the 3rd output channel CH3 of the second output group GP2 may output a data voltage corresponding to the second pixel P2 of the first area A1.

[0125] During the second segment, the 2nd output channel CH2 of the first output group GP1 may output a data voltage corresponding to the fourth pixel P4 of the second area A2, and the 4th output channel CH4 of the second output group GP2 may output a data voltage corresponding to the first pixel P1 of the first area A1.

[0126] As described above, the data driving circuit 210 including the 2-way multiplexer 211 may include a plurality of output groups GP1, GP2, GP3, ..., GP719 and GP720 formed by binding every two output channels, and a plurality of fan-out lines FL1 to FL1440 electrically connected to the output groups GP1, GP2, GP3, ..., GP719 and GP720 of the data driving circuit 210 may have a structure in which some of the 4N-3, 4N-2, 4N-1 and 4N fan-out lines cross (here, N is a positive integer).

[0127] The odd (or even) numbered output groups GP1, GP2, GP3, ..., and GP719 of the output groups GP1, GP2, GP3, ..., GP719 and GP720 can be directly electrically connected to the data lines DL721 to DL1440, and the even (or odd) numbered output groups GP2, GP4, ..., and GP720 of the output groups GP1, GP2, GP3, ..., GP719 and GP720 can be electrically connected to the data lines DL1 to DL720 through the bypass lines CL1 to CL720. The odd (or even) numbered output groups GP1, GP3, ..., and GP719 of the data driving circuit 210 can output data voltages according to the arrangement order of the data lines DL721 to DL1440 arranged in the second area A2, and the even (or odd) numbered output groups GP2, GP4, ..., and GP720 of the data driving circuit 210 can output data voltages according to the reverse arrangement order of the data lines DL1 to DL720 arranged in the first area A1.

[0128] Therefore, the order of the data voltages output from the plurality of output channels CH1 to CH1440 of the data driving circuit 210 can be changed, and thus the arrangement of the fan-out lines FL1 to FL1440 can be simplified. As a result, the non-display area (or referred to as an invalid space) of the display device 1000 can be reduced, and the line resistance can be reduced.

[0129] Figure 5 is a plan view illustrating an output channel of a driving circuit electrically connected to a fan-out line of a display device according to an exemplary embodiment of the present disclosure.

[0130] refer to Figure 1 and Figure 5, the structural relationship and interconnection relationship between the 1st data line DL1 to the 1440th data line DL1440 arranged in the first side area LA of the display part DA, the 1st bypass line CL1 to the 720th bypass line CL720, the 1st output line FL1 to the 1440th output line FL1440 arranged in the fan-out area FOA, and the 1st output channel CH1 to the 1440th output channel CH1440 of the data driving circuit 220 will be described.

[0131] The data driving circuit 220 may include a 4-way demultiplexer 221 and a plurality of output channels CH1 to CH1440 .

[0132] The 4-demultiplexer 221 may output a data voltage for each output group formed by binding every four output lines.

[0133] The 4-way demultiplexer 221 may include a plurality of first switches SW1 , a plurality of second switches SW2 , a plurality of third switches SW3 , and a plurality of fourth switches SW4 .

[0134] The first switch SW1 may be electrically connected to, for example, 4N-3th output channels CH1, CH5, ..., and CH1437 (where N is a positive integer) of the output channels CH1 to CH1440. The first switch SW1 may be turned on in response to a first turn-on control signal, and each of the 4N-3th output channels CH1, CH5, ..., and CH1437 may output a corresponding data voltage.

[0135] The second switch SW2 may be electrically connected to, for example, the 4N-2 th output channels CH2, CH6, ..., and CH1438 of the output channels CH1 to CH1440. The second switch SW2 may be turned on in response to a second turn-on control signal, and each of the 4N-2 th output channels CH2, CH6, ..., and CH1438 may output a corresponding data voltage.

[0136] The third switch SW3 may be electrically connected to, for example, the 4N-1th output channels CH3, CH7, ..., and CH1439 of the output channels CH1 to CH1440. The third switch SW3 may be turned on in response to a third turn-on control signal, and each of the 4N-1th output channels CH3, CH7, ..., and CH1439 may output a corresponding data voltage.

[0137] The fourth switch SW4 may be electrically connected to, for example, 4Nth output channels CH4, CH8, ..., and CH1440 of the output channels CH1 to CH1440. The fourth switch SW4 may be turned on in response to a fourth turn-on control signal, and each of the 4Nth output channels CH4, CH8, ..., and CH1440 may output a corresponding data voltage.

[0138] The 4-demultiplexer 221 may output data voltages corresponding to one horizontal line to the output channels CH1 to CH1440 based on first, second, third, and fourth turn-on control signals obtained by dividing one horizontal segment of the frame segment into four segments.

[0139] According to driving of the 4-demultiplexer 221 , the output channels CH1 , CH2 , . . . , CH1439 , and CH1440 may be divided into a plurality of output groups GP1 , GP2 , . . . , GP359 , and GP360 formed by binding every four output channels.

[0140] The 1st to 1440th fan-out lines FL1 to FL1440 may be electrically connected to the output channels CH1 to CH1440 in response to driving of the 4-demultiplexer 221 of the data driving circuit 220 .

[0141] The first fan-out line FL1 may electrically connect the first output channel CH1 to the 721st data line DL721 .

[0142] The 2nd fan-out line FL2 may cross the 5th fan-out line FL5 and may electrically connect the 2nd output channel CH2 to the 722nd data line DL722.

[0143] The 3rd fan-out line FL3 may cross the 5th fan-out line FL5 and the 6th fan-out line FL6 and may electrically connect the 3rd output channel CH3 to the 723rd data line DL723.

[0144] The 4th fan-out line FL4 may cross the 5th fan-out line FL5, the 6th fan-out line FL6, and the 7th fan-out line FL7, and may electrically connect the 4th output channel CH4 to the 724th data line DL724.

[0145] The 5th fan-out line FL5 may electrically connect the 5th output channel CH5 to the 720th bypass line CL720 disposed between the 721st data line DL721 and the 722nd data line DL722 .

[0146] The 6th fan-out line FL6 may electrically connect the 6th output channel CH6 to the 719th bypass line CL719 disposed between the 722nd data line DL722 and the 723rd data line DL723 .

[0147] The 7th fan-out line FL7 may electrically connect the 7th output channel CH7 to the 718th bypass line CL718 disposed between the 723rd data line DL723 and the 724th data line DL724.

[0148] The 8th fan-out line FL8 may electrically connect the 8th output channel CH8 to the 717th bypass line CL717 disposed between the 724th data line DL724 and the 725th data line DL725.

[0149] The first output group GP1 of the data driving circuit 220 may include the 1st output channel CH1, the 2nd output channel CH2, the 3rd output channel CH3 and the 4th output channel CH4, and the second output group GP2 of the data driving circuit 220 may include the 5th output channel CH5, the 6th output channel CH6, the 7th output channel CH7 and the 8th output channel CH8.

[0150] Therefore, the output groups GP1, GP2, GP3, ..., and GP360 may include odd-numbered output groups GP1, GP3, ..., and GP359 and even-numbered output groups GP2, GP4, ..., and GP360.

[0151] The output channels CH1, CH2, CH3, CH4, . . . included in the odd-numbered output groups GP1, GP3, . . . , and GP359 may be sequentially electrically connected to the 721st to 1440th data lines DL721 to DL1440 arranged in the second area A2.

[0152] The output channels CH1, CH2, CH3, CH4, . . . included in the odd-numbered output groups GP1, GP3, . . . and GP359 may output data voltages according to an arrangement order of the 721st to 1440th data lines DL721 to DL1440 arranged in the second area A2.

[0153] The output channels CH5, CH6, CH7, CH8, ... included in the even-numbered output groups GP2, GP4, ..., and GP360 may be electrically connected to the 1st to 720th data lines DL1 to DL720 arranged in the first area A1 according to a reverse arrangement order through the 1st to 720th bypass lines CL1 to CL720.

[0154] Output channels CH5, CH6, CH7, CH8, . . . included in the even-numbered output groups GP2, GP4, . . . and GP360 may output data voltages according to the reverse arrangement order of the 1st to 720th data lines DL1 to DL720 arranged in the first area A1.

[0155] For example, in the first area A1, a first pixel P1 electrically connected to the 717th data line DL717, a second pixel P2 electrically connected to the 718th data line DL718, a third pixel P3 electrically connected to the 719th data line DL719, and a fourth pixel P4 electrically connected to the 720th data line DL720 may be arranged. In the second area A2, a fifth pixel P5 electrically connected to the 721st data line DL721, a sixth pixel P6 electrically connected to the 722nd data line DL722, a seventh pixel P7 electrically connected to the 723rd data line DL723, and an eighth pixel P8 electrically connected to the 724th data line DL724 may be arranged.

[0156] According to the driving of the 4-way distributor 221, the first switch SW1 can be turned on in the first segment in a horizontal segment, the second switch SW2 can be turned on in the second segment in a horizontal segment, the third switch SW3 can be turned on in the third segment in a horizontal segment, and the fourth switch SW4 can be turned on in the fourth segment in a horizontal segment.

[0157] During the first segment, the 1st output channel CH1 of the first output group GP1 may output a data voltage corresponding to the fifth pixel P5 of the second area A2, and the 5th output channel CH5 of the second output group GP2 may output a data voltage corresponding to the fourth pixel P4 of the first area A1.

[0158] During the second segment, the 2nd output channel CH2 of the first output group GP1 may output a data voltage corresponding to the sixth pixel P6 of the second area A2, and the 6th output channel CH6 of the second output group GP2 may output a data voltage corresponding to the third pixel P3 of the first area A1.

[0159] During the third segment, the 3rd output channel CH3 of the first output group GP1 may output a data voltage corresponding to the seventh pixel P7 of the second area A2, and the 7th output channel CH7 of the second output group GP2 may output a data voltage corresponding to the second pixel P2 of the first area A1.

[0160] During the fourth segment, the 4th output channel CH4 of the first output group GP1 may output a data voltage corresponding to the eighth pixel P8 of the second area A2, and the 8th output channel CH8 of the second output group GP2 may output a data voltage corresponding to the first pixel P1 of the first area A1.

[0161] As described above, the data driving circuit 220 including the 4-way demultiplexer 221 may include a plurality of output groups GP1, GP2, GP3, ..., and GP360 formed by binding every four output channels, and a plurality of fan-out lines FL1 to FL1440 electrically connected to the output groups GP1, GP2, GP3, ..., and GP360 of the data driving circuit 220 may have a structure in which some of the 8N-7, 8N-6, 8N-5, 8N-4, 8N-3, 8N-2, 8N-1, and 8N fan-out lines cross (here, N is a positive integer).

[0162] The odd (or even) numbered output groups GP1, GP3, ..., and GP359 of the output groups GP1, GP2, GP3, ..., and GP360 may be directly electrically connected to the data lines DL721 to DL1440, and the even (or odd) numbered output groups GP2, GP4, ..., and GP360 of the output groups GP1, GP2, GP3, ..., and GP360 may be electrically connected to the data lines DL1 to DL720 through the bypass lines CL1 to CL720. The odd (or even) numbered output groups GP1, GP3, ..., and GP359 of the data driving circuit 220 may output data voltages according to the arrangement order of the data lines DL721 to DL1440 arranged in the second area A2, and the even (or odd) numbered output groups GP2, GP4, ..., and GP360 of the data driving circuit 220 may output data voltages according to the reverse arrangement order of the data lines DL1 to DL720 arranged in the first area A1.

[0163] Therefore, the order of the data voltages output from the plurality of output channels CH1 to CH1440 of the data driving circuit 220 can be changed, and thus the arrangement of the fan-out lines FL1 to FL1440 can be simplified. As a result, the non-display area (which may be referred to as an invalid space) of the display device 1000 can be reduced, and the line resistance can be reduced.

[0164] Figure 6 is a conceptual diagram describing an output channel of a driving circuit electrically connected to a fan-out line according to an exemplary embodiment of the present disclosure.

[0165] refer to Figure 6 , the data driving circuit 230 may include a 2-way demultiplexer 231 and a plurality of output channels CH1 to CH1440.

[0166] The 2-demultiplexer 231 may output a data voltage for each output group formed by binding every two output lines. The 2-demultiplexer 231 may include a plurality of input terminals IN1, IN2, ..., and IN720, a plurality of first switches SW1, a plurality of second switches SW2, and a plurality of output lines OL1, OL2, ..., OL1439, and OL1440.

[0167] The first switch SW1 may electrically connect the input terminals IN1 , IN2 , . . . , and IN720 to, for example, odd-numbered output lines OL1 , OL3 , . . . , OL1437 , and OL1439 among the output lines OL1 , OL2 , . . . , OL1439 , and OL1440 .

[0168] The first switch SW1 may be turned on in response to a first turn-on control signal and may output data voltages corresponding to the odd-numbered output lines OL1 , OL3 , . . . , OL1437 , and OL1439 .

[0169] The second switch SW2 may electrically connect the input terminals IN1, IN2, ..., and IN720 to, for example, even-numbered output lines OL2, OL4, ..., OL1438, and OL1440 among the output lines OL1, OL2, ..., OL1439, and OL1440. The second switch SW2 may be turned on in response to a second turn-on control signal and may output data voltages corresponding to the even-numbered output lines OL2, OL4, ..., OL1438, and OL1440.

[0170] The output lines OL1 , OL2 , . . . , OL1439 , and OL1440 of the 2-demultiplexer 231 may be electrically connected to the output channels CH1 to CH1440 of the data driving circuit 230 .

[0171] The first output line OL1 may be electrically connected to the 1st output channel CH1, and the second output line OL2 may cross the third output line OL3 and be electrically connected to the 3rd output channel CH3.

[0172] The third output line OL3 may cross the second output line OL2 and may be electrically connected to the 2nd output channel CH2. The fourth output line OL4 may be electrically connected to the 4th output channel CH4.

[0173] The output channels CH1 to CH1440 of the data driving circuit 230 may be electrically connected to the 1st to 1440th fan-out lines FL1 to FL1440 .

[0174] refer to Figure 2, the odd-numbered fan-out lines FL1, FL3, ..., and FL1439 of the 1st to 1440th fan-out lines FL1440 may be sequentially electrically connected to the 721st to 1440th data lines DL721 to DL1440th data lines arranged in the second area A2. The even-numbered fan-out lines FL2, FL4, ..., and FL1440 of the 1st to 1440th fan-out lines FL1440 may be electrically connected to the 1st to 720th data lines DL720 arranged in the first area A1 through the 1st to 720th bypass lines CL720 according to a reverse arrangement order.

[0175] According to driving of the 2-demultiplexer 231 , the first switch SW1 may be turned on in a first segment of one horizontal segment, and the second switch SW2 may be turned on in a second segment of one horizontal segment.

[0176] During the first segment, the first output line OL1 and the third output line OL3 of the 2-demultiplexer 231 electrically connected to the first switch SW1 can output data voltages. The first output channel CH1 electrically connected to the first output line OL1 and the second output channel CH2 electrically connected to the third output line OL3 can output data voltages.

[0177] refer to Figure 2 , the first output channel CH1 may output a data voltage corresponding to the fifth pixel P5 of the second area A2, and the second output channel CH2 may output a data voltage corresponding to the fourth pixel P4 of the first area A1.

[0178] During the second segment, the second output line OL2 and the fourth output line OL4 of the 2-demultiplexer 231 electrically connected to the second switch SW2 can output the data voltage. The third output channel CH3 electrically connected to the second output line OL2 and the fourth output channel CH4 electrically connected to the fourth output line OL4 can output the data voltage.

[0179] refer to Figure 2 , the 3rd output channel CH3 may output a data voltage corresponding to the sixth pixel P6 of the second area A2, and the 4th output channel CH4 may output a data voltage corresponding to the third pixel P3 of the first area A1.

[0180] As described above, the data driving circuit 230 including the 2-demultiplexer 231 may electrically connect the 4N-3rd, 4N-2nd, 4N-1st, and 4Nth output lines to the plurality of output channels CH1 to CH1440 of the data driving circuit 230 after the output lines are crossed. Therefore, the odd-numbered (or even-numbered) output channels CH1, CH3, ..., and CH1439 among the output channels CH1 to CH1440 of the data driving circuit 230 may be directly electrically connected to the data lines DL721 to DL1440, and the even-numbered (or odd-numbered) output channels CH2, CH4, ..., and CH1440 of the output channels CH1 to CH1440 may be electrically connected to the data lines DL1 to DL720 through the bypass lines CL1 to CL720. The odd (or even) numbered output channels CH1, CH3, ..., and CH1439 of the data driving circuit 230 can output data voltages according to the arrangement order of the data lines DL721 to DL1440 arranged in the second area A2, and the even (or odd) numbered output channels CH2, CH4, ..., and CH1440 of the data driving circuit 230 can output data voltages according to the reverse arrangement order of the data lines DL1 to DL720 arranged in the first area A1.

[0181] Therefore, the order of data voltages output from the plurality of output channels CH1 to CH1440 of the data driving circuit 230 may be changed, and thus the arrangement of the fan-out lines FL1 to FL1440 may be simplified. As a result, the non-display area of ​​the display device 1000 may be reduced, and line resistance may be lowered.

[0182] Figure 7 is a conceptual diagram describing an output channel of a driving circuit electrically connected to a fan-out line according to an exemplary embodiment of the present disclosure.

[0183] refer to Figure 7 , the data driving circuit 240 may include a 4-way demultiplexer 241 and a plurality of output channels CH1 to CH1440 .

[0184] The 4-demultiplexer 241 may output a data voltage for each output group formed by binding every four output lines.

[0185] The 4-way demultiplexer 241 may include a plurality of input terminals IN1 , IN2 , . . . , and IN360 , a plurality of first switches SW1 , a plurality of second switches SW2 , a plurality of third switches SW3 , a plurality of fourth switches SW4 , and a plurality of output lines OL1 , OL2 , . . . , OL1439 , and OL1440 .

[0186] The first switch SW1 may electrically connect the input terminals IN1 , IN2 , . . . , and IN360 to, for example, 4N-3 th output lines OL1 , OL5 , . . . , and OL1437 among the output lines OL1 , OL2 , . . . , OL1439 , and OL1440 .

[0187] The second switch SW2 may electrically connect the input terminals IN1 , IN2 , . . . , and IN360 to, for example, the 4N-2 th output line OL2 , OL6 , . . . , and OL1438 among the output lines OL1 , OL2 , . . . , OL1439 , and OL1440 .

[0188] The third switch SW3 may electrically connect the input terminals IN1 , IN2 , . . . , and IN360 to, for example, the 4N−1th output lines OL3 , OL7 , . . . , and OL1439 among the output lines OL1 , OL2 , . . . , OL1439 , and OL1440 .

[0189] The fourth switch SW4 may electrically connect the input terminals IN1 , IN2 , . . . , and IN360 to, for example, 4N-th output lines OL4 , OL8 , . . . , and OL1440 among the output lines OL1 , OL2 , . . . , OL1439 , and OL1440 .

[0190] The output lines OL1 , OL2 , . . . , OL1439 , and OL1440 of the 4-demultiplexer 241 may be electrically connected to the output channels CH1 to CH1440 of the data driving circuit 230 .

[0191] The first output line OL1 may be electrically connected to the 1st output channel CH1 .

[0192] The second output line OL2 may cross the fifth output line OL5 and may be electrically connected to the 3rd output channel CH3. The third output line OL3 may cross the fifth output line OL5 and the sixth output line OL6 and may be electrically connected to the 5th output channel CH5. The fourth output line OL4 may cross the fifth output line OL5, the sixth output line OL6, and the seventh output line OL7 and may be electrically connected to the 7th output channel CH7.

[0193] The fifth output line OL5 may cross the second output line OL2, the third output line OL3, and the fourth output line OL4, and may be electrically connected to the second output channel CH2. The sixth output line OL6 may cross the third output line OL3 and the fourth output line OL4, and may be electrically connected to the fourth output channel CH4. The seventh output line OL7 may cross the fourth output line OL4, and may be electrically connected to the sixth output channel CH6. The eighth output line OL8 may be electrically connected to the eighth output channel CH8.

[0194] The output channels CH1 to CH1440 of the data driving circuit 240 may be electrically connected to the 1st to 1440th fan-out lines FL1 to FL1440 .

[0195] refer to Figure 2 , the odd-numbered fan-out lines FL1, FL3, ..., and FL1439 of the 1st to 1440th fan-out lines FL1440 may be sequentially electrically connected to the 721st to 1440th data lines DL721 to DL1440th data lines arranged in the second area A2. The even-numbered fan-out lines FL2, FL4, ..., and FL1440 of the 1st to 1440th fan-out lines FL1440 may be electrically connected to the 1st to 720th data lines DL720 arranged in the first area A1 through the 1st to 720th bypass lines CL720 according to a reverse arrangement order.

[0196] According to the driving of the 4-way distributor 241, the first switch SW1 can be turned on in the first segment of a horizontal segment, the second switch SW2 can be turned on in the second segment of a horizontal segment, the third switch SW3 can be turned on in the third segment of a horizontal segment, and the fourth switch SW4 can be turned on in the fourth segment of a horizontal segment.

[0197] During the first segment, the first output line OL1 and the fifth output line OL5 of the 4-demultiplexer 241 electrically connected to the first switch SW1 can output data voltages. The first output channel CH1 electrically connected to the first output line OL1 and the second output channel CH2 electrically connected to the fifth output line OL5 can output data voltages.

[0198] refer to Figure 2 , the first output channel CH1 may output a data voltage corresponding to the fifth pixel P5 of the second area A2, and the second output channel CH2 may output a data voltage corresponding to the fourth pixel P4 of the first area A1.

[0199] During the second segment, the second output line OL2 and the sixth output line OL6 of the 4-demultiplexer 241 electrically connected to the second switch SW2 can output data voltages. The third output channel CH3 electrically connected to the second output line OL2 and the fourth output channel CH4 electrically connected to the sixth output line OL6 can output data voltages.

[0200] refer to Figure 2 , the 3rd output channel CH3 may output a data voltage corresponding to the sixth pixel P6 of the second area A2, and the 4th output channel CH4 may output a data voltage corresponding to the third pixel P3 of the first area A1.

[0201] During the third segment, the third output line OL3 and the seventh output line OL7 of the 4-demultiplexer 241 electrically connected to the third switch SW3 can output the data voltage. The fifth output channel CH5 electrically connected to the third output line OL3 and the sixth output channel CH6 electrically connected to the seventh output line OL7 can output the data voltage.

[0202] refer to Figure 2 , the 5th output channel CH5 may output a data voltage corresponding to the seventh pixel P7 of the second area A2, and the 6th output channel CH6 may output a data voltage corresponding to the second pixel P2 of the first area A1.

[0203] During the fourth segment, the fourth output line OL4 and the eighth output line OL8 of the 4-demultiplexer 241 electrically connected to the fourth switch SW4 can output the data voltage. The 7th output channel CH7 electrically connected to the fourth output line OL4 and the 8th output channel CH8 electrically connected to the eighth output line OL8 can output the data voltage.

[0204] refer to Figure 2 , the 7th output channel CH7 may output a data voltage corresponding to the eighth pixel P8 of the second area A2, and the 8th output channel CH8 may output a data voltage corresponding to the first pixel P1 of the first area A1.

[0205] As described above, the data driving circuit 240 including the 4-way demultiplexer 241 can electrically connect the 8N-7th, 8N-6th, 8N-5th, 8N-4th, 8N-3th, 8N-2th, 8N-1th and 8Nth output lines to multiple output channels CH1 to CH1440 of the data driving circuit 240 after the output lines are crossed.

[0206] Therefore, the odd (or even) numbered output channels CH1, CH3, ..., and CH1439 among the output channels CH1 to CH1440 of the data driving circuit 240 may be directly electrically connected to the data lines DL721 to DL1440, and the even (or odd) numbered output channels CH2, CH4, ..., and CH1440 of the output channels CH1 to CH1440 may be electrically connected to the data lines DL1 to DL720 through the bypass lines CL1 to CL720. The odd (or even) numbered output channels CH1, CH3, ..., and CH1439 of the data driving circuit 240 may output data voltages according to the arrangement order of the data lines DL721 to DL1440 arranged in the second area A2, and the even (or odd) numbered output channels CH2, CH4, ..., and CH1440 of the data driving circuit 240 may output data voltages according to the reverse arrangement order of the data lines DL1 to DL720 arranged in the first area A1.

[0207] Therefore, the order of data voltages output from the plurality of output channels CH1 to CH1440 of the data driving circuit 240 may be changed, and thus the arrangement of the fan-out lines FL1 to FL1440 may be simplified. As a result, the non-display area of ​​the display device 1000 may be reduced, and line resistance may be lowered.

[0208] Hereinafter, the same components as those of the previous embodiment will be described with reference to the same reference numerals, and the overlapping description will not be repeated.

[0209] Figure 8 is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure.

[0210] refer to Figure 8 , the display device 1000A may include a display portion DA on which an image is displayed and a peripheral portion PA adjacent to the display portion DA and at least partially surrounding the display portion DA.

[0211] The display portion DA may have a substantially rectangular shape having rounded sides defined in a first direction D1 and a second direction D2 perpendicular to the first direction D1 when viewed in a plan view.

[0212] The display portion DA may include a first side area LA and a second side area RA that are laterally symmetrical about a center line CT extending mainly in the first direction D1.

[0213] Each of the first side area LA and the second side area RA may include a first area A1, a second area A2, and a third area A3. The first area A1 refers to an area corresponding to a rounded side portion of the display part DA, the second area A2 refers to an area corresponding to a first straight side portion adjacent to the first area A1 corresponding to the rounded side portion, and the third area A3 refers to an area corresponding to a second straight side portion adjacent to the first straight side portion.

[0214] In the first side area LA, first to i-th data lines DL1 to DLi may be arranged, where i is a positive integer.

[0215] In addition, the 1st to kth data lines DL1 to DLk may be arranged in the first area A1 of the first side area LA, the k+1th to DLk+1th to DLmth data lines may be arranged in the second area A2 of the first side area LA, and the m+1th to DLm+1th to DLith data lines may be arranged in the third area A3 of the first side area LA, where k, m, and i are positive integers (k <m<i)。

[0216] The display portion DA may include a bypass line area CLA in which a plurality of bypass lines CL1 to CLk are arranged. In addition, first to kth bypass lines CL1 to CLk may be arranged in the first and second areas A1 and A2 of the first side area LA.

[0217] Each of the 1st to kth bypass lines CL1 to CLk may include a first straight line portion electrically connected to an end of a fan-out line arranged in the fan-out area, a crossing portion crossing the data lines arranged in the first and second areas A1 and A2, and a second straight line portion electrically connected to an end of the data line arranged in the first area A1.

[0218] For example, the first to k-th bypass lines CL1 to CLk may be electrically connected to the first to k-th data lines DL1 to DLk arranged in the first area A1.

[0219] The first to kth bypass lines CL1 to CLk may not be arranged in the third area A3 , but only the (m+1)th to (i)th data lines DLm+1 to DLi may be arranged in the third area A3 .

[0220] The second side area RA may include first, second, and third areas A1, A2, and A3 symmetrical to the first side area LA, and a plurality of data lines and bypass lines symmetrical to those arranged in the first side area LA may be arranged in the second side area RA.

[0221] The peripheral portion PA may include a first non-display area NDA1 and a second non-display area NDA2.

[0222] The first non-display area NDA1 may be an area extending mainly in the first direction D1 from straight side portions corresponding to the second and third areas A2 and A3 of the display part DA. The first non-display area NDA1 may not exist in a rounded side portion corresponding to the first area A1 of the display part DA.

[0223] The first non-display area NDA1 may include a pad area PDA and a fan-out area FOA. The fan-out area FOA may include a bending area BA.

[0224] Fig. 9 Is a description and Figure 8 The fan-out lines shown in FIG. 1 are electrically connected to a plan view of the output channels of a driving circuit.

[0225] In an exemplary embodiment of the present disclosure, the display device may include 1st to 2880th data lines, and the data driving circuit 300 may include 1st to 2880th output channels configured to output data voltages corresponding to the 1st to 2880th data lines.

[0226] refer to Figure 8 and Fig. 9 , the first side area LA and the second side area RA of the display portion DA may be laterally symmetrical (eg, mirror-symmetrical) with respect to the center line CT of the display portion DA.

[0227] Hereinafter, the structural relationship and interconnection relationship between the 1st data line DL1 to the 1440th data line DL1440 arranged in the first side area LA of the display part DA, the 1st bypass line CL1 to the 680th bypass line CL680, the 1st fan-out line FL1 to the 1440th fan-out line FL1440 arranged in the fan-out area FOA, and the 1st output channel CH1 to the 1440th output channel CH1440 of the data driving circuit 300 will be described.

[0228] The 1st to 1440th data lines DL1 to DL1440 may be sequentially arranged along a first lateral direction (eg, forward direction D21 ) of the second direction D2 .

[0229] The 1st data line DL1 to the 680th data line DL680 can be sequentially arranged in the first area A1 along the forward direction D21, the 681st data line DL681 to the 1360th data line DL1360 can be sequentially arranged in the second area A2 along the forward direction D21, and the 1361st data line DL1361 to the 1440th data line DL1440 can be sequentially arranged in the third area A3 along the forward direction D21.

[0230] The 1st to 1440th fan-out lines FL1 to FL1440 may be sequentially arranged along the advancing direction D21 .

[0231] Odd-numbered fan-out lines FL1, FL3, ..., and FL1359 among the 1st to 1360th data lines DL1 to DL1360 arranged in the first and second areas A1 and A2 may be sequentially electrically connected to the 681st to 1360th data lines DL681 to DL1360th data lines DL1360 arranged in the second area A2. Even-numbered fan-out lines FL2, FL4, ..., and FL1360 of the 1st to 1360th fan-out lines FL1 to FL1360 may be electrically connected to the 1st to 680th data lines DL680 arranged in the first area A1 through the 1st to 680th bypass lines CL1 to CL680 according to a reverse arrangement order.

[0232] The first straight line portions L1 of the 1st to 680th bypass lines CL1 to CL680 may be alternately arranged between the 681st to 1360th data lines DL681 to DL1360 arranged in the second area A2.

[0233] For example, the first straight line portion L1 of the first bypass line CL1 may be electrically connected to the end of the 1360th fan-out line FL1360 , and the second straight line portion L2 of the first bypass line CL1 may be electrically connected to the end of the first data line DL1 .

[0234] The first straight line portion L1 of the 680th bypass line CL680 may be electrically connected to the end of the 2nd fan-out line FL2 , and the second straight line portion L2 of the 680th bypass line CL680 may be electrically connected to the end of the 680th data line DL680 .

[0235] The data driving circuit 300 may include a plurality of output channels CH1 to CH1440 .

[0236] The 1st to 1440th output channels CH1 to CH1440 may be arranged along the forward direction D21 and may be electrically connected to the fan-out lines FL1 to FL1440 arranged in the forward direction D21.

[0237] Odd-numbered output channels CH1 , CH3 , . . . , and CH1359 among the 1st to 1360th output channels CH1 to CH1360 may output data voltages according to an arrangement order of the 681st to 1360th data lines DL681 to DL1360 arranged in the second area A2 .

[0238] Even-numbered output channels CH2, CH4, . . . , and CH1360 among the 1st to 1360th output channels CH1 to CH1360 may output data voltages according to a reverse arrangement order of the 1st to 680th data lines DL1 to DL680 arranged in the first area A1.

[0239] The 1361st to 1440th output channels CH1361 to CH1440 may output data voltages according to the arrangement order of the 1361st to 1440th data lines DL1361 to DL1440 arranged in the third area A3.

[0240] The odd (or even) numbered first output channels CH1, CH3, ..., and CH1359 among the output channels CH1 to CH1440 of the data driving circuit 300 can be directly electrically connected to the data lines DL681 to DL1360, the even (or odd) numbered first output channels CH2, CH4, ..., and CH1360 of the output channels CH1 to CH1440 can be electrically connected to the data lines DL1 to DL680 through the bypass lines CL1 to CL680, and the second output channels CH1361 to CH1440 among the output channels CH1 to CH1440 can be directly electrically connected to the data lines DL1361 to DL1440. The odd (or even) numbered first output channels CH1, CH3, ..., and CH1359 may output data voltages according to the arrangement order of the data lines DL681 to DL1360 arranged in the second area A2, the even (or odd) numbered first output channels CH2, CH4, ..., and CH1360 may output data voltages according to the reverse arrangement order of the data lines DL1 to DL680 arranged in the first area A1, and the second output channels CH1361 to CH1440 may output data voltages according to the arrangement order of the data lines DL1361 to DL1440 arranged in the third area A3.

[0241] Therefore, the order of data voltages output from the plurality of output channels CH1 to CH1440 of the data driving circuit 300 may be changed, and thus the arrangement of the fan-out lines FL1 to FL1440 may be simplified. As a result, the non-display area of ​​the display device 1000A may be reduced, and line resistance may be lowered.

[0242] like Figure 4 As shown in FIG. 1 , the data driving circuit 210 according to an exemplary embodiment of the present disclosure may include a 2-way demultiplexer 211 .

[0243] In this case, if Figure 4 As shown in , the 1st to 1360th fan-out lines FL1 to FL1360 corresponding to the 1st to 1360th data lines DL1 to DL1360 arranged in the first and second areas A1 and A2 may be electrically connected to the data lines DL1 to DL1360 and the bypass lines CL1 to CL680, in which the 4N-3rd, 4N-2nd, 4N-1st, and 4Nth fan-out lines are alternately arranged while some of the 4N-3rd, 4N-2nd, 4N-1st, and 4Nth fan-out lines are crossed (here, N is a positive integer). At the same time, as Fig. 9As shown in , the 1361st to 1440th fan-out lines FL1361 to FL1440 corresponding to the 1361st to 1440th data lines DL1361 to DL1440 arranged in the third area A3 may be directly electrically connected to the 1361st to 1440th data lines DL1361 to DL1440 in the third area A3 without crossing.

[0244] like Figure 5 As shown in , the data driving circuit 220 according to an exemplary embodiment of the present disclosure may include a 4-way demultiplexer 221 .

[0245] In this case, if Figure 5 As shown in , the 1st to 1360th fan-out lines FL1 to FL1360 corresponding to the 1st to 1360th data lines DL1 to DL1360 arranged in the first and second areas A1 and A2 may be electrically connected to the data lines DL1 to DL1360 and the bypass lines CL1 to CL680, in which some of the 8N-7th, 8N-6th, 8N-5th, 8N-4th, 8N-3rd, 8N-2nd, 8N-1st, and 8N-4th fan-out lines are alternately arranged while crossing (here, N is a positive integer). At the same time, as Fig. 9 As shown in , the 1361st to 1440th fan-out lines FL1361 to FL1440 corresponding to the 1361st to 1440th data lines DL1361 to DL1440 arranged in the third area A3 may be directly electrically connected to the 1361st to 1440th data lines DL1361 to DL1440 in the third area A3 without crossing.

[0246] like Figure 6 As shown in , the data driving circuit 230 according to an exemplary embodiment of the present disclosure may include a 2-demultiplexer 231 in which some of the 4N-3rd, 4N-2nd, 4N-1st, and 4Nth output lines are crossed (here, N is a positive integer).

[0247] In this case, if Figure 6 As shown in , the 1st to 1360th fan-out lines FL1 to FL1360 corresponding to the 1st to 1360th data lines DL1 to DL1360 arranged in the first and second areas A1 and A2 may be directly electrically connected to the alternately arranged data lines DL1 to DL1360 and bypass lines CL1 to CL680 without crossing. Fig. 9As shown in , the 1361st to 1440th fan-out lines FL1361 to FL1440 corresponding to the 1361st to 1440th data lines DL1361 to DL1440 arranged in the third area A3 may be directly electrically connected to the 1361st to 1440th data lines DL1361 to DL1440 in the third area A3 without crossing.

[0248] like Figure 7 As shown in , the data driving circuit 240 according to an exemplary embodiment of the present disclosure may include a 4-way demultiplexer 241 in which some of the 8N-7, 8N-6, 8N-5, 8N-4, 8N-3, 8N-2, 8N-1 and 8N output lines are crossed.

[0249] In this case, if Figure 7 As shown in , the 1st to 1360th fan-out lines FL1 to FL1360 corresponding to the 1st to 1360th data lines DL1 to DL1360 arranged in the first and second areas A1 and A2 may be directly electrically connected to the alternately arranged data lines DL1 to DL1360 and bypass lines CL1 to CL680 without crossing. Fig. 9 As shown in , the 1361st to 1440th fan-out lines FL1361 to FL1440 corresponding to the 1361st to 1440th data lines DL1361 to DL1440 arranged in the third area A3 may be directly electrically connected to the 1361st to 1440th data lines DL1361 to DL1440 in the third area A3 without crossing.

[0250] As described above, the order of the data voltages output from the plurality of output channels CH1 to CH1440 of the data driving circuits 200, 210, 220, 230, 240, and 300 can be changed, and thus the arrangement of the fan-out lines FL1 to FL1440 can be simplified. As a result, the non-display area of ​​the display devices 1000 and 1000A can be reduced, and the line resistance can be reduced.

[0251] The present invention can be applied to an organic light-emitting display device and an electronic device including the organic light-emitting display device. For example, the present invention can be applied to a cellular phone, a smart phone, a video phone, a smart tablet, a smart watch, a tablet computer (PC), a car navigation system or an infotainment console, a television, a computer monitor, a laptop computer, a head mounted display (HMD) device, etc.

[0252] The foregoing is an explanation of exemplary embodiments of the present disclosure and should not be construed as limiting the exemplary embodiments of the present disclosure. Although some exemplary embodiments of the present disclosure have been described, it will be readily understood by those skilled in the art that many modifications may be made to the disclosed structures and methods without departing substantially from the present disclosure.

Claims

1. A display device, comprising: A display portion having a rectangular area with at least one rounded edge, a plurality of data lines are arranged in the rectangular area, the display portion comprising a first area corresponding to the rounded edge portion and a second area corresponding to the straight edge portion and adjacent to the first area; a data driving circuit comprising a plurality of output channels configured to output data voltages, wherein odd-numbered output channels of the plurality of output channels output data voltages according to an arrangement order of data lines disposed in the second region, and wherein even-numbered output channels of the plurality of output channels output data voltages according to a reverse arrangement order of data lines disposed in the first region; and a plurality of fan-out lines, arranged in a fan-out region between the data driving circuit and the second region, the plurality of fan-out lines being electrically connected to the plurality of output channels, Wherein, all odd-numbered fan-out lines of the plurality of fan-out lines are formed by a first metal layer, and all even-numbered fan-out lines of the plurality of fan-out lines are formed by a second metal layer.

2. The display device according to claim 1, further comprising: A plurality of bypass lines are provided in the first area and the second area, Wherein, each of the plurality of bypass lines comprises: a first straight line portion disposed between the data lines disposed in the second region and including an end portion electrically connected to the fan-out line; a crossing portion crossing the data line; and A second straight line portion is provided between the data lines provided in the first region and includes an end portion electrically connected to the data line arranged in the first region.

3. The display device according to claim 2, wherein: The odd-numbered fan-out lines of the plurality of fan-out lines electrically connect the odd-numbered output channels to the data lines arranged in the second region, and the even-numbered fan-out lines of the plurality of fan-out lines electrically connect the even-numbered output channels to the bypass lines arranged in the second region.

4. The display device according to claim 1, wherein: The display portion further comprises: A third area is adjacent to the second area and corresponds to the straight side portion of the display portion.

5. The display device according to claim 4, wherein: The data driving circuit further comprises: A plurality of output channels are configured to output data voltages according to an arrangement sequence of the data lines arranged in the third region.

6. A display device comprising: A display portion having a rectangular area with at least one rounded edge, a plurality of data lines are arranged in the rectangular area, the display portion comprising a first area corresponding to the rounded edge portion and a second area corresponding to the straight edge portion and adjacent to the first area; A data driving circuit, comprising: an n-multiplexer configured to output a data voltage for each group formed by binding every n output channels; and a plurality of output channels configured to output a plurality of data voltages, wherein the output channels of the odd-numbered groups output the data voltages according to an arrangement order of the data lines arranged in the second area, and the output channels of the even-numbered groups output the data voltages according to a reverse arrangement order of the data lines arranged in the first area; and a plurality of fan-out lines, arranged in a fan-out region between the data driving circuit and the second region, the plurality of fan-out lines being electrically connected to the plurality of output channels, Wherein, all odd-numbered fan-out lines of the plurality of fan-out lines are formed by a first metal layer, and all even-numbered fan-out lines of the plurality of fan-out lines are formed by a second metal layer.

7. The display device according to claim 6, further comprising: A plurality of bypass lines are provided in the first area and the second area, Wherein, each of the plurality of bypass lines comprises: a first straight line portion disposed between the data lines disposed in the second region and including an end portion electrically connected to the fan-out line; a crossing portion crossing the data line; and A second straight line portion is provided between the data lines provided in the first region and includes an end portion electrically connected to the data line arranged in the first region.

8. The display device according to claim 7, wherein: When the data driving circuit includes a 2-multiplexer, a 4N-3 fan-out line electrically connected to a 4N-3 output channel is electrically connected to a first data line arranged in the second area, a 4N-2 fan-out line electrically connected to a 4N-2 output channel is electrically connected to a second data line arranged in the second area, a 4N-1 fan-out line electrically connected to a 4N-1 output channel is electrically connected to a first straight line portion of a first bypass line between the first data line and the second data line arranged in the second area, and a 4N fan-out line electrically connected to a 4N output channel is electrically connected to a first straight line portion of a second bypass line between the second data line and a third data line arranged in the second area, wherein N is a positive integer.

9. The display device according to claim 7, wherein: When the data driving circuit includes a 4-way demultiplexer, the 8N-7th fan-out line electrically connected to the 8N-7th output channel is electrically connected to the first data line arranged in the second area, the 8N-6th fan-out line electrically connected to the 8N-6th output channel is electrically connected to the second data line arranged in the second area, the 8N-5th fan-out line electrically connected to the 8N-5th output channel is electrically connected to the third data line arranged in the second area, the 8N-4th fan-out line electrically connected to the 8N-4th output channel is electrically connected to the fourth data line arranged in the second area, and the 8N-3rd fan-out line electrically connected to the 8N-3rd output channel is electrically connected to the first data line arranged in the second area. The 8N-2 fan-out line electrically connected to the 8N-2 output channel is electrically connected to the first straight line portion of the second bypass line between the second data line and the third data line arranged in the second area, the 8N-1 fan-out line electrically connected to the 8N-1 output channel is electrically connected to the first straight line portion of the third bypass line between the third data line and the fourth data line arranged in the second area, and the 8N fan-out line electrically connected to the 8N output channel is electrically connected to the first straight line portion of the fourth bypass line between the fourth data line and the fifth data line arranged in the second area, wherein N is a positive integer.

10. The display device according to claim 7, wherein: The display portion further comprises: The third region is adjacent to the second region and corresponds to the straight side portion.

11. The display device according to claim 10, wherein: The data driving circuit further comprises: A plurality of output channels are configured to output data voltages according to an arrangement sequence of the data lines arranged in the third region.

12. A display device comprising: A display portion having a rectangular area with at least one rounded edge, a plurality of data lines are arranged in the rectangular area, the display portion comprising a first area corresponding to the rounded edge portion and a second area corresponding to the straight edge portion and adjacent to the first area; A data driving circuit, comprising: an n-multiplexer configured to output a data voltage for each group formed by binding every n output lines; and a plurality of output channels electrically connected to the plurality of output lines of the n-multiplexer, wherein odd-numbered output channels of the plurality of output channels output data voltages according to an arrangement order of the data lines arranged in the second area, and even-numbered output channels of the plurality of output channels output data voltages according to a reverse arrangement order of the data lines arranged in the first area; and a plurality of fan-out lines, arranged in a fan-out region between the data driving circuit and the second region, the plurality of fan-out lines being electrically connected to the plurality of output channels, Wherein, all odd-numbered fan-out lines of the plurality of fan-out lines are formed by a first metal layer, and all even-numbered fan-out lines of the plurality of fan-out lines are formed by a second metal layer.

13. The display device according to claim 12, further comprising: A plurality of bypass lines are provided in the first area and the second area, Wherein, each of the plurality of bypass lines includes: a first straight line portion, which is arranged between the data lines arranged in the second area and includes an end portion electrically connected to the fan-out line; a crossing portion, which crosses the data line; and a second straight line portion, which is arranged between the data lines arranged in the first area and includes an end portion electrically connected to the data line arranged in the first area.

14. The display device according to claim 12, wherein: When the data driving circuit includes a 2-way demultiplexer, the 4N-3 output line is electrically connected to the 4N-3 output channel, the 4N-2 output line is electrically connected to the 4N-1 output channel, the 4N-1 output line is electrically connected to the 4N-2 output channel, and the 4N output line is electrically connected to the 4N output channel, where N is a positive integer.

15. The display device according to claim 12, wherein: When the data driving circuit includes a 4-way demultiplexer, the 8N-7th output line is electrically connected to the 8N-7th output channel, the 8N-6th output line is electrically connected to the 8N-5th output channel, the 8N-5th output line is electrically connected to the 8N-3th output channel, the 8N-4th output line is electrically connected to the 8N-1th output channel, the 8N-3th output line is electrically connected to the 8N-6th output channel, the 8N-2th output line is electrically connected to the 8N-4th output channel, the 8N-1th output line is electrically connected to the 8N-2th output channel, and the 8Nth output line is electrically connected to the 8N-1th output channel, where N is a positive integer.

16. The display device according to claim 12, wherein: The display portion further comprises: The third region is adjacent to the second region and corresponds to the straight side portion.

17. The display device according to claim 16, wherein: The data driving circuit further comprises: A plurality of output channels are configured to output data voltages according to an arrangement sequence of the data lines arranged in the third region.

Images