HEMT (High Electron Mobility Transistor) integrated luminous chip, preparation method thereof, epitaxial wafer and display backboard

Abstract

The invention discloses an HEMT integrated light-emitting chip and a preparation method thereof, an epitaxial wafer and a display backboard, the HEMT integrated light-emitting chip comprises an N-type semiconductor layer, an intrinsic semiconductor layer, a first quantum well layer and a second quantum well layer which are stacked in sequence from bottom to top, the first quantum well layer and the second quantum well layer are different in light-emitting color, and the energy band widths of the first quantum well layer and the second quantum well layer are reduced in sequence; the second quantum well layer is arranged on the second light-emitting area on the first quantum well layer, barrier layers and P-type semiconductor layers which are stacked in sequence are arranged on the first light-emitting area on the first quantum well layer and the second quantum well layer, and source electrodes are correspondingly arranged on the P-type semiconductor layers; each barrier layer is provided with a grid electrode which is arranged at an interval with the P-type semiconductor layer; the N-type semiconductor layer is provided with a common drain electrode which is connected with the N-type semiconductor layer and penetrates through the electrode hole. The HEMT integrated light-emitting chip manufactured through the method is more compact in structure, high in dimming capacity and higher in light-emitting efficiency, and single-color and double-color display is achieved.

Description

Technical Field

[0001] This application relates to the field of display, and in particular to a HEMT integrated light-emitting chip and its fabrication method, epitaxial wafer, and display backplane. Background Technology

[0002] HEMT (High Electron Mobility Transistor) and LED (Light Emitting Diode) are devices with significant applications in the electronics and optoelectronics fields, possessing enormous potential and a wide range of applications. HEMT is a high electron mobility transistor that exhibits excellent performance in high-frequency and microwave circuits, and is commonly used in RF power amplifiers, microwave receivers, and RF switches. LED is a semiconductor device that converts electrical energy into light energy, and is widely used in lighting, displays, and communications.

[0003] In recent years, with the development of electronic and optoelectronic integration technology, how to apply HEMT to MicroLED has become a challenge in this field. Chinese patent document CN117153961A discloses an integrated backplane for driving MicroLEDs using HEMT and its fabrication method. The method includes growing an HEMT epitaxial structure on a substrate, sequentially growing three monochromatic LED epitaxial structures on the HEMT epitaxial structure to obtain an epitaxial wafer, etching to partition the epitaxial wafer on the substrate, depositing a passivation layer, etching vias, and then depositing conductors to connect the n-GaN layers of the three LED regions to one HEMT region, and connecting the remaining three HEMT regions to the p-GaN layer of one LED region. This method places the epitaxial layers of the three-color LED devices on the HEMT structure layer, representing a design for applying HEMT to the MicroLED display field. However, there are still many limitations in further fabricating dual-color MicroLED structures with strong dimming capabilities and high luminous efficiency. Summary of the Invention

[0004] In view of the shortcomings of the above-mentioned related technologies, the purpose of this application is to provide a HEMT integrated light-emitting chip and its preparation method, epitaxial wafer, and display backplane, which have a more compact structure, strong dimming capability and higher luminous efficiency, and realize monochrome and dual-color display.

[0005] This application provides an HEMT integrated light-emitting chip, comprising an N-type semiconductor layer, an intrinsic semiconductor layer, a first quantum well layer, and a second quantum well layer stacked sequentially from bottom to top. The first quantum well layer and the second quantum well layer emit different colors, and the band widths of the first quantum well layer and the second quantum well layer decrease sequentially. The first quantum well layer includes a first light-emitting region and a second light-emitting region. The second quantum well layer is disposed on the second light-emitting region. A first barrier layer and a first P-type semiconductor layer are sequentially stacked on the surface of the first light-emitting region. A first source is disposed on the first P-type semiconductor layer, and a first gate is disposed on the first barrier layer at a distance from the first P-type semiconductor layer. A second barrier layer and a second P-type semiconductor layer are sequentially stacked on the surface of the second quantum well layer. A second source is disposed on the second P-type semiconductor layer, and a second gate is disposed on the second barrier layer at a distance from the second P-type semiconductor layer. A common drain is disposed on the N-type semiconductor layer and connected to it and passing through the intrinsic semiconductor or sequentially passing through the intrinsic semiconductor layer and the exposed first quantum well layer.

[0006] Optionally, the first quantum well layer corresponding to the first light-emitting region and the first quantum well layer corresponding to the second light-emitting region are spaced apart.

[0007] Optionally, the common drain electrode is disposed between the first light-emitting region and the second light-emitting region.

[0008] Optionally, both the first quantum well layer and the second quantum well layer include at least one of the following: an In-doped InGaN layer, an Al-doped AlGaN layer, an undoped GaN layer, and an In- and Al-doped AlGaInN layer.

[0009] Optionally, both the first quantum well layer and the second quantum well layer are In-doped InGaN layers; the In doping content of the first quantum well layer and the second quantum well layer increases sequentially.

[0010] Optionally, the first quantum well layer is a blue quantum well layer and the second quantum well layer is a green quantum well layer; or the first quantum well layer is a blue quantum well layer and the second quantum well layer is a red quantum well layer; or the first quantum well layer is a green quantum well layer and the second quantum well layer is a red quantum well layer.

[0011] Optionally, both the first barrier layer and the second barrier layer include at least one of AlN barrier layer and AlGaN barrier layer.

[0012] Optionally, both the first barrier layer and the second barrier layer are Al-doped AlGaN barrier layers.

[0013] Optionally, the N-type semiconductor layer includes at least one of an N-type GaN layer, an N-type AlGaN layer, and an N-type InGaN layer; The first P-type semiconductor layer and the second P-type semiconductor layer are made of the same material. The first P-type semiconductor layer includes at least one of a P-type GaN layer, a P-type AlGaN layer, and a P-type InGaN layer.

[0014] Optionally, the buffer layer is an undoped uGaN buffer layer, the N-type semiconductor layer is an N-type GaN layer, and both the first P-type semiconductor layer and the second P-type semiconductor layer are P-type GaN layers.

[0015] Optionally, the HEMT integrated light-emitting chip can be a MiniLED or a MicroLED.

[0016] Optionally, it also includes a substrate and a buffer layer, wherein the buffer layer and the substrate are stacked sequentially on the side of the N-type semiconductor layer away from the intrinsic semiconductor layer.

[0017] This application also provides an HEMT integrated epitaxial wafer for fabricating the HEMT integrated light-emitting chip, comprising a substrate, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a dual-color quantum well layer stacked sequentially from bottom to top. The dual-color quantum well layer includes a primary first quantum well layer and a primary second quantum well layer stacked sequentially on the intrinsic semiconductor layer. The primary first quantum well layer and the primary second quantum well layer emit different colors, and the band widths of the primary first quantum well layer and the primary second quantum well layer decrease sequentially.

[0018] Optionally, growing a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a dual-color quantum well layer sequentially from bottom to top on the surface of the substrate includes performing the following steps: Under a first preset temperature and a first preset pressure, a buffer layer of a first preset thickness is grown on the surface of the substrate; Under a second preset temperature and a second preset pressure, an N-type semiconductor layer of a second preset thickness is grown on the surface of the buffer layer; An intrinsic semiconductor layer of a third preset thickness is grown on the surface of the N-type semiconductor layer at a third preset temperature and a third preset pressure. Under a fourth preset temperature and a fourth preset pressure, the original first quantum well layer of a fourth preset thickness is grown on the surface of the intrinsic semiconductor layer; Under a fifth preset temperature and a fifth preset pressure, the original second quantum well layer of a fifth preset thickness is grown on the surface of the original first quantum well layer; The sequential growth of the barrier layer and the P-type semiconductor layer includes performing the following steps: Under a sixth preset temperature and a sixth preset pressure, a barrier layer of a sixth preset thickness is grown on the etched epitaxial wafer; At a seventh preset temperature and a seventh preset pressure, a P-type semiconductor layer of a seventh preset thickness is grown on the surface of the barrier layer.

[0019] Optionally, the original first quantum well layer and the original second quantum well layer are made of the same material.

[0020] This application also provides a method for fabricating a HEMT integrated light-emitting chip, the method comprising the following steps: The HEMT integrated epitaxial wafer is provided, comprising a substrate, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a dual-color quantum well layer stacked sequentially from bottom to top. The dual-color quantum well layer comprises a primary first quantum well layer and a primary second quantum well layer stacked sequentially on the intrinsic semiconductor layer. The primary first quantum well layer and the primary second quantum well layer emit different colors, and the band widths of the primary first quantum well layer and the primary second quantum well layer decrease sequentially. The dual-color quantum well stack is etched to form a first quantum well layer and a second quantum well layer stacked on the first quantum well layer. The first quantum well layer includes a first light-emitting region and a second light-emitting region, and the second quantum well layer is disposed on the second light-emitting region. A barrier layer and a P-type semiconductor layer are grown sequentially. The P-type semiconductor layer and the barrier layer are etched sequentially to form a first barrier layer and a first P-type semiconductor layer that are sequentially stacked on the first light-emitting region, and a second barrier layer and a second P-type semiconductor layer that are sequentially stacked on the second quantum well layer. Etching the intrinsic semiconductor layer or sequentially etching the exposed first quantum well layer and the intrinsic semiconductor layer until the N-type semiconductor layer is exposed to form an electrode hole; An electrode layer is grown on the epitaxial wafer and inside the electrode holes after the electrode holes have been etched. The electrode layer is etched to form a first source and a second source respectively disposed on the first P-type semiconductor layer and the second P-type semiconductor layer, a first gate and a second gate respectively disposed on the first barrier layer and the second barrier layer, and a common drain connected to the exposed N-type semiconductor layer and passing through the electrode hole; the first source is connected to the first P-type semiconductor layer, and the first gate is spaced apart from the first P-type semiconductor layer; the second source is connected to the second P-type semiconductor layer, and the second gate is spaced apart from the second P-type semiconductor layer, to obtain a HEMT integrated light-emitting chip.

[0021] Optionally, the etching of the dual-color quantum well stack to form a first quantum well layer and a second quantum well layer stacked on the first quantum well layer, wherein the first quantum well layer includes a first light-emitting region and a second light-emitting region, and the second quantum well layer is disposed on the second light-emitting region; includes the following steps: The original second quantum well layer is etched down to the original first quantum well layer to obtain a second quantum well layer stacked on the first quantum well layer. The first quantum well layer includes a first light-emitting region and a second light-emitting region, and the second quantum well layer is disposed on the second light-emitting region.

[0022] Optionally, after obtaining the second quantum well layer, the following steps are also included: The first quantum well layer between the first light-emitting region and the second light-emitting region is etched down to the intrinsic semiconductor layer, such that the first quantum well layer corresponding to the first light-emitting region and the first quantum well layer corresponding to the second light-emitting region are spaced apart.

[0023] Optionally, after etching the electrode layer to form a first source and a second source respectively disposed on the first P-type semiconductor layer and the second P-type semiconductor layer, a first gate and a second gate respectively disposed on the first barrier layer and the second barrier layer, and a common drain connected to the exposed N-type semiconductor layer and passing through the electrode via; the first source is connected to the first P-type semiconductor layer, and the first gate is spaced apart from the first P-type semiconductor layer; the second source is connected to the second P-type semiconductor layer, and the second gate is spaced apart from the second P-type semiconductor layer, the process further includes the following step: The buffer layer is disassembled to peel off the substrate.

[0024] This application also provides a display backplane, including a driving substrate and the HEMT integrated light-emitting chip, wherein the HEMT integrated light-emitting chip is bonded to the driving substrate.

[0025] This application presents a HEMT integrated light-emitting chip that combines HEMT and LED, resulting in a more compact structure. Unlike traditional HEMT structures where an additional LED structure is grown on top of the HEMT structure, this structure cleverly combines the two to form a novel structure that simultaneously satisfies the definitions of both structures. This allows the structure to both exhibit the characteristics of HEMT structure's independent control and signal enhancement, while also satisfying the light-emitting characteristics of LED structure. The fabrication of a two-dimensional electron gas within the quantum well using the HEMT structure significantly improves electron migration efficiency, thereby increasing the number of electrons and holes emitting light in the active region, reducing the turn-on voltage, and increasing the luminous brightness. By controlling the presence and concentration of holes within the quantum well layer through the energization of the drain electrode, monochromatic and dual-color light emission can be controlled. Furthermore, the concentration of the two-dimensional electron gas is controlled by the magnitude of the voltage applied to the two gates, adjusting the ratio of luminous brightness between the two colors. This allows for free mixing of light, resulting in strong dimming capabilities and higher luminous efficiency, enabling monochromatic and dual-color displays. Utilizing a common-drain structure and a pre-epitaxy-then-growth method, only epitaxy followed by etching and electrode evaporation is required, reducing the complexity of the manufacturing process. By reducing the number of layers and thickness required for epitaxy, miniaturization is achieved while reducing the distance that electrons and holes need to migrate, thus improving photoelectric performance and reducing the impact of lattice adaptation caused by multilayer growth. Attached Figure Description

[0026] Figure 1 A schematic diagram of the structure of the grown quantum well layer is provided for the embodiments of this application; Figure 2 This is a schematic diagram of the etched quantum well layer provided in an embodiment of this application; Figure 3 A schematic diagram of the growth barrier layer and electrode layer provided in an embodiment of this application; Figure 4 This is a schematic diagram of the etch barrier layer and electrode layer provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of the HEMT integrated light-emitting chip provided in the embodiments of this application; Figure 6 A flowchart illustrating the fabrication method of the HEMT integrated light-emitting chip provided in this application embodiment; Figure 7 A schematic diagram of the formation of a two-dimensional electron gas provided in an embodiment of this application; Figure 8 A schematic diagram illustrating the migration of electrons in the blue and green quantum well layers, as provided in an embodiment of this application.

[0027] Explanation of reference numerals in the attached figures: 1-Substrate; 2-Buffer layer; 3-N-type semiconductor layer; 4-Intrinsic semiconductor layer; 5-Original first quantum well layer; 5'-First quantum well layer; 6-Original second quantum well layer; 6'-Second quantum well layer; 7-Barrier layer; 71-First barrier layer; 72-Second barrier layer; 8-P-type semiconductor layer; 81-First P-type semiconductor layer; 82-Second P-type semiconductor layer; Q1-First light-emitting region; Q2-Second light-emitting region; D1-First source; D2-Second source; G1-First gate; G2-Second gate; S-Common drain; A-Electrode hole. Detailed Implementation

[0028] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0030] In the description of this application, the terms "first," "second," etc., are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0031] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] The specific embodiments of this application will be further described below with reference to the accompanying drawings.

[0033] See Figure 5As shown in the figure, this application discloses an HEMT integrated light-emitting chip, characterized in that it includes an N-type semiconductor layer 3, an intrinsic semiconductor layer 4, a first quantum well layer 5', and a second quantum well layer 6' stacked sequentially from bottom to top. The first quantum well layer 5' and the second quantum well layer 6' emit different colors, and their band widths decrease sequentially. The first quantum well layer 5' includes a first light-emitting region Q1 and a second light-emitting region Q2. The second quantum well layer 6' is disposed on the second light-emitting region Q2. A first barrier layer 71 and a first P-type semiconductor are sequentially stacked on the surface of the first light-emitting region Q1. Layer 81, the first P-type semiconductor layer 81 is provided with a first source D1, the first barrier layer 71 is provided with a first gate G1 disposed at a distance from the first P-type semiconductor layer 81; a second barrier layer 72 and a second P-type semiconductor layer 82 are sequentially stacked on the surface of the second quantum well layer 6', the second P-type semiconductor layer 82 is provided with a second source D2, the second barrier layer 72 is provided with a second gate G2 disposed at a distance from the second P-type semiconductor layer 82; the N-type semiconductor layer 3 is provided with a common drain S connected to it and passing through the intrinsic semiconductor 4 or sequentially passing through the intrinsic semiconductor layer 4 and the exposed first quantum well layer 5'.

[0034] This application presents a HEMT integrated light-emitting chip that combines HEMT and LED, resulting in a more compact structure. Unlike traditional methods that involve growing an additional LED structure on top of a HEMT structure, this structure cleverly combines the two to form a novel structure that simultaneously satisfies the definitions of both. This allows the structure to exhibit the characteristics of HEMT structure's independent control and signal enhancement while also satisfying the light-emitting characteristics of LED structure. By utilizing the HEMT structure to prepare a two-dimensional electron gas within the quantum well, electron migration efficiency is significantly improved, thereby increasing the number of electrons and holes emitting light in the active region, reducing the turn-on voltage, and increasing the luminous brightness. The presence and concentration of holes within the quantum well layer are controlled by energizing the drain electrode (D), enabling the regulation of monochromatic and dual-color light emission. Furthermore, the concentration of the two-dimensional electron gas is controlled by the magnitude of the voltage applied to the two gates, thus adjusting the ratio of luminous brightness between the two colors. This allows for free mixing of light, resulting in strong dimming capabilities and higher luminous efficiency, enabling both monochromatic and dual-color displays.

[0035] In this embodiment, the exposed first quantum well layer 5' refers to the portion other than the portion overlapping with the first quantum well layer 5'. The portion overlapping with the first quantum well layer 5' includes the portion where the first barrier layer 71 and the second quantum well layer 6' overlap with the first quantum well layer 5'.

[0036] The HEMT integrated light-emitting chip of this application uses a source electrode for injecting holes, which migrate towards the quantum well layer. The common drain electrode (S) is used to inject electrons into the N-type semiconductor layer (3), which also migrate towards the quantum well layer. By utilizing the applied voltage to the gate, the concentration of the two-dimensional electron gas and the depth of the channel can be controlled, thereby modulating the luminous intensity and ultimately achieving a light mixing effect. See also... Figure 7 As shown, when an external voltage is applied to the gate, electrons continuously migrate upwards under the influence of the applied voltage. Simultaneously, due to the wider bandgap of the barrier layer 7 and the lower energy level of the quantum well layer, electrons are trapped within the well. Furthermore, because the width of the well is very small, a two-dimensional electron gas is formed at the quantum well layer. When the second quantum well layer 6' overlaps with the first quantum well layer 5', since the bandgap of the second quantum well layer 6' is lower than that of the first quantum well layer 5', electrons do not accumulate in the first quantum well layer 5' but instead form a 2DEG channel in the second quantum well layer 6'. For example, see [link to example]. Figure 8 As shown, if the first quantum well layer 5' is a blue quantum well layer and the second quantum well layer 6' is a green quantum well layer, because the energy level of the green quantum well layer is lower, electrons will not accumulate in the blue quantum well layer. Instead, a two-dimensional electron gas (2DEG) will form in the green quantum well layer, whose thickness is much smaller than that of the green quantum well layer. Therefore, the blue quantum well layer does not have a high-concentration electron channel for electron-hole recombination. At the same time, the electron migration in the 2DEG is much greater than that of holes, and the holes will be rapidly depleted at the channel and will not diffuse. Furthermore, because the green quantum well layer has the smallest bandgap, an additional quantum well will actually form at the green light location. This will further restrict the leakage of holes to the blue quantum well layer, ensuring that the blue quantum well layer does not emit light.

[0037] When emitting light in two colors, by controlling the number of holes injected into the first source D1 and the second source D2, the number of electrons injected into the common drain S, and the magnitude of the gate voltage, a 2DEG channel can be formed in the first quantum well layer 5' and the second quantum well layer 6', respectively. At each 2DEG channel, electrons and holes recombine to achieve emitting light in two colors.

[0038] Monochromatic or bicolor light emission can be achieved by controlling the energization of the first source D1 and / or the second source D2. When no source is energized, there is only electron gas in the quantum well layer, and no hole recombination occurs, so no light is emitted, which is equivalent to the positive electrode wire being broken, forming an open circuit. By energizing the first source D1 and / or the second source D2, the first quantum well layer 5' can be controlled to emit a first color light, the second quantum well layer 6' to emit a second color light, and to emit mixed light. For example, the first quantum well layer 5' is a blue quantum well layer, and the second quantum well layer 6' is a green quantum well layer. When emitting bicolor light, voltages V1 and V2 are applied to the first gate G1 and the second gate G2, respectively. Voltage V2 is greater than voltage V1. At this time, the electron gas concentration in the green quantum well layer is greater, the brightness is stronger, and blue-green mixed light is emitted. In this embodiment, the first quantum well layer 5' corresponding to the first light-emitting region Q1 and the first quantum well layer 5' corresponding to the second light-emitting region Q2 are spaced apart. This means that the first quantum well layer 5' corresponding to the first light-emitting region Q1 and the first quantum well layer 5' corresponding to the second light-emitting region Q2 are two unconnected parts.

[0039] In this embodiment, the common drain S is disposed between the first light-emitting region Q1 and the second light-emitting region Q2. In this case, the common drain S is connected to the N-type semiconductor layer and passes through the intrinsic semiconductor 4, and the first quantum well layer 5' between the first light-emitting region Q1 and the second light-emitting region Q2 has been etched away. In another embodiment, the common drain S is connected to the N-type semiconductor layer 3 and sequentially passes through the intrinsic semiconductor layer 4 and the exposed first quantum well layer 5'. In this case, the exposed first quantum well layer 5' can be the first quantum well layer 5' exposed on either the first light-emitting region Q1 or the second light-emitting region Q2.

[0040] In this embodiment, both the first quantum well layer 5' and the second quantum well layer 6' include at least one of the following: an In-doped InGaN layer, an Al-doped AlGaN layer, an undoped GaN layer, and an In-doped or Al-doped AlGaInN layer. The emission color of the first quantum well layer 5' and the second quantum well layer 6' can be adjusted according to the content of In or Al doping. Optionally, both the first quantum well layer 5' and the second quantum well layer 6' are In-doped InGaN layers; the In doping content of the first quantum well layer 5' and the second quantum well layer 6' increases sequentially. The In doping concentration of the first quantum well layer 5' and the second quantum well layer 6' ranges from 1E17cm / VS to 5E17cm / VS.

[0041] In this embodiment, the first quantum well layer 5' is a blue quantum well layer and the second quantum well layer 6' is a green quantum well layer; or the first quantum well layer 5' is a blue quantum well layer and the second quantum well layer 6' is a red quantum well layer; or the first quantum well layer 5' is a green quantum well layer and the second quantum well layer 6' is a red quantum well layer. For example, the energy barrier height of the blue quantum well layer is higher than that of the green quantum well layer and lower than that of the intrinsic semiconductor layer 4, and much lower than that of the barrier layer 7. When electrons migrate upwards, they can smoothly migrate to the green quantum well layer without being blocked by the high energy barrier of the barrier layer 7, ensuring that the green quantum well layer can emit light smoothly.

[0042] In this embodiment, both the first barrier layer 71 and the second barrier layer 72 include at least one of an AlN barrier layer and an AlGAN barrier layer. Optionally, both the first barrier layer 71 and the second barrier layer 72 are Al-doped AlGAN barrier layers.

[0043] In this embodiment, the buffer layer 2 includes at least one of a uGAN buffer layer, an AlN buffer layer, and an AlGAN / GAN superlattice buffer layer. Optionally, the buffer layer 2 is an undoped uGAN buffer layer.

[0044] In this embodiment, the N-type semiconductor layer 3 includes at least one of an N-type GAN layer, an N-type AlGAN layer, and an N-type InGAN layer. Optionally, the N-type semiconductor layer 3 is an N-type GAN layer.

[0045] In this embodiment, the first P-type semiconductor layer 81 and the second P-type semiconductor layer 82 are made of the same material. The first P-type semiconductor layer 81 includes at least one of a P-type GAN layer, a P-type AlGAN layer, and a P-type InGAN layer. Optionally, both the first P-type semiconductor layer 81 and the second P-type semiconductor layer 82 are P-type GAN layers.

[0046] In this embodiment, the substrate 1 includes at least one of sapphire, silicon, silicon carbide, and gallium nitride. Optionally, the substrate 1 is a sapphire substrate.

[0047] In this embodiment, a substrate 1 and a buffer layer 2 are also included. The buffer layer 2 and the substrate 1 are sequentially stacked on the side of the N-type semiconductor layer 3 away from the intrinsic semiconductor layer 4. The HEMT integrated light-emitting chip of this application can be manufactured without removing the substrate 1, although the light-emitting efficiency will be slightly reduced compared to removing the substrate 1.

[0048] See Figure 1 As shown in the embodiment of this application, a HEMT integrated epitaxial wafer is also disclosed. The wafer is characterized in that it is used to fabricate the aforementioned HEMT integrated light-emitting chip and includes, from bottom to top, a substrate 1, a buffer layer 2, an N-type semiconductor layer 3, an intrinsic semiconductor layer 4, and a dual-color quantum well layer. The dual-color quantum well layer includes a primary first quantum well layer 5 and a primary second quantum well layer 6 sequentially stacked on the intrinsic semiconductor layer 4. The primary first quantum well layer 5 and the primary second quantum well layer 6 emit different colors, and the band widths of the primary first quantum well layer 5 and the primary second quantum well layer 6 decrease sequentially.

[0049] In this embodiment, the step of growing a buffer layer 2, an N-type semiconductor layer 3, an intrinsic semiconductor layer 4, and a dual-color quantum well layer sequentially from bottom to top on the surface of the substrate 1 includes performing the following steps: Under a first preset temperature and a first preset pressure, a buffer layer 2 of a first preset thickness is grown on the surface of the substrate 1; wherein the first preset temperature ranges from 1020℃ to 1080℃, the first preset pressure ranges from 200mbAr to 600mbAr, and the first preset thickness ranges from 1.5μm to 2μm. Under a second preset temperature and a second preset pressure, an N-type semiconductor layer 3 of a second preset thickness is grown on the surface of the buffer layer 2; wherein the value of the second preset temperature ranges from 1040℃ to 1060℃, the value of the second preset pressure ranges from 200mbAr to 400mbAr, the value of the second preset thickness ranges from 1.5μm to 2μm, and the N-type doping concentration of the N-type semiconductor layer 3 ranges from 6E18cm / VS to 3E19cm / VS; Under a third preset temperature and a third preset pressure, an intrinsic semiconductor layer 4 of a third preset thickness is grown on the surface of the N-type semiconductor layer 3; wherein the value of the third preset temperature ranges from 700℃ to 800℃, the value of the third preset pressure ranges from 200mbAr to 400mbAr, and the value of the third preset thickness ranges from 100nm to 200nm. Under a fourth preset temperature and a fourth preset pressure, the original first quantum well layer 5 with a fourth preset thickness is grown on the surface of the intrinsic semiconductor layer 4; wherein the value of the fourth preset temperature is in the range of 650℃~800℃, the value of the fourth preset pressure is in the range of 200mbAr~400mbAr, the value of the fourth preset thickness is in the range of 80nm~200nm, and the value of the number of loops of the original first quantum well layer 5 is in the range of 5~8. Under a fifth preset temperature and a fifth preset pressure, the original second quantum well layer 6 with a fifth preset thickness is grown on the surface of the original first quantum well layer 5; the fifth preset temperature ranges from 620℃ to 770℃, the fifth preset pressure ranges from 200mbAr to 400mbAr, and the fifth preset thickness ranges from 80nm to 200nm; the number of cycles of the original second quantum well layer 6 ranges from 5 to 8.

[0050] In this embodiment, the sequential growth of the barrier layer 7 and the P-type semiconductor layer 8 includes performing the following steps: Under a sixth preset temperature and a sixth preset pressure, a barrier layer 7 of a sixth preset thickness is grown on the etched epitaxial wafer; the sixth preset temperature ranges from 800℃ to 950℃, the sixth preset pressure ranges from 100mbAr to 200mbAr, and the sixth preset thickness ranges from 30nm to 50nm. At a seventh preset temperature and a seventh preset pressure, a P-type semiconductor layer 8 of a seventh preset thickness is grown on the surface of the barrier layer 7. The seventh preset temperature ranges from 800°C to 900°C, the seventh preset pressure ranges from 200 mbAr to 600 mbAr, the seventh preset thickness ranges from 50 nm to 80 nm, and the P-type doping concentration ranges from 1E19 cm / VS to 2E20 cm / VS. This can be achieved by growing the layer on an MOCVD using TMGA / TEGA and NH3 as a Group III metal source and a Group V compound.

[0051] Optionally, the original first quantum well layer 5 and the original second quantum well layer 6 are made of the same material. For example, both the first quantum well layer 5 and the original second quantum well layer 6 are made of In-doped InGaN layers; however, their doping concentrations may be different or the same.

[0052] See Figures 1 to 6 As shown in the figure, this application discloses a method for fabricating a HEMT integrated light-emitting chip, which is used in the above-mentioned HEMT integrated light-emitting chip. The steps include: The above-mentioned HEMT integrated epitaxial wafer is provided. The HEMT integrated epitaxial wafer includes a substrate 1, a buffer layer 2, an N-type semiconductor layer 3, an intrinsic semiconductor layer 4, and a dual-color quantum well layer stacked sequentially from bottom to top. The dual-color quantum well layer includes a primary first quantum well layer 5 and a primary second quantum well layer 6 stacked sequentially on the intrinsic semiconductor layer 4. The primary first quantum well layer 5 and the primary second quantum well layer 6 emit different colors, and the band widths of the primary first quantum well layer 5 and the primary second quantum well layer 6 decrease sequentially. The dual-color quantum well stack is etched to form a first quantum well layer 5' and a second quantum well layer 6' stacked on the first quantum well layer 5'. The first quantum well layer 5' includes a first light-emitting region Q1 and a second light-emitting region Q2. The second quantum well layer 6' is disposed on the second light-emitting region Q2. Barrier layer 7 and P-type semiconductor layer 8 are grown sequentially; The P-type semiconductor layer 8 and the barrier layer 7 are etched sequentially to form a first barrier layer 71 and a first P-type semiconductor layer 81 that are sequentially stacked on the first light-emitting region Q1, and a second barrier layer 72 and a second P-type semiconductor layer 82 that are sequentially stacked on the second quantum well layer 6'. Etch the intrinsic semiconductor layer 4 or sequentially etch the exposed first quantum well layer 5' and the intrinsic semiconductor layer 4 until the N-type semiconductor layer 3 is exposed to form an electrode hole A; An electrode layer is grown on the epitaxial wafer and inside the electrode hole A after the etching of the electrode hole A is completed; The electrode layers are etched to form a first source D1 and a second source D2 respectively disposed on the first P-type semiconductor layer 81 and the second P-type semiconductor layer 82, a first gate G1 and a second gate G2 respectively disposed on the first barrier layer 71 and the second barrier layer 72, and a common drain S connected to the exposed N-type semiconductor layer 3 and passing through the electrode hole A; the first source D1 is connected to the first P-type semiconductor layer 81, and the first gate G1 is spaced apart from the first P-type semiconductor layer 81; the second source D2 is connected to the second P-type semiconductor layer 82, and the second gate G2 is spaced apart from the second P-type semiconductor layer 82, to obtain a HEMT integrated light-emitting chip.

[0053] By utilizing a common-drain S-type structure and an epitaxial growth-then-growth approach, the process is simplified by using only epitaxy followed by etching and electrode evaporation. This reduces the number of epitaxial layers and the required thickness, achieving miniaturization while lowering the distance electrons and holes need to migrate, thus improving optoelectronic performance and reducing the impact of lattice fit issues caused by multilayer growth.

[0054] For example, a second quantum well layer 6 is regrown on the original first quantum well layer 5, and then half of the original second quantum well layer 6 is etched away to a depth down to the original first quantum well layer 5. In practice, besides etching half, free area etching (such as 1 / 3) can also be performed according to the requirements of light intensity, brightness, and area. Different masks can be used for etching depending on the requirements of light mixing and monochromaticity. For example, a dual-color structure with strong light mixing can be etched using multiple microporous masks. For strong monochromaticity, a semi-circular mask can be used. Furthermore, the shape of the mask etching can also be used to fabricate a gradient-color dual-color HEMT integrated light-emitting chip structure. After this, a second epitaxial growth of a barrier layer 7 is performed, and finally, a P-type semiconductor layer 8 is grown. Typically, photoresist is used to protect the structural layers that need to be retained before etching.

[0055] In this embodiment, etching the dual-color quantum well stack forms a first quantum well layer 5' and a second quantum well layer 6' stacked on the first quantum well layer 5'. The first quantum well layer 5' includes a first light-emitting region Q1 and a second light-emitting region Q2, and the second quantum well layer 6' is disposed on the second light-emitting region Q2. The process includes the following steps: The original second quantum well layer 6 is etched down to the original first quantum well layer 5, resulting in a second quantum well layer 6' stacked on top of the first quantum well layer 5'. The first quantum well layer 5' includes a first light-emitting region Q1 and a second light-emitting region Q2, and the second quantum well layer 6' is disposed on the second light-emitting region Q2. At this time, the first quantum well layer 5' is not etched; this first quantum well layer 5' is the original first quantum well layer 5. Thus, when etching electrode hole A, the exposed first quantum well layer 5' and the intrinsic semiconductor layer 4 must be etched sequentially until the N-type semiconductor layer 3 is exposed, forming electrode hole A.

[0056] In this embodiment, etching the dual-color quantum well stack includes the following steps: The original second quantum well layer 6 is etched down to the original first quantum well layer 5 to obtain a second quantum well layer 6' stacked on the first quantum well layer 5'. The first quantum well layer 5' includes a first light-emitting region Q1 and a second light-emitting region Q2. The second quantum well layer 6' is disposed on the second light-emitting region Q2. The first quantum well layer 5' between the first light-emitting region Q1 and the second light-emitting region Q2 is etched down to the intrinsic semiconductor layer 4, such that the first quantum well layer 5' corresponding to the first light-emitting region Q1 and the first quantum well layer 5' corresponding to the second light-emitting region Q2 are spaced apart. At this time, when etching the electrode hole A, the exposed first quantum well layer 5' and the intrinsic semiconductor layer 4 can be etched sequentially until the N-type semiconductor layer 3 is exposed to form the electrode hole A; alternatively, the intrinsic semiconductor layer 4 can be etched until the N-type semiconductor layer 3 is exposed to form the electrode hole A. In this case, the electrode hole A is located between the first light-emitting region Q1 and the second light-emitting region Q2. At this time, the common drain S is also located between the first light-emitting region Q1 and the second light-emitting region Q2.

[0057] In this embodiment, both the first quantum well layer 5' and the second quantum well layer 6' include at least one of the following: an In-doped InGAN layer, an Al-doped InGAN layer, an In-doped GAN layer, an Al-doped GAN layer, an In-doped AlGAN layer, and an Al-doped AlGAN layer. The emission color of the first quantum well layer 5' and the second quantum well layer 6' can be adjusted according to the content of In or Al doping. Optionally, both the first quantum well layer 5' and the second quantum well layer 6' are In-doped InGAN layers; the In doping content of the first quantum well layer 5' and the second quantum well layer 6' increases sequentially. The In doping concentration of the first quantum well layer 5' and the second quantum well layer 6' ranges from 1E17 cm / VS to 5E17 cm / VS.

[0058] In this embodiment, both the first barrier layer 71 and the second barrier layer 72 include at least one of an AlN barrier layer and an AlGAN barrier layer. Optionally, both the first barrier layer 71 and the second barrier layer 72 are Al-doped AlGAN barrier layers.

[0059] In this embodiment, after obtaining the second quantum well layer 6', the following steps are included: The first quantum well layer 5' between the first light-emitting region Q1 and the second light-emitting region Q2 is etched up to the intrinsic semiconductor layer 4, such that the first quantum well layer 5' corresponding to the first light-emitting region Q1 and the first quantum well layer 5' corresponding to the second light-emitting region Q2 are spaced apart.

[0060] In this embodiment, after etching the electrode layer to form a first source D1 and a second source D2 respectively disposed on the first P-type semiconductor layer 81 and the second P-type semiconductor layer 82, a first gate G1 and a second gate G2 respectively disposed on the first barrier layer 71 and the second barrier layer 72, and a common drain S connected to the exposed N-type semiconductor layer 3 and passing through the electrode hole A; the first source D1 is connected to the first P-type semiconductor layer 81, and the first gate G1 is spaced apart from the first P-type semiconductor layer 81; the second source D2 is connected to the second P-type semiconductor layer 82, and the second gate G2 is spaced apart from the second P-type semiconductor layer 82, the following step is further included: The buffer layer 2 is decomposed to peel off the substrate 1. The decomposition of the buffer layer 2 can be carried out by thermal decomposition, photolysis, chemical decomposition, etc., and the method selected according to the actual situation is not limited here.

[0061] This application also discloses a display backplane, including a driving substrate and the above-mentioned HEMT integrated light-emitting chip, wherein the HEMT integrated light-emitting chip is bonded to the driving substrate.

[0062] In this embodiment, the HEMT integrated light-emitting chip can be a MiniLED, MicroLED, nano-sized LED, or LED of other sizes. It is not limited here, and can be selected according to the actual situation.

[0063] As one implementation method, the display back panel can be used as a direct display or a backlight module. When the display back panel is used as a direct display, it can be a television, VR / AR device, smart wearable device, mobile phone, automotive display, etc.

[0064] This application presents a HEMT integrated light-emitting chip that combines HEMT and LED, resulting in a more compact structure. Unlike traditional HEMT structures where an additional LED structure is grown on top of the HEMT structure, this structure cleverly combines the two to form a novel structure that simultaneously satisfies the definitions of both structures. This allows the structure to both exhibit the characteristics of HEMT structure's independent control and signal enhancement, while also satisfying the light-emitting characteristics of LED structure. The fabrication of a two-dimensional electron gas within the quantum well using the HEMT structure significantly improves electron migration efficiency, thereby increasing the number of electrons and holes emitting light in the active region, reducing the turn-on voltage, and increasing the luminous brightness. By controlling the presence and concentration of holes within the quantum well layer through the energization of the drain electrode, monochromatic and dual-color light emission can be controlled. Furthermore, the concentration of the two-dimensional electron gas is controlled by the magnitude of the voltage applied to the two gates, adjusting the ratio of luminous brightness between the two colors. This allows for free mixing of light, resulting in strong dimming capabilities and higher luminous efficiency, enabling monochromatic and dual-color displays. Utilizing a common-drain structure and a pre-epitaxy-then-growth method, only epitaxy followed by etching and electrode evaporation is required, reducing the complexity of the manufacturing process. By reducing the number of layers and thickness required for epitaxy, miniaturization is achieved while reducing the distance that electrons and holes need to migrate, thus improving photoelectric performance and reducing the impact of lattice adaptation caused by multilayer growth.

[0065] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A HEMT integrated light-emitting chip, characterized in that, It includes an N-type semiconductor layer, an intrinsic semiconductor layer, a first quantum well layer and a second quantum well layer stacked from bottom to top. The first quantum well layer and the second quantum well layer emit different colors, and the band widths of the first quantum well layer and the second quantum well layer decrease sequentially. The first quantum well layer includes a first light-emitting region and a second light-emitting region. The second quantum well layer is disposed on the second light-emitting region. A first barrier layer and a first P-type semiconductor layer are sequentially stacked on the surface of the first light-emitting region. A first source is disposed on the first P-type semiconductor layer, and a first gate is disposed on the first barrier layer at a distance from the first P-type semiconductor layer. A second barrier layer and a second P-type semiconductor layer are sequentially stacked on the surface of the second quantum well layer. A second source is disposed on the second P-type semiconductor layer, and a second gate is disposed on the second barrier layer at a distance from the second P-type semiconductor layer. A common drain is disposed on the N-type semiconductor layer and connected to it and passing through the intrinsic semiconductor or sequentially passing through the intrinsic semiconductor layer and the exposed first quantum well layer.

2. The HEMT integrated light-emitting chip as described in claim 1, characterized in that, The first quantum well layer corresponding to the first light-emitting region and the first quantum well layer corresponding to the second light-emitting region are spaced apart.

3. The HEMT integrated light-emitting chip as described in claim 2, characterized in that, The common drain electrode is disposed between the first light-emitting region and the second light-emitting region.

4. The HEMT integrated light-emitting chip as described in any one of claims 1 to 3, characterized in that, Both the first quantum well layer and the second quantum well layer include at least one of the following: an In-doped InGaN layer, an Al-doped AlGaN layer, an undoped GaN layer, and an In-doped and Al-doped AlGaInN layer.

5. The HEMT integrated light-emitting chip as described in claim 4, characterized in that, Both the first quantum well layer and the second quantum well layer are In-doped InGaN layers; the In doping content of the first quantum well layer and the second quantum well layer increases sequentially.

6. The HEMT integrated light-emitting chip as described in claim 5, characterized in that, The first quantum well layer is a blue quantum well layer and the second quantum well layer is a green quantum well layer; or the first quantum well layer is a blue quantum well layer and the second quantum well layer is a red quantum well layer; or the first quantum well layer is a green quantum well layer and the second quantum well layer is a red quantum well layer.

7. The HEMT integrated light-emitting chip as described in claim 5 or 6, characterized in that, Both the first barrier layer and the second barrier layer include at least one of AlN barrier layer and AlGaN barrier layer.

8. The HEMT integrated light-emitting chip as described in claim 7, characterized in that, Both the first barrier layer and the second barrier layer are Al-doped AlGaN barrier layers.

9. The HEMT integrated light-emitting chip as described in claim 8, characterized in that, The N-type semiconductor layer includes at least one of an N-type GaN layer, an N-type AlGaN layer, and an N-type InGaN layer; The first P-type semiconductor layer and the second P-type semiconductor layer are made of the same material. The first P-type semiconductor layer includes at least one of a P-type GaN layer, a P-type AlGaN layer, and a P-type InGaN layer.

10. The HEMT integrated light-emitting chip as described in claim 9, characterized in that, The N-type semiconductor layer is an N-type GaN layer, and both the first P-type semiconductor layer and the second P-type semiconductor layer are P-type GaN layers.

11. The HEMT integrated light-emitting chip as described in claim 1, 2, 3, 5, 6, 8, 9, or 10, characterized in that, The HEMT integrated light-emitting chip can be a MiniLED or a MicroLED.

12. The HEMT integrated light-emitting chip as described in claim 1, 2, 3, 5, 6, 8, 9, or 10, characterized in that, It also includes a substrate and a buffer layer, wherein the buffer layer and the substrate are stacked sequentially on the side of the N-type semiconductor layer away from the intrinsic semiconductor layer.

13. A HEMT integrated epitaxial wafer, characterized in that, For fabricating an HEMT integrated light-emitting chip as described in any one of claims 1 to 12, the chip comprises, from bottom to top, a substrate, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a dual-color quantum well layer, wherein the dual-color quantum well layer comprises a primary first quantum well layer and a primary second quantum well layer sequentially stacked on the intrinsic semiconductor layer, wherein the primary first quantum well layer and the primary second quantum well layer emit different colors, and the band widths of the primary first quantum well layer and the primary second quantum well layer decrease sequentially.

14. The HEMT integrated epitaxial wafer as described in claim 13, characterized in that, The step of growing a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a dual-color quantum well layer sequentially from bottom to top on the surface of the substrate includes performing the following steps: Under a first preset temperature and a first preset pressure, a buffer layer of a first preset thickness is grown on the surface of the substrate; Under a second preset temperature and a second preset pressure, an N-type semiconductor layer of a second preset thickness is grown on the surface of the buffer layer; Under a third preset temperature and a third preset pressure, an intrinsic semiconductor layer of a third preset thickness is grown on the surface of the N-type semiconductor layer; Under a fourth preset temperature and a fourth preset pressure, the original first quantum well layer of a fourth preset thickness is grown on the surface of the intrinsic semiconductor layer; Under a fifth preset temperature and a fifth preset pressure, the original second quantum well layer of a fifth preset thickness is grown on the surface of the original first quantum well layer; The sequential growth of the barrier layer and the P-type semiconductor layer includes performing the following steps: Under a sixth preset temperature and a sixth preset pressure, a barrier layer of a sixth preset thickness is grown on the etched epitaxial wafer; At a seventh preset temperature and a seventh preset pressure, a P-type semiconductor layer of a seventh preset thickness is grown on the surface of the barrier layer.

15. The HEMT integrated epitaxial wafer as described in claim 13, characterized in that, The original first quantum well layer and the original second quantum well layer are made of the same material.

16. A method for fabricating an HEMT integrated light-emitting chip, used to fabricate the HEMT integrated light-emitting chip as described in any one of claims 1 to 12, characterized in that the step... include: A HEMT integrated epitaxial wafer as described in any one of claims 13 to 15 is provided, the HEMT integrated epitaxial wafer comprising, from bottom to top, a substrate, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer and a dual-color quantum well layer, wherein the dual-color quantum well layer comprises a primary first quantum well layer and a primary second quantum well layer sequentially stacked on the intrinsic semiconductor layer, the primary first quantum well layer and the primary second quantum well layer emitting different colors, and the band widths of the primary first quantum well layer and the primary second quantum well layer decreasing sequentially; The dual-color quantum well stack is etched to form a first quantum well layer and a second quantum well layer stacked on the first quantum well layer. The first quantum well layer includes a first light-emitting region and a second light-emitting region, and the second quantum well layer is disposed on the second light-emitting region. A barrier layer and a P-type semiconductor layer are grown sequentially. The P-type semiconductor layer and the barrier layer are etched sequentially to form a first barrier layer and a first P-type semiconductor layer that are sequentially stacked on the first light-emitting region, and a second barrier layer and a second P-type semiconductor layer that are sequentially stacked on the second quantum well layer. Etching the intrinsic semiconductor layer or sequentially etching the exposed first quantum well layer and the intrinsic semiconductor layer until the N-type semiconductor layer is exposed to form an electrode hole; An electrode layer is grown on the epitaxial wafer and inside the electrode holes after the electrode holes have been etched. The electrode layer is etched to form a first source and a second source respectively disposed on the first P-type semiconductor layer and the second P-type semiconductor layer, a first gate and a second gate respectively disposed on the first barrier layer and the second barrier layer, and a common drain connected to the exposed N-type semiconductor layer and passing through the electrode hole; the first source is connected to the first P-type semiconductor layer, and the first gate is spaced apart from the first P-type semiconductor layer; the second source is connected to the second P-type semiconductor layer, and the second gate is spaced apart from the second P-type semiconductor layer, to obtain a HEMT integrated light-emitting chip.

17. The method for fabricating a HEMT integrated light-emitting chip as described in claim 16, characterized in that, The etching of the dual-color quantum well stack forms a first quantum well layer and a second quantum well layer stacked on the first quantum well layer. The first quantum well layer includes a first light-emitting region and a second light-emitting region, and the second quantum well layer is disposed on the second light-emitting region. The process includes the following steps: The original second quantum well layer is etched down to the original first quantum well layer to obtain a second quantum well layer stacked on the first quantum well layer. The first quantum well layer includes a first light-emitting region and a second light-emitting region, and the second quantum well layer is disposed on the second light-emitting region.

18. The method for fabricating a HEMT integrated light-emitting chip as described in claim 17, characterized in that, After obtaining the second quantum well layer, the following steps are included: The first quantum well layer between the first light-emitting region and the second light-emitting region is etched down to the intrinsic semiconductor layer, such that the first quantum well layer corresponding to the first light-emitting region and the first quantum well layer corresponding to the second light-emitting region are spaced apart.

19. The method for fabricating a HEMT integrated light-emitting chip as described in claim 16, characterized in that, After etching the electrode layer to form a first source and a second source respectively disposed on the first P-type semiconductor layer and the second P-type semiconductor layer, a first gate and a second gate respectively disposed on the first barrier layer and the second barrier layer, and a common drain connected to the exposed N-type semiconductor layer and passing through the electrode via; the first source is connected to the first P-type semiconductor layer, and the first gate is spaced apart from the first P-type semiconductor layer; the second source is connected to the second P-type semiconductor layer, and the second gate is spaced apart from the second P-type semiconductor layer, the process further includes the following steps: The buffer layer is disassembled to peel off the substrate.

20. A display back panel, characterized in that, It includes a driving substrate and an HEMT integrated light-emitting chip as described in any one of claims 1 to 12, wherein the HEMT integrated light-emitting chip is bonded to the driving substrate.

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