HEMT (High Electron Mobility Transistor) integrated luminous chip, preparation method thereof, epitaxial wafer and display backboard

Abstract

The invention discloses an HEMT integrated light-emitting chip and a preparation method thereof, an epitaxial wafer and a display backboard, and the method comprises the steps: providing an HEMT integrated epitaxial wafer, the HEMT integrated epitaxial wafer comprises a three-color quantum well lamination layer, the three-color quantum well lamination layer comprises an original first quantum well layer, an original second quantum well layer and an original third quantum well layer, and the original first quantum well layer, the original second quantum well layer and the original third quantum well layer are stacked in sequence, and the energy band widths of the original first quantum well layer, the original second quantum well layer and the original third quantum well layer are reduced in sequence; etching the three-color quantum well laminated layer to form a first quantum well layer, a second quantum well layer laminated on the first quantum well layer and a third quantum well layer laminated on the second quantum well layer; sequentially growing and etching a barrier layer and a P-type semiconductor layer to form the barrier layer and the P-type semiconductor layer corresponding to each quantum well, and etching an electrode hole; and growing an electrode layer and etching to form a corresponding source electrode, a drain electrode and a common drain electrode. According to the HEMT integrated light-emitting chip and the preparation method thereof, the HEMT structure is utilized to prepare two-dimensional electron gas in the well, the electron migration efficiency is greatly improved, and single-color, double-color and three-color display can be achieved.

Description

Technical Field

[0001] This application relates to the field of display, and in particular to a HEMT integrated light-emitting chip and its fabrication method, epitaxial wafer, and display backplane. Background Technology

[0002] HEMT (High Electron Mobility Transistor) and LED (Light Emitting Diode) are devices with significant applications in the fields of electronics and optoelectronics, possessing enormous potential and a wide range of applications. HEMT is a high electron mobility transistor that exhibits excellent performance in high-frequency and microwave circuits, and is commonly used in RF power amplifiers and microwave receivers. LED is a semiconductor device that converts electrical energy into light energy, and is widely used in lighting, displays, and communications.

[0003] In recent years, with the development of electronic and optoelectronic integration technology, how to apply HEMT to MicroLED has become a challenge in this field. Chinese patent document CN117153961A discloses an integrated backplane for driving MicroLED with HEMT and its fabrication method. The method includes growing an HEMT epitaxial structure on a substrate, sequentially growing three monochromatic LED epitaxial structures on the HEMT epitaxial structure to obtain an epitaxial wafer, etching to partition the epitaxial wafer on the substrate, depositing a passivation layer, etching vias, and then depositing conductors to connect the n-GaN layers of the three LED regions to a single HEMT region, and connecting the remaining three HEMT regions to the p-GaN layer of one LED region. This method integrates the HEMT and three-color LED devices on a single substrate at the epitaxial end, representing a design for applying HEMT to the MicroLED display field. Summary of the Invention

[0004] In view of the shortcomings of the above-mentioned related technologies, the purpose of this application is to provide an HEMT integrated light-emitting chip and its preparation method, epitaxial wafer, and display backplane, which realizes the combination of HEMT structure and LED, resulting in a more compact structure. By utilizing the HEMT structure to prepare a two-dimensional electron gas in the trap, the electron migration efficiency is greatly improved, the number of electrons and holes emitting light in the active region is increased, the turn-on voltage is reduced and the luminous brightness is increased, and monochrome, dual-color and tri-color displays can be realized.

[0005] This application provides an HEMT integrated light-emitting chip, comprising an N-type semiconductor layer, an intrinsic semiconductor layer, a first quantum well layer, a second quantum well layer, and a third quantum well layer stacked sequentially from bottom to top. The first quantum well layer, the second quantum well layer, and the third quantum well layer emit different colors, and the band widths of the first quantum well layer, the second quantum well layer, and the third quantum well layer decrease sequentially. The first quantum well layer includes a first light-emitting region, a second light-emitting region, and a third light-emitting region. A second quantum well layer is disposed on the second and third light-emitting regions. The third quantum well layer is disposed on the second quantum well layer corresponding to the third light-emitting region. A first barrier layer and a first P-type semiconductor layer are sequentially stacked on the first light-emitting region. A first source electrode connected to the first P-type semiconductor layer is disposed on the first P-type semiconductor layer. A first gate electrode spaced apart from the first P-type semiconductor layer is disposed on the first barrier layer. The second quantum well layer corresponding to the second light-emitting region is sequentially stacked on... A second barrier layer and a second P-type semiconductor layer are stacked on top of each other. A second source electrode connected to the second P-type semiconductor layer is disposed on the second P-type semiconductor layer, and a second gate electrode spaced apart from the second P-type semiconductor layer is disposed on the second barrier layer. A third barrier layer and a third P-type semiconductor layer are stacked on top of each other in sequence. A third source electrode connected to the third P-type semiconductor layer is disposed on the third P-type semiconductor layer, and a third gate electrode spaced apart from the third P-type semiconductor layer is disposed on the third barrier layer. A common drain electrode connected to and extending along the direction of the first quantum well layer is disposed on the N-type semiconductor layer.

[0006] Optionally, the second quantum well layer on the second light-emitting region and the second quantum well layer on the third light-emitting region are spaced apart.

[0007] Optionally, the first quantum well layer corresponding to the first light-emitting region, the first quantum well layer corresponding to the second light-emitting region, and the first quantum well layer corresponding to the third light-emitting region are spaced apart.

[0008] Optionally, the first quantum well layer, the second quantum well layer, and the third quantum well layer each include at least one of the following: an In-doped InGaN layer, an Al-doped AlGaN layer, an undoped GaN layer, and an Al- and In-doped AlInGaN layer.

[0009] Optionally, the first quantum well layer, the second quantum well layer, and the third quantum well layer are all In-doped InGaN layers; the first quantum well layer is a blue quantum well layer, the second quantum well layer is a green quantum well layer, and the third quantum well layer is a red quantum well layer, with the In doping content of the first quantum well layer, the second quantum well layer, and the third quantum well layer increasing sequentially.

[0010] Optionally, the first barrier layer, the second barrier layer, and the third barrier layer each include at least one of AlN barrier layer and AlGaN barrier layer.

[0011] Optionally, the first barrier layer, the second barrier layer, and the third barrier layer are all Al-doped AlGaN barrier layers.

[0012] Optionally, the N-type semiconductor layer includes at least one of an N-type GaN layer and an N-type AlGaN layer; The first P-type semiconductor layer, the second P-type semiconductor layer, and the third P-type semiconductor layer are made of the same material, and the first P-type semiconductor layer includes at least one of a P-type GaN layer and a P-type AlGaN layer.

[0013] Optionally, it also includes a substrate, a nucleation layer, and a buffer layer, wherein the buffer layer, the nucleation layer, and the substrate are sequentially stacked on the side of the N-type semiconductor layer away from the intrinsic semiconductor layer.

[0014] This application also provides an HEMT integrated epitaxial wafer for fabricating the aforementioned HEMT integrated light-emitting chip, comprising a substrate, a nucleation layer, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a three-color quantum well stack, which are stacked sequentially from bottom to top. The three-color quantum well stack includes a primary first quantum well layer, a primary second quantum well layer, and a primary third quantum well layer, which are sequentially stacked on the intrinsic semiconductor layer. The band widths of the primary first quantum well layer, the primary second quantum well layer, and the primary third quantum well layer decrease sequentially.

[0015] Optionally, the step of growing a core layer, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a tri-color quantum well stack sequentially from bottom to top on the surface of the substrate includes performing the following steps: Under a first preset temperature and a first preset pressure, the nucleation layer of a first preset thickness is grown on the surface of the substrate; Under a second preset temperature and a second preset pressure, a buffer layer of a second preset thickness is grown on the surface of the nucleation layer; Under a third preset temperature and a third preset pressure, the N-type semiconductor layer of a third preset thickness is grown on the surface of the buffer layer; Under a fourth preset temperature and a fourth preset pressure, an intrinsic semiconductor layer of a fourth preset thickness is grown on the surface of the N-type semiconductor layer; Under a fifth preset temperature and a fifth preset pressure, the original first quantum well layer of a fifth preset thickness is grown on the surface of the intrinsic semiconductor layer; Under a sixth preset temperature and a sixth preset pressure, the original second quantum well layer with a sixth preset thickness is grown on the surface of the first quantum well layer; Under a seventh preset temperature and a seventh preset pressure, the original third quantum well layer with a seventh preset thickness is grown on the surface of the second quantum well layer; The sequential growth of the barrier layer and the P-type semiconductor layer includes performing the following steps: Under an eighth preset temperature and an eighth preset pressure, a barrier layer of an eighth preset thickness is grown on the etched epitaxial wafer; At a ninth preset temperature and a ninth preset pressure, a P-type semiconductor layer of a ninth preset thickness is grown on the surface of the barrier layer.

[0016] Optionally, the original first quantum well layer, the original second quantum well layer, and the original third quantum well layer are made of the same material.

[0017] This application also provides a method for fabricating a HEMT integrated light-emitting chip, the method comprising the following steps: The HEMT integrated epitaxial wafer is provided, comprising, from bottom to top, a substrate, a nucleation layer, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a three-color quantum well stack, wherein the three-color quantum well stack comprises a first quantum well layer, a second quantum well layer, and a third quantum well layer sequentially stacked on the intrinsic semiconductor layer, and the band widths of the first quantum well layer, the second quantum well layer, and the third quantum well layer decrease sequentially. The three-color quantum well stack is etched to form a first quantum well layer, a second quantum well layer stacked on the first quantum well layer, and a third quantum well layer stacked on the second quantum well layer. The first quantum well layer includes a first light-emitting region, a second light-emitting region, and a third light-emitting region. The second quantum well layer is disposed on the second light-emitting region and the third light-emitting region. The third quantum well layer is disposed on the second quantum well layer corresponding to the third light-emitting region. A barrier layer and a P-type semiconductor layer are grown sequentially. The P-type semiconductor layer and the barrier layer are etched sequentially to form a first barrier layer and a first P-type semiconductor layer that are sequentially stacked on the first light-emitting region, a second barrier layer and a second P-type semiconductor layer that are sequentially stacked on the second quantum well layer corresponding to the second light-emitting region, and a third barrier layer and a third P-type semiconductor layer that are sequentially stacked on the third quantum well layer. Etch the exposed first quantum well layer and the intrinsic semiconductor layer until the N-type semiconductor layer is exposed to form an electrode hole; An electrode layer is grown on the epitaxial wafer and inside the electrode holes after the electrode holes have been etched. The electrode layers are etched to form a first source, a second source, and a third source respectively disposed on the first P-type semiconductor layer, the second P-type semiconductor layer, and the third P-type semiconductor layer; a first gate, a second gate, and a third gate respectively disposed on the first barrier layer, the second barrier layer, and the third barrier layer; and a common drain connected to the N-type semiconductor layer and extending along the direction of the first quantum well layer; the first source is connected to the first P-type semiconductor layer, and the first gate is spaced apart from the first P-type semiconductor layer; the second source is connected to the second P-type semiconductor layer, and the second gate is spaced apart from the second P-type semiconductor layer; the third source is connected to the third P-type semiconductor layer, and the third gate is spaced apart from the third P-type semiconductor layer, to obtain a HEMT integrated light-emitting chip.

[0018] Optionally, the etching of the three-color quantum well stack forms a first quantum well layer, a second quantum well layer stacked on the first quantum well layer, and a third quantum well layer stacked on the second quantum well layer. The first quantum well layer includes a first light-emitting region, a second light-emitting region, and a third light-emitting region. The second quantum well layer is disposed on the second light-emitting region and the third light-emitting region, and the third quantum well layer is disposed on the second quantum well layer corresponding to the third light-emitting region. This includes the following steps: The original third quantum well layer is etched down to the original second quantum well layer to obtain a third quantum well layer stacked on the original second quantum well layer; The original second quantum well layer between the second light-emitting region and the third light-emitting region is etched down to the original first quantum well layer, so that the second quantum well layer on the second light-emitting region and the second quantum well layer on the third light-emitting region are spaced apart.

[0019] Optionally, after etching the original second quantum well layer between the second light-emitting region and the third light-emitting region down to the original first quantum well layer, such that the second quantum well layer on the second light-emitting region and the second quantum well layer on the third light-emitting region are spaced apart, the method further includes the following steps: The original first quantum well layer between the first light-emitting region and the second light-emitting region, the original first quantum well layer between the second light-emitting region and the third light-emitting region, and the original first quantum well layer between the first light-emitting region and the third light-emitting region are etched, such that the first quantum well layer corresponding to the first light-emitting region, the first quantum well layer corresponding to the second light-emitting region, and the first quantum well layer corresponding to the third light-emitting region are spaced apart.

[0020] Optionally, after etching the electrode layer to form a first source, a second source, and a third source respectively disposed on the first P-type semiconductor layer, the second P-type semiconductor layer, and the third P-type semiconductor layer; a first gate, a second gate, and a third gate respectively disposed on the first barrier layer, the second barrier layer, and the third barrier layer; and a common drain connected to the N-type semiconductor layer and extending along the direction of the first quantum well layer; the first source is connected to the first P-type semiconductor layer, and the first gate is spaced apart from the first P-type semiconductor layer; the second source is connected to the second P-type semiconductor layer, and the second gate is spaced apart from the second P-type semiconductor layer; the third source is connected to the third P-type semiconductor layer, and the third gate is spaced apart from the third P-type semiconductor layer, the method further includes the following step: The buffer layer is disassembled to peel off the substrate.

[0021] This application also provides a display backplane, including a driving substrate and the HEMT integrated light-emitting chip, wherein the HEMT integrated light-emitting chip is bonded to the driving substrate.

[0022] This application presents a HEMT integrated light-emitting chip that combines an HEMT structure with an LED. In terms of fabrication, it leverages the characteristic of HEMTs—that an applied gate voltage can attract and aggregate electrons in the undoped region to form a thin electron gas with high mobility. Simultaneously, it utilizes the different bandwidths and barrier heights of various quantum wells to directly and continuously epitaxially grow three quantum well layers without the need for additional growth of the corresponding complete structure, reducing the overall epitaxial thickness and simplifying the fabrication process, resulting in a more compact structure. The fabrication of a two-dimensional electron gas within the well using the HEMT structure significantly improves electron mobility, thereby increasing the number of electrons and holes emitting light in the active region, reducing the turn-on voltage, and increasing brightness. The quantum wells are in direct contact with the barrier layer without any gaps, ensuring no impact on light emission and avoiding uncontrollable light mixing that reduces luminous efficiency. The quantum wells can be controlled by individually or simultaneously controlling the source current and by varying voltages. The presence and concentration of holes within the chip allow for the control of monochromatic, dual-color, and tri-color emission. Utilizing the electron aggregation property under the influence of the HEMT gate voltage and electric field, the number and density of electrons in the non-emitting region are reduced, decreasing leakage current and the probability of non-radiative recombination emission. This also improves the monochromaticity of individual emitting regions. The concentration of the two-dimensional electron gas is controlled by the magnitude of the applied gate voltage, allowing for the adjustment of the brightness ratio of different colors and enabling free mixing of light. The common-drain structure and epitaxial growth followed by etching and electrode evaporation reduce the complexity of the manufacturing process. This HEMT integrated light-emitting chip not only improves device performance and functional density but also helps reduce system cost and power consumption. Realizing electronic and optoelectronic functions on a single chip provides new possibilities for optical communication, optical detection, and integrated optoelectronic systems. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of the HEMT integrated light-emitting chip after the first epitaxy, provided in an embodiment of this application. Figure 2 for Figure 1 A schematic diagram of the structure after etching a stack of three-color quantum wells in the middle; Figure 3 In order to be in Figure 2 A schematic diagram of the structure after growing a barrier layer and a P-type semiconductor layer on the substrate; Figure 4 for Figure 3 A schematic diagram of the structure after etching the barrier layer and the P-type semiconductor layer in the middle; Figure 5 for Figure 4 A schematic diagram of the HEMT integrated light-emitting chip with electrodes fabricated in the middle; Figure 6 This is a schematic diagram of the structure of a HEMT integrated light-emitting chip provided in another embodiment of this application; Figure 7 A flowchart illustrating the fabrication method of the HEMT integrated light-emitting chip provided in this application embodiment; Figure 8 A schematic diagram of forming a two-dimensional electron gas channel within a quantum well, provided for an embodiment of this application; Figure 9 A schematic diagram illustrating the migration of electrons from a first quantum well layer with a high band width to a second quantum well layer with a low band width, provided as an embodiment of this application. Figure 10 This is a schematic diagram illustrating the migration of electrons from a second quantum well layer with a lower band width to a third quantum well layer with an even lower band width, as provided in an embodiment of this application.

[0024] Explanation of reference numerals in the attached figures: 1-Substrate; 2-Nucleation layer; 3-Buffer layer; 4-N-type semiconductor layer; 5-Intrinsic semiconductor layer; 6-Original first quantum well layer; 6'-First quantum well layer; Q1-First light-emitting region; Q2-Second light-emitting region; Q3-Third light-emitting region; 7-Original second quantum well layer; 7'-Second quantum well layer; 8-Original third quantum well layer; 8'-Third quantum well layer; 9-Barrier layer; 91-First barrier layer; 92-Second barrier layer; 93-Third barrier layer; 10-P-type semiconductor layer; P1-First P-type semiconductor layer; P2-Second P-type semiconductor layer; P3-Third P-type semiconductor layer; A-Electrode hole; D1-First source; D2-Second source; D3-Third source; G1-First gate; G2-Second gate; G3-Third gate; S-Common drain. Detailed Implementation

[0025] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0027] In the description of this application, the terms "first," "second," etc., are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0028] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] The specific embodiments of this application will be further described below with reference to the accompanying drawings.

[0030] See Figures 5 to 6 As shown in the figure, this application discloses an HEMT integrated light-emitting chip, including an N-type semiconductor layer 4, an intrinsic semiconductor layer 5, a first quantum well layer 6', a second quantum well layer 7', and a third quantum well layer 8' stacked sequentially from bottom to top. The first quantum well layer 6', the second quantum well layer 7', and the third quantum well layer 8' emit different colors, and the band widths of the first quantum well layer 6', the second quantum well layer 7', and the third quantum well layer 8' decrease sequentially. The first quantum well layer 6' includes a first light-emitting region Q1, a second light-emitting region Q2, and a third light-emitting region Q3. The second quantum well layer 7' is disposed on the second light-emitting region Q2 and the third light-emitting region Q3. The third quantum well layer 8' is disposed on the second quantum well layer 7' corresponding to the third light-emitting region Q3. A first barrier layer 91 and a first P-type semiconductor layer P1 are sequentially stacked on the first light-emitting region Q1. A first source D1 connected to the first P-type semiconductor layer P1 is disposed on the first P-type semiconductor layer P1. A first gate G1 spaced apart from the first P-type semiconductor layer P1 is disposed on the first barrier layer 91. The second quantum well layer 7' corresponding to the second light-emitting region Q2 is... The second quantum well layer 8' has a second barrier layer 92 and a second P-type semiconductor layer P2 stacked on it. A second source D2 connected to the second P-type semiconductor layer P2 is disposed on the second barrier layer 92 and a second gate G2 disposed at a distance from the second P-type semiconductor layer P2. The third quantum well layer 8' has a third barrier layer 93 and a third P-type semiconductor layer P3 stacked on it. A third source D3 connected to the third P-type semiconductor layer P3 is disposed on the third P-type semiconductor layer P3 and a third gate G3 disposed at a distance from the third P-type semiconductor layer P3. The N-type semiconductor layer 4 has a common drain S connected to it and extending along the direction of the first quantum well layer 6'.

[0031] This application presents a HEMT integrated light-emitting chip that combines HEMT and LED structures. By directly contacting the quantum well and the barrier layer without any gap, the light emission is unaffected. This avoids the situation where, when an applied gate voltage creates a downward electric field, electrons injected from the N-type semiconductor layer 4 are not blocked by the barrier layer with its high bandgap and high energy barrier before reaching the uppermost light-emitting region, thus reducing light emission efficiency and causing uncontrollable light mixing. In terms of tri-color integration, only the common electron injection and common drain S are maintained. By applying a gate voltage, a two-dimensional electron gas channel (2DEG channel) can be formed at the interface between the quantum well layer and the barrier layer. The magnitude of the applied gate voltage can effectively control the concentration of the 2DEG, greatly improving electron migration efficiency. This increases the number of electrons and holes emitting light in the active region, reduces the turn-on voltage, and increases brightness. Simultaneously, electrons in other regions will accumulate at the 2DEG channel, reducing the probability of electron-hole recombination in other regions and improving the efficiency of light emission recombination. By controlling the concentration of the two-dimensional electron gas and the depth of the channel by applying different voltages to the gate, the luminous intensity can be modulated, ultimately achieving a light mixing effect. The two-dimensional electron gas originates from the barrier formed by the huge energy barrier difference between the quantum well layer and the barrier layer, and the high-mobility electron gas channel formed by the attraction of electrons by the strong electric field under the gate voltage. The electron gas is also used for the combined light emission of the LED. See also Figure 8 As shown, by applying a voltage to the gate, electrons continuously migrate upwards under the influence of the applied voltage. Simultaneously, due to the wider energy band of the barrier layer and the lower energy level of the quantum well layer, electrons are trapped within the well. Furthermore, because the width of the well is very small, a two-dimensional electron gas forms at the quantum well. Similarly, the energy level of the second quantum well layer 7' is even lower, so electrons do not accumulate in the first quantum well layer 6', but instead form a 2DEG channel in the second quantum well layer 7'. The same applies to the third quantum well layer 8', which will not be elaborated upon here.

[0032] Furthermore, individual or mixed dimming can be controlled by injecting holes individually or simultaneously into the source. When no source is energized, only a two-dimensional electron gas exists in the quantum well layer, with no recombination of electrons and holes, and no light is emitted. By individually energizing different regions of the source, it is possible to control the emission of blue light, green light, red light, or mixed light. The recombination of light by LEDs originates from the recombination of electrons and holes in the active region. Therefore, the prerequisite for light emission is that the active region must simultaneously contain electrons and holes. Since the two-dimensional electron gas is only a very thin layer, much smaller than the epitaxial thickness, and the specially designed stepped structure causes electrons to tend to migrate to the lowest band, a large number of recombinated electrons exist only in the topmost layer of each quantum well in the overall structure. That is, electrons accumulate at the interface between the quantum well layer and its corresponding barrier layer, and do not diffuse or remain in other surrounding quantum well layers. Meanwhile, the stepped structure, due to its varying bandgap widths, tends to favor the lowest bandgap for hole migration (e.g., red light emission is confined to the red quantum well layer). Therefore, each emitting region can emit monochromatic light independently. By controlling the source electrodes to inject holes, monochromatic, bicolor, and tricolor light emission can be achieved. Specifically, energizing the first source electrode D1, the second source electrode D2, or the third source electrode D3 can cause the first quantum well layer 6', the second quantum well layer 7', or the third quantum well layer 8' to emit monochromatic light. Energizing at least two of the first, second, and third source electrodes D1, D2, and D3 can cause at least two of the first, second, and third quantum well layers 6', 7', and 8' to emit light, achieving bicolor and tricolor emission.

[0033] In terms of process, the external voltage of HEMT gate can attract and gather electrons in the undoped region to form a thin electron gas with high mobility. At the same time, by taking advantage of the different energy bandwidths and energy barrier heights of different quantum wells, electrons and holes can be directly confined to the interface with high electron concentration and mobility, preventing electron or hole diffusion from causing recombination and light emission in other regions. Therefore, three quantum wells can be directly and continuously epitaxially grown without the need to grow the corresponding complete structure, which reduces the overall epitaxial thickness and simplifies the process steps.

[0034] In this embodiment, a substrate 1, a nucleation layer 2, and a buffer layer 3 are also included. The buffer layer 3, the nucleation layer 2, and the substrate 1 are sequentially stacked on the side of the N-type semiconductor layer 4 away from the intrinsic semiconductor layer 5. The HEMT integrated light-emitting chip of this application may or may not have a substrate 1; the difference lies in the luminous efficiency, with better luminous efficiency when the substrate 1 is removed.

[0035] In this embodiment, the second quantum well layer 7' on the second light-emitting region Q2 and the second quantum well layer 7' on the third light-emitting region Q3 are spaced apart.

[0036] In this embodiment, the first quantum well layer 6' corresponding to the first light-emitting region Q1, the first quantum well layer 6' corresponding to the second light-emitting region Q2, and the first quantum well layer 6' corresponding to the third light-emitting region Q3 are spaced apart.

[0037] In this embodiment, the first quantum well layer 6', the second quantum well layer 7', and the third quantum well layer 8' each include at least one of the following: an In-doped InGaN layer, an Al-doped AlGaN layer, an undoped GaN layer, and an AlInGaN layer doped with Al and In. The color rendering of each quantum well is adjusted by regulating the In and Al content. In some embodiments, other substances can also be used to adjust the color rendering of each quantum well, and this is not a limitation. The process utilizes the characteristic that the gate voltage of a HEMT can attract and gather electrons from undoped regions to form a thin electron gas with high mobility. Simultaneously, it utilizes the different bandwidths and barrier heights of quantum wells with different In or Al compositions, for example, to directly confine electrons and holes to interfaces with high electron concentration and mobility, preventing electron or hole diffusion from causing recombination and luminescence in other regions. Therefore, three quantum well layers can be directly and continuously epitaxially grown without the need for additional growth of the corresponding complete structure, reducing the overall epitaxial thickness and simplifying the process steps.

[0038] In this embodiment, the first quantum well layer 6', the second quantum well layer 7', and the third quantum well layer 8' are all In-doped InGaN layers; the first quantum well layer 6' is a blue quantum well layer, the second quantum well layer 7' is a green quantum well layer, and the third quantum well layer 8' is a red quantum well layer, with the In doping content of the first quantum well layer 6', the second quantum well layer 7', and the third quantum well layer 8' increasing sequentially. The In doping concentration of the first quantum well layer 6', the second quantum well layer 7', and the third quantum well layer 8' ranges from 1E17cm / VS to 5E17cm / VS; the loop count of the first quantum well layer 6' and the second quantum well layer 7' ranges from 5 to 8; and the loop count of the third quantum well layer 8' ranges from 3 to 6. By utilizing the different bandwidth and barrier height of InGaN with different In compositions, the barrier height decreases with higher In content. Therefore, the barrier of the red quantum well is lower than that of the green quantum well, which is lower than that of the blue quantum well. Electrons and holes can be directly confined to the interface with high electron concentration and mobility, preventing electron or hole diffusion from causing recombination and luminescence in other regions. Thus, three layers of InGaN can be epitaxially grown continuously without the need to grow the corresponding complete structure, reducing the overall epitaxial thickness and simplifying the process steps.

[0039] See Figure 9 and Figure 10 As shown, the green light-emitting region of the HEMT-MiGroLED simultaneously contains both blue and green quantum well layers. The green quantum well layer has a higher In content and a lower corresponding energy level, so electrons do not accumulate in the blue quantum well layer but instead form a 2DEG channel in the green quantum well layer. The same principle applies to the red quantum well layer, which will not be elaborated upon here.

[0040] In this embodiment, the first barrier layer 91, the second barrier layer 92 and the third barrier layer 93 each include at least one of AlN barrier layer and AlGaN barrier layer.

[0041] In this embodiment, the first barrier layer 91, the second barrier layer 92, and the third barrier layer 93 are all Al-doped AlGaN barrier layers. The Al content in the Al-doped AlGaN barrier layer is between 15% and 25%.

[0042] In this embodiment, the nucleation layer 2 includes a nitride nucleation layer; the nucleation layer 2 is, for example, a nitride nucleation layer, and in other embodiments, it may be other different types of nucleation layers, which are not limited here. Further, the nitride nucleation layer includes at least one of an ALN ​​nucleation layer, a GaN nucleation layer, and an AlGaN nucleation layer.

[0043] In this embodiment, the buffer layer 3 includes at least one of a uGaN buffer layer, an AlN buffer layer, and an AlGaN / GaN superlattice buffer layer; uGaN is an undoped GaN buffer layer.

[0044] In this embodiment, the N-type semiconductor layer 4 includes at least one of an N-type GaN layer and an N-type AlGaN layer.

[0045] In this embodiment, the first P-type semiconductor layer P1, the second P-type semiconductor layer P2, and the third P-type semiconductor layer P3 are made of the same material, and the first P-type semiconductor layer P1 includes at least one of a P-type GaN layer and a P-type AlGaN layer.

[0046] The substrate 1 includes at least one of sapphire, silicon, silicon carbide and gallium nitride.

[0047] In this embodiment, the nucleation layer 2 is an AlN nucleation layer, the buffer layer 3 is a uGaN buffer layer, the N-type semiconductor layer 4 is an N-type GaN layer, the intrinsic semiconductor layer 5 is an I-type GaN layer, and the first P-type semiconductor layer P1, the second P-type semiconductor layer P2, and the third P-type semiconductor layer P3 are all P-type AlGaN layers. The N-type doping concentration of the N-type semiconductor layer 4 ranges from 6E18 cm / VS to 3E19 cm / VS. The P-type doping concentration of the P-type semiconductor layer 10 ranges from 1E19 cm / VS to 2E20 cm / VS.

[0048] In this embodiment, the intrinsic semiconductor layer 5 includes a type I GaN layer. In other embodiments, intrinsic semiconductors of other materials may be used, and this is not limited here.

[0049] This embodiment also discloses a HEMT integrated epitaxial wafer for fabricating the aforementioned HEMT integrated light-emitting chip. It includes, from bottom to top, a substrate 1, a nucleation layer 2, a buffer layer 3, an N-type semiconductor layer 4, an intrinsic semiconductor layer 5, and a three-color quantum well stack. The three-color quantum well stack includes a first quantum well layer 6, a second quantum well layer 7, and a third quantum well layer 8 sequentially stacked on the intrinsic semiconductor layer 5. The band widths of the first quantum well layer 6, the second quantum well layer 7, and the third quantum well layer 8 decrease sequentially. The three-color quantum well stack, i.e., the first quantum well layer 6, the second quantum well layer 7, and the third quantum well layer 8, emit different colors.

[0050] In this embodiment, the original first quantum well layer 6, the original second quantum well layer 7, and the original third quantum well layer 8 are made of the same material. For example, the original first quantum well layer 6, the original second quantum well layer 7, and the original third quantum well layer 8 are all made of In-doped InGaN layers; however, their doping element concentrations may be different or the same.

[0051] In this embodiment, the step of growing a core layer 2, a buffer layer 3, an N-type semiconductor layer 4, an intrinsic semiconductor layer 5, and a tri-color quantum well stack sequentially from bottom to top on the surface of the substrate 1 includes performing the following steps: Under a first preset temperature and a first preset pressure, a nucleation layer 2 of a first preset thickness is grown on the surface of the substrate 1. The first preset temperature ranges from 500℃ to 650℃, the first preset pressure ranges from 400 mbar to 600 mbar, and the first preset thickness ranges from 10 nm to 20 nm.

[0052] Under a second preset temperature and a second preset pressure, a buffer layer 3 of a second preset thickness is grown on the surface of the nucleation layer 2. The first preset temperature ranges from 1020℃ to 1080℃, the first preset pressure ranges from 200 mbar to 600 mbar, and the second preset thickness ranges from 1.5 μm to 2 μm.

[0053] Under a third preset temperature and a third preset pressure, an N-type semiconductor layer 4 of a third preset thickness is grown on the surface of the buffer layer 3. The third preset temperature ranges from 1040℃ to 1060℃, the third preset pressure ranges from 200 mbar to 400 mbar, and the third preset thickness ranges from 1.5 μm to 2 μm.

[0054] Under a fourth preset temperature and a fourth preset pressure, an intrinsic semiconductor layer 5 of a fourth preset thickness is grown on the surface of the N-type semiconductor layer 4. The fourth preset temperature ranges from 700°C to 800°C, the fourth preset pressure ranges from 200 mbar to 400 mbar, and the fourth preset thickness ranges from 100 nm to 200 nm.

[0055] Under a fifth preset temperature and a fifth preset pressure, a primary first quantum well layer 6 of a fifth preset thickness is grown on the surface of the intrinsic semiconductor layer 5. The fifth preset temperature ranges from 650℃ to 800℃; the fifth preset pressure ranges from 200 mbar to 400 mbar; and the fifth preset thickness ranges from 80 nm to 200 nm. Under a sixth preset temperature and a sixth preset pressure, the original second quantum well layer 7 with a sixth preset thickness is grown on the surface of the first quantum well layer 6. The sixth preset temperature ranges from 620℃ to 770℃, the sixth preset pressure ranges from 200 mbar to 400 mbar, and the sixth preset thickness ranges from 80 nm to 200 nm. Under a seventh preset temperature and a seventh preset pressure, the original third quantum well layer 8 with a seventh preset thickness is grown on the surface of the second quantum well layer 7. The seventh preset temperature ranges from 580℃ to 700℃, the seventh preset pressure ranges from 200 mbar to 400 mbar, and the seventh preset thickness ranges from 40 to 100 nm.

[0056] In this embodiment, the barrier layer 9 and the P-type semiconductor layer 10 are grown sequentially, including the following steps: The barrier layer 9 is grown at an eighth preset temperature and an eighth preset pressure, with an eighth preset thickness. The eighth preset temperature ranges from 800°C to 950°C, the eighth preset pressure ranges from 100 mbar to 200 mbar, and the eighth preset thickness ranges from 30 nm to 50 nm.

[0057] At a ninth preset temperature and a ninth preset pressure, a P-type semiconductor layer 10 of a ninth preset thickness is grown on the surface of the barrier layer 9. The ninth preset temperature ranges from 800°C to 900°C, the ninth preset pressure ranges from 200 mbar to 600 mbar, and the ninth preset thickness ranges from 50 nm to 80 nm.

[0058] See Figures 1 to 7 As shown in the embodiments, this application also discloses a method for fabricating a HEMT integrated light-emitting chip, which is used to fabricate the above-mentioned HEMT integrated light-emitting chip, and the steps include: The above-mentioned HEMT integrated epitaxial wafer is provided. The HEMT integrated epitaxial wafer includes a substrate 1, a nucleation layer 2, a buffer layer 3, an N-type semiconductor layer 4, an intrinsic semiconductor layer 5, and a three-color quantum well stack, which are stacked sequentially from bottom to top. The three-color quantum well stack includes a first quantum well layer 6, a second quantum well layer 7, and a third quantum well layer 8, which are stacked sequentially on the intrinsic semiconductor layer 5. The band widths of the first quantum well layer 6, the second quantum well layer 7, and the third quantum well layer 8 decrease sequentially. The three-color quantum well stack is etched to form a first quantum well layer 6', a second quantum well layer 7' stacked on the first quantum well layer 6', and a third quantum well layer 8' stacked on the second quantum well layer 7'. The first quantum well layer 6' includes a first light-emitting region Q1, a second light-emitting region Q2, and a third light-emitting region Q3. The second quantum well layer 7' is disposed on the second light-emitting region Q2 and the third light-emitting region Q3. The third quantum well layer 8' is disposed on the second quantum well layer 7' corresponding to the third light-emitting region Q3. Barrier layer 9 and P-type semiconductor layer 10 are grown sequentially; The P-type semiconductor layer 10 and the barrier layer 9 are etched sequentially to form a first barrier layer 91 and a first P-type semiconductor layer P1 sequentially stacked on the first light-emitting region Q1, a second barrier layer 92 and a second P-type semiconductor layer P2 sequentially stacked on the second quantum well layer 7' corresponding to the second light-emitting region Q2, and a third barrier layer 93 and a third P-type semiconductor layer P3 sequentially stacked on the third quantum well layer 8'. Etch the exposed first quantum well layer 6' and the intrinsic semiconductor layer 5 until the N-type semiconductor layer 4 is exposed to form an electrode hole A; An electrode layer is grown on the epitaxial wafer and inside the electrode hole A after etching of electrode hole A is completed; The electrode layers are etched to form a first source D1, a second source D2, and a third source D3 respectively disposed on the first P-type semiconductor layer P1, the second P-type semiconductor layer P2, and the third P-type semiconductor layer P3; a first gate G1, a second gate G2, and a third gate G3 respectively disposed on the first barrier layer 91, the second barrier layer 92, and the third barrier layer 93; and a common drain S connected to the N-type semiconductor layer 4 and extending along the direction of the first quantum well layer 6'; the first source D1 is connected to the first P-type semiconductor layer P1, and the first gate G1 is spaced apart from the first P-type semiconductor layer P1; the second source D2 is connected to the second P-type semiconductor layer P2, and the second gate G2 is spaced apart from the second P-type semiconductor layer P2; the third source D3 is connected to the third P-type semiconductor layer P3, and the third gate G3 is spaced apart from the third P-type semiconductor layer P3, to obtain a HEMT integrated light-emitting chip.

[0059] This application presents a HEMT integrated light-emitting chip that combines HEMT and LED structures. By directly contacting the barrier layer on each quantum well without any gaps, the light emission is not affected. This avoids the situation where, when an applied gate voltage creates a downward electric field, electrons injected from the N-type semiconductor layer 4 are not blocked by the barrier layer with its high bandgap and high energy barrier before reaching the uppermost light-emitting region, thus reducing light emission efficiency and causing uncontrollable light mixing. In terms of tri-color integration, only the common electron injection and common drain S are maintained. By applying a gate voltage, a two-dimensional electron gas channel (2DEG channel) can be formed at the interface between the quantum well layer and the barrier layer. The magnitude of the applied gate voltage can effectively control the concentration of the two-dimensional electron gas, greatly improving electron migration efficiency. This increases the number of electrons and holes emitting light in the active region, reduces the turn-on voltage, and increases the brightness. At the same time, electrons in other regions will accumulate at the two-dimensional electron gas channel, reducing the probability of electron-hole recombination in other regions and improving the efficiency of light emission recombination. By controlling the concentration of the two-dimensional electron gas and the depth of the channel by applying different voltages to the gate, the luminous intensity can be modulated, ultimately achieving a light mixing effect. The two-dimensional electron gas originates from the barrier formed by the huge energy barrier difference between the quantum well layer and the barrier layer 9, and the high-mobility electron gas channel formed by the attraction of electrons by the strong electric field under the gate voltage. The electron gas is also used for the combined light emission of the LED. See also Figure 9As shown, by applying a voltage to the gate, electrons continuously migrate upwards under the influence of the applied voltage. Simultaneously, due to the wider energy band of the barrier layer and the lower energy level of the quantum well layer, electrons are trapped within the well. Furthermore, because the width of the well is very small, a two-dimensional electron gas forms at the quantum well. Similarly, the energy level of the second quantum well layer 7' is even lower, so electrons do not accumulate in the first quantum well layer 6', but instead form a 2DEG channel in the second quantum well layer 7'. The same applies to the third quantum well layer 8', which will not be elaborated upon here.

[0060] The required area and etching area of ​​the third quantum well layer 8', the second quantum well layer 7' and the first quantum well layer 6' are determined according to actual needs. For example, the required area and etching area of ​​each quantum well layer are planned as a whole according to the degree of color mixing of the emitted light, and no limit is imposed here.

[0061] In this embodiment, the In doping concentration of the original first quantum well layer 6, the original second quantum well layer 7, and the original third quantum well layer 8 all range from 1E17cm / VS to 5E17cm / VS; the cycle number of the original first quantum well layer 6 and the original second quantum well layer 7 ranges from 5 to 8; and the cycle number of the original third quantum well layer 8 ranges from 3 to 6.

[0062] The original second quantum well layer 7 and third quantum well layer 8 are sequentially grown on the original first quantum well layer 6. For example, half of the original third quantum well layer 8 is etched away to a depth down to the original second quantum well layer 7, and then 1 / 3 of the original second quantum well layer 7 is etched away. After completion, a barrier layer 9 is grown epitaxially in a second stage, and finally a P-type semiconductor layer 10 is grown. The specific growth method is as follows: TMGa / TEGa and NH3 are used as group III metal sources and group V compounds for growth on MOCVD. According to actual needs, such as the degree of color mixing of light emission, the three-color light emission area and light emission distribution, the area and shape of each etching can be freely customized, such as etching 1 / 2 and 1 / 4. Corresponding masks are designed for etching to meet different customized needs. The etching process is as follows: After the original third quantum well layer 8 is grown, it is protected with photoresist, leaving the part for light emission. The remaining part is etched down to the original second quantum well layer 7. The light emission part is protected again with photoresist, and the other area is etched down to the original first quantum well layer 6 in a second etching. A secondary epitaxial growth process is performed to grow a barrier layer 9 and a P-type semiconductor layer 10. Etching separates the region into three different light-emitting areas, and simultaneously etches to expose part of the barrier layer 9 for gate plating. Finally, the corresponding electrodes are plated.

[0063] In this embodiment, the three-color quantum well stack is etched to form a first quantum well layer 6', a second quantum well layer 7' stacked on the first quantum well layer 6', and a third quantum well layer 8' stacked on the second quantum well layer 7'. The first quantum well layer 6' includes a first light-emitting region Q1, a second light-emitting region Q2, and a third light-emitting region Q3. The second quantum well layer 7' is disposed on the second light-emitting region Q2 and the third light-emitting region Q3. The third quantum well layer 8' is disposed on the second quantum well layer 7' corresponding to the third light-emitting region Q3. The process includes the following steps: The original third quantum well layer 8 is etched down to the original second quantum well layer 7 to obtain the third quantum well layer 8' stacked on the original second quantum well layer 7; The original second quantum well layer 7 between the second light-emitting region Q2 and the third light-emitting region Q3 is etched down to the original first quantum well layer 6, so that the second quantum well layer 7' on the second light-emitting region Q2 and the second quantum well layer 7' on the third light-emitting region Q3 are spaced apart.

[0064] In this embodiment, after etching the original second quantum well layer 7 between the second light-emitting region Q2 and the third light-emitting region Q3 down to the original first quantum well layer 6, so that the second quantum well layer 7' on the second light-emitting region Q2 and the second quantum well layer 7' on the third light-emitting region Q3 are spaced apart, the following steps are further included: The original first quantum well layer 6 between the first light-emitting region Q1 and the second light-emitting region Q2, the original first quantum well layer 6 between the second light-emitting region Q2 and the third light-emitting region Q3, and the original first quantum well layer 6 between the first light-emitting region Q1 and the third light-emitting region Q3 are etched, such that the first quantum well layer 6' corresponding to the first light-emitting region Q1, the first quantum well layer 6' corresponding to the second light-emitting region Q2, and the first quantum well layer 6' corresponding to the third light-emitting region Q3 are spaced apart.

[0065] In this embodiment, after etching the electrode layer to form a first source D1, a second source D2, and a third source D3 respectively disposed on the first P-type semiconductor layer P1, the second P-type semiconductor layer P2, and the third P-type semiconductor layer P3; a first gate G1, a second gate G2, and a third gate G3 respectively disposed on the first barrier layer 91, the second barrier layer 92, and the third barrier layer 93; and a common drain S connected to the N-type semiconductor layer 4 and extending along the direction of the first quantum well layer 6'; the first source D1 is connected to the first P-type semiconductor layer P1, and the first gate G1 is spaced apart from the first P-type semiconductor layer P1; the second source D2 is connected to the second P-type semiconductor layer P2, and the second gate G2 is spaced apart from the second P-type semiconductor layer P2; the third source D3 is connected to the third P-type semiconductor layer P3, and the third gate G3 is spaced apart from the third P-type semiconductor layer P3, the following steps are further included: The buffer layer 3 is decomposed to peel off the substrate 1. By decomposing the buffer layer 3, the nucleation layer 2 on the substrate 1 can also be peeled off. The decomposition of the buffer layer 3 can be carried out by thermal decomposition, photolysis, chemical decomposition, etc., and the method selected according to the actual situation is not limited here.

[0066] In this embodiment, the original first quantum well layer 6, the original second quantum well layer 7, and the original third quantum well layer 8 each include at least one of the following: an In-doped InGaN layer, an Al-doped AlGaN layer, an undoped GaN layer, and an Al- and In-doped AlInGaN layer. The color rendering of each quantum well is adjusted by regulating the In and Al content in the original first quantum well layer 6, the original second quantum well layer 7, and the original third quantum well layer 8. In some embodiments, other substances can also be used to adjust the color rendering of each quantum well, and this is not a limitation. The process utilizes the characteristic that the gate voltage of a HEMT can attract and gather electrons from undoped regions to form a thin electron gas with high mobility. Simultaneously, it utilizes the characteristics of quantum wells with different In or Al compositions having different bandwidths and barrier heights, for example, directly confining electrons and holes to interfaces with high electron concentration and mobility, preventing electron or hole diffusion from causing recombination and luminescence in other regions. Therefore, three quantum well layers can be directly and continuously epitaxially grown without the need for additional growth of the corresponding complete structure, reducing the overall epitaxial thickness and simplifying the process steps.

[0067] In this embodiment, the original first quantum well layer 6, the original second quantum well layer 7, and the original third quantum well layer 8 are all In-doped InGaN layers; the original first quantum well layer 6 is a blue quantum well layer, the original second quantum well layer 7 is a green quantum well layer, and the original third quantum well layer 8 is a red quantum well layer, with the In doping content of the original first quantum well layer 6, the original second quantum well layer 7, and the original third quantum well layer 8 increasing sequentially. The In doping concentration of the original first quantum well layer 6, the original second quantum well layer 7, and the original third quantum well layer 8 ranges from 1E17cm / VS to 5E17cm / VS; the loop number of the original first quantum well layer 6 and the original second quantum well layer 7 ranges from 5 to 8; and the loop number of the original third quantum well layer 8 ranges from 3 to 6.

[0068] In this embodiment, the barrier layer 9 includes at least one of an AlN barrier layer and an AlGaN barrier layer.

[0069] In this embodiment, the barrier layer 9 is an Al-doped AlGaN barrier layer. The Al content in the barrier layer 9 is between 15% and 25%.

[0070] In this embodiment, the nucleation layer 2 includes a nitride nucleation layer; the nucleation layer 2 is, for example, a nitride nucleation layer, and in other embodiments, it may be other different types of nucleation layers, which are not limited here. Further, the nitride nucleation layer includes at least one of an ALN ​​nucleation layer, a GaN nucleation layer, and an AlGaN nucleation layer.

[0071] In this embodiment, the buffer layer 3 includes at least one of a uGaN buffer layer, an AlN buffer layer, and an AlGaN / GaN superlattice buffer layer; uGaN is an undoped GaN buffer layer.

[0072] In this embodiment, the N-type semiconductor layer 4 includes at least one of an N-type GaN layer and an N-type AlGaN layer.

[0073] In this embodiment, the first P-type semiconductor layer P1, the second P-type semiconductor layer P2, and the third P-type semiconductor layer P3 are made of the same material, and the first P-type semiconductor layer P1 includes at least one of a P-type GaN layer and a P-type AlGaN layer.

[0074] The substrate 1 includes at least one of sapphire, silicon, silicon carbide and gallium nitride.

[0075] In this embodiment, the nucleation layer 2 is an AlN nucleation layer, the buffer layer 3 is a uGaN buffer layer, the N-type semiconductor layer 4 is an N-type GaN layer, the intrinsic semiconductor layer 5 is an I-type GaN layer, and the first P-type semiconductor layer P1, the second P-type semiconductor layer P2, and the third P-type semiconductor layer P3 are all P-type AlGaN layers. The N-type doping concentration of the N-type semiconductor layer 4 ranges from 6E18 cm / VS to 3E19 cm / VS. The P-type doping concentration of the P-type semiconductor layer 10 ranges from 1E19 cm / VS to 2E20 cm / VS.

[0076] In this embodiment, the intrinsic semiconductor layer 5 includes a type I GaN layer. In other embodiments, intrinsic semiconductors of other materials may be used, and this is not limited here.

[0077] In this embodiment, the HEMT integrated light-emitting chip can be a MiniLED, MicroLED, nano-sized LED, or LED of other sizes. It is not limited here, and can be selected according to the actual situation.

[0078] This application also discloses a display backplane, including a driving substrate and the aforementioned HEMT integrated light-emitting chip, wherein the HEMT integrated light-emitting chip is bonded to the driving substrate. In some embodiments, the display backplane can serve as a backlight for a display module or as a direct display for the display module, without specific limitations. The display backplane can be, for example, a television, mobile phone, tablet computer, personal digital assistant (PDA), in-vehicle computer, smartwatch, AR, and VR, etc. This disclosure does not impose any special limitations on the specific form of the aforementioned display device.

[0079] This application presents a HEMT integrated light-emitting chip that combines a HEMT structure with an LED. In terms of fabrication, it leverages the characteristic of HEMTs—that an applied gate voltage can attract and aggregate electrons in undoped regions to form a thin electron gas with high mobility. Simultaneously, it utilizes the different bandwidths and barrier heights of various quantum wells to directly and continuously epitaxially grow three quantum well layers without the need for additional growth of the corresponding complete structure. This reduces the overall epitaxial thickness, simplifies the fabrication process, and results in a more compact structure. The fabrication of a two-dimensional electron gas within the well using the HEMT structure significantly improves electron mobility, thereby increasing the number of electrons and holes emitting light in the active region, reducing the turn-on voltage, and increasing brightness. The direct contact between the quantum wells and the barrier layer without any intervening gaps does not affect light emission, avoiding uncontrollable light mixing that reduces luminous efficiency. By controlling the source current individually or simultaneously and adjusting the voltage to control the presence and concentration of holes within the quantum well, monochromatic, bicolor, and tricolor light emission can be regulated. Utilizing the electron aggregation property under the influence of the HEMT gate voltage and electric field, the number and density of electrons in the non-light-emitting region are reduced, leakage current and the probability of non-radiative recombination light emission are decreased, and the monochromaticity of light emission in the individual light-emitting region is improved. The concentration of the two-dimensional electron gas is controlled by the magnitude of the applied gate voltage, which adjusts the brightness ratio of different colors of light emission, allowing for free mixing of light. Employing a pre-epitaxy-coated structure, followed by etching and electrode evaporation, reduces the complexity of the manufacturing process. This HEMT integrated light-emitting chip not only improves device performance and functional density but also helps reduce system cost and power consumption.

[0080] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A HEMT integrated light-emitting chip, characterized in that, It includes an N-type semiconductor layer, an intrinsic semiconductor layer, a first quantum well layer, a second quantum well layer, and a third quantum well layer stacked sequentially from bottom to top. The first quantum well layer, the second quantum well layer, and the third quantum well layer emit different colors, and the band widths of the first quantum well layer, the second quantum well layer, and the third quantum well layer decrease sequentially. The first quantum well layer includes a first light-emitting region, a second light-emitting region, and a third light-emitting region. A second quantum well layer is disposed on the second and third light-emitting regions. The third quantum well layer is disposed on the second quantum well layer corresponding to the third light-emitting region. A first barrier layer and a first P-type semiconductor layer are sequentially stacked on the first light-emitting region. A first source electrode connected to the first P-type semiconductor layer is disposed on the first P-type semiconductor layer. A first gate electrode spaced apart from the first P-type semiconductor layer is disposed on the first barrier layer. The second quantum well layer corresponding to the second light-emitting region is sequentially stacked on... A second barrier layer and a second P-type semiconductor layer are stacked on top of each other. A second source electrode connected to the second P-type semiconductor layer is disposed on the second P-type semiconductor layer, and a second gate electrode spaced apart from the second P-type semiconductor layer is disposed on the second barrier layer. A third barrier layer and a third P-type semiconductor layer are stacked on top of each other in sequence. A third source electrode connected to the third P-type semiconductor layer is disposed on the third P-type semiconductor layer, and a third gate electrode spaced apart from the third P-type semiconductor layer is disposed on the third barrier layer. A common drain electrode connected to and extending along the direction of the first quantum well layer is disposed on the N-type semiconductor layer.

2. The HEMT integrated light-emitting chip as described in claim 1, characterized in that, The second quantum well layer on the second light-emitting region and the second quantum well layer on the third light-emitting region are spaced apart.

3. The HEMT integrated light-emitting chip as described in claim 2, characterized in that, The first quantum well layer corresponding to the first light-emitting region, the first quantum well layer corresponding to the second light-emitting region, and the first quantum well layer corresponding to the third light-emitting region are spaced apart.

4. The HEMT integrated light-emitting chip as described in any one of claims 1 to 3, characterized in that, The first quantum well layer, the second quantum well layer, and the third quantum well layer each include at least one of the following: an In-doped InGaN layer, an Al-doped AlGaN layer, an undoped GaN layer, and an Al- and In-doped AlInGaN layer.

5. The HEMT integrated light-emitting chip as described in claim 4, characterized in that, The first quantum well layer, the second quantum well layer, and the third quantum well layer are all In-doped InGaN layers; the first quantum well layer is a blue quantum well layer, the second quantum well layer is a green quantum well layer, and the third quantum well layer is a red quantum well layer, with the In doping content of the first quantum well layer, the second quantum well layer, and the third quantum well layer increasing sequentially.

6. The HEMT integrated light-emitting chip according to claim 5, characterized in that, The first barrier layer, the second barrier layer, and the third barrier layer each include at least one of AlN barrier layer and AlGaN barrier layer.

7. The HEMT integrated light-emitting chip as described in claim 6, characterized in that, The first barrier layer, the second barrier layer, and the third barrier layer are all Al-doped AlGaN barrier layers.

8. The HEMT integrated light-emitting chip as described in claim 7, characterized in that, The N-type semiconductor layer includes at least one of an N-type GaN layer and an N-type AlGaN layer; The first P-type semiconductor layer, the second P-type semiconductor layer, and the third P-type semiconductor layer are made of the same material, and the first P-type semiconductor layer includes at least one of a P-type GaN layer and a P-type AlGaN layer.

9. The HEMT integrated light-emitting chip as described in claim 7, characterized in that, It also includes a substrate, a nucleation layer, and a buffer layer, wherein the buffer layer, the nucleation layer, and the substrate are sequentially stacked on the side of the N-type semiconductor layer away from the intrinsic semiconductor layer.

10. A HEMT integrated epitaxial wafer, used to fabricate the HEMT integrated light-emitting chip as described in any one of claims 1 to 9, characterized in that, The material comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a three-color quantum well stack. The three-color quantum well stack includes a first quantum well layer, a second quantum well layer, and a third quantum well layer that are sequentially stacked on the intrinsic semiconductor layer. The band widths of the first quantum well layer, the second quantum well layer, and the third quantum well layer decrease sequentially.

11. The HEMT integrated epitaxial wafer as described in claim 10, characterized in that, The process of growing a core layer, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a tri-color quantum well stack sequentially from bottom to top on the surface of the substrate includes performing the following steps: Under a first preset temperature and a first preset pressure, the nucleation layer of a first preset thickness is grown on the surface of the substrate; Under a second preset temperature and a second preset pressure, a buffer layer of a second preset thickness is grown on the surface of the nucleation layer; Under a third preset temperature and a third preset pressure, the N-type semiconductor layer of a third preset thickness is grown on the surface of the buffer layer; Under a fourth preset temperature and a fourth preset pressure, an intrinsic semiconductor layer of a fourth preset thickness is grown on the surface of the N-type semiconductor layer; Under a fifth preset temperature and a fifth preset pressure, the original first quantum well layer of a fifth preset thickness is grown on the surface of the intrinsic semiconductor layer; Under a sixth preset temperature and a sixth preset pressure, the original second quantum well layer with a sixth preset thickness is grown on the surface of the first quantum well layer; Under a seventh preset temperature and a seventh preset pressure, the original third quantum well layer with a seventh preset thickness is grown on the surface of the second quantum well layer; The sequential growth of the barrier layer and the P-type semiconductor layer includes performing the following steps: Under an eighth preset temperature and an eighth preset pressure, a barrier layer of an eighth preset thickness is grown on the etched epitaxial wafer; At a ninth preset temperature and a ninth preset pressure, a P-type semiconductor layer of a ninth preset thickness is grown on the surface of the barrier layer.

12. The HEMT integrated epitaxial wafer as described in claim 10, characterized in that, The original first quantum well layer, the original second quantum well layer, and the original third quantum well layer are made of the same material.

13. A method for fabricating a HEMT integrated light-emitting chip, used to fabricate the HEMT integrated light-emitting chip as described in any one of claims 1 to 9, characterized in that the step include: A HEMT integrated epitaxial wafer as described in any one of claims 10 to 12 is provided, the HEMT integrated epitaxial wafer comprising, from bottom to top, a substrate, a nucleation layer, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a three-color quantum well stack, wherein the three-color quantum well stack comprises a primary first quantum well layer, a primary second quantum well layer, and a primary third quantum well layer sequentially superimposed on the intrinsic semiconductor layer, and the band widths of the primary first quantum well layer, the primary second quantum well layer, and the primary third quantum well layer decrease sequentially; The three-color quantum well stack is etched to form a first quantum well layer, a second quantum well layer stacked on the first quantum well layer, and a third quantum well layer stacked on the second quantum well layer. The first quantum well layer includes a first light-emitting region, a second light-emitting region, and a third light-emitting region. The second quantum well layer is disposed on the second light-emitting region and the third light-emitting region. The third quantum well layer is disposed on the second quantum well layer corresponding to the third light-emitting region. A barrier layer and a P-type semiconductor layer are grown sequentially. The P-type semiconductor layer and the barrier layer are etched sequentially to form a first barrier layer and a first P-type semiconductor layer that are sequentially stacked on the first light-emitting region, a second barrier layer and a second P-type semiconductor layer that are sequentially stacked on the second quantum well layer corresponding to the second light-emitting region, and a third barrier layer and a third P-type semiconductor layer that are sequentially stacked on the third quantum well layer. Etch the exposed first quantum well layer and the intrinsic semiconductor layer until the N-type semiconductor layer is exposed to form an electrode hole; An electrode layer is grown on the epitaxial wafer and inside the electrode holes after the electrode holes have been etched. The electrode layers are etched to form a first source, a second source, and a third source respectively disposed on the first P-type semiconductor layer, the second P-type semiconductor layer, and the third P-type semiconductor layer; a first gate, a second gate, and a third gate respectively disposed on the first barrier layer, the second barrier layer, and the third barrier layer; and a common drain connected to the N-type semiconductor layer and extending along the direction of the first quantum well layer; the first source is connected to the first P-type semiconductor layer, and the first gate is spaced apart from the first P-type semiconductor layer; the second source is connected to the second P-type semiconductor layer, and the second gate is spaced apart from the second P-type semiconductor layer; the third source is connected to the third P-type semiconductor layer, and the third gate is spaced apart from the third P-type semiconductor layer, to obtain a HEMT integrated light-emitting chip.

14. The method for fabricating a HEMT integrated light-emitting chip as described in claim 13, characterized in that, The etching of the three-color quantum well stack forms a first quantum well layer, a second quantum well layer stacked on the first quantum well layer, and a third quantum well layer stacked on the second quantum well layer. The first quantum well layer includes a first light-emitting region, a second light-emitting region, and a third light-emitting region. The second quantum well layer is disposed on the second light-emitting region and the third light-emitting region. The third quantum well layer is disposed on the second quantum well layer corresponding to the third light-emitting region. The process includes the following steps: The original third quantum well layer is etched down to the original second quantum well layer to obtain a third quantum well layer stacked on the original second quantum well layer; The original second quantum well layer between the second light-emitting region and the third light-emitting region is etched down to the original first quantum well layer, so that the second quantum well layer on the second light-emitting region and the second quantum well layer on the third light-emitting region are spaced apart.

15. The method for fabricating a HEMT integrated light-emitting chip as described in claim 14, characterized in that, After etching the original second quantum well layer between the second light-emitting region and the third light-emitting region down to the original first quantum well layer, so that the second quantum well layer on the second light-emitting region and the second quantum well layer on the third light-emitting region are spaced apart, the method further includes the following steps: The original first quantum well layer between the first light-emitting region and the second light-emitting region, the original first quantum well layer between the second light-emitting region and the third light-emitting region, and the original first quantum well layer between the first light-emitting region and the third light-emitting region are etched, such that the first quantum well layer corresponding to the first light-emitting region, the first quantum well layer corresponding to the second light-emitting region, and the first quantum well layer corresponding to the third light-emitting region are spaced apart.

16. The method for fabricating a HEMT integrated light-emitting chip according to any one of claims 13 to 15, characterized in that, After etching the electrode layer to form a first source, a second source, and a third source respectively disposed on the first P-type semiconductor layer, the second P-type semiconductor layer, and the third P-type semiconductor layer; a first gate, a second gate, and a third gate respectively disposed on the first barrier layer, the second barrier layer, and the third barrier layer; and a common drain connected to the N-type semiconductor layer and extending along the direction of the first quantum well layer; the first source is connected to the first P-type semiconductor layer, and the first gate is spaced apart from the first P-type semiconductor layer; the second source is connected to the second P-type semiconductor layer, and the second gate is spaced apart from the second P-type semiconductor layer; and the third source is connected to the third P-type semiconductor layer, and the third gate is spaced apart from the third P-type semiconductor layer, the process further includes the following steps: The buffer layer is disassembled to peel off the substrate.

17. A display back panel, characterized in that, It includes a driving substrate and a HEMT integrated light-emitting chip as described in any one of claims 1 to 9, wherein the HEMT integrated light-emitting chip is bonded to the driving substrate.

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