Magnetic random access memory and its reading and writing method

Abstract

The present invention provides a magnetic random access memory and a read-write method thereof, wherein the magnetic random access memory comprises: a storage array mainly composed of a plurality of storage units, the storage array is controlled by a plurality of word lines, a plurality of bit lines and a plurality of source lines, and each storage unit has a magnetic tunnel junction; when the magnetic random access memory performs a read or write operation, the bit lines and source lines connected to the non-read-write storage units adjacent to the storage units to be read or written in the storage array are of equal potential. Thus, even if the corresponding word line turns on the MOS tube of the non-read-write storage unit adjacent to the storage unit to be read or written, since the source region and the drain region of the MOS tube of the non-read-write storage unit are of equal potential, no current will flow through the MOS tube, so there will be no problem of misreading and miswriting.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a magnetic random access memory and a reading and writing method thereof. Background Art

[0002] Magnetic Random Access Memory (MRAM) is a new memory and storage technology that can read and write randomly as fast as SRAM / DRAM, and can also permanently retain data after power failure like Flash memory.

[0003] Please refer to Figure 6 The existing conventional magnetic random access memory includes: a storage array 1 mainly composed of a plurality of storage cells, a word line decoder 2 for setting the potential on the word line WL; a bit line decoder 3 for setting the potential on the bit line BL; a source line decoder 4 for setting the potential on the source line SL. The storage array 1 is controlled by a plurality of word lines WL, a plurality of bit lines BL and a plurality of source lines SL, and each storage cell is composed of a magnetic tunnel junction MJT and a MOS tube. Each storage cell needs to be connected to three wires: the gate of the MOS tube is connected to the word line WL of the chip, which is responsible for connecting or disconnecting the cell; one pole (source or drain) of the MOS tube is connected to the source line SL, and the other pole (drain or source) of the MOS tube is connected to one pole of the magnetic tunnel junction, and the other pole of the magnetic tunnel junction is connected to the bit line BL. Specifically, in the memory array 1, three consecutive word lines are marked as WLn-1, WLn, and WLn+1, three consecutive bit lines are marked as BLn-1, BLn, and BLn+1, and three consecutive source lines are marked as SLn-1, SLn, and SLn+1. Figure 6 It can be seen that the upper and lower adjacent memory cells share the same word line WL, but do not share the same source line SL and the same bit line BL, that is, the source line SL and the bit line BL of the two upper and lower adjacent memory cells are isolated from each other.

[0004] Please continue to refer to Figure 6 The reading and writing method of the magnetic random access memory is to apply corresponding potentials on the word lines, bit lines and source lines connected to the storage cells to be read or written. For example, assuming that the storage cells determined by the word lines WLn, bit lines BLn and source lines SLn are the storage cells to be read or written, defined as celln, then the corresponding potentials are applied to the connected word lines WLn, bit lines BLn and source lines SLn.

[0005] In the above-mentioned magnetic random access memory, since the upper and lower adjacent memory cells do not share the bit line and the source line, the area of ​​a single MRAM memory cell is relatively large, and the requirement of high storage density MRAM cannot be met.

[0006] In addition, with the continuous advancement of MRAM technology, some high-storage-density MRAMs have emerged, but these high-storage-density MRAMs have problems with misreading and writing during the reading and writing process.

[0007] Therefore, how to further reduce the size of the MRAM storage unit to improve the density of the MRAM and prevent misreading and writing of the high storage density MRAM has become one of the technical problems that those skilled in the art need to solve urgently. Summary of the invention

[0008] The object of the present invention is to provide a magnetic random access memory and a reading and writing method thereof, so as to further reduce the MRAM storage unit to improve the density of the MRAM and prevent misreading and writing of the MRAM with high storage density.

[0009] In order to solve the above technical problems, the present invention provides a magnetic random access memory, comprising: a storage array mainly composed of a plurality of storage cells, the storage array is controlled by a plurality of word lines, a plurality of bit lines and a plurality of source lines, and each storage cell has a magnetic tunnel junction; when the magnetic random access memory performs a read or write operation, the source lines and bit lines connected to the non-read-write storage cells adjacent to the storage cells to be read or written in the storage array have the same potential.

[0010] Optionally, the non-read-write memory cell adjacent to the memory cell that needs to be read or written includes: sharing the same word line with the memory cell that needs to be read or written.

[0011] Optionally, the bit lines and source lines of a portion of the non-read-write memory cells are of equal potential and equal to the potential of the bit lines of the memory cells that need to be read or written; the bit lines and source lines of another portion of the non-read-write memory cells are of equal potential and equal to the potential of the source lines of the memory cells that need to be read or written.

[0012] Optionally, the magnetic random access memory comprises:

[0013] A semiconductor substrate, wherein a plurality of active regions are arranged in a strip shape along a first direction and a second direction, each of the active regions extends along a third direction, the second direction is perpendicular to the first direction, and the third direction intersects both the first direction and the second direction;

[0014] All the word lines are arranged on the semiconductor substrate along a first direction, and each word line extends along a second direction and straddles a plurality of active regions, and each word line divides the corresponding active region into a source region and a drain region;

[0015] Each of the source lines is formed through the first metal layer and connected to the corresponding source region;

[0016] The bottom of each magnetic tunnel junction is connected to the corresponding drain region through the corresponding second metal layer, and the top is connected to the third metal layer, and the third metal layer is used to form the corresponding bit line;

[0017] Each of the active regions and the word line disposed above the active region forms a corresponding MOS tube, and the corresponding MOS tube formed at the active region and the corresponding magnetic tunnel junction above the drain region form a storage unit.

[0018] Optionally, the magnetic random access memory comprises:

[0019] A semiconductor substrate, wherein a plurality of active regions extending in a strip shape along a first direction and arranged along a second direction are provided in the semiconductor substrate;

[0020] All the word lines are arranged on the semiconductor substrate along a first direction, and each word line extends along a second direction and straddles a plurality of active regions, and each word line divides the corresponding active region into a source region and a drain region;

[0021] Each of the source lines is formed through the first metal layer and connected to the corresponding source region;

[0022] The bottom of each magnetic tunnel junction is connected to the corresponding drain region through the corresponding second metal layer, and the top is connected to the third metal layer, and the third metal layer is used to form a corresponding bit line;

[0023] Each of the active regions and the word line disposed above the active region forms a corresponding MOS tube, and the corresponding MOS tube formed at the active region and the corresponding magnetic tunnel junction above the drain region form a storage unit.

[0024] Optionally, each of the storage units has at least one MOS tube.

[0025] Optionally, the source region and drain region of the MOS tube of each memory cell other than the memory cell on the array boundary of the magnetic random access memory are shared with the surrounding adjacent memory cells, and the area of ​​each memory cell is 4F. 2 , where F is the characteristic size.

[0026] Optionally, an angle between the first direction and the third direction includes but is not limited to 45 degrees.

[0027] Optionally, the magnetic random access memory further includes: a word line decoder for setting the potential on the word line; a bit line decoder for setting the potential on the bit line; and a source line decoder for setting the potential on the source line.

[0028] Based on the same inventive concept, the present invention also provides a method for reading and writing a magnetic random access memory, comprising:

[0029] Setting the potentials on the word line, bit line and source line connected to the memory cell to be read or written;

[0030] Determine a non-read-write memory cell adjacent to the memory cell to be read or written, and set the potential of a source line or a bit line connected to the non-read-write memory cell to be equal to the potential of a source line or a bit line connected to the memory cell to be read or written;

[0031] Perform a read or write operation on the storage unit that needs to be read or written.

[0032] Compared with the prior art, the magnetic random access memory and the reading and writing method thereof of the present invention have the following beneficial effects:

[0033] 1. When the magnetic random access memory performs a read or write operation, the source line and the bit line connected to the non-read-write memory cell adjacent to the memory cell to be read or written in the memory array are at the same potential. Therefore, even if the corresponding word line turns on the MOS transistor of the non-read-write memory cell adjacent to the memory cell to be read or written, since the source region and the drain region of the MOS transistor of the non-read-write memory cell are at the same potential, no current will flow through the MOS transistor, so there will be no problem of misreading or miswriting.

[0034] 2. The active area in the magnetic random access memory is a strip-shaped structure that extends continuously in one direction, and two adjacent storage cells that share the same word line in the word line extension direction can further share the same source line or the same bit line. Therefore, under the premise of occupying the same substrate area, the substrate area space can be effectively utilized to achieve a smaller characteristic size of the storage unit and a higher storage density, and the chip cost is lower.

[0035] 3. The unit area can be 4F 2 (F is the characteristic size) of the densely packed storage array to improve storage density and device integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 1 is a schematic diagram of an equivalent circuit structure of a magnetic random access memory according to an embodiment of the present invention;

[0037] Figure 2 It is a schematic diagram of an example of the layout structure of a magnetic random access memory according to an embodiment of the present invention;

[0038] Figure 3 is along Figure 2 A schematic cross-sectional structure diagram of the XX' line in the magnetic random access memory shown in FIG. 1 (structures such as the interlayer dielectric layer are omitted, and the source line and the bit line are parallel and do not overlap in the vertical direction);

[0039] Figure 4 is along Figure 2 Another schematic diagram of the cross-sectional structure of the XX' line in the magnetic random access memory shown in FIG. 1 (structures such as the interlayer dielectric layer are omitted, and the source line and the bit line overlap in the vertical direction and may intersect in different planes);

[0040] Figure 5A to Figure 5C are three other exemplary schematic diagrams of the layout structure of a magnetic random access memory according to an embodiment of the present invention;

[0041] Figure 6 It is a schematic diagram of the equivalent circuit structure of an existing typical magnetic random access memory. DETAILED DESCRIPTION

[0042] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. The meaning of "and / or" in this article is to choose one or both.

[0043] Please refer to Figure 1 An embodiment of the present invention provides a magnetic random access memory, comprising: a memory array 1 mainly composed of a plurality of memory cell cells, the memory array 1 being controlled by a plurality of word lines WL, a plurality of bit lines BL and a plurality of source lines SL, each memory cell cell being composed of a magnetic tunnel junction MJT and a MOS tube, and each memory cell cell needs to be connected to three lines: a gate of the MOS tube being connected to the word line WL of a chip, responsible for connecting or disconnecting the cell; one pole (source or drain) of the MOS tube being connected to the source line SL, the other pole (drain or source) of the MOS tube being connected to one pole of the magnetic tunnel junction, and the other pole of the magnetic tunnel junction being connected to the bit line BL.

[0044] When the magnetic random access memory performs a read or write operation, the source line SL and the bit line BL connected to the non-read or write memory cells adjacent to the memory cells to be read or written in the memory array are at the same potential, wherein the non-read or write memory cells adjacent to the memory cells to be read or written are all memory cells that share the same word line WL with the memory cells to be read or written, or a string of memory cells that share the same word line WL with the memory cells to be read or written. It should be noted that Figure 1In the memory array 1 shown in the figure, although only three consecutive word lines WLn-1, WLn, WLn+1, three consecutive bit lines BLn-1, BLn, BLn+1, three consecutive source lines SLn-1, SLn, SLn+1 and the MOS wafers and magnetic tunnel junctions connected thereto are shown, those skilled in the art can foresee that the memory array 1 of this embodiment should be arranged along the Figure 1 The four directions of up, down, left and right are extended regularly accordingly.

[0045] In this embodiment, the magnetic random access memory further includes: a word line decoder 2 for setting the potential on the word line WL; a bit line decoder 3 for setting the potential on the bit line BL; and a source line decoder 4 for setting the potential on the source line SL.

[0046] Please refer to Figure 1 The reading and writing method of the magnetic random access memory of this embodiment comprises:

[0047] First, the potentials of the word line, bit line, and source line connected to the memory cell to be read or written are set.

[0048] Next, determine the non-read-write memory cells adjacent to the memory cells that need to be read or written. Specifically, the memory cells in the memory array are divided into three categories: (1) memory cells that need to be read or written; (2) non-read-write memory cells adjacent to the memory cells that need to be read or written, that is, those memory cells that share the same word line with the memory cells that need to be read or written; (3) other irrelevant memory cells, that is, those memory cells that do not share the same word line with the memory cells that need to be read or written. For example, assuming that the memory cell determined by the word line WLn, the bit line BLn and the source line SLn is a memory cell that needs to be read or written, and is defined as celln, then all the memory cells that share the same word line WLn with the memory cell celln are non-read-write memory cells adjacent to the memory cell celln that needs to be read or written, and these non-read-write memory cells include the memory cell determined by the word line WLn, the bit line BLn and the source line SLn-1 (defined as celln-1), and the memory cell determined by the word line WLn, the bit line BLn+1 and the source line SLn (defined as celln+1), wherein the memory cell celln that needs to be read or written and the non-read-write memory cell celln-1 not only share the same word line WLn, but also further share the same bit line BLn, and the memory cell celln that needs to be read or written and the non-read-write memory cell celln+1 not only share the same word line WLn, but also further share the same source line SLn.

[0049] Then, the source line and the bit line connected to each of the non-read-write memory cells are set to the same potential. Specifically, the memory cells determined by the above-mentioned word line WLn, bit line BLn and source line SLn are the memory cells celln that need to be read or written, and it is assumed that the memory array 1 has m word lines WL0~WLm-1, k bit lines BL0~BLk-1 and k source lines SL0~SLk-1, 0≤n≤m-1 and 0≤n≤k-1, m, n, k are all integers greater than 1, then the bit lines and source lines of all memory cells that share the same word line WLn with the memory cell celln that needs to be read or written are set to the same potential, at this time, the potentials of the source lines SL0~SLn-1 and the bit lines BL0~BLn-1 are equal to the potential of the bit line BLn, and the potentials of the source lines SLn+1~SLk-1 and the bit lines BLn+1~BLk-1 are equal to the potential of the source line SLn. That is, among all the non-read-write memory cells adjacent to the memory cell celln that needs to be read or written (i.e., all the memory cells that share the same word line WLn with the memory cell celln that needs to be read or written), a portion of the non-read-write memory cells (i.e., Figure 1 The bit lines and source lines of the memory cells along WLn and arranged above the bit line BLn are of equal potential and are equal to the potential of the bit line BLn of the memory cell celln that needs to be read or written; the other part of the non-read and write memory cells is in Figure 1 The bit line and source line of the memory cell along WLn and arranged below the source line SLn are of equal potential and are equal to the potential of the source line SLn of the memory cell celln to be read or written. Specifically, Figure 1 In the example, the bit line BLn and the source line SLn-1 connected to the memory cell celln-1 determined by the three lines WLn, the bit line BLn and the source line SLn-1 are set to the same potential, and the bit line BLn+1 and the source line SLn connected to the memory cell celln+1 determined by the word line WLn, the bit line BLn+1 and the source line SLn are set to the same potential. The potentials of the bit line BLn and the source line SLn are different.

[0050] Afterwards, the storage unit that needs to be read or written is read or written according to the above settings.

[0051] When the storage cell celln that needs to be read or written is read or written, even if the word line WLn connected to it turns on the MOS tubes of the non-read-write storage cells that share the word line WLn and are adjacent to the storage cells that need to be read or written, the bit lines BL and source lines SL connected to these non-read-write storage cells are at the same potential, that is, the source and drain regions of the MOS tubes of these non-read-write storage cells are at the same potential, so no current will flow through the MOS tubes of these non-read-write storage cells adjacent to the storage cells that need to be read or written, that is, when the storage cell celln that needs to be read or written is read or written, it will not cause erroneous reading or writing of the non-read-write storage cells that are adjacent to it and share the same word line. Please refer to Figure 1 When the storage cell celln is read or written, the MOS tubes of the storage cell celln-1 and the storage cell celln+1 are turned on. However, since the bit line BLn and the source line SLn-1 connected to the storage cell celln-1 are at the same potential, and the bit line BLn+1 and the source line SLn connected to the storage cell celln+1 are at the same potential, the source region and the drain region of the MOS tube of the storage cell celln-1 are at the same potential, and the source region and the drain region of the MOS tube of the storage cell celln+1 are at the same potential. Therefore, no current will flow through the MOS tube of the storage cell celln-1 and the MOS tube of the storage cell celln+1, and the storage cell celln-1 and the storage cell celln+1 will not be misread or written.

[0052] The circuit of the magnetic random access memory and the reading and writing method thereof based on the present embodiment can realize a smaller storage unit layout design to achieve a higher storage density, for example, the storage unit area is realized as 4F. 2 (F is the characteristic dimension). Figures 2 to 5C The invention has 4F 2 Layout design of magnetic random access memory based on storage cell area.

[0053] Please refer to Figure 2 As an example, the layout structure of the magnetic random access memory of this embodiment specifically includes: a semiconductor substrate 100, a plurality of word lines WL, a plurality of source lines SL, a plurality of magnetic tunnel junctions 106 and a plurality of bit lines BL. Figure 2 Although only the area defined by the word lines WLn-2 to WLn+1, the source lines SLn-1 to SLn+1, and the bit lines BLn to BLn+1 are shown in the figure, those skilled in the art can foresee that the layout structure of this embodiment should be along the Figure 2 The layout structure is obtained by regularly extending the four directions of up, down, left and right.

[0054] The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. Impurities may be implanted into the semiconductor substrate 100 to form an active region 101, and the impurities may include n-type impurities such as phosphorus and arsenic, or p-type impurities such as boron and gallium. The interval between adjacent active regions 101 is a field region (not shown), and the field region may be formed by a shallow trench isolation (STI) process or a local field oxidation isolation (LOCOS) process.

[0055] In this embodiment, a plurality of active regions 101 are formed in the semiconductor substrate 100, and all active regions 101 are in strip shape and can be arranged along a first direction and a second direction perpendicular to each other, and the length of the active region 101 extends along a third direction, the third direction intersects with both the first direction and the second direction, and the angle between the third direction and the first direction includes but is not limited to 45 degrees, that is, it can be 45 degrees or not. All active regions 101 are arranged in an array, wherein each active region 101 can extend continuously in the third direction to the entire third direction length of the corresponding semiconductor substrate 100, or can be disconnected in certain areas, thereby forming a plurality of active region 101 blocks aligned in the first direction and the second direction.

[0056] A plurality of word lines WL are arranged along a first direction and formed on the semiconductor substrate 100, and each word line WL extends along a second direction and is arranged across a plurality of active regions 101, wherein the second direction is perpendicular to the first direction. Each word line WL divides the corresponding active region 101 into a source region 101a and a drain region 101b. Each active region 101 and the corresponding word line WL arranged above the active region 101 form a corresponding MOS transistor, that is, the word line WL serves as the gate of the MOS transistor, the active regions 101 on both sides of the word line WL are the source region 101a and the drain region 101b of the MOS transistor respectively, and the active region 101 covered by the word line WL is the channel region of the MOS transistor. The material of the word line WL may be polysilicon or metal gate material, and there is a gate dielectric layer (not shown) between the word line WL and the semiconductor substrate 100, and a sidewall (SideWall or Spacer, not shown) may also be formed on the sidewall of the word line WL. The line width of the word line WL may be equal to or smaller than the column pitch of the plug array formed by the source contact plug and the drain contact plug to avoid the word line WL overlapping with other active regions 101 to cause interference between memory cells and affect device performance.

[0057] A plurality of source lines SL are formed through the first metal layer 103 and connected to corresponding source regions 101 a through corresponding source contact plugs 102 .

[0058] The bottom of each magnetic tunnel junction (MTJ) 106 is connected to the corresponding drain region 101b through the corresponding second metal layer 105 and the drain contact plug 104 under the second metal layer 105, and the top of each magnetic tunnel junction 106 is connected to the third metal layer 107, and the third metal layer 107 is used to form a corresponding bit line BL. The MOS transistor formed at each active area 101 and the magnetic tunnel junction 106 above the active area 101 form a storage unit cell, and the area of ​​each storage unit cell is 2F*2F=4F 2 Adjacent memory cells sharing the same word line WL may further share the same bit line BL or the same source line SL. The source contact plug 102, the drain contact plug 104, the first metal layer 103, the second metal layer 105, and the third metal layer 107 may all include metal and / or metal nitride. All source contact plugs 102 and drain contact plugs 104 are arranged in rows and columns into a plug array, the row direction of the plug array being the first direction perpendicular to the second direction, and the column direction of the plug array being the second direction, thereby arranging the magnetic tunnel junctions 106 into a corresponding array according to the layout of the plug array.

[0059] Each magnetic tunnel junction 106 may include a barrier layer (not shown), a pinning layer, a lower ferromagnetic layer, an antiferromagnetic coupling spacer layer, and an upper ferromagnetic layer, etc., which are sequentially formed on the second metal layer 105. The barrier layer can reduce or avoid abnormal growth of metal in the pinning layer, the lower ferromagnetic layer, the ferromagnetic coupling spacer layer, and the upper ferromagnetic layer, etc. The barrier layer may include an amorphous metal or metal nitride, such as tantalum, tantalum nitride, titanium, titanium nitride, etc. The pinning layer may include, for example, FeMn, IrMn, PtMn, MnO, MnS, MnTe, MnF2, FeF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, Cr, etc. The lower ferromagnetic layer and the upper ferromagnetic layer may include, for example, Fe, Ni, Co, etc. The antiferromagnetic coupling spacer layer may include, for example, Ru, Ir, Rh, etc. The lower ferromagnetic layer may have a fixed or "pinned" magnetic orientation, while the upper ferromagnetic layer has a variable or "free" magnetic orientation and may be switched between two or more different magnetic polarities, each representing a different data state, such as a different binary state. However, in other embodiments, the MTJ 106 may be "flipped" vertically so that the lower ferromagnetic layer has a "free" magnetic orientation and the upper ferromagnetic layer has a "fixed" magnetic orientation.

[0060] Please refer to Figure 2 and Figure 3In this embodiment, the bit line BL and the source line SL are arranged in parallel, and the metal layers where the bit line BL and the source line SL are located do not overlap at all. The bit line BL contacts the drain region through the magnetic tunnel junction 106, the second metal layer 105 and the drain contact plug 104 in sequence, and the source line SL contacts the source region through the source contact plug 102. All the drain contact plugs 104 and the source contact plugs 102 are arranged in a plug array along the first direction and the second direction, please refer to Figure 2 , in a top-view angle, the row direction of the plug array is the first direction, the column direction of the plug array is the second direction, the drain contact plugs 104 of two adjacent rows are aligned, the drain contact plugs 104 of two adjacent columns are aligned, the source contact plugs 102 of two adjacent rows are aligned, the source contact plugs 102 of two adjacent columns are aligned, and a row of source contact plugs 102 is sandwiched between the drain contact plugs 104 of two adjacent rows. And the bit line BL intersects and is perpendicular to the word line WL (that is, the projection of the bit line BL and the word line WL on the surface of the semiconductor substrate 100 intersects and is perpendicular, and in fact the bit line BL and the word line WL are perpendicularly intersecting in different planes). At this time, in this embodiment, the two adjacent storage cells sharing the same word line WL can further share the same bit line BL or the same source line SL. Figure 3 The structure of source line SL and bit line BL shown in the figure can reduce the interference between adjacent memory cells and improve the device performance. On the other hand, it can relatively increase the distance between two adjacent contact plugs on two adjacent bit lines BL, reduce the difficulty of making contact plugs, avoid problems such as bridging, and improve the device performance. At this time, the intersection connection part of each word line WL and each bit line BL corresponds to a memory cell. Each memory cell can be a 1 transistor (T) 1 magnetic tunnel junction (MTJ) structure. The area of ​​each memory cell is 2F*2F=4F. 2 Wherein F is a characteristic dimension, and the length of each storage unit cell in a direction perpendicular to the second direction is 2F, and the length in the second direction is 2F.

[0061] In addition, adjacent word lines WL, adjacent bit lines BL, adjacent source lines SL, adjacent magnetic tunnel junctions 106, adjacent contact plugs, word line WL and bit line BL, word line WL and source line SL, word line WL and magnetic tunnel junction 106, source line SL and magnetic tunnel junction 106, source line SL and bit line, and second metal layers 105 of adjacent memory cell cells are all insulated and isolated by corresponding insulating dielectric layers (not shown).

[0062] It should also be noted that in the technical solution of the present invention, the layout of the active area and the word line is not limited to the top view angle. Figure 2The layout structure shown in the figure, the layout of the bit line BL and the source line SL is not limited to the top view angle Figure 2 The layout structure shown in the figure is not limited to the cross-sectional view. Figure 3 The layout structure shown can be any other suitable layout. For example, please refer to Figure 4 In other embodiments of the present invention, the bit line BL and the source line SL may also be arranged to intersect with each other in different planes. Figure 4 As shown, the metal layers where the bit line BL and the source line SL are located partially overlap, and the bit line BL contacts a part of the metal layer 103' of the metal layer 103 where the source line SL is located through the magnetic tunnel junction 106, the second metal layer 105 and the drain contact plug 104' in sequence, the metal layer 103' contacts the drain region through the drain contact plug 104, and the source line SL contacts the source region through the source contact plug 102. The bit line BL is also perpendicular to the word line WL.

[0063] For another example, see Figure 5A In other embodiments of the present invention, Figure 2 Based on the layout of the word line WL and the active area 101, the bit line BL and the source line SL are arranged in parallel, and the bit line BL intersects the word line WL in different planes but is not perpendicular (that is, the bit line BL intersects with the projection of the word line WL on the surface of the semiconductor substrate 100 and the angle is not 90 degrees). Optionally, the bit line BL and the source line SL are arranged along the third direction. At this time, the memory cells in two adjacent rows can further share the same bit line BL or the same source line SL, that is, the adjacent memory cells sharing the same word line WL can further share the same bit line BL or the same source line SL. Similarly, Figure 5A Although only the area defined by the word lines WLn-2 to WLn+1, the source lines SLn-2 to SLn+1, and the bit lines BLn-1 to BLn+2 is shown, those skilled in the art can foresee that the layout structure of this embodiment should be along the Figure 5A The layout structure is obtained by regularly extending the four directions of up, down, left and right.

[0064] For another example, please refer to Figure 5B In other embodiments of the present invention, a layout in which the word lines WL and the active area 101 are perpendicular to each other is adopted. Specifically, the layout structure of the magnetic random access memory of this embodiment specifically includes: a semiconductor substrate 100, a plurality of word lines WL, a plurality of source lines SL, a plurality of magnetic tunnel junctions 106, and a plurality of bit lines BL. In this example, two adjacent storage cells sharing the same word line WL can further share the same source line SL or the same bit line BL. Similarly, Figure 5BAlthough only the area defined by the word lines WLn-1 to WLn+1, the source lines SLn-1 to SLn+1, and the bit lines BLn-2 to BLn+1 are shown in the figure, those skilled in the art can foresee that the layout structure of this embodiment should be along the Figure 5B The layout structure is obtained by regularly extending the four directions of up, down, left and right.

[0065] In this embodiment, a plurality of active regions 101 are formed in the semiconductor substrate 100, each active region 101 extends in a continuous strip along the first direction, and all active regions 101 are arranged in parallel along the second direction. Each active region 101 can extend continuously in the first direction to the length of the entire memory array region of the corresponding semiconductor substrate 100. The size of each memory cell in the memory array defined by the active region array is 2F in the first direction and 2F in the second direction, and the area of ​​each memory cell is 2F*2F=4F. 2 , where F is the minimum size corresponding to the process manufacturing of this magnetic random access memory array as a part or a large part of a semiconductor integrated circuit chip, and is often referred to as the feature size.

[0066] A plurality of word lines WL are arranged along a first direction and formed on the semiconductor substrate 100, and each word line WL extends along a second direction and is arranged across a plurality of active regions 101, wherein the second direction is perpendicular to the first direction. Each word line WL divides the corresponding active region into a source region 101a and a drain region 101b. Each active region 101 and the word line WL arranged above the active region 101 form a corresponding MOS transistor, that is, the word line WL serves as the gate of the MOS transistor, the active regions 101 on both sides of the word line WL are the source region 101a and the drain region 101b of the MOS transistor, respectively, and the active region 101 covered by the word line WL is the channel region of the MOS transistor. There is also a gate dielectric layer (not shown) between the word line WL and the semiconductor substrate 100, and a sidewall (SideWall or Spacer, not shown) may also be formed on the sidewall of the word line WL. The line width of the word line WL may be equal to or smaller than the column pitch of the plug array formed by the source contact plug and the drain contact plug to avoid interference between memory cells and affect device performance.

[0067] A plurality of source lines SL are formed through the first metal layer 103 and connected to corresponding source regions 101 a through corresponding source contact plugs 102 .

[0068] The bottom of each magnetic tunnel junction (MTJ) 106 is connected to the corresponding drain region 101b through the corresponding second metal layer 105 and the drain contact plug 104 under the second metal layer 105, and the top of each magnetic tunnel junction 106 is connected to the third metal layer 107, and the third metal layer 107 is used to form the corresponding bit line BL. Among them, the MTJ 106 is only formed on the drain region of the MOS tube connected to the bit line BL, and the corresponding MOS tube formed at each active region 101 and the magnetic tunnel junction 106 above the active region 101b of the drain region of the MOS tube constitute a storage unit.

[0069] Please combine Figure 3 and Figure 5B In this embodiment, the bit line BL and the source line SL are arranged in parallel, and the metal layers where the bit line BL and the source line SL are located do not overlap at all. The bit line BL contacts the drain region through the magnetic tunnel junction 106, the second metal layer 105 and the drain contact plug 104 in sequence, and the source line SL contacts the source region through the source contact plug 102. All the drain contact plugs 104 and the source contact plugs 102 are arranged in rows and columns to form a plug array. Please continue to refer to Figure 5B In a top view, in each row of plugs, the drain contact plugs 104 and the source contact plugs 102 are arranged alternately, and in each column of plugs, the drain contact plugs 104 and the source contact plugs 102 are also arranged alternately, and the drain contact plugs 104 in two adjacent rows are staggered and misaligned, the source contact plugs 102 in two adjacent rows are staggered and misaligned, the drain contact plugs 104 in two adjacent columns are staggered and misaligned, and the source contact plugs 102 in two adjacent columns are staggered and misaligned. In addition, the bit line BL intersects with the word line WL and is not perpendicular (that is, the projection of the bit line BL and the word line WL on the surface of the semiconductor substrate 100 intersects with each other and is not perpendicular, and in fact, the bit line BL and the word line WL intersect in different planes), for example, the angle between the bit line BL and the word line WL can be 45 degrees, but is not limited to 45 degrees.

[0070] For another example, please combine Figure 4 and Figure 5B In other embodiments of the present invention, Figure 5B Based on the layout of the word line WL and the active area 101, the bit line BL and the source line SL are arranged to intersect each other in different planes and are perpendicular to the word line WL. Please refer to Figure 4As shown, the metal layers where the bit line BL and the source line SL are located partially overlap, and the bit line BL contacts a part of the metal layer 103' of the metal layer 103 where the source line SL is located through the magnetic tunnel junction 106, the second metal layer 105 and the drain contact plug 104' in sequence, the metal layer 103' contacts the drain region through the drain contact plug 104, and the source line SL contacts the source region through the source contact plug 102. The bit line BL is also perpendicular to the word line WL.

[0071] For another example, please refer to Figure 5C In other embodiments of the present invention, Figure 5B Based on the layout of the word line WL and the active area 101, the bit line BL and the source line SL are arranged in parallel, and the bit line BL intersects the word line WL perpendicularly in different planes (that is, the projection of the bit line BL and the word line WL on the surface of the semiconductor substrate 100 intersects and is perpendicular, and in fact, the bit line BL and the word line WL are perpendicular in different planes). At this time, the memory cells in two adjacent rows can further share the same bit line BL or the same source line SL, that is, the adjacent memory cells sharing the same word line WL can further share the same bit line BL or the same source line SL. Similarly, Figure 5C Although only the area defined by the word lines WLn-1 to WLn+1, the source lines SLn to SLn+1, and the bit lines BLn-1 to BLn+1 is shown, those skilled in the art can foresee that the layout structure of this embodiment should be along the Figure 5C The layout structure is obtained by regularly extending the four directions of up, down, left and right.

[0072] In summary, the magnetic random access memory of the present invention can effectively utilize the substrate area space under the premise of occupying the same substrate area through the layout mode of connecting the active area extending in a strip shape and intersecting multiple word lines, so as to achieve a smaller characteristic size of the storage unit and a higher storage density, and a lower chip cost. Furthermore, it can achieve a unit area of ​​4F 2 (F is the characteristic size) of the densely packed storage array, improving the storage density and device integration. More importantly, when the magnetic random access memory performs a read or write operation, the source line and the bit line connected to the non-read-write storage unit adjacent to the storage unit to be read or written in the storage array are at the same potential. Therefore, even if the corresponding word line turns on the MOS tube of the non-read-write storage unit adjacent to the storage unit to be read or written, since the source region and the drain region of the MOS tube of the non-read-write storage unit are at the same potential, no current will flow through the MOS tube, so there will be no problem of misreading and miswriting.

[0073] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A magnetic random access memory, characterized in that: The magnetic random access memory comprises: a memory array mainly composed of a plurality of memory cells, the memory array is controlled by a plurality of word lines, a plurality of bit lines and a plurality of source lines, and each memory cell has a magnetic tunnel junction; when the magnetic random access memory performs a read or write operation, the potential of the bit line and the source line of the memory cell to be read or written in the memory array are different, and the potential of the bit line and the source line connected to the non-read or write memory cell adjacent to the memory cell to be read or written is the same; Among them, the non-read-write memory cells adjacent to the memory cells that need to be read or written include: memory cells that share the same word line with the memory cells that need to be read or written; and among the non-read-write memory cells that share the same word line with the memory cells that need to be read or written, the bit lines and source lines of a part of the non-read-write memory cells are of the same potential and equal to the potential of the bit lines of the memory cells that need to be read or written, and the bit lines and source lines of another part of the non-read-write memory cells are of the same potential and equal to the potential of the source lines of the memory cells that need to be read or written, and at least two of the source lines of the non-read-write memory cells have different potentials.

2. The magnetic random access memory according to claim 1, wherein: The magnetic random access memory comprises: A semiconductor substrate, wherein a plurality of active regions are arranged in a strip shape along a first direction and a second direction, each of the active regions extends along a third direction, the second direction is perpendicular to the first direction, and the third direction intersects both the first direction and the second direction; All the word lines are arranged on the semiconductor substrate along a first direction, and each word line extends along a second direction and straddles a plurality of active regions, and each word line divides the corresponding active region into a source region and a drain region; Each of the source lines is formed through the first metal layer and connected to the corresponding source region; The bottom of each magnetic tunnel junction is connected to the corresponding drain region through the corresponding second metal layer, and the top is connected to the third metal layer, and the third metal layer is used to form the corresponding bit line; Each of the active regions and the word line disposed above the active region forms a corresponding MOS tube, and the corresponding MOS tube formed at the active region and the corresponding magnetic tunnel junction above the drain region form a storage unit.

3. The magnetic random access memory according to claim 1, wherein: The magnetic random access memory comprises: A semiconductor substrate, wherein a plurality of active regions extending in a strip shape along a first direction and arranged along a second direction are provided in the semiconductor substrate; All the word lines are arranged on the semiconductor substrate along a first direction, and each word line extends along a second direction and straddles a plurality of active regions, and each word line divides the corresponding active region into a source region and a drain region; Each of the source lines is formed through the first metal layer and connected to the corresponding source region; The bottom of each magnetic tunnel junction is connected to the corresponding drain region through the corresponding second metal layer, and the top is connected to the third metal layer, and the third metal layer is used to form a corresponding bit line; Each of the active regions and the word line disposed above the active region forms a corresponding MOS tube, and the corresponding MOS tube formed at the active region and the corresponding magnetic tunnel junction above the drain region form a storage unit.

4. The magnetic random access memory according to claim 2 or 3, characterized in that: Each of the storage units has at least one MOS tube.

5. The magnetic random access memory according to claim 4, characterized in that: The source region and drain region of the MOS tube of each memory cell except the memory cell on the array boundary of the magnetic random access memory are shared with the surrounding adjacent memory cells, and the area of ​​each memory cell is 4F. 2 , where F is the feature size.

6. The magnetic random access memory according to claim 2, wherein: The angle between the first direction and the third direction includes but is not limited to 45 degrees.

7. The magnetic random access memory according to claim 1, wherein: The magnetic random access memory further comprises: a word line decoder for setting the potential on the word line; a bit line decoder for setting the potential on the bit line; and a source line decoder for setting the potential on the source line.

8. A method for reading and writing a magnetic random access memory according to any one of claims 1 to 7, characterized in that: include: Respectively setting the potentials of the word line, the bit line and the source line connected to the memory cell to be read or written, and the potentials of the bit line and the source line of the memory cell to be read or written are different; Determine a non-read-write memory cell adjacent to the memory cell that needs to be read or written, the non-read-write memory cell adjacent to the memory cell that needs to be read or written includes a memory cell that shares the same word line with the memory cell that needs to be read or written, set the source line and the bit line connected to a portion of the non-read-write memory cells that share the same word line with the memory cell that needs to be read or written to be equipotential and equal to the potential of the bit line of the memory cell that needs to be read or written, and set the bit line and the source line of another portion of the non-read-write memory cells that share the same word line with the memory cell that needs to be read or written to be equipotential and equal to the potential of the source line of the memory cell that needs to be read or written; Perform a read or write operation on the storage unit that needs to be read or written.

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