Magnetic random access memory array and semiconductor device

Abstract

The present invention provides a magnetic random access memory array and semiconductor device, which effectively utilizes space by staggering the active regions of two adjacent rows under the premise of occupying the same substrate area, realizes a smaller characteristic size of the memory unit, has a higher overall density, and has a lower chip cost. Furthermore, it can realize a unit area of ​​8F 2 (F is the characteristic size) of the densely packed memory array, improving the storage density and device integration. In addition, the source line and the bit line can intersect with the word line and are not perpendicular, so that the memory cells corresponding to the adjacent active areas on the same row and column do not share the same bit line, thereby reducing the interference between adjacent memory cells and improving device performance.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a magnetic random access memory array and a semiconductor device. Background Art

[0002] Magnetic Random Access Memory (MRAM) is a new memory and storage technology that can read and write randomly as fast as SRAM / DRAM, and can also retain data permanently after power failure like Flash memory. Each MRAM storage cell consists of a magnetic tunnel junction and a MOS tube, or two magnetic tunnel junctions and two MOS tubes. Each storage cell needs to be connected to three wires: the gate of the MOS tube is connected to the word line of the chip, which is responsible for turning on or off the unit; one pole of the MOS tube (source or drain) is connected to the source line, and the other pole of the MOS tube (drain or source) is connected to one pole of the magnetic tunnel junction, and the other pole of the magnetic tunnel junction is connected to the bit line.

[0003] As MRAM technology continues to advance, how to further reduce the size of MRAM storage cells to increase the density of MRAM has become one of the technical issues that technicians in this field need to solve urgently. Summary of the invention

[0004] An object of the present invention is to provide a magnetic random access memory array and a semiconductor device having a reduced memory cell area and an increased memory density.

[0005] In order to solve the above technical problems, the present invention provides a magnetic random access memory array, comprising:

[0006] A semiconductor substrate, wherein a plurality of active regions arranged in an array in rows and columns are provided in the semiconductor substrate, and the active regions in two adjacent rows are arranged in a staggered manner;

[0007] A plurality of word lines are formed on the semiconductor substrate, and each of the word lines extends along a column direction and straddles a plurality of active regions in the same column, and each of the word lines divides a corresponding active region into a source region and a drain region;

[0008] A plurality of source lines, each of the source lines is formed through the first metal layer and connected to a corresponding source region;

[0009] A plurality of magnetic tunnel junctions, each of which has a bottom connected to a corresponding drain region through a corresponding second metal layer and a top connected to a third metal layer, wherein the third metal layer is used to form a corresponding bit line.

[0010] Optionally, each of the active regions and the word line disposed above the active region form a corresponding MOS tube, and the MOS tube and the magnetic tunnel junction above the drain region form a storage unit, and the area of ​​the storage unit is 8F. 2 , where F is the characteristic size of the magnetic random access memory array, and the length of the memory cell in the row direction is twice the length in the column direction.

[0011] Optionally, a distance between two adjacent active regions in the same row is smaller than a length of the active region in the row direction.

[0012] Optionally, the bit line and the source line are arranged in parallel.

[0013] Optionally, the bit line intersects the word line at different planes and is not perpendicular to the word line, or the bit line is perpendicular to the word line.

[0014] Optionally, when the bit line and the word line intersect at different planes and are not perpendicular, two adjacent storage cells on the same row and the same column do not share the bit line and the source line; when the bit line and the word line are perpendicular, the storage cells in two adjacent rows share the same bit line and / or the same source line.

[0015] Optionally, when the bit line intersects the word line at different planes and is not perpendicular, the angle between the bit line and the word line includes but is not limited to 45 degrees.

[0016] Optionally, each of the drain regions is connected to the second metal layer at the bottom of the magnetic tunnel junction through a drain contact plug located above the drain region, and each of the source regions is connected to the source line through a source contact plug located above the source region; the drain contact plugs and the source contact plugs are arranged into a plug array in the rows and columns.

[0017] Optionally, the drain contact plugs and the source contact plugs in each column of the plug array are arranged alternately, and the drain contact plugs and the source contact plugs in each row of the plug array are arranged alternately.

[0018] Based on the same inventive concept, the present invention also provides a semiconductor device, including the magnetic random access memory array described in the present invention.

[0019] Compared with the prior art, the magnetic random access memory array and the semiconductor device having the magnetic random access memory array of the present invention have the following beneficial effects:

[0020] 1. Under the premise of occupying the same substrate area, the staggered arrangement between two adjacent rows of active areas effectively utilizes the space, achieves a smaller characteristic size of the storage unit, higher overall density, and lower chip cost.

[0021] 2. The unit area can be 8F 2 (F is the characteristic size of the magnetic random storage array) to improve storage density and device integration.

[0022] 3. The source line and the bit line can be made to intersect with the word line and not be perpendicular, thereby increasing the distance between two adjacent bit lines or two source lines, reducing the difficulty of manufacturing the source line, the bit line, the drain contact plug and the source contact plug, and then reducing the interference between adjacent storage cells and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the layout structure of a magnetic random access memory array according to a specific embodiment of the present invention (structures such as bit lines BL and source lines SL are omitted);

[0024] Figure 2 This is an embodiment of the present invention. Figure 1 A schematic diagram of the cross-sectional structure of the XX' line in the magnetic random access memory array shown (structures such as the interlayer dielectric layer are omitted);

[0025] Figure 3 It is a schematic diagram of the layout of source lines and bit lines of a magnetic random access memory array according to a specific embodiment of the present invention;

[0026] Figure 4 It is another schematic diagram of the layout of source lines and bit lines of a magnetic random access memory array according to a specific embodiment of the present invention;

[0027] Figure 5 Another embodiment of the present invention is along Figure 1 Another schematic cross-sectional structure diagram of the XX' line in the magnetic random access memory array is shown (structures such as the interlayer dielectric layer are omitted). DETAILED DESCRIPTION

[0028] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. The meaning of "and / or" in this article is to choose one or both.

[0029] Please refer to Figures 1 to 3 An embodiment of the present invention provides a magnetic random access memory array, including a semiconductor substrate 100, a plurality of word lines WL, a plurality of source lines SL, a plurality of magnetic tunnel junctions 106, and a plurality of bit lines BL.

[0030] The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. Impurities may be implanted into the semiconductor substrate 100 to form an active region 101, and the impurities may include n-type impurities such as phosphorus and arsenic, or p-type impurities such as boron and gallium. The interval between adjacent active regions 101 is a field region (not shown), and the field region may be formed by a shallow trench isolation (STI) process or a local field oxidation isolation (LOCOS) process.

[0031] In this embodiment. A plurality of active areas 101 are formed in the semiconductor substrate 100, and all the active areas 101 are arranged into an array in rows and columns, and the active areas 101 in two adjacent rows are arranged alternately, and the active areas 101 in every other row are aligned in the column direction. Each active area 101 is rectangular (or a short strip structure), and its long side extends along the row direction. The spacing D between two adjacent active areas 101 in the same row (i.e., the column spacing of the array) is less than the extension length L of the active area 101 in the row direction. For example, when L=3D, and the width of the active area 101 is also D, and the row spacing of the array is also D, the size of each storage unit cell in the storage array defined by the active area array is 4F in the row direction, and the size in the column direction is 2F, and the area of ​​each storage unit cell is 4F*2F=8F 2 , where F is the minimum size corresponding to the process manufacturing of this magnetic random access memory array as a part or a large part of a semiconductor integrated circuit chip, and is often referred to as the feature size.

[0032] A plurality of word lines WL are formed on the semiconductor substrate 100, and each word line WL extends along the column direction and is arranged across the plurality of active regions 101 in the same column and the corresponding intervals between the active regions 101 in the column. Each word line WL divides the corresponding active region 101 into a source region 101a and a drain region 101b. Each active region 101 and the word line WL arranged above the active region 101 form a corresponding MOS transistor, that is, the word line WL serves as the gate of the MOS transistor, the active regions 101 on both sides of the word line WL are the source region 101a and the drain region 101b of the MOS transistor respectively, and the active region 101 covered by the word line WL is the channel region of the MOS transistor. The material of the word line WL can be polysilicon or metal gate material, and there is a gate dielectric layer (not shown) between the word line WL and the semiconductor substrate 100, and a sidewall (SideWall or Spacer, not shown) may also be formed on the sidewall of the word line WL. The line width of the word line WL may be equal to or smaller than the column spacing D of the array formed by the active regions 101 to avoid the word line WL overlapping with unnecessary active regions 101 to cause interference between memory cells and affect device performance.

[0033] A plurality of source lines SL are formed through the first metal layer 103 and connected to corresponding source regions 101 a through corresponding source contact plugs 102 .

[0034] The bottom of each magnetic tunnel junction (MTJ) 106 is connected to the corresponding drain region 101b through the corresponding second metal layer 105 and the drain contact plug 104 under the second metal layer 105, and the top of each magnetic tunnel junction 106 is connected to the third metal layer 107, and the third metal layer 107 is used to form the corresponding bit line BL. Among them, the MTJ 106 is only made on the drain region of the MOS transistor connected to the bit line BL, and the corresponding MOS transistor formed at each active area 101 and the magnetic tunnel junction 106 above the drain region 101b of the MOS transistor constitute a storage unit. The source contact plug 102, the drain contact plug 104, the first metal layer 103, the second metal layer 105, and the third metal layer 107 can all include metal and / or metal nitride. The magnetic tunnel junction 106 may include a barrier layer (not shown), a pinning layer, a lower ferromagnetic layer, an antiferromagnetic coupling spacer layer, and an upper ferromagnetic layer, etc., which are sequentially formed on the second metal layer 105. The barrier layer can reduce or avoid abnormal growth of metals in the pinning layer, the lower ferromagnetic layer, the ferromagnetic coupling spacer layer, and the upper ferromagnetic layer. The barrier layer may include an amorphous metal or metal nitride, such as tantalum, tantalum nitride, titanium, titanium nitride, etc. The pinning layer may include, but is not limited to, materials such as FeMn, IrMn, PtMn, MnO, MnS, MnTe, MnF2, FeF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, and Cr. The lower ferromagnetic layer and the upper ferromagnetic layer may include, but are not limited to, metals such as Fe, Ni, and Co. The antiferromagnetic coupling spacer layer may include, but is not limited to, materials such as Ru, Ir, and Rh. The lower ferromagnetic layer may have a fixed or "pinned" magnetic orientation, while the upper ferromagnetic layer has a variable or "free" magnetic orientation and may be switched between two or more different magnetic polarities, each representing a different data state, such as a different binary state. However, in other embodiments, the MTJ 106 may be "flipped" vertically so that the lower ferromagnetic layer has a "free" magnetic orientation and the upper ferromagnetic layer has a "fixed" magnetic orientation.

[0035] Please refer to Figure 2 and Figure 3 In this embodiment, the bit line BL and the source line SL are arranged in parallel, and the metal layers where the bit line BL and the source line SL are located do not overlap at all. The bit line BL contacts the drain region through the magnetic tunnel junction 106, the second metal layer 105 and the drain contact plug 104 in sequence, and the source line SL contacts the source region through the source contact plug 102. All the drain contact plugs 104 and the source contact plugs 102 are arranged in rows and columns to form a plug array. Please refer to Figure 1 and Figure 3 In a top view, in each row of plugs, the drain contact plugs 104 and the source contact plugs 102 are arranged alternately, and in each column of plugs, the drain contact plugs 104 and the source contact plugs 102 are also arranged alternately, and the drain contact plugs 104 in two adjacent rows are staggered and misaligned, the source contact plugs 102 in two adjacent rows are staggered and misaligned, the drain contact plugs 104 in two adjacent columns are staggered and misaligned, and the source contact plugs 102 in two adjacent columns are staggered and misaligned. Moreover, the bit line BL intersects with the word line WL in different planes and is not perpendicular (that is, the projection of the bit line BL and the word line WL on the surface of the semiconductor substrate 100 intersects and is not perpendicular), for example, the angle between the bit line BL and the word line WL can be 45 degrees, but is not limited to 45 degrees.

[0036] In addition, adjacent word lines WL, adjacent bit lines BL, adjacent source lines SL, adjacent magnetic tunnel junctions 106, adjacent contact plugs, word line WL and bit line BL, word line WL and source line SL, word line WL and magnetic tunnel junction 106, source line SL and magnetic tunnel junction 106, source line SL and bit line, and second metal layers 105 of adjacent memory cell cells are all insulated and isolated by corresponding insulating dielectric layers (not shown).

[0037] Figure 3 The structure of the source line SL and the bit line BL shown in the figure can reduce the interference between adjacent memory cells and improve the device performance on the one hand; on the other hand, it can relatively increase the distance between two adjacent contact plugs on the same source line SL or bit line BL, reduce the difficulty of making the source line, the bit line and the contact plug, avoid the problem of bridging, and then reduce the interference between adjacent memory cells and improve the device performance. At this time, the intersection connection part of each word line WL and each bit line BL corresponds to a memory cell, and each memory cell is a 1 transistor (T) 1 magnetic tunnel junction (MTJ) structure.

[0038] It should be noted that the layout of the bit lines BL and the source lines SL is not limited to Figure 3 The layout structure shown in the figure is not limited to the cross-sectional view. Figure 2 The layout structure shown can be any other suitable layout. For example, please refer to Figure 4 In other embodiments of the present invention, the bit line BL and the source line SL are arranged in parallel, and the bit line BL intersects the word line WL perpendicularly and diametrically (that is, the projection of the bit line BL and the word line WL on the surface of the semiconductor substrate 100 intersects and is perpendicular). In this case, the memory cell cells in two adjacent rows share the same bit line BL and / or the same source line SL. For another example, please refer to Figure 5In other embodiments of the present invention, the bit line BL and the source line SL may also be arranged to intersect with each other in different planes, the metal layers where the bit line BL and the source line SL are located partially overlap, the bit line BL sequentially contacts the metal layer 103' of the metal layer 103 where the source line SL is located through the magnetic tunnel junction 106, the second metal layer 105 and the drain contact plug 104', the metal layer 103' contacts the drain region 101b through the drain contact plug 104, and the source line SL contacts the source region 101a through the source contact plug 102. The bit line BL is also perpendicular to the word line WL.

[0039] Please refer to Figures 1 to 5 Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device, including the above-mentioned magnetic random access memory array, the structure of the bit line BL and the source line SL of the magnetic random access memory array can be as follows Figure 3 As shown or Figure 4 The semiconductor device may be a memory, a sensitive amplifier, a magnetic sensor, a storage-computing integrated chip, etc.

[0040] In summary, the magnetic random access memory array and the semiconductor device having the magnetic random access memory array of the present invention effectively utilize the space by staggered arrangement between two adjacent rows of active regions under the premise of occupying the same substrate area, realize a smaller characteristic size of the memory unit, a higher overall density, and a lower chip cost. Furthermore, a unit area of ​​8F can be realized. 2 (F is the characteristic size) of the densely packed memory array, improving the storage density and device integration. In addition, the source line and the bit line can be made to intersect with the word line in different planes and not perpendicular, so that the memory cells corresponding to the adjacent active areas on the same row and column do not share the same source line and bit line, thereby reducing the interference between adjacent memory cells and improving device performance.

[0041] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A magnetic random access memory array, characterized in that: include: A semiconductor substrate, wherein a plurality of active regions arranged in an array in rows and columns are provided in the semiconductor substrate, and the active regions in two adjacent rows are arranged in a staggered manner; A plurality of word lines are formed on the semiconductor substrate, and each of the word lines extends along a column direction and straddles a plurality of active regions in the same column, and each of the word lines divides a corresponding active region into a source region and a drain region; A plurality of source lines, each of the source lines is formed through the first metal layer and connected to a corresponding source region; A plurality of magnetic tunnel junctions, each of which is connected to the corresponding drain region at the bottom through the corresponding second metal layer and connected to the third metal layer at the top, and the third metal layer is used to form a corresponding bit line; The source line and the bit line intersect the word line in different planes and are not perpendicular to each other, and two adjacent storage units in the same row and the same column do not share the bit line and the source line.

2. The magnetic random access memory array according to claim 1, characterized in that: Each of the active regions and the word line disposed above the active region form a corresponding MOS tube, and the MOS tube and the magnetic tunnel junction above the drain region form a storage unit, and the area of ​​the storage unit is 8F. 2 , where F is the characteristic size of the magnetic random access memory array, and the length of the memory cell in the row direction is twice the length in the column direction.

3. The magnetic random access memory array according to claim 1, characterized in that: The distance between two adjacent active regions in the same row is smaller than the length of the active region in the row direction.

4. The magnetic random access memory array according to claim 1, characterized in that: The bit line and the source line are arranged in parallel.

5. The magnetic random access memory array according to claim 4, characterized in that: When the bit line intersects the word line in different planes and is not perpendicular, the angle between the bit line and the word line includes but is not limited to 45 degrees.

6. The magnetic random access memory array according to claim 1, characterized in that: Each of the drain regions is connected to the second metal layer at the bottom of the magnetic tunnel junction through a drain contact plug located above the drain region, and each of the source regions is connected to the source line through a source contact plug located above the source region; the drain contact plugs and the source contact plugs are arranged into a plug array in the rows and columns.

7. The magnetic random access memory array according to claim 6, characterized in that: The drain contact plugs and the source contact plugs in each column of the plug array are arranged alternately, and the drain contact plugs and the source contact plugs in each row of the plug array are arranged alternately.

8. A semiconductor device, characterized in that: The invention comprises the magnetic random access memory array as claimed in any one of claims 1 to 7.

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