Time Coded Modulator Circuit

Abstract

The present application describes a time coded modulator circuit (200), and in particular, describes a PWM modulator suitable for use in a class D amplifier. A forward signal path receives a digital input signal (Din) and outputs an output PWM signal (Sout) and includes a first PWM modulator (101). A feedback path provides feedback to an input of the first PWM modulator (101). The feedback path includes an ADC (203) that receives a first PWM signal (Sa) derived from the output PWM signal. The ADC (203) includes a second PWM modulator (401) that generates a second PWM signal (Sb) based on the first PWM signal. A controller (201) controls the second PWM modulator so that a PWM carrier of the second PWM signal matches a PWM carrier phase and frequency of the output PWM signal.

Description

Technical Field

[0001] The field of representative embodiments of the present disclosure relates to methods, apparatus and / or implementations related to or associated with time-encoded modulator (TEM) circuits, and in particular, to PWM (pulse width modulation) modulators. Background Art

[0002] Time coded modulators (TEMs) for encoding an input signal into a time coded signal such as a PWM (pulse width modulation) signal are known and have been proposed for use in a variety of applications. For example, digital PWM modulators have been proposed for use in class D amplifiers or drivers. Summary of the invention

[0003] Figure 1 An example of a circuit 100 having a PWM modulator 101, in this example a class D amplifier circuit, is depicted. The PWM modulator 101 is configured to generate a PWM signal based on a digital input signal Din, and to drive an output stage 102 using the PWM signal output from the PWM modulator 101. The output stage includes a plurality of switches for selectively connecting an output node of the output stage 102 to one of a plurality of defined voltages, such as a positive supply voltage and ground, or a positive supply voltage and a negative supply voltage. The output node thus varies between these voltage levels, with the duty cycle being controlled by the PWM signal output so that the average voltage of the output signal Sout depends on the value of the digital input signal Sin. The output signal Sout may be supplied to a load (not shown), for example, to drive an output transducer such as a loudspeaker. The output signal Sout may be at least partially filtered by the load and / or by an output filter (not shown) so that the load experiences an analog drive signal. In this example, Figure 1 A half-bridge output stage 102 is depicted for outputting the output signal Sout to a load, but it will be appreciated that a class D amplifier may be implemented using a full-bridge output stage.

[0004] Although this class D circuit can be operated in open-loop mode, analog effects within the amplifier circuit can cause distortion. For example, output stage transistor on-resistance, limited rise and fall times, propagation delays, and power supply fluctuations can cause distortion in the output signal Sout. Therefore, the class D circuit can usually be operated in a closed-loop operation mode that uses negative feedback to suppress such distortion. The class D amplifier circuit 100 therefore also includes a feedback path having an analog-to-digital converter (ADC) 103, which is used to receive a feedback signal from the output tap via an anti-aliasing filter 104 and convert the feedback signal to digital. The digital feedback signal is subtracted from the input signal to generate an error signal, which is input to a loop filter 105, such as an integrator. The output of the loop filter 105 is combined with the digital input signal in the forward signal path in this example.

[0005] Can be advantageously implemented for many applications such as Figure 1 The class-D amplifier circuit 100 is shown in FIG.

[0006] Embodiments of the present disclosure are directed to improvements in time coded modulator circuits, such as time coded modulator circuits suitable for use with class D amplifiers, which may have advantages in size and / or gain.

[0007] According to one aspect of the present disclosure, there is provided a modulator circuit, the modulator circuit comprising:

[0008] a forward signal path for receiving a digital input signal and outputting an output PWM signal, the forward signal path comprising a first PWM modulator;

[0009] a feedback path for providing feedback to an input terminal of the first PWM modulator, the feedback path comprising an ADC configured to receive a first PWM signal derived from the output PWM signal;

[0010] wherein the ADC comprises a second PWM modulator configured to generate a second PWM signal based on the first PWM signal; and

[0011] A controller is used to control the second PWM modulator so that the PWM carrier of the second PWM signal matches the PWM carrier of the output PWM signal in phase and frequency.

[0012] The ADC may be configured to combine the first PWM signal with the second PWM signal generated by the second PWM modulator at an input of the ADC.

[0013] In some examples, the controller may be configured to monitor the first PWM signal and adaptively control the ADC based on the monitored first PWM signal to match a PWM carrier of the second PWM signal with a PWM carrier of the first PWM signal.

[0014] In some examples, the controller may be configured to monitor the first PWM signal and the second PWM signal to determine any phase difference between defined signal transitions in the first PWM signal and the second PWM signal, and control the ADC to reduce the phase difference. The controller may form a phase-locked loop with at least a portion of the second PWM modulator. The controller may include a phase and frequency detector for determining the phase difference. In some examples, the controller may be configured to adaptively control the frequency of a reference waveform, wherein the reference waveform defines a PWM cycle period of the second PWM modulator. The reference waveform may be a triangular waveform.

[0015] In some examples, the controller may include a control oscillator for generating an oscillating signal at a controlled frequency, wherein the second PWM modulator includes a triangular waveform generator configured to generate a ramp-up and ramp-down triangular waveform based on the oscillating signal. In some examples, the controller may include a square wave generator for generating a square wave, which is supplied to an integrator to generate a triangular waveform. The square wave generator may be configured so that the square wave has a controllably variable cycle period and has an amplitude that varies with any change in the cycle period, so that the product of the amplitude and the period is substantially constant. The square wave generator may include: a control oscillator for generating an oscillating signal having a frequency controlled by a first control current; and a digital-to-analog converter for generating a square wave based on the oscillating signal. The digital-to-analog converter may be biased by a second control current that varies with the first control current.

[0016] In some examples, a first reference waveform may define a PWM cycle period of a first PWM modulator, and the controller may be configured to define a PWM cycle period of a second PWM modulator using the first reference waveform.

[0017] In some examples, the ADC may further include a time-decoding converter configured to convert the second PWM signal into a digital feedback signal.

[0018] The modulator circuit may further include a class D output stage controlled by the first PWM modulator. The class D output stage may be located in the forward signal path. The first PWM signal received by the ADC may be derived from the PWM output signal output from the class D output stage.

[0019] In some examples, the amplitude controller may control the amplitude of at least one of the first PWM signal and the second PWM signal combined at the input of the ADC.

[0020] The modulator circuit may be implemented as an integrated circuit.In some implementations, the modulator circuit may also include an audio output transducer configured to be driven by the output PWM signal.

[0021] An aspect also relates to an electronic device comprising a modulator circuit of any of the implementations discussed herein.

[0022] On the other hand, a modulator circuit is provided, which includes: a first PWM modulator in a forward signal path, the first PWM modulator being used to output a PWM output signal; a second PWM modulator in a feedback path, the second PWM modulator being configured to receive a first PWM signal obtained from the PWM output signal and generate a second PWM signal; and a controller, the controller being used to control the second PWM modulator so that a PWM carrier of the second PWM signal matches a PWM carrier of the first PWM signal in phase and frequency.

[0023] On the other hand, a modulator circuit is provided, comprising: a first PWM modulator in a forward signal path; and a second PWM modulator in a feedback path; and a controller for controlling the second PWM modulator so that a PWM carrier of the second PWM modulator matches a PWM carrier of the first PWM modulator in phase and frequency.

[0024] Any of the various features of the various implementations discussed herein may be implemented with any one or more of the other described features in any and all suitable combinations, unless explicitly indicated to the contrary. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to better understand the examples of the present disclosure, and to more clearly show how the examples may be implemented, reference will now be made, by way of example only, to the following drawings, in which:

[0026] Figure 1 A class D amplifier circuit with a digital PWM modulator is depicted;

[0027] Figure 2 depicts a class D amplifier circuit according to one embodiment;

[0028] Figure 3a and Figure 3b An example of generating a PWM signal is shown;

[0029] Figure 4An example of a PWM ADC and a controller for controlling the timing of a PWM carrier is depicted; and

[0030] Figure 5 Another example of a controller for controlling the timing of a PWM carrier is depicted. DETAILED DESCRIPTION

[0031] The following description sets forth exemplary embodiments according to the present disclosure. Other exemplary embodiments and implementations will be apparent to those of ordinary skill in the art. In addition, those of ordinary skill in the art will recognize that various equivalent technologies may be applied as substitutes or combinations of the embodiments discussed below, and all such equivalents will be deemed to be covered by the present disclosure.

[0032] As discussed above, Figure 1 A class D amplifier circuit with a digital PWM modulator 101 capable of operating in a closed-loop mode of operation is depicted. Using a digital PWM modulator 101 is advantageous because it can be easily implemented using smaller semiconductor process node geometries. For at least some applications, a smaller circuit area is generally desired for cost and / or space reasons.

[0033] As also described above, to reduce distortion, the digital PWM modulator 101 may be capable of operating as part of a feedback loop, with the ADC 103 located in the feedback path. The input to the feedback ADC is filtered using an anti-aliasing filter 104 to remove tones in the feedback signal.

[0034] Typically, filter 104 may be implemented as an RC filter with a cutoff only outside the signal band of interest (eg, the audio band for audio applications.) This generally requires a relatively large capacitance, with attendant impact on circuit area.

[0035] Embodiments of the present disclosure implement the feedback ADC as a PWM-based ADC that operates such that a PWM carrier component of the PWM-based ADC matches a PWM carrier component of a PWM signal generated by a PWM modulator in a forward signal path.

[0036] Figure 2 An example of a circuit 200 including a time coded modulator, in this case a class D amplifier circuit, is depicted, wherein the same reference numerals are used to identify the circuit as in Figure 1 Components similar to those shown in FIG.

[0037] Figure 2 The PWM modulator 101 is shown arranged in the forward signal path to Figure 1In the same manner as discussed above, a PWM signal is generated based on the digital input signal Din to drive the output stage 102 to provide a PWM output signal Sout. The class D circuit is capable of operating in a closed-loop operation mode with feedback and therefore has a feedback path with the ADC 203 to provide a feedback signal. Figure 2 In the example of , the feedback signal is combined with the input signal to provide an error signal, which is filtered by a loop filter 105, which may be, for example, a first order integrator, but it will be appreciated that other arrangements may be implemented.

[0038] exist Figure 2 In an embodiment of the present invention, the ADC 203 in the feedback path is a PWM ADC 203. Those skilled in the art will appreciate that a PWM ADC is an ADC that operates to generate a PWM signal based on its input signal, and therefore includes a PWM modulator. Various types of PWM ADCs are known and may be used for the PWM ADC 203, as will be discussed in more detail below. The PWM modulator 101 in the forward signal path is therefore a first PWM modulator, and the PWM ADC 203 includes a second PWM modulator. The circuit 200 also includes a controller configured to control the PWM ADC 203 so that the PWM carrier of the ADC 203 matches the PWM carrier phase and frequency of the PWM signal generated by the PWM modulator 101 in the forward signal path.

[0039] Those skilled in the art will appreciate that a PWM modulator, such as PWM modulator 101, operates to generate a PWM signal in which the duty cycle of the PWM signal encodes the value of the input to the PWM modulator. That is, the PWM signal transitions between a first signal level and a second signal level and the ratio of time spent at the first signal level (i.e., pulse width) in each PWM cycle compared to the time spent at the second signal level are controlled based on the input to the PWM modulator. The PWM cycle period and the corresponding cycle frequency are referred to as the PWM carrier period (or just the carrier period) and the PWM carrier frequency (or just the carrier frequency), respectively, because the carrier signal, which is actually at the PWM carrier frequency, is modulated to encode the input data by varying the pulse width. The term PWM carrier or just carrier therefore refers to this underlying signal structure of the PWM signal, and in some aspects, the PWM carrier may be considered to be a PWM signal generated for a stationary input signal.

[0040] For some PWM modulators, the PWM carrier frequency may be defined by or relative to a reference waveform received or generated by the PWM modulator. For example, some PWM modulators compare the modulator input signal to a time-varying reference waveform (such as a triangular waveform or a sawtooth waveform) to generate a PWM signal. In that case, the frequency of the reference waveform defines the PWM carrier.

[0041] Figure 3a A PWM modulator such as may be implemented by the PWM modulator 101 is generally depicted according to one example, wherein an input Din1 is compared to a reference waveform REF by a comparator 301 to generate a PWM signal Spwm output from the modulator 101. In the example of FIG. 3 , the reference waveform REF is a triangular waveform that steadily ramps from a first value defined relative to an input range of the input signal to a second value and then ramps back to the first value at a ramp rate of the same magnitude. In the example of FIG. 3 , the reference waveform REF is initially low, and the signal level of the PWM signal Spwm is low, until the value of the reference waveform REF increases above the value of the input signal, at which point the PWM signal Spwm goes high and remains low until the reference waveform drops back below the value of the input signal. For this example, the period P during which the reference waveform REF ramps up and then ramps down defines the PWM carrier period and therefore the carrier frequency. It will be appreciated that there is one PWM pulse per cycle period, and that the PWM signal includes a signal component generated by the PWM carrier frequency. Of course, it will be appreciated that other arrangements for generating a PWM signal may be used, but generally speaking the PWM signal will contain some components due to the PWM carrier.

[0042] See also Figure 2 , because the PWM modulator 101 drives the output stage 102, the output signal Sout will also include a signal component at the PWM carrier frequency of the PWM modulator 101. This PWM carrier frequency component is one of the main sources of tone in the feedback signal. Figure 1 In the conventional circuit 100 shown in FIG. 1 , the tone may cause undesirable problems at the input of the ADC 103 and therefore needs to be filtered by the AAF 104 .

[0043] However, in Figure 2In the circuit of FIG. 201 , the ADC in the feedback path is a PWM ADC 203, and the circuit is controlled by the controller 201 such that the PWM carrier component of the PWM ADC 203 matches the PWM carrier phase and frequency of the signal generated by the PWM modulator 101. If the carrier of the PWM-based ADC 203 matches the carrier phase and frequency of the PWM signal generated by the PWM modulator 101, the PWM tones at the input of the ADC 203 can be at least partially canceled or suppressed by the operation of the ADC 203. Specifically, the PWM tones generated by the operation of the PWM ADC 203 are phase-matched with the PWM tones generated by the PWM modulator 101, which means that these tones can be at least partially canceled at the input of the ADC 203.

[0044] Suppressing the PWM tones in this way means that the requirements for filtering the signal supplied as input signal Sa to the ADC in the feedback path are significantly reduced. In some implementations, the anti-aliasing filter may be omitted, i.e., there may be no filter in the feedback path upstream of the ADC 203. In some implementations, while it may still be beneficial to apply some filtering to the feedback signal upstream of the ADC 203, the requirements for such filtering may be more relaxed than conventional approaches in cases where the PWM tones in the feedback signal are not a big problem. Therefore, in some implementations, there may be a filter 204 in the feedback path upstream of the ADC 203, but the filter 204 may be implemented as a filter that is significantly smaller in circuit area, e.g., with a smaller capacitor area, compared to conventional filters 104.

[0045] In closed loop operation, the use of a PWM ADC 203 having a PWM carrier phase-matched to the PWM carrier of the PWM signal generated by the PWM modulator 101 in the forward signal path thus significantly reduces the need for filtering of the feedback signal. This means that the filter upstream of the ADC in the feedback path can be significantly smaller than would otherwise be the case, or even omitted entirely, thus saving circuit area, and therefore saving circuit size and cost.

[0046] In addition, applying less filtering to the feedback signal can reduce the delay of the feedback path, and therefore reduce the overall delay of the feedback loop, which can be beneficial to allow a greater gain within the feedback loop. Those skilled in the art will understand that the responsiveness of the feedback loop to any change depends on the loop delay, and the gain within the feedback loop is usually set relative to the loop delay. If the loop delay is relatively long, the gain can be limited to avoid overshoot. That is, if there is a certain error between the input and the output, the operation of the loop will apply a certain error correction until the correct value is reached, at which time error correction is no longer required, but the loop delay will limit the response speed, which can result in a certain overshoot, and the overshoot depends on the gain. The reduced delay can allow the use of a larger gain, which can be beneficial to the performance of the Class D amplifier in at least some applications.

[0047] Using the PWM ADC 203 in the feedback path for closed loop operation of the digital PWM modulator in the forward signal path and matching the PWM carrier of the PWM ADC to the PWM carrier of the PWM signal in the forward signal path may therefore provide advantages in size, cost, and / or performance.

[0048] The PWM carrier of the PWM ADC 203 may be controlled to match the PWM carrier of the PWM signal generated in the forward signal path in various ways.

[0049] In one implementation, the PWM modulator 101 may generate its PWM output signal using a time-varying reference waveform REF, such as a waveform related to Figure 3b The triangular waveform or sawtooth waveform discussed, and the same reference waveform may also be used for the PWM ADC 203 .

[0050] Figure 2 It is thus illustrated that the controller 201 may control the PWM ADC 203 using the same reference waveform REF as used by the PWM modulator 101 in the forward signal path. In some implementations, the controller 201 may generate the reference waveform REF and provide a version thereof to the PWM modulator 101. Alternatively, the controller 201 may receive a version of the reference waveform REF generated by the PWM modulator 101 or from some other source and use the version to control the PWM ADC 203. In such implementations, the controller 201 may include components of the PWM ADC 203 for generating the PWM signal, such as a comparator for comparing the reference waveform REF with a signal derived from the input of the ADC 203.

[0051] Using the same reference waveform for the PWM modulator 101 and the PWM ADC 203 in the forward signal path will ideally provide a degree of synchronization of the PWM carrier. Ideally, the carriers will be exactly matched, however, in practice, the analog effects and influences of the load may result in some timing differences in the PWM signal Sout supplied to the output of the ADC 203 as the ADC input Sa and the PWM signal generated within the PWM ADC 203. If the load driven by the output signal has a relatively strong reactive property, there will be phase variations due to the load.

[0052] To provide maximum suppression of the PWM tones, the PWM tones generated by the operation of the PWM ADC 203 should match in phase and amplitude the PWM tones in the input of the PWM ADC 203. However, effective suppression is more sensitive to phase errors, and thus phase variations in the PWM output signal Sout, and thus the ADC input Sa, compared to the operation of the PWM ADC 203 may adversely affect the effective suppression of the tones.

[0053] In some applications, using the same reference waveform for the PWM modulator 101 and the PWM ADC 203 in the forward signal path may provide a sufficient degree of phase matching of the PWM carrier so that the PWM tones at the input of the ADC 203 are suppressed to a sufficient degree for that application. However, in some applications it may be desirable to ensure a greater degree of phase matching of the carrier than would be expected simply by using the same reference waveform.

[0054] Therefore, in some implementations, such as Figure 2 As shown in FIG. 2 , the controller 201 may be configured to monitor the signal Sa input to the PWM ADC 203 and control the carrier of the PWM ADC 203 based on the monitoring. The controller 201 may thus selectively change the timing of the carrier of the PWM ADC 203 based on the monitored signal Sa so as to match the phase and frequency of the carrier of the PWM ADC 203 with the ADC input signal Sa.

[0055] Specifically, in some implementations, the controller 201 may include a phase detector for detecting the extent of any phase difference between the PWM carrier of the signal Sa input to the PWM ADC 203 and the PWM carrier of the PWM ADC 203. The controller may be configured to control one or more timing parameters of the PWM ADC 203 so as to minimize the total phase difference and thus provide frequency and phase matching of the PWM carrier. The controller 201 may essentially be implemented as part of a phase-locked loop device for locking the PWM carrier of the PWM ADC 203 to the PWM carrier of the ADC input signal Sa.

[0056] Figure 4 One example of a controller 201 for controlling the generation of a PWM signal within a PWM ADC 203 is depicted. The PWM ADC 203 includes a PWM modulator 401 that receives an ADC input signal Sa (a first PWM signal) and generates a PWM signal Sb (a second PWM signal). The ADC input signal Sa, i.e., the first PWM signal, is combined with feedback from the output of the PWM modulator 401 (i.e., with a version of the second PWM signal Sb) and applied to the input of an integrator formed by an operational amplifier 402 and a capacitor 403. The output of the integrator is supplied to a comparator 404, which compares the integrator output with a triangular waveform provided by a triangular waveform generator 405 in this example to generate the ADC PWM signal Sb. However, equally, the output of the integrator may be combined with a triangular waveform and compared with a defined threshold. Those skilled in the art will appreciate that the PWM carrier of the PWM signal Sb is defined by the triangular waveform generated by the triangular waveform generator 405.

[0057] exist Figure 4 In the example of , the controller 201 controls the triangular waveform generator 405 so as to control the timing parameters of the triangular waveform, and thus controls the PWM carrier of the signal Sb to match the PWM carrier of the input Sa. Those skilled in the art will appreciate that the controller 201 actually operates as a phase locked loop (PLL), wherein the input Sa is the reference signal of the PLL. The signal Sa input to the ADC is supplied to a phase and frequency detector (PFD) 406, which also receives the signal Sb generated by the ADC PWM modulator 401. The PFD 406 determines the amount of any phase lag or lead between defined signal transitions, for example, high to low and / or low to high in the signal Sb and the corresponding signal transitions in the signal Sa. The measured time difference (i.e., phase lag or phase lead) in the signal transitions is filtered by a low pass filter (LPF) 407 to provide an indication of any phase difference (i.e., phase error). For PWM signals such as those discussed with respect to FIG. 3 , where each PWM pulse is symmetrical in time about the midpoint of the associated cycle period, the phase difference of the two signal transitions (i.e., high to low and low to high) is determined, so LPF 407 indicates the average phase difference over each cycle, and therefore represents the extent of any phase mismatch between the PWM carriers of signals Sa and Sb. The output of filter 407 is used to adjust the operation of digitally controlled oscillator (NCO) 408, which generates the oscillating signal used by triangle waveform generator 405.

[0058] If the output of LPF 407 indicates a phase error in the PWM carrier of signal Sb and ADC input Sa, the frequency of NCO 408 is adjusted, for example, increasing the frequency in case the PWM carrier of signal Sb has a phase lag compared to the PWM carrier of signal Sa so as to advance the start of the PWM cycle, and alternatively decreasing the frequency in case the signal Sb has a phase lead so as to postpone the PWM cycle. The controller 201 thus locks the PWM carrier of signal Sb generated by ADC PWM modulator 401 to match the PWM carrier of input Sa of ADC 203.

[0059] The triangular waveform generator 405 operates to generate a triangular waveform whose period is defined by the oscillating signal generated by the NCO 408. For example, if the NCO 408 generates a signal with high and low pulses of equal duration at a controlled frequency, the state of the NCO output may control the ramp generator to ramp up or down, respectively.

[0060] It will be appreciated that changing the period of the triangular wave should ideally not result in any significant change in the offset of the triangular waveform. Figure 3b As discussed in the example of , a triangular wave may ramp from a first value to a second value during a PWM cycle, and then ramp back to the first value, and the first and second values ​​may be set relative to an expected range of an input signal. Ideally, the first and second values ​​should not change significantly with any change in the cycle period, because any change in the first and second values ​​(i.e., the offset of the triangular wave) will result in a change in the conversion gain of the PWM modulator 401 of the ADC 203. The triangular waveform generator 405 may therefore be configured so that there is no significant change in the offset of the triangular waveform when the cycle changes, and may be particularly configured to change the ramp rate of the triangular waveform according to any change in the cycle period. Those skilled in the art will appreciate that there are various ways in which such a triangular waveform generator may be implemented. For example, the triangular waveform generator 405 may include more than one current source to drive a defined charging current and a discharging current into an integrator within a period defined by an oscillating signal from the NCO 408. The current source may be controlled based on an indication of the cycle period / frequency to change the intensity of the charging current and the discharging current.

[0061] The controller 201 thus controls the operation of the PWM ADC 203 such that the PWM carrier of the PWM signal Sb generated by the PWM ADC 203 matches the PWM carrier phase and frequency of the signal Sa input to the ADC 203. This means that at the input of the PWM ADC 203, the signal Sa input to the ADC 203 is combined with the ADC feedback from the ADC output signal Sb having a phase and frequency matched carrier, and the PWM tones in the input are at least partially suppressed as discussed above.

[0062] In some examples, the PWM signal Sb generated by the PWM ADC 203 may be converted into a suitable digital number by a time decoding converter (TDC) 409. For example, the TDC may include: a voltage controlled oscillator for generating an oscillator signal that varies between two frequencies Fhi and Flo based on the signal level of the PWM signal Sb; and a counter for counting the number of oscillations in a counting cycle, the number indicating the duty cycle of the PWM signal Sb and thus the value of the signal Sa input to the ADC 203.

[0063] Any mismatch in amplitude between the signal Sa input to the ADC 203 and the feedback from the PWM signal Sb generated by the ADC 203 may adversely affect the amount of rejection, but mismatches in phase have a greater impact. The amplitude of the signal Sa input to the ADC depends on any level shift applied to the signal tapped from the forward signal path and the value of the input resistance of the ADC. The amplitude of the feedback from the ADC PWM signal Sb depends on the amplitude of the PWM signal generated by the PWM modulator 401 and the value of the feedback resistance. In some examples, the PWM modulator 401 may be designed together with any level shift or scaling applied to the feedback signal tapped from the forward signal path so that the relevant amplitudes are sufficiently matched. However, in some examples, there may be an amplitude controller 410 configured to control the amplitude of at least one of the signals. Figure 4 It is shown that the amplitude controller may control the value R1 of the feedback resistor of the PWM modulator 401 to control the amplitude of the feedback from the signal Sb. The amplitude controller 410 may monitor the digital signal generated by the ADC 203 to monitor any amplitude error, for example by bandpass filtering at an appropriate frequency range.

[0064] Figure 5 Another example of a suitable controller 201 for controlling the timing of a PWM carrier of a PWM ADC 203 is shown, wherein components similar to those described above are identified by the same reference numerals. Figure 4 For clarity, Figure 5 Some details of ADC 203 are omitted, and can be understood by referring to Figure 4The details are implemented in a manner similar to that shown in FIG.

[0065] Figure 5 The controller 201 of the example includes a square wave generator 501 operable to generate a square waveform having a controllably variable period. The square wave generator 501 is configured such that the amplitude of the square wave varies with the period such that the product of the amplitude and the period remains substantially constant. Integrating such a square wave will produce a triangular waveform whose period varies with the period of the square wave but has a substantially constant total offset. The controller 201 can thus control the period and therefore the frequency of the square waveform in a similar manner as discussed above to control the PWM carrier.

[0066] Figure 5 Thus, the controller 201 is shown to include a PFD 406 which receives an indication of the timing of the signal Sa input to the ADC 203 and the signal Sb generated by the PWM modulator 401 of the ADC. The PFD 406 is coupled to the reference Figure 4 The extent of any phase difference between these signals is determined in a manner similar to that discussed above. Figure 5 In the example of , the PFD controls a voltage source, in this example a charge pump 502, to generate a control voltage supplied to a square wave generator 501 via a passive filter 503. The control voltage is converted into a control current Ic by an amplifier 504 in this example, thereby adjusting the current through the resistor to generate a voltage equal to the control voltage. The control current Ic is also supplied to a current controlled oscillator (ICO) 505 to generate an oscillating signal having a frequency controlled by the control current and thus the control voltage. The output from the ICO 505 is optionally supplied to an IDAC 506 via a frequency divider (not shown) so that the IDAC 506 generates an output square wave. The IDAC is biased using the control current Ic so that the amplitude of the output of the IDAC 506 scales with the control current. Of course, it will be understood that the current used to control the ICO 505 and / or the current biasing the IDAC 506 can be a scaled version of the control current Ic.

[0067] As reference Figure 4As discussed, in the PWM ADC 203, a triangular waveform may be supplied to one input of the comparator 404 for comparison with the output of the integrator 402 / 403. In other implementations, the triangular waveform may be combined with the output of the integrator 402 / 403. In another implementation, the square wave generated by the square wave generator 501 may be supplied to the input of the integrator op amp 402 instead. In other words, the square wave may be combined with the ADC input Sa and the feedback from Sb. In this case, the integrator of the PWM modulator 401 (i.e., formed by the op amp 402 and the capacitor 403) also acts as the triangular waveform generator 405 and converts the square wave signal component into a triangular wave component in the signal provided to the comparator 404.

[0068] In any case, the controller 201 adjusts the timing of the square wave so as to minimize the overall phase difference between the PWM output Sb and the input Sa of the ADC 203 and thus locks the PWM carrier of the PWM ADC 203 to the PWM carrier of the input Sa.

[0069] Embodiments of the present disclosure therefore relate to a modulator circuit having: a forward signal path, the forward signal path including a PWM modulator for outputting an output PWM signal, wherein the modulator circuit is capable of operating in a closed-loop operating mode; an ADC, the ADC operating in a feedback path. In embodiments of the present disclosure, the ADC in the feedback path is a PWM ADC, and the PWM ADC is controlled to operate using a PWM carrier that matches the PWM carrier phase of the output PWM signal and therefore matches the PWM carrier phase in the signal input to the ADC. In at least some examples, the PWM ADC receives a first PWM signal tapped from the forward signal path and generates a second PWM signal, and monitors the first PWM signal to adaptively control the second PWM signal. The first PWM signal can be combined with the second PWM signal at the input of the ADC to suppress the PWM tone at the input of the ADC.

[0070] Examples have been discussed above with reference to a Class D amplifier or driver circuit, but the principles described are applicable to closed-loop PWM modulators that can be used in other applications. Figure 2 , the output stage 102 may not be present or may have a different form in some applications. It will also be understood that embodiments may be implemented in a differential arrangement and thus the signals discussed may be differential signals, for example the PWM modulator 101 may be a differential PWM modulator.

[0071] In some implementations, the modulator circuit may additionally be capable of operating in an open-loop operating mode, wherein the PWM modulator 101 in the forward signal path is capable of operating without any feedback. In the open-loop operating mode, components of the feedback path may be disabled, which may allow for power conservation. Thus, the open-loop operating mode may be enabled in some situations where reduced power consumption is desired and / or the performance benefits provided by the feedback path activity are not required. In some applications, the circuit may dynamically transition between an open-loop operating mode and a closed-loop operating mode, for example, based on an indication of a signal level or the required performance or power consumption. Additionally or alternatively, in some implementations, the circuit may be operated in the open-loop mode as part of a startup or reset process, wherein the circuit is subsequently transitioned to a closed-loop operating mode.

[0072] Embodiments may advantageously be implemented as part of an audio processing circuit, for example, an audio amplifier for providing an audio drive signal to an audio output transducer such as a loudspeaker, which may be a transducer of a host device and / or a transducer of an accessory device that may be removably connected to the host device in use.

[0073] Embodiments may be arranged as part of audio and / or signal processing circuitry, for example audio circuitry such as a codec that may be provided in a host device.Circuits according to embodiments of the invention may be implemented as integrated circuits.

[0074] Embodiments may be incorporated into a host electronic device, which may be, for example, a portable device and / or a device capable of operating using battery power. The host device may be a device having one or more loudspeakers and / or connectors provided as part of the host device for wired connection to a loudspeaker of a removable accessory device that may be removably connected to the host device during use. The host device may include a wireless communication module for receiving input data. The host device may be a communication device such as a mobile phone or smart phone or the like, a computing device such as a notebook, laptop computer or tablet computing device, a wearable device such as a smart watch. The host device may alternatively be an accessory device for use with any such communication device, computing device, or wearable device.

[0075] The skilled person will recognize that some aspects of the above-described apparatus and methods may be embodied as processor control code, for example, located on a non-volatile carrier medium such as a disk, CD- or DVD-ROM, a programmed memory such as a read-only memory (firmware), or a data carrier such as an optical signal or an electrical signal carrier. For many applications, the embodiments will be implemented on a DSP (digital signal processor), an ASIC (application specific integrated circuit), or an FPGA (field programmable gate array). Thus, the code may include conventional program code or microcode, or, for example, code for setting up or controlling an ASIC or FPGA. The code may also include code for dynamically configuring a reconfigurable device such as a reprogrammable logic gate array. Similarly, the code may include code for a hardware description language such as Verilog TM The code may be distributed among multiple coupled components that communicate with each other. Where appropriate, the embodiments may also be implemented using code that runs on a field (re)programmable analog array or similar device to configure analog hardware.

[0076] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude a plurality, and a single feature or other unit may fulfill the functions of several units recited in the claims. Any reference numbers or signs in the claims should not be construed as limiting their scope.

Claims

1. A modulator circuit, the modulator circuit comprising: a forward signal path for receiving a digital input signal and outputting an output PWM signal, the forward signal path comprising a first PWM modulator; a feedback path for providing feedback to an input terminal of the first PWM modulator, the feedback path comprising an ADC configured to receive a first PWM signal derived from the output PWM signal; wherein the ADC comprises a second PWM modulator configured to generate a second PWM signal based on the first PWM signal; and A controller is used to control the second PWM modulator so that the PWM carrier of the second PWM signal matches the PWM carrier of the output PWM signal in phase and frequency. 2 . The modulator circuit of claim 1 , wherein the ADC is configured to combine the first PWM signal with the second PWM signal generated by the second PWM modulator at an input of the ADC.

3. The modulator circuit of claim 1 or claim 2, wherein the controller is configured to monitor the first PWM signal and adaptively control the ADC based on the monitored first PWM signal to match the PWM carrier of the second PWM signal with the PWM carrier of the first PWM signal.

4. The modulator circuit of any one of claims 1 to 2, wherein the controller is configured to monitor the first PWM signal and the second PWM signal to determine any phase difference between defined signal transitions in the first PWM signal and the second PWM signal, and to control the ADC to reduce the phase difference.

5. The modulator circuit of claim 4, wherein the controller forms a phase locked loop with at least part of the second PWM modulator.

6. The modulator circuit of claim 4, wherein the controller comprises a phase and frequency detector for determining the phase difference.

7. The modulator circuit of any one of claims 1 to 2, wherein the controller is configured to adaptively control a frequency of a reference waveform, wherein the reference waveform defines a PWM cycle period of the second PWM modulator.

8. The modulator circuit of claim 7 , wherein the reference waveform is a triangular waveform, and the controller comprises a control oscillator for generating an oscillating signal at a controlled frequency, wherein the second PWM modulator comprises a triangular waveform generator configured to generate a ramp-up and ramp-down triangular waveform based on the oscillating signal.

9. The modulator circuit of claim 7 , wherein the reference waveform is a triangular waveform, and the controller comprises a square wave generator for generating a square wave, the square wave being supplied to an integrator to generate the triangular waveform, wherein the square wave generator is configured such that the square wave has a controllably variable cycle period and has an amplitude that varies with any change in the cycle period such that the product of the amplitude and the period is constant.

10. The modulator circuit of claim 9, wherein the square wave generator comprises: a control oscillator for generating an oscillation signal having a frequency controlled by a first control current; and a digital-to-analog converter for generating the square wave based on the oscillation signal, wherein the digital-to-analog converter is biased by a second control current that varies with the first control current.

11. A modulator circuit as claimed in claim 1 or claim 2, wherein a first reference waveform defines a PWM cycle period of the first PWM modulator, and the controller is configured to use the first reference waveform to define a PWM cycle period of the second PWM modulator.

12. The modulator circuit of any one of claims 1 to 2, wherein the ADC further comprises a time-decoding converter for converting the second PWM signal into a digital feedback signal.

13. The modulator circuit of any one of claims 1 to 2, further comprising a class-D output stage controlled by the first PWM modulator.

14. The modulator circuit of claim 13, wherein the class-D output stage is located within the forward signal path, and the first PWM signal received by the ADC is derived from a PWM output signal output from the class-D output stage.

15. The modulator circuit of claim 2, further comprising an amplitude controller for controlling an amplitude of at least one of the first PWM signal and the second PWM signal combined at the input of the ADC.

16. The modulator circuit of any one of claims 1 to 2 implemented as an integrated circuit.

17. The modulator circuit of any one of claims 1 to 2, further comprising an audio output transducer configured to be driven by the output PWM signal.

18. An electronic device comprising a modulator circuit as claimed in any preceding claim.

19. A modulator circuit, the modulator circuit comprising: A first PWM modulator, the first PWM modulator is located in a forward signal path, and the first PWM modulator is used to output a PWM output signal; a second PWM modulator, the second PWM modulator being located in a feedback path, the second PWM modulator being configured to receive the first PWM signal derived from the PWM output signal and generate a second PWM signal; A controller is used to control the second PWM modulator so that the PWM carrier of the second PWM signal matches the PWM carrier of the first PWM signal in phase and frequency.

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