A method, system, apparatus, and storage medium for chip development

Abstract

The application provides a chip research and development method, system, device and storage medium, the method comprises the following steps: generating a SPEC file according to a chip architecture, and generating a register conversion circuit code according to the SPEC file; the register conversion circuit code is put into a storage server, and a register conversion circuit index is written into a resource directory; the register conversion circuit code is read based on the register conversion circuit index, and syntax checking is performed on the register conversion circuit code; and it is judged whether there is a syntax error in the register conversion circuit code; in response to the fact that there is no syntax error in the register conversion circuit code, logic synthesis is performed according to the register conversion circuit code to generate a net list, the net list is put into the storage server, and a net list index is written into the resource directory; and the net list is read based on the net list index, and formal verification and timing analysis are performed on the net list. The application can maximize resource utilization and improve research and development efficiency.

Description

Technical Field

[0001] This field relates to chip development, and more specifically, to a method, system, apparatus, and storage medium for chip development. Background Technology

[0002] Chip development is a process of creating something from scratch, from market demand analysis to overall architecture design, from the generation of the first version of RTL (register-transfer level) to RTL spyglass syntax checking, RTL simulation, RTL DC (design compiler) synthesis to generate a netlist, netlist CDC checking, netlist-RTL formality comparison, netlist simulation, netlist DFT (drawing step-out) checking, and later static timing analysis, timing convergence, and finally tape-out. This cycle involves numerous EDA (Electronic Design Automation) tools, each with different server resource requirements, and these requirements also vary at different stages. Finding an intelligent and reasonable method to achieve the optimal solution is paramount in chip development. Existing technologies have the following shortcomings: 1. Disorganized allocation of server resources corresponding to EDA software resources; 2. Random storage of RTL, DOC (document), netlist, and other resources throughout the development cycle, resulting in redundant storage and wasted server resources. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a method, system, computer equipment, and computer-readable storage medium for chip development. This invention places DOC, RTL, and netlist in a storage server and stores different resources in different EDA tool servers, thereby achieving orderly storage and management of R&D products, reasonable scheduling of EDA resources, and reasonable allocation of R&D resources, thus maximizing resource utilization and improving R&D efficiency.

[0004] To achieve the above objectives, one aspect of this invention provides a method for chip development, comprising the following steps: generating a SPEC file based on the chip architecture, generating register translation circuit code based on the SPEC file, placing the register translation circuit code in a storage server and writing the register translation circuit index into a resource directory; reading the register translation circuit code based on the register translation circuit index and performing syntax checks on the register translation circuit code, and determining whether there are any syntax errors in the register translation circuit code; in response to the absence of syntax errors in the register translation circuit code, performing logic synthesis based on the register translation circuit code to generate a netlist, placing the netlist in a storage server and writing the netlist index into a resource directory; and reading the netlist based on the netlist index and performing formal verification and timing analysis on the netlist.

[0005] In some implementations, the method further includes: determining a register translation circuit index and a netlist index in the resource directory, scheduling a verification server in the cluster to perform pre-simulation verification of the register translation circuit code based on the register translation circuit index, and performing post-simulation verification of the netlist based on the netlist index.

[0006] In some implementations, the step of performing logic synthesis based on the register translation circuit code to generate a netlist includes: determining a register translation circuit index in the resource directory, and scheduling a logic synthesis server in the cluster based on the register translation circuit index to convert the register translation circuit code into a process-dependent gate-level netlist.

[0007] In some implementations, the step of reading the netlist based on the netlist index and performing formal verification and timing analysis on the netlist includes: determining the netlist index in the resource directory, opening the netlist in the storage server according to the netlist index, and scheduling the formal verification server and timing analysis server in the cluster to perform formal verification and timing analysis respectively.

[0008] In another aspect, this invention provides a chip development system, comprising: a creation module configured to generate a SPEC file based on a chip architecture, generate register translation circuit code based on the SPEC file, place the register translation circuit code in a storage server, and write a register translation circuit index into a resource directory; a checking module configured to read the register translation circuit code based on the register translation circuit index, perform syntax checking on the register translation circuit code, and determine whether there are syntax errors in the register translation circuit code; a netlist module configured to, in response to the absence of syntax errors in the register translation circuit code, perform logic synthesis based on the register translation circuit code to generate a netlist, place the netlist in a storage server, and write a netlist index into a resource directory; and an execution module configured to read the netlist based on the netlist index and perform formal verification and timing analysis on the netlist.

[0009] In some implementations, the system further includes a verification module configured to: determine a register translation circuit index and a netlist index in the resource directory, schedule a verification server in the cluster to perform pre-simulation verification of the register translation circuit code based on the register translation circuit index, and perform post-simulation verification of the netlist based on the netlist index.

[0010] In some implementations, the netlist module is configured to: determine a register translation circuit index in the resource directory, and schedule a logic synthesis server in the cluster based on the register translation circuit index to convert the register translation circuit code into a process-dependent gate-level netlist.

[0011] In some implementations, the execution module is configured to: determine a netlist index in the resource directory, open a netlist in the storage server according to the netlist index, and schedule a formal verification server and a time series analysis server in the cluster to perform formal verification and time series analysis, respectively.

[0012] In another aspect of the present invention, a computer device is provided, comprising: at least one processor; and a memory storing computer instructions executable on the processor, the instructions, when executed by the processor, implementing the steps of the method described above.

[0013] In another aspect, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method steps.

[0014] This invention has the following beneficial technical effects: by placing DOC, RTL, and netlist in a storage server and storing different resources in different EDA tool servers, it achieves orderly storage and management of R&D products during the R&D process, reasonable scheduling of EDA resources, and reasonable allocation of R&D resources, thereby maximizing resource utilization and improving R&D efficiency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram illustrating an embodiment of the chip development method provided by the present invention;

[0017] Figure 2 A schematic diagram of an embodiment of the chip development system provided by the present invention;

[0018] Figure 3 A schematic diagram of the hardware structure of an embodiment of the computer device for chip development provided by the present invention;

[0019] Figure 4 A schematic diagram illustrating an embodiment of the computer storage medium for chip development provided by the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0021] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0022] The first aspect of this invention provides an embodiment of a method for chip development. Figure 1 The diagram shown is an embodiment of the chip development method provided by the present invention. Figure 1 As shown, the embodiments of the present invention include the following steps:

[0023] S1. Generate a SPEC file based on the chip architecture, and generate register conversion circuit code based on the SPEC file. Place the register conversion circuit code into the storage server and write the register conversion circuit index into the resource directory.

[0024] S2. Read the register conversion circuit code based on the register conversion circuit index and perform a syntax check on the register conversion circuit code, and determine whether there are any syntax errors in the register conversion circuit code;

[0025] S3. In response to the absence of syntax errors in the register translation circuit code, perform logic synthesis based on the register translation circuit code to generate a netlist, place the netlist in a storage server, and write the netlist index to a resource directory; and

[0026] S4. Read the netlist based on the netlist index and perform formal verification and timing analysis on the netlist.

[0027] In this embodiment of the invention, a SPEC file is generated based on the chip architecture. RTL code is developed based on the SPEC. After performing a syntax check (SPYGLASS) on the RTL code, pre-simulation (PRE-SIM) is performed. After simulation, DC synthesis is performed to generate a netlist file. After performing post-simulation (PRE-SIM) on the netlist file, formal verification (Formality) and static timing analysis (PT) are performed. After the process is completed, tape-out (trial production) is performed, and the development process ends.

[0028] A SPEC file is generated based on the chip architecture, and register conversion circuit code is generated based on the SPEC file. The register conversion circuit code is placed in the storage server, and the register conversion circuit index is written to the resource directory.

[0029] A SPEC file is generated based on the chip architecture. The local server submits a task to the server cluster, locates the DOC index in the resource directory, automatically schedules the Evince server in the cluster to open the DOC in the storage server, generates a SPEC file based on the DOC, and places it on the storage server. The SPEC file is then encoded, and the generated RTL index is saved in the resource directory, while the RTL file is stored on the storage server.

[0030] The register conversion circuit code is read based on the register conversion circuit index, and a syntax check is performed on the register conversion circuit code to determine whether there are any syntax errors in the register conversion circuit code.

[0031] Perform SPYGLASS syntax checking based on the RTL code. The local server submits the task to the cluster, locates the RTL index in the resource directory, automatically schedules the SPYGLASS server in the cluster, and opens the RTL in the storage server.

[0032] In response to the absence of syntax errors in the register translation circuit code, logic synthesis is performed based on the register translation circuit code to generate a netlist, and the netlist is placed in the storage server and the netlist index is written to the resource directory.

[0033] In some implementations, the step of performing logic synthesis based on the register translation circuit code to generate a netlist includes: determining a register translation circuit index in the resource directory; scheduling a logic synthesis server in the cluster based on the register translation circuit index to convert the register translation circuit code into a process-dependent gate-level netlist; and performing logic synthesis (DC) based on the RTL code. The local server submits a task to the cluster, locates the RTL index in the resource directory, automatically schedules the DC server in the cluster, and opens the RTL in the storage server.

[0034] The netlist is read based on the netlist index, and formal verification and timing analysis are performed on the netlist.

[0035] In some implementations, the step of reading the netlist based on the netlist index and performing formal verification and timing analysis on the netlist includes: determining the netlist index in the resource directory, opening the netlist in the storage server according to the netlist index, and scheduling the formal verification server and timing analysis server in the cluster to perform formal verification and timing analysis respectively. Formal verification (Formality) is performed based on the netlist. The local server submits a task to the cluster, finds the netlist index in the resource directory, automatically schedules the Formality server in the cluster, and opens the netlist in the storage server. Timing analysis (PT) is performed based on the netlist. The local server submits a task to the cluster, finds the netlist index in the resource directory, automatically schedules the PT server in the cluster, and opens the netlist in the storage server.

[0036] In some implementations, the method further includes: determining a register translation circuit index and a netlist index in the resource directory, scheduling a verification server in the cluster to perform pre-simulation verification of the register translation circuit code based on the register translation circuit index, and performing post-simulation verification of the netlist based on the netlist index.

[0037] Pre-simulation is performed based on the RTL code. The local server submits the task to the cluster, locates the RTL index in the resource directory, automatically schedules the simulation server in the cluster, and opens the RTL in the storage server. Post-simulation is performed based on the netlist. The local server submits the task to the cluster, locates the netlist index in the resource directory, automatically schedules the simulation server in the cluster, and opens the netlist in the storage server.

[0038] This invention, through placing DOC, RTL, and netlist in a storage server and classifying and storing different resources in different EDA tool servers, achieves orderly storage and management of R&D products during the R&D process, reasonable scheduling of EDA resources, and reasonable allocation of R&D resources, thereby maximizing resource utilization and improving R&D efficiency.

[0039] It should be noted that the steps in each embodiment of the above-mentioned chip development method can be interleaved, substituted, added, or deleted. Therefore, these reasonable permutations and combinations of the chip development method should also fall within the protection scope of this invention, and the protection scope of this invention should not be limited to the embodiments.

[0040] Based on the above objectives, a second aspect of the present invention provides a system for chip development. For example... Figure 2 As shown, system 200 includes the following modules: a creation module, configured to generate a SPEC file based on the chip architecture, generate register translation circuit code based on the SPEC file, place the register translation circuit code in a storage server, and write the register translation circuit index to a resource directory; a checking module, configured to read the register translation circuit code based on the register translation circuit index, perform syntax checking on the register translation circuit code, and determine whether there are any syntax errors in the register translation circuit code; a netlist module, configured to, in response to the absence of syntax errors in the register translation circuit code, perform logic synthesis based on the register translation circuit code to generate a netlist, place the netlist in a storage server, and write the netlist index to a resource directory; and an execution module, configured to read the netlist based on the netlist index and perform formal verification and timing analysis on the netlist.

[0041] In some implementations, the system further includes a verification module configured to: determine a register translation circuit index and a netlist index in the resource directory, schedule a verification server in the cluster to perform pre-simulation verification of the register translation circuit code based on the register translation circuit index, and perform post-simulation verification of the netlist based on the netlist index.

[0042] In some implementations, the netlist module is configured to: determine a register translation circuit index in the resource directory, and schedule a logic synthesis server in the cluster based on the register translation circuit index to convert the register translation circuit code into a process-dependent gate-level netlist.

[0043] In some implementations, the execution module is configured to: determine a netlist index in the resource directory, open a netlist in the storage server according to the netlist index, and schedule a formal verification server and a time series analysis server in the cluster to perform formal verification and time series analysis, respectively.

[0044] Based on the above objectives, a third aspect of the present invention provides a computer device, comprising: at least one processor; and a memory storing computer instructions executable by the processor to perform the following steps: S1, generating a SPEC file based on a chip architecture, generating register translation circuit code based on the SPEC file, placing the register translation circuit code in a storage server, and writing a register translation circuit index into a resource directory; S2, reading the register translation circuit code based on the register translation circuit index, performing syntax checking on the register translation circuit code, and determining whether there are syntax errors in the register translation circuit code; S3, in response to the absence of syntax errors in the register translation circuit code, performing logic synthesis based on the register translation circuit code to generate a netlist, placing the netlist in a storage server, and writing a netlist index into a resource directory; and S4, reading the netlist based on the netlist index and performing formal verification and timing analysis on the netlist.

[0045] In some implementations, the steps further include: determining a register translation circuit index and a netlist index in the resource directory, scheduling a verification server in the cluster to perform pre-simulation verification of the register translation circuit code based on the register translation circuit index, and performing post-simulation verification of the netlist based on the netlist index.

[0046] In some implementations, the step of performing logic synthesis based on the register translation circuit code to generate a netlist includes: determining a register translation circuit index in the resource directory, and scheduling a logic synthesis server in the cluster based on the register translation circuit index to convert the register translation circuit code into a process-dependent gate-level netlist.

[0047] In some implementations, the step of reading the netlist based on the netlist index and performing formal verification and timing analysis on the netlist includes: determining the netlist index in the resource directory, opening the netlist in the storage server according to the netlist index, and scheduling the formal verification server and timing analysis server in the cluster to perform formal verification and timing analysis respectively.

[0048] This invention, through placing DOC, RTL, and netlist in a storage server and classifying and storing different resources in different EDA tool servers, achieves orderly storage and management of R&D products during the R&D process, reasonable scheduling of EDA resources, and reasonable allocation of R&D resources, thereby maximizing resource utilization and improving R&D efficiency.

[0049] like Figure 3 The diagram shown is a hardware structure schematic of an embodiment of the computer device developed using the chip described above, provided by the present invention.

[0050] For example Figure 3 Taking the device shown as an example, the device includes a processor 301 and a memory 302.

[0051] Processor 301 and memory 302 can be connected via a bus or other means. Figure 3 Taking the example of a connection between China and Israel via a bus.

[0052] The memory 302, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the chip development method in the embodiments of this application. The processor 301 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 302, thereby realizing the chip development method.

[0053] Memory 302 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by using the chip development method, etc. Furthermore, memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 302 may optionally include memory remotely located relative to processor 301, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0054] The computer instructions 303 corresponding to one or more chip development methods are stored in the memory 302. When executed by the processor 301, the chip development method in any of the above method embodiments is executed.

[0055] The chip development method includes the following steps: generating a SPEC file based on the chip architecture, generating register translation circuit code based on the SPEC file, placing the register translation circuit code in a storage server and writing the register translation circuit index into a resource directory; reading the register translation circuit code based on the register translation circuit index and performing syntax checks on the register translation circuit code to determine whether there are any syntax errors in the register translation circuit code; in response to the absence of syntax errors in the register translation circuit code, performing logic synthesis based on the register translation circuit code to generate a netlist, placing the netlist in a storage server and writing the netlist index into a resource directory; and reading the netlist based on the netlist index and performing formal verification and timing analysis on the netlist.

[0056] In some implementations, the method further includes: determining a register translation circuit index and a netlist index in the resource directory, scheduling a verification server in the cluster to perform pre-simulation verification of the register translation circuit code based on the register translation circuit index, and performing post-simulation verification of the netlist based on the netlist index.

[0057] In some implementations, the step of performing logic synthesis based on the register translation circuit code to generate a netlist includes: determining a register translation circuit index in the resource directory, and scheduling a logic synthesis server in the cluster based on the register translation circuit index to convert the register translation circuit code into a process-dependent gate-level netlist.

[0058] In some implementations, the step of reading the netlist based on the netlist index and performing formal verification and timing analysis on the netlist includes: determining the netlist index in the resource directory, opening the netlist in the storage server according to the netlist index, and scheduling the formal verification server and timing analysis server in the cluster to perform formal verification and timing analysis respectively.

[0059] Any embodiment of the computer device that performs the above-described chip development method can achieve the same or similar effects as any of the aforementioned method embodiments.

[0060] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs a method for chip development.

[0061] like Figure 4The diagram shown is a schematic representation of an embodiment of the computer storage medium developed using the chip described above by the present invention. Figure 4 Taking the computer storage medium shown as an example, the computer-readable storage medium 401 stores a computer program 402 that, when executed by a processor, performs the above method.

[0062] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program for the chip development method can be stored in a computer-readable storage medium. When executed, the program can include the processes of the embodiments of the above methods. The storage medium for the program can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The above computer program embodiments can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0063] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0064] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0065] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0066] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0067] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for chip development, characterized in that, Includes the following steps: A SPEC file is generated based on the chip architecture, and register conversion circuit code is generated based on the SPEC file. The register conversion circuit code is placed in the storage server and the register conversion circuit index is written to the resource directory. The register conversion circuit code is read based on the register conversion circuit index, and a syntax check is performed on the register conversion circuit code to determine whether there are any syntax errors in the register conversion circuit code; In response to the absence of syntax errors in the register translation circuit code, logic synthesis is performed based on the register translation circuit code to generate a netlist, the netlist is placed in the storage server and the netlist index is written to the resource directory; as well as The netlist is read based on the netlist index, and formal verification and timing analysis are performed on the netlist. The process of generating a SPEC file based on the chip architecture includes: the local server submitting a task to the server cluster, finding the DOC index in the resource directory, automatically scheduling the Evince server in the cluster and opening the DOC in the storage server, generating a SPEC file based on the DOC, and placing it on the storage server.

2. The method according to claim 1, characterized in that, The method also includes: The register translation circuit index and netlist index are determined in the resource directory. The verification server in the cluster is scheduled to perform pre-simulation verification of the register translation circuit code according to the register translation circuit index, and the netlist is performed post-simulation verification according to the netlist index.

3. The method according to claim 1, characterized in that, The step of performing logic synthesis based on the register-to-conversion circuit code to generate a netlist includes: The register translation circuit index is determined in the resource directory, and the logic synthesis server in the cluster is scheduled according to the register translation circuit index to convert the register translation circuit code into a process-related gate-level netlist.

4. The method according to claim 1, characterized in that, The step of reading the netlist based on the netlist index and performing formal verification and timing analysis on the netlist includes: The netlist index is determined in the resource directory, the netlist in the storage server is opened according to the netlist index, and the formal verification server and the time series analysis server in the cluster are scheduled to perform formal verification and time series analysis respectively.

5. A system for chip development, characterized in that, include: Create a module, configure it to generate a SPEC file based on the chip architecture, generate register conversion circuit code based on the SPEC file, put the register conversion circuit code into the storage server, and write the register conversion circuit index into the resource directory; The inspection module is configured to read the register conversion circuit code based on the register conversion circuit index, perform syntax checks on the register conversion circuit code, and determine whether there are any syntax errors in the register conversion circuit code. The netlist module is configured to, in response to the absence of syntax errors in the register translation circuit code, perform logic synthesis based on the register translation circuit code to generate a netlist, place the netlist in the storage server, and write the netlist index to the resource directory; as well as The execution module is configured to read the netlist based on the netlist index and perform formal verification and timing analysis on the netlist; The creation module is also used for: submitting a task from the local server to the server cluster, finding the DOC index in the resource directory, automatically scheduling the Evince server in the cluster and opening the DOC in the storage server, generating a SPEC file based on the DOC, and placing it in the storage server.

6. The system according to claim 5, characterized in that, The system also includes a verification module, configured for: The register translation circuit index and netlist index are determined in the resource directory. The verification server in the cluster is scheduled to perform pre-simulation verification of the register translation circuit code according to the register translation circuit index, and the netlist is performed post-simulation verification according to the netlist index.

7. The system according to claim 5, characterized in that, The netlist module is configured to: The register translation circuit index is determined in the resource directory, and the logic synthesis server in the cluster is scheduled according to the register translation circuit index to convert the register translation circuit code into a process-related gate-level netlist.

8. The system according to claim 5, characterized in that, The execution module is configured to: The netlist index is determined in the resource directory, the netlist in the storage server is opened according to the netlist index, and the formal verification server and the time series analysis server in the cluster are scheduled to perform formal verification and time series analysis respectively.

9. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-4.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-4.

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