Clock conversion circuit

Abstract

A clock conversion circuit is disclosed that includes a first switch connected between a first input node for receiving a second input clock and a first node and operative in response to a first logic state of the first input clock, the second input clock delayed by up to 90 degrees with respect to the first input clock; a second switch connected between a second input node for receiving the first input clock and a second node and operative in response to a second logic state of the second input clock; and a third switch connected between the second node and a ground node and operative in response to a first logic state of the second input clock opposite the second logic state of the second input clock.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0079733, filed on June 30, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure described herein relate to clock conversion circuits. Background Technology

[0004] Memory devices may include various circuits for generating, processing, or storing data. For example, a memory device may include various circuits for storing or outputting data based on clock signals, data signals, and command signals. Nowadays, as the amount of data to be processed in memory devices increases, the frequency of clock signals also increases.

[0005] Because processing high-frequency clock signals directly at the memory device is computationally intensive, the memory device can use multiple clock signals with different phases, and the memory device can switch the duty cycle of the clock signals. In this case, factors such as skew or duty cycle errors in the switched clock signals can lead to abnormal operation of the memory device or reduced reliability of the data stored therein. Therefore, a clock switching circuit that is robust to clock signal skew and duty cycle errors is needed. Summary of the Invention

[0006] Embodiments of this disclosure provide a clock conversion circuit in which the edge types of the input clocks used for duty cycle conversion are consistent with each other, and the output stage has a symmetrical structure.

[0007] According to an example embodiment, a clock conversion circuit includes: a first switch connected between a first input node for receiving a second input clock and a first node, and operating in response to a first logic state of the first input clock, the second input clock being delayed by up to 90 degrees relative to the first input clock; a second switch connected between a second input node for receiving the first input clock and a second node, and operating in response to a second logic state of the second input clock; and a third switch connected between the second node and a ground node, and operating in response to a first logic state of the second input clock that is opposite to the second logic state of the second input clock.

[0008] According to an example embodiment, a clock conversion circuit includes a first clock circuit, a second clock circuit, a third clock circuit, and a fourth clock circuit, wherein the first through fourth clock circuits generate an output four-phase clock including a first output clock, a second output clock, a third output clock, and a fourth output clock based on an input four-phase clock including a first input clock, a second input clock, a third input clock, and a fourth input clock. The first clock circuit includes a first switch connected between a first input node for receiving the second input clock and a first node and configured to operate in response to a first logic state of the first input clock, a second switch connected between a second input node for receiving the first input clock and a second node and configured to operate in response to a second logic state of the second input clock, and a third switch connected between the second node and a ground node and configured to operate in response to a first logic state of the second input clock opposite the second logic state of the second input clock.

[0009] According to an example embodiment, a clock conversion circuit includes a first switch connected between a first input node for receiving a first input clock and a first node and operating in response to a first logic state of a second input clock delayed by up to 90 degrees with respect to the first input clock, a second switch connected between a second input node for receiving a second input clock and a second node and operating in response to a second logic state of the first input clock, and a third switch connected between the first node and a power supply node and operating in response to a second logic state of the second input clock opposite the first logic state of the second input clock. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent from a detailed description of example embodiments thereof taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a clock conversion circuit.

[0012] Figure 2 is a table illustrating Figure 1 input clocks and output clocks of the clock conversion circuit of

[0013] Figure 3A is a circuit diagram illustrating the clock conversion circuit in detail.

[0014] Figure 3B is a table illustrating Figure 3A input clocks and output clocks of the clock conversion circuit of

[0015] Figure 4A is a circuit diagram illustrating the clock conversion circuit in detail.

[0016] Figure 4B is a graph showing an input clock and an output clock of the clock conversion circuit of Figure 4A .

[0017] Figure 5A is a block diagram showing the clock conversion circuit according to an embodiment of the present disclosure in detail.

[0018] Figure 5B is a graph showing an input clock and an output clock of the clock conversion circuit of Figure 5A according to an example embodiment.

[0019] Figure 5C is a block diagram showing the first to fourth clock circuits of Figure 5A according to an example embodiment in detail.

[0020] Figure 6 is a block diagram showing the clock conversion circuit according to an embodiment of the present disclosure in detail.

[0021] Figure 7 is a block diagram showing the clock conversion circuit according to an embodiment of the present disclosure in detail.

[0022] Figure 8 is a block diagram showing the clock conversion circuit according to an embodiment of the present disclosure in detail.

[0023] Figure 9 is a block diagram showing the clock conversion circuit including a latch inverter according to an embodiment of the present disclosure in detail.

[0024] Figure 10 is a block diagram showing the clock conversion circuit including a buffer according to an embodiment of the present disclosure in detail.

[0025] Figure 11 is a block diagram showing the simplified clock conversion circuit according to an embodiment of the present disclosure in detail.

[0026] Figure 12A is a block diagram showing the clock conversion circuit according to an embodiment of the present disclosure in detail.

[0027] Figure 12B is a graph showing an input clock and an output clock of the clock conversion circuit of Figure 12A according to an example embodiment.

[0028] Figure 12C is a block diagram showing the first to fourth clock circuits of Figure 12A according to an example embodiment in detail.

[0029] Figure 13 is a block diagram showing the clock conversion circuit according to an embodiment of the present disclosure in detail.

[0030] Figure 14 is a block diagram illustrating a clock conversion circuit according to an embodiment of the disclosure in detail.

[0031] Figure 15 is a block diagram illustrating a clock conversion circuit according to an embodiment of the disclosure in detail.

[0032] Figure 16 is a block diagram illustrating a clock conversion circuit including a latch inverter according to an embodiment of the disclosure in detail.

[0033] Figure 17 is a block diagram illustrating a clock conversion circuit including a buffer according to an embodiment of the disclosure in detail.

[0034] Figure 18 is a block diagram illustrating a simplified clock conversion circuit according to an embodiment of the disclosure in detail.

[0035] Figure 19 is a block diagram illustrating a memory system according to an embodiment of the disclosure.

[0036] Figure 20 is a block diagram illustrating a memory device of Figure 19 according to an example embodiment in detail.

[0037] Figure 21 is a circuit diagram illustrating an input / output circuit of Figure 20 according to an example embodiment in detail.

[0038] Figure 22 is a graph illustrating a data signal generated at a DQ pad of Figure 21 according to an example embodiment.

[0039] Figure 23 is a block diagram illustrating a memory module according to an embodiment of the disclosure.

[0040] Figure 24 is a block diagram illustrating an electronic system according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0041] Hereinafter, embodiments of the disclosure can be described in detail with reference to the accompanying drawings so as to be easily practiced by one of ordinary skill in the art to which the disclosure pertains. Hereinafter, for the sake of brevity of description with regard to embodiments of the disclosure, the same or like component will be designated by the same or like reference numeral, and a repeated description of the same or like component will be omitted.

[0042] In the following drawings or detailed description, a module can be connected with any other component as well as components shown in the drawings or described in the detailed description. A module or component can be directly or indirectly connected. A module or component can be connected by communication or can be physically connected.

[0043] Figure 1 is a block diagram illustrating a clock conversion circuit 100. Referring to Figure 1 , the clock conversion circuit 100 receives first to fourth input clocks ICLK1 to ICLK4 from an input clock generator ICG and generates first to fourth output clocks OCLK1 to ICLK4 and first to fourth inverted output clocks OCLK1B to OCLK4B.

[0044] Each of the first to fourth input clocks ICLK1 to ICLK4 can be a clock signal in which a first logic state (e.g., a logic high level) and a second logic state (e.g., a logic low level) are repeated at a given period. The first to fourth output clocks OCLK1 to OCLK4 can be clock signals having a duty cycle different from that of the first to fourth input clocks ICLK1 to ICLK4. The duty cycle can represent a ratio of a time interval corresponding to the first logic state within a time interval (or a time period) having the first logic state and the second logic state.

[0045] The first to fourth inverted output clocks OCLK1B to OCLK4B can be clock signals whose logic states are opposite to those of the first to fourth output clocks OCLK1 to OCLK4, respectively. This will be described more fully with reference to Figure 2 .

[0046] That is, the clock conversion circuit 100 can be a circuit that converts a duty cycle of the first to fourth input clocks ICLK1 to ICLK4. For example, a duty cycle of the first output clock OCLK1 can be half of a duty cycle of the first input clock ICLK1.

[0047] The clock conversion circuit 100 can receive the first to fourth input clocks ICLK1 to ICLK4 from the input clock generator ICG. The input clock generator ICG can generate the first to fourth input clocks ICLK1 to ICLK4 based on a reference clock RCLK. In this case, the first to fourth input clocks ICLK1 to ICLK4 can be signals having the same period and the same duty cycle but having different phases.

[0048] For example, the phase of the first input clock ICLK1 can be the same as the phase of the reference clock RCLK. The phase of the second input clock ICLK2 can be delayed by up to 90 degrees with respect to the phase of the reference clock RCLK (or the second input clock ICLK2 can be delayed by up to 90 degrees with respect to the reference clock RCLK). The phase of the third input clock ICLK3 can be delayed by up to 180 degrees with respect to the phase of the reference clock RCLK. The phase of the fourth input clock ICLK4 can be delayed by up to 270 degrees with respect to the phase of the reference clock RCLK. That is, the input clock generator ICG can be a device that generates input four-phase clocks including the first to fourth input clocks ICLK1 to ICLK4.

[0049] The clock conversion circuit 100 can include first to fourth clock circuits 110 to 140. The first clock circuit 110 can generate a first output clock OCLK1 and a first inverted output clock OCLK1B based on the first to fourth input clocks ICLK1 to ICLK4. The second clock circuit 120 can generate a second output clock OCLK2 and a second inverted output clock OCLK2B based on the first to fourth input clocks ICLK1 to ICLK4. The third clock circuit 130 can generate a third output clock OCLK3 and a third inverted output clock OCLK3B based on the first to fourth input clocks ICLK1 to ICLK4. The fourth clock circuit 140 can generate a fourth output clock OCLK4 and a fourth inverted output clock OCLK4B based on the first to fourth input clocks ICLK1 to ICLK4.

[0050] For example, the clock conversion circuit 100 can be a device that generates output four-phase clocks including the first to fourth output clocks OCLK1 to OCLK4 and inverted output four-phase clocks including the first to fourth inverted output clocks OCLK1B to OCLK4B based on input four-phase clocks including the first to fourth input clocks ICLK1 to ICLK4.

[0051] In an example embodiment, assuming that there is no duty cycle error or skew, the first to fourth output clocks OCLK1 to OCLK4 can be signals having the same period and the same duty cycle but having different phases. For example, assuming that the phase of the first output clock OCLK1 is 0 degrees, the phases of the second to fourth output clocks OCLK2 to OCLK4 can be 90 degrees, 180 degrees, and 270 degrees, respectively.

[0052] As described above, according to an embodiment of the disclosure, it is possible to provide a clock conversion circuit 100 that generates output four-phase clocks and inverted output four-phase clocks based on input four-phase clocks.

[0053] Figure 2 is shown Figure 1of the input clock and the output clock of the clock conversion circuit 100. In Figure 2 The waveforms of the input clocks ICLK1 to ICLK4, the waveforms of the output clocks OCLK1 to OCLK4, and the waveforms of the inverted output clocks OCLK1B to OCLK4B over time are shown in Figure 2 In the graph of the waveforms of the input clocks ICLK1 to ICLK4, the waveforms of the output clocks OCLK1 to OCLK4, and the waveforms of the inverted output clocks OCLK1B to OCLK4B, the horizontal direction represents time. The vertical direction represents a logic state.

[0054] The first input clock ICLK1 can be a clock signal in which a first logic state and a second logic state are periodically repeated. The first input clock ICLK1 can have a period Tp and a duty ratio Dy1. For example, the period Tp can correspond to a time interval from time TO to time T4. For example, the duty ratio Dy1 can be 50%.

[0055] In an example embodiment, the first input clock ICLK1 can have the first logic state in a time interval from time TO to time T2. The first input clock ICLK1 can have the second logic state in a time interval from time T2 to time T4. For example, the first logic state can correspond to a logic high level, and the second logic state can correspond to a logic low level.

[0056] The phases of the second to fourth input clocks ICLK2 to ICLK4 can be different from the phase of the first input clock ICLK1. For example, the phase of the second input clock ICLK2 can be delayed by up to 90 degrees with respect to the phase of the first input clock ICLK1. The phase of the third input clock ICLK3 can be delayed by up to 180 degrees with respect to the phase of the first input clock ICLK1. The phase of the fourth input clock ICLK4 can be delayed by up to 270 degrees with respect to the phase of the first input clock ICLK1.

[0057] In this case, a time interval from time TO to time T1 can correspond to a phase of 90 degrees. A time interval from time TO to time T2 can correspond to a phase of 180 degrees. A time interval from time TO to time T3 can correspond to a phase of 270 degrees.

[0058] The first output clock OCLK1 can be a clock signal in which a first logic state and a second logic state are periodically repeated. In this case, a duty ratio Dy2 of the first output clock OCLK1 can be different from a duty ratio Dy1 of the first input clock ICLK1. For example, the duty ratio Dy1 can be 50%, and the duty ratio Dy2 can be 25%.

[0059] In an example embodiment, the first output clock OCLK1 can have a first logic state in a time interval from time TO to time T1. The first output clock OCLK1 can have a second logic state in a time interval from time T1 to time T4.

[0060] The phases of the second to fourth output clocks OCLK2 to OCLK4 can be different from the phase of the first output clock OCLK1. For example, the phase of the second output clock OCLK2 can be delayed from the phase of the first output clock OCLK1 by up to 90 degrees. The phase of the third output clock OCLK3 can be delayed from the phase of the first output clock OCLK1 by up to 180 degrees. The phase of the fourth output clock OCLK4 can be delayed from the phase of the first output clock OCLK1 by up to 270 degrees.

[0061] The first to fourth inverted output clocks OCLK1B to OCLK4B can be clock signals whose logic states are opposite to the logic states of the first to fourth output clocks OCLK1 to OCLK4, respectively. For example, in the time interval from time TO to time T1, the first output clock OCLK1 can have a first logic state, and the first inverted output clock OCLK1B can have a second logic state. For example, in the time interval from time T1 to time T4, the first output clock OCLK1 can have a second logic state, and the first inverted output clock OCLK1B can have a first logic state.

[0062] Figure 3A is a circuit diagram that illustrates the clock conversion circuit 100a in detail. Referring to Figure 3A , the clock conversion circuit 100a can include first to fourth clock circuits 110a to 140a. The first to fourth clock circuits 110a to 140a can output first to fourth output clocks OCLK1 to OCLK4, respectively.

[0063] Specifically, the first clock circuit 110a can generate the first output clock OCLK1 and the first inverted output clock OCLK1B based on the first to fourth input clocks ICLK1 to ICLK4. The structures of the second to fourth clock circuits 120a to 140a can be similar to that of the first clock circuit 110a. For simplicity of explanation, the detailed structures of the second to fourth clock circuits 120a to 140a will be omitted.

[0064] The first clock circuit 110a can invert a result of a NAND logical operation of the first input clock ICLK1 and the fourth input clock ICLK4 to generate the first output clock OCLK1. The first clock circuit 110a can perform a NAND logical operation on an inverted version of the third input clock ICLK3 and an inverted version of the second input clock ICLK2 to generate the first inverted output clock OCLK1B. However, the edge types of the input clocks ICLK1 to ICLK4 for duty cycle conversion can be different, causing a problem in which the first clock circuit 110a can be susceptible to duty cycle errors of the input clocks ICLK1 to ICLK4. This will be described with reference to Figure 3B more fully described.

[0065] Figure 3B is a graph illustrating Figure 3A input clocks and output clocks of the clock conversion circuit 100a. In Figure 3B the waveform of the first input clock ICLK1, the waveform of the fourth input clock ICLK4, the waveform of the first output clock OCLK1, and the waveform of the first inverted output clock OCLK1B are illustrated. In Figure 3B the graph of the clock conversion circuit 100a, the horizontal direction represents time. The vertical direction represents a logic state. The first input clock ICLK1 can have a period Tp.

[0066] The first clock circuit 110a can perform a NAND logical operation of the first input clock ICLK1 and the fourth input clock ICLK4. At time Ta1, the first clock circuit 110a can change a logic state of the first output clock OCLK1 based on a rising edge of the first input clock ICLK1. The rising edge can indicate a switching of a logic state of a clock signal from a low level to a high level (or a transition of a logic state of a clock signal from low to high). At time Ta2, the first clock circuit 110a can change the logic state of the first output clock OCLK1 based on a falling edge of the fourth input clock ICLK4. The falling edge can indicate a switching of the logic state of the clock signal from the high level to the low level (or the transition of the logic state of the clock signal from high to low).

[0067] Due to a process or degradation of a semiconductor device including the clock conversion circuit 100a, the input clocks ICLK1 to ICLK4 can have duty cycle errors. The duty cycle error can refer to a difference between an actual duty cycle value and an expected (or target) duty cycle value. The clock conversion circuit 100a operating based on different types of edges (i.e., rising edges and falling edges) can be susceptible to the duty cycle errors of the input clocks ICLK1 to ICLK4. Accordingly, there is a need for a technique for generating an output clock based on the same type of edge (i.e., a rising edge or a falling edge).

[0068] Figure 4Ais a circuit diagram that illustrates the clock conversion circuit 100b in detail. Referring to Figure 4A , the clock conversion circuit 100b can include first to fourth clock circuits 110b to 140b. The first to fourth clock circuits 110b to 140b output first to fourth output clocks OCLK1 to OCLK4, respectively. The first clock circuit 110b can generate the first output clock OCLK1 and a first inverted output clock OCLK1B based on a first input clock ICLK1 and a second input clock ICLK2.

[0069] The structures of the second to fourth clock circuits 120b to 140b can be similar to that of the first clock circuit 110b. For simplicity of explanation, detailed structures of the second to fourth clock circuits 120b to 140b will be omitted.

[0070] When the first input clock ICLK1 has a first logic state that is a high level, the first clock circuit 110b can provide the second input clock ICLK2 to a node Nx1. When the first input clock ICLK1 has a second logic state, the first clock circuit 110b can feed back a voltage of a node Nx2 to the node Nx1 through an inverter INVx. The inverter INVx can be driven based on a power supply voltage Vdd and a ground GND. A voltage similar to a waveform of the first inverted output clock OCLK1B can be formed at the node Nx1.

[0071] The first clock circuit 110b can generate the first output clock OCLK1 and the first inverted output clock OCLK1B based on the voltage of the node Nx1. That is, unlike the first clock circuit 110a of Figure 3A , the first clock circuit 110b can generate the first output clock OCLK1 and the first inverted output clock OCLK1B based on the same type of edge.

[0072] However, in the first clock circuit 110b, since an output stage (e.g., an inverter INV) connected to the node Nx1 has an asymmetric structure, a timing error can occur between the first output clock OCLK1 and the first inverted output clock OCLK1B. This will be described more fully with reference to Figure 4B .

[0073] Figure 4B is a graph that illustrates input clocks and output clocks of the clock conversion circuit 100b of Figure 4A . In Figure 4B , a waveform of the first input clock ICLK1, a waveform of the second input clock ICLK2, a waveform of the first output clock OCLK1, and a waveform of the first inverted output clock OCLK1B are illustrated. In Figure 4BIn the graph, the horizontal direction represents time. The vertical direction represents a logic state. The first input clock ICLK1 can have a period Tp.

[0074] The first clock circuit 110b can generate the first output clock OCLK1 and the first inverted output clock OCLK1B based on the rising edge of the first input clock ICLK1 and the rising edge of the second input clock ICLK2. That is, because the first clock circuit 110b operates based on the same type of edge (i.e., the rising edge), the first clock circuit 110b can be robust to duty cycle error of the input clocks ICLK1 and ICLK2.

[0075] Because the output stage (e.g., inverters INV) connected to the node Nx1 of the first clock circuit 110b has an asymmetric structure, skew can occur. In particular, the first output clock OCLK1 can be generated by three inverters INV connected in series to the node Nx1. The first inverted output clock OCLK1B can be generated by two inverters INV connected in series to the node Nx1. Because the time that the three inverters INV delay is different from the time that the two inverters INV delay, skew can occur between the first output clock OCLK1 and the first inverted output clock OCLK1B.

[0076] For example, the first output clock OCLK1 generated by the three inverters INV connected in series can be delayed by up to a time interval Tx1 by the operation of the three inverters INV. The time interval Tx1 can be the interval from time Tb1 to time Tb3. The first inverted output clock OCLK1B generated by the two inverters INV connected in series can be delayed by up to a time interval Tx2 by the operation of the two inverters INV. The time interval Tx2 can be the interval from time Tb1 to time Tb2. Here, the time interval Tx1 can be longer than the time interval Tx2.

[0077] As described above, the first clock circuit 110b can be advantageous in that the first clock circuit 110b operates based on the same type of edge, but can be disadvantageous in that skew can occur between the first output clock OCLK1 and the first inverted output clock OCLK1B due to the asymmetric structure of the output stage. Accordingly, there is a need for a clock circuit that generates output clocks based on the same type of edge and has a symmetric structure.

[0078] Figure 5A is a block diagram that illustrates in detail the clock conversion circuit 1100 according to an embodiment of the disclosure. Referring to Figure 5AThe clock conversion circuit 1100 can include first to fourth clock circuits 1110 to 1140. The first clock circuit 1110 can generate a first output clock OCLK1 and a first inverted output clock OCLK1B based on a first input clock ICLK1 and a second input clock ICLK2. Reference will be made to FIGS. 11A and 11B to describe the first clock circuit 1110. Figure 5C The structures of the second to fourth clock circuits 1120 to 1140 will be described more fully.

[0079] The first clock circuit 1110 can include a first switch SW1, a second switch / SW2, a third switch SW3, a first inverter INV1, and a second inverter INV2. Here, the symbol " / " of the second switch / SW2 can mean that the second switch / SW2 operates in response to an inverted logic state. For example, in a case where clock signals sequentially having a first logic state and a second logic state are applied to the first switch SW1 and the second switch / SW2, the first switch SW1 can be turned on in a time interval in which the clock signal is in the first logic state, and the second switch / SW2 can be turned on in a time interval in which the clock signal is in the second logic state.

[0080] The first clock circuit 1110 can receive the second input clock ICLK2 through a first input node N11. The first clock circuit 1110 can receive the first input clock ICLK1 through a second input node N12. The first clock circuit 1110 can output the first output clock OCLK1 through a first output node N01. The first clock circuit 1110 can output the first inverted output clock OCLK1B through a second output node N02.

[0081] The first input clock ICLK1 and the second input clock ICLK2 can be clock signals having the same period and the same duty cycle and in which a first logic state and a second logic state are periodically repeated. The phase of the second input clock ICLK2 can be delayed by up to 90 degrees with respect to the phase of the first input clock ICLK1. The first output clock OCLK1 can be a clock signal having the same period as the first input clock ICLK1 and having a shorter duty cycle than the first input clock ICLK1. The first inverted output clock OCLK1B can be a clock signal whose logic state is opposite to that of the first output clock OCLK1.

[0082] The first switch SW1 can be connected between the first input node N11 and a first node N1. The first switch SW1 can operate in response to the first logic state of the first input clock ICLK1 on the second input node N12.

[0083] For example, the first switch SW1 can be turned on in a time interval in which the first input clock ICLK1 has a first logic state (e.g., a logic high level), and can be turned off in a time interval in which the first input clock ICLK1 has a second logic state (e.g., a logic low level), but the disclosure is not limited thereto.

[0084] The second switch / SW2 can be connected between the second input node Ni2 and the second node N2. The second switch / SW2 can operate in response to a second logic state of the second input clock ICLK2 on the first input node Ni1.

[0085] For example, the second switch / SW2 can be turned on in a time interval in which the second input clock ICLK2 has a second logic state (e.g., a logic low level), and can be turned off in a time interval in which the second input clock ICLK2 has a first logic state (e.g., a logic high level), but the disclosure is not limited thereto.

[0086] The third switch SW3 can be connected between the second node N2 and a ground node. The ground node can be a node to which a ground GND is supplied. The ground GND can be a voltage corresponding to the second logic state (e.g., a logic low level). The third switch SW3 can operate in response to a first logic state of the second input clock ICLK2 on the first input node Ni1.

[0087] For example, the third switch SW3 can be turned on in a time interval in which the second input clock ICLK2 has a first logic state (e.g., a logic high level), and can be turned off in a time interval in which the second input clock ICLK2 has a second logic state (e.g., a logic low level), but the disclosure is not limited thereto.

[0088] The first inverter INV1 can be connected between the first node N1 and the first output node No1. The first inverter INV1 can invert a voltage of the first node N1, and can output the inverted voltage to the first output node No1. Inverting a voltage can refer to inverting a logic state. For example, when the voltage at the first node N1 corresponds to the first logic state, the first inverter INV1 can output a voltage corresponding to the second logic state to the first output node No1. When the voltage at the first node N1 corresponds to the second logic state, the first inverter INV1 can output a voltage corresponding to the first logic state to the first output node No1.

[0089] The second inverter INV2 can be connected between the second node N2 and the second output node No2. The second inverter INV2 can invert a voltage of the second node N2, and can output the inverted voltage to the second output node No2.

[0090] The output stage of the clock conversion circuit 1100 according to the embodiment of the disclosure can have a symmetrical structure. For example, one switch and one inverter can be inserted between the first output node No1 from which the first output clock OCLK1 is generated and the first input node Ni1. One switch and one inverter can be inserted between the second output node No2 from which the first inverted output clock OCLK1B is generated and the second input node Ni2. Since the number of elements (including switches and inverters) for the first output clock OCLK1 is equal to the number of elements (including switches and inverters) for the first inverted output clock OCLK1B, skew between the first output clock OCLK1 and the first inverted output clock OCLK1B can be suppressed.

[0091] The clock conversion circuit 1100 according to the embodiment of the disclosure can include a first clock circuit 1110 that generates a first output clock OCLK1 and a first inverted output clock OCLK1B based on edges of the same type. The first clock circuit 1110 will be described with reference to Figure 5B The process in which the first clock circuit 1110 of the clock conversion circuit 1100 generates the first output clock OCLK1 and the first inverted output clock OCLK1B will be described.

[0092] Figure 5B is a graph showing input and output clocks of the clock conversion circuit 1100 according to an example embodiment. In Figure 5A the waveforms of the first input clock ICLK1, the waveforms of the second input clock ICLK2, the waveforms of the first output clock OCLK1, and the waveforms of the first inverted output clock OCLK1B are shown. In Figure 5B the graph, the horizontal direction represents time. The vertical direction represents a logic state. Figure 5B

[0093] The first input clock ICLK1 can have a period Tp. The period Tp can include first to fourth time intervals Tp1 to Tp4. The first time interval Tp1 can be a time interval from a 0-degree phase to a 90-degree phase. The second time interval Tp2 can be a time interval from the 90-degree phase to a 180-degree phase. The third time interval Tp3 can be a time interval from the 180-degree phase to a 270-degree phase. The fourth time interval Tp4 can be a time interval from the 270-degree phase to a 360-degree phase.

[0094] In an example embodiment, the voltage waveform at the first node N1 can be similar to the voltage waveform of the first inverted output clock OCLK1B. The voltage waveform at the first node N1 can be based on the rising edge of the first input clock ICLK1 and the rising edge of the second input clock ICLK2.

[0095] ​For example, in the first time interval Tpl, the first switch SWl can be turned on, but the second input clock ICLK2 can have the second logic state. In this case, the first node Nl can have a voltage corresponding to the second logic state. In the second time interval Tp2, the first switch SWl can remain in the on state, and the second input clock ICLK2 can have the first logic state. In this case, the first node Nl can have a voltage corresponding to the first logic state. Because the first switch SWl is turned off in the third time interval Tp3 and the fourth time interval Tp4, the first node Nl can maintain the voltage of the second time interval Tp2 in the third time interval Tp3 and the fourth time interval Tp4.

[0096] In an example embodiment, the first inverter INVl can generate the first output clock OCLKl based on the voltage of the first node Nl. Due to the first inverter INVl, the first output clock OCLKl can be delayed from the first input clock ICLKl by up to a time interval Tx3. The time interval Tx3 can be an interval from time Tc1 to time Tc2.

[0097] In an example embodiment, a voltage waveform at the second node N2 can be similar to a voltage waveform of the first output clock OCLKl. The voltage waveform at the second node N2 can be based on a rising edge of the first input clock ICLKl and a rising edge of the second input clock ICLK2.

[0098] For example, in the first time interval Tpl, the second switch / SW2 can be turned on, the third switch SW3 can be turned off, and the first input clock ICLKl can have the first logic state. In this case, the second node N2 can have a voltage corresponding to the first logic state. For example, in the second time interval Tp2 and the third time interval Tp3, the second switch / SW2 can be turned off, the third switch SW3 can be turned on, and the ground GND can be provided to the second node N2 through the turned on switch SW3. In this case, the second node N2 can have a voltage corresponding to the second logic state. In the fourth time interval Tp4, the second switch / SW2 can be turned on, the third switch SW3 can be turned off, and the first input clock ICLKl can have the second logic state. In this case, the second node N2 can have a voltage corresponding to the second logic state.

[0099] In an example embodiment, the second inverter INV2 can generate the first inverted output clock OCLKlB based on the voltage of the second node N2. Due to the second inverter INV2, the first inverted output clock OCLKlB can be delayed from the first input clock ICLKl by up to a time interval Tx4. The time interval Tx4 can be an interval from time Tc1 to time Tc2.

[0100] Unlike the first clock circuit 110b, Figure 4A The first clock circuit 1110 can be configured in such a way that the number of inverters for the first output clock OCLK1 is equal to the number of inverters for the first inverted output clock OCLK1B, and thus, the time interval Tx4 can be equal to the time interval Tx3, unlike the first clock circuit 110b. For example, since the first clock circuit 1110 has a symmetric structure, skew between the first output clock OCLK1 and the first inverted output clock OCLK1B can be suppressed at the first clock circuit 1110.

[0101] As described above, according to embodiments of the present disclosure, a first clock circuit 1110 is provided that generates output clocks based on the same type of edges and has a symmetric structure. For example, this characteristic is also applied to the second to fourth clock circuits 1120 to 1140 of the clock conversion circuit 1100, not limited to the first clock circuit 1110. The characteristics of the second to fourth clock circuits 1120 to 1140 will be described more fully with reference to Figure 5C

[0102] Figure 5C is a block diagram illustrating in detail the first to fourth clock circuits 1110 to 1140 of Figure 5A the clock conversion circuit 1100 including the first to fourth clock circuits 1110 to 1140 is illustrated in Figure 5C Figure 5C the switches SW1, / SW2, and SW3 and the inverters INV1 and INV2 of the first clock circuit 1110 in Figure 5A the switches SW1, / SW2, and SW3 and the inverters INV1 and INV2 of the first clock circuit 1110 in

[0103] With reference to Figure 5C the switches SW1, / SW2, and SW3 and the inverters INV1 and INV2 of each of the second to fourth clock circuits 1120 to 1140 can be similar to those of the first clock circuit 1110. However, the second to fourth clock circuits 1120 to 1140 can differ from the first clock circuit 1110 in terms of the input clocks provided to the input nodes N11 and N12 and the output clocks generated at the output nodes N01 and N02.

[0104] ​​The second clock circuit 1120 can receive a third input clock ICLK3 through a first input node Nil. The second clock circuit 1120 can receive a second input clock ICLK2 through a second input node Ni2. The second clock circuit 1120 can generate a second output clock OCLK2 and a second inverted output clock OCLK2B based on the second input clock ICLK2 and the third input clock ICLK3. The second clock circuit 1120 can output the second output clock OCLK2 through a first output node No1. The second clock circuit 1120 can output the second inverted output clock OCLK2B through a second output node No2.

[0105] A phase of the second input clock ICLK2 can be delayed by up to 90 degrees with respect to a phase of the first input clock ICLK1. A phase of the third input clock ICLK3 can be delayed by up to 180 degrees with respect to the phase of the first input clock ICLK1. A phase of the second output clock OCLK2 can be delayed by up to 90 degrees with respect to a phase of the first output clock OCLK1 of the first clock circuit 1110. The second inverted output clock OCLK2B can be a signal whose logic state is opposite to a logic state of the second output clock OCLK2.

[0106] The third clock circuit 1130 can receive a fourth input clock ICLK4 through a first input node Nil. The third clock circuit 1130 can receive the third input clock ICLK3 through a second input node Ni2. The third clock circuit 1130 can generate a third output clock OCLK3 and a third inverted output clock OCLK3B based on the third input clock ICLK3 and the fourth input clock ICLK4. The third clock circuit 1130 can output the third output clock OCLK3 through a first output node No1. The third clock circuit 1130 can output the third inverted output clock OCLK3B through a second output node No2.

[0107] A phase of the fourth input clock ICLK4 can be delayed by up to 270 degrees with respect to the phase of the first input clock ICLK1. A phase of the third output clock OCLK3 can be delayed by up to 180 degrees with respect to the phase of the first output clock OCLK1 of the first clock circuit 1110. The third inverted output clock OCLK3B can be a signal whose logic state is opposite to a logic state of the third output clock OCLK3.

[0108] The fourth clock circuit 1140 can receive the first input clock ICLK1 through a first input node Ni1. The fourth clock circuit 1140 can receive the fourth input clock ICLK4 through a second input node Ni2. The fourth clock circuit 1140 can generate a fourth output clock OCLK4 and a fourth inverted output clock OCLK4B based on the fourth input clock ICLK4 and the first input clock ICLK1. The fourth clock circuit 1140 can output the fourth output clock OCLK4 through a first output node No1. The fourth clock circuit 1140 can output the fourth inverted output clock OCLK4B through a second output node No2.

[0109] The phase of the fourth input clock ICLK4 can be delayed from the phase of the first input clock ICLK1 by up to 270 degrees. The phase of the fourth output clock OCLK4 can be delayed from the phase of the first output clock OCLK1 of the first clock circuit 1110 by up to 270 degrees. The fourth inverted output clock OCLK4B can be a signal whose logic state is opposite to that of the fourth output clock OCLK4.

[0110] In an example embodiment, in the clock conversion circuit 1100, nodes for receiving the same input clock can be implemented with one node. For example, the first input node Ni1 of the first clock circuit 1110 can be the second input node Ni2 of the second clock circuit 1120. The first input node Ni1 of the second clock circuit 1120 can be the second input node Ni2 of the third clock circuit 1130. The first input node Ni1 of the third clock circuit 1130 can be the second input node Ni2 of the fourth clock circuit 1140. The first input node Ni1 of the fourth clock circuit 1140 can be the second input node Ni2 of the first clock circuit 1110.

[0111] As described above, according to an embodiment of the disclosure, the clock conversion circuit 1100 is provided, which generates output clocks based on the same type of edges and includes the first clock circuit 1110 to the fourth clock circuit 1140 each having a symmetric structure. In Figures 5A to 5C The clock conversion circuit 1100 operating based on rising edges is disclosed in the above. However, the same type of edges (e.g., rising edges) described above are not limited thereto. For example, a clock conversion circuit 2100 operating based on falling edges will be described with reference to Figures 12A to 12C

[0112] Figure 6 is a block diagram illustrating in detail the clock conversion circuit 1200 according to an embodiment of the disclosure. Reference is made to Figure 6 ​The clock conversion circuit 1200 can include first to fourth clock circuits 1210 to 1240. Each of the first to fourth clock circuits 1210 to 1240 can include switches SW1, / SW2, SW3, and / SW4 and inverters INV1 and INV2.

[0113] The switches SW1, / SW2, and SW3 and the inverters INV1 and INV2 of each of the first to fourth clock circuits 1210 to 1240 are similar to those of each of the first to fourth clock circuits 1110 to 1140 of FIG. 11, and thus, additional description will be omitted to avoid redundancy. Figure 5C

[0114] Figure 5C Unlike the first to fourth clock circuits 1110 to 1140 of FIG. 11, each of the first to fourth clock circuits 1210 to 1240 can further include a fourth switch / SW4 connected between the first node N1 and a power supply node. The power supply node can be a node to which a power supply voltage Vdd is supplied. The power supply voltage Vdd can be a voltage corresponding to a first logic state (e.g., a logic high level). The fourth switch / SW4 can be used to stably maintain a voltage of the first node N1. The fourth switch / SW4 can operate in response to a second logic state of an input clock applied to the second input node Ni2.

[0115] In an example embodiment, the fourth switch / SW4 of the first clock circuit 1210 can be connected between the first node N1 and the power supply node and can operate in response to the second logic state of the first input clock ICLK1 on the second input node Ni2.

[0116] For example, the fourth switch / SW4 can be turned on in a time interval in which the first input clock ICLK1 has the second logic state (e.g., a logic low level) and can be turned off in a time interval in which the first input clock ICLK1 has the first logic state (e.g., a logic high level), but the present disclosure is not limited thereto.

[0117] As described above, according to an embodiment of the present disclosure, in a time interval in which the first input clock ICLK1 has the second logic state, the fourth switch / SW4 can supply the power supply voltage Vdd to the first node N1, and thus, a voltage of the first node N1 can be stably maintained in a specific time interval (e.g., Tp3 and Tp4 of FIG. 12). Figure 5B

[0118] Figure 7 is a block diagram illustrating in detail a clock conversion circuit 1300 according to an embodiment of the present disclosure. Reference is made to FIG. 11 for the description of the clock conversion circuit 1300. Figure 7 ​​​The clock conversion circuit 1300 can include first to fourth clock circuits 1310 to 1340. The structures of the second to fourth clock circuits 1320 to 1340 can be similar to that of the first clock circuit 1310. For simplicity of explanation, detailed structures of the second to fourth clock circuits 1320 to 1340 will be omitted.

[0119] The first clock circuit 1310 can differ from the first clock circuit 1110 of FIG. 11 in that the first, second, and third switches SW1, SW2, and SW3 are implemented with transistors, and the first clock circuit 1310 further operates based on third and fourth input clocks ICLK3 and ICLK4. The phase of the third input clock ICLK3 can be delayed by up to 180 degrees with respect to the phase of the first input clock ICLK1. The phase of the fourth input clock ICLK4 can be delayed by up to 270 degrees with respect to the phase of the first input clock ICLK1. Figure 5A The first clock circuit 1310 can include a first switch SW1, a second switch SW2, a third switch SW3, a first inverter INV1, and a second inverter INV2. The inverters INV1 and INV2 are similar to the inverters INV1 and INV2 of the first clock circuit 1110 of FIG. 11, and thus additional description will be omitted to avoid redundancy.

[0120] Figure 5A The first switch SW1 can be implemented with a transmission gate connected between the first input node Ni1 and the first node N1 and configured to operate based on the first input clock ICLK1 and the third input clock ICLK3, in an example embodiment. The transmission gate can be a switching element including an NMOS transistor and a PMOS transistor connected in parallel for the purpose of controlling connection between an input node and an output node.

[0121] For example, the first switch SW1 can include a first NMOS transistor connected between the first input node Ni1 and the first node N1 and configured to operate in response to the first input clock ICLK1. The first switch SW1 can further include a first PMOS transistor connected between the first input node Ni1 and the first node N1 and configured to operate in response to the third input clock ICLK3. By including the first NMOS transistor and the first PMOS transistor connected in parallel, strength of the first switch SW1 can be enhanced.

[0122] The second switch SW2 can be implemented with a transmission gate connected between the second input node Ni2 and the second node N2 and configured to operate based on the second input clock ICLK2 and the fourth input clock ICLK4, in an example embodiment.

[0123] The second switch SW2 can be implemented with a transmission gate connected between the second input node Ni2 and the second node N2 and configured to operate based on the second input clock ICLK2 and the fourth input clock ICLK4, in an example embodiment. ​

[0124] For example, the second switch SW2 can include a second NMOS transistor connected between the second input node Ni2 and the second node N2 and configured to operate in response to the fourth input clock ICLK4. The second switch SW2 can further include a second PMOS transistor connected between the second input node Ni2 and the second node N2 and configured to operate in response to the second input clock ICLK2. By including the second NMOS transistor and the second PMOS transistor connected in parallel, strength of the second switch SW2 can be enhanced.

[0125] In an example embodiment, the third switch SW3 can include a third NMOS transistor connected between the second node N2 and a ground node and configured to operate in response to the second input clock ICLK2. The ground node can be a node to which a ground GND is supplied.

[0126] As described above, according to an embodiment of the disclosure, a clock conversion circuit 1300 including first and second switches SW1 and SW2 whose strengths are enhanced can be provided.

[0127] Figure 8 is a block diagram illustrating in detail a clock conversion circuit 1400 according to an embodiment of the disclosure. Referring to Figure 8 , the clock conversion circuit 1400 can include first to fourth clock circuits 1410 to 1440. Structures of the second to fourth clock circuits 1420 to 1440 can be similar to that of the first clock circuit 1410. For simplicity of explanation, detailed structures of the second to fourth clock circuits 1420 to 1440 will be omitted.

[0128] The first clock circuit 1410 can include first to fourth switches SW1 to SW4, a first inverter INV1, and a second inverter INV2. The switches SW1 to SW4 and the inverters INV1 and INV2 are similar to those of Figure 7 , and thus additional description will be omitted to avoid redundancy.

[0129] In an example embodiment, the fourth switch SW4 can include a third PMOS transistor connected between the first node N1 and a power supply node and configured to operate in response to the first input clock ICLK1. The power supply node can be a node to which a power supply voltage Vdd is supplied. A voltage of the first node N1 can be stably maintained by the third PMOS transistor of the fourth switch SW4.

[0130] Figure 9This is a block diagram showing in detail a clock conversion circuit 1500 including latch inverters LINV1 and LINV2 according to embodiments of the present disclosure. (See reference...) Figure 9 The clock conversion circuit 1500 may include first to fourth clock circuits 1510 to 1540. The structure of the second to fourth clock circuits 1520 to 1540 may be similar to that of the first clock circuit 1510. For the sake of simplicity, the detailed structure of the second to fourth clock circuits 1520 to 1540 will be omitted.

[0131] The first clock circuit 1510 may include switches SW1, / SW2, and SW3, inverters INV1 and INV2, and latched inverters LINV1 and LINV2. Switches SW1, / SW2, and SW3, and inverters INV1 and INV2 are similar to... Figure 5A The switches SW1, SW2, and SW3, as well as the inverters INV1 and INV2, are described in detail here; therefore, additional descriptions will be omitted to avoid repetition.

[0132] The first latch inverter LINV1 can be connected between the first node N1 and the second node N2. The first latch inverter LINV1 can invert the voltage of the first node N1 and output the inverted voltage to the second node N2. The voltage of the second node N2 can be stably maintained by the first latch inverter LINV1.

[0133] The second latch inverter LINV2 can be connected between the first node N1 and the second node N2. LINV2 inverts the voltage at the second node N2 and outputs the inverted voltage to the first node N1. The voltage at the first node N1 can be stably maintained by LINV2.

[0134] Figure 10 This is a block diagram showing in detail a clock conversion circuit 1600 including buffers BF1 and BF2 according to an embodiment of the present disclosure. Reference Figure 10 The clock conversion circuit 1600 may include first to fourth clock circuits 1610 to 1640. The structure of the second to fourth clock circuits 1620 to 1640 may be similar to that of the first clock circuit 1610. For the sake of simplicity, the detailed structure of the second to fourth clock circuits 1620 to 1640 will be omitted.

[0135] The first clock circuit 1610 may include switches SW1, / SW2, and SW3, N first buffers BF1, and M second buffers BF2. Here, "N" and "M" are natural numbers. Switches SW1, / SW2, and SW3 are similar to... Figure 5A The switches SW1, / SW2, and SW3 are used; therefore, additional descriptions will be omitted to avoid repetition.

[0136] The first clock circuit 1610 can include N first buffers BF1 between the first node N1 and the first output node No1. The first buffers BF1 can be modules or circuits that transfer a voltage of an input terminal to an output terminal. Unlike the first inverters INV1, Figure 9 The first buffers BF1 can be modules or circuits that transfer a voltage without inverting the logic state (e.g., not inverting) the logic state.

[0137] The first clock circuit 1610 can include M second buffers BF2 between the second node N2 and the second output node No2. The second buffers BF2 can be modules or circuits that transfer a voltage of an input terminal to an output terminal without inverting the logic state.

[0138] In an example embodiment, unlike the first clock circuit 1110 of Figure 5A The first clock circuit 1610 can generate a first inverted output clock OCLK1B at the first output node No1 and can generate the first output clock OCLK1 at the second output node No2. For example, since the N first buffers BF1 transfer the voltage of the first node N1 without inverting, the first inverted output clock OCLK1B can be generated at the first output node No1. Also, since the M second buffers BF2 transfer the voltage of the second node N2 without inverting, the first output clock OCLK1 can be generated at the second output node No2.

[0139] In an example embodiment, a buffer can be implemented with two inverters connected in series. For example, one of the N first buffers BF1 can be implemented with two first inverters INV1 connected in series. One of the M second buffers BF2 can be implemented with two second inverters INV2 connected in series.

[0140] In an example embodiment, "N" and "M" can be equal. Since the number of the first buffers BF1 connected between the first node N1 and the first output node No1 is equal to the number of the second buffers BF2 connected between the second node N2 and the second output node No2, skew between the first output clock OCLK1 and the first inverted output clock OCLK1B can be suppressed.

[0141] In an example embodiment, even though "N" and "M" are different, a first time interval in which N first buffers BF1 transfer a voltage of a first node N1 to a first output node No1 can be equal to a time interval in which M second buffers BF2 transfer a voltage of a second node N2 to a second output node No2. For example, the disclosure is not limited to a case where "N" and "M" are equal, and includes a case where a delay time in which the first output clock OCLK1 is delayed by a corresponding output stage (e.g., an inverter and / or a buffer) is equal to a delay time in which the first inverted output clock OCLK1B is delayed by a corresponding output stage (e.g., an inverter and / or a buffer).

[0142] In an example embodiment, unlike the example shown in FIG. 17, the first clock circuit 1610 can include N first inverters INV1 connected in series between the first node N1 and the first output node No1, instead of N first buffers BF1 connected in series therebetween. Also, the first clock circuit 1610 can include M second inverters INV2 connected in series between the second node N2 and the second output node No2, instead of M second buffers BF2 connected in series therebetween. Figure 10

[0143] In this case, a first time interval corresponding to a delay of the N first inverters INV1 can be equal to a second time interval corresponding to a delay of the M second inverters INV2. For example, when "N" and "M" are equal and "N" is an odd number, the first output clock OCLK1 can be generated at the first output node No1, and the first inverted output clock OCLK1B can be generated at the second output node No2. For example, when "N" and "M" are equal and "N" is an even number, the first inverted output clock OCLK1B can be generated at the first output node No1, and the first output clock OCLK1 can be generated at the second output node No2.

[0144] Figure 11 is a block diagram illustrating in detail a clock conversion circuit 1700 according to an embodiment of the disclosure. Referring to Figure 11 , the clock conversion circuit 1700 can include first to fourth clock circuits 1710 to 1740. The structures of the second to fourth clock circuits 1720 to 1740 can be similar to that of the first clock circuit 1710. For simplicity of explanation, detailed structures of the second to fourth clock circuits 1720 to 1740 will be omitted.

[0145] The first clock circuit 1710 can include switches SW1, / SW2, and SW3. The switches SW1, / SW2, and SW3 are similar to the switches SW1, / SW2, and SW3 of the first clock circuit 1610 of FIG. 16, and thus additional description will be omitted to avoid redundancy. Figure 5A Figure 5A ​​The first clock circuit 1710 can not include the first inverter INV1 and the second inverter INV2, unlike the first clock circuit 1110. For example, in the first clock circuit 1710, the first node N1 can be shorted to the first output node No1, and the second node N2 can be shorted to the second output node No2.

[0146] Since the first inverter INV1 and the second inverter INV2 are omitted, the area of the semiconductor chip including the first clock circuit 1710 can be reduced. In addition, the power consumption of the first clock circuit 1710 can be reduced.

[0147] Figure 12A is a block diagram illustrating a clock conversion circuit 2100 according to an embodiment of the disclosure in detail. Unlike the clock conversion circuit 1100 (refer to Figure 5A ) that operates based on a rising edge, the clock conversion circuit 2100 can operate based on a falling edge. The clock conversion circuit 2100 can include first to fourth clock circuits 2110 to 2140, with reference to Figure 12A . The structure of the second to fourth clock circuits 2120 to 2140 will be described more fully with reference to Figure 12C .

[0148] The first clock circuit 2110 can include a first switch SW1, a second switch SW2, a third switch SW3, a first inverter INV1, and a second inverter INV2. The first inverter INV1 and the second inverter INV2 are similar to the first inverter INV1 and the second inverter INV2 of the first clock circuit 1110, and thus additional description will be omitted to avoid repetition. Figure 5A

[0149] The first clock circuit 2110 can receive the first input clock ICLK1 through a first input node Ni1. The first clock circuit 2110 can receive the second input clock ICLK2 through a second input node Ni2. The first clock circuit 2110 can output the first output clock OCLK1 through a first output node No1. The first clock circuit 2110 can output the first inverted output clock OCLK1B through a second output node No2.

[0150] The first switch SW1 can be connected between the first input node Ni1 and the first node N1. The first switch SW1 can operate in response to a first logic state of the second input clock ICLK2 on the second input node Ni2.

[0151] ​For example, the first switch SW1 can be turned on in a time interval in which the second input clock ICLK2 has a first logic state (e.g., a logic high level), and can be turned off in a time interval in which the second input clock ICLK2 has a second logic state (e.g., a logic low level), but the present disclosure is not limited thereto.

[0152] The second switch / SW2 can be connected between the second input node Ni2 and the second node N2. The second switch / SW2 can operate in response to a second logic state of the first input clock ICLK1 on the first input node Ni1.

[0153] For example, the second switch / SW2 can be turned on in a time interval in which the first input clock ICLK1 has a second logic state (e.g., a logic low level), and can be turned off in a time interval in which the first input clock ICLK1 has a first logic state (e.g., a logic high level), but the present disclosure is not limited thereto.

[0154] The third switch / SW3 can be connected between the first node N1 and a power supply node. The power supply node can be a node to which a power supply voltage Vdd is supplied. The third switch / SW3 can operate in response to a second logic state of the second input clock ICLK2.

[0155] For example, the third switch / SW3 can be turned on in a time interval in which the second input clock ICLK2 has a second logic state (e.g., a logic low level), and can be turned off in a time interval in which the second input clock ICLK2 has a first logic state (e.g., a logic high level), but the present disclosure is not limited thereto.

[0156] As described above, according to an embodiment of the present disclosure, unlike the clock conversion circuit 1100 that operates based on rising edges of the same type Figure 5A , a clock conversion circuit 2100 that generates a first output clock OCLK1 and a first inverted output clock OCLK1B based on falling edges of the same type is provided. Reference will be made to Figure 12B to describe a process in which a first clock circuit 2110 of the clock conversion circuit 2100 generates the first output clock OCLK1 and the first inverted output clock OCLK1B.

[0157] Figure 12B is a graph that illustrates input clocks and output clocks of the clock conversion circuit of Figure 12A . In Figure 12B , a waveform of the first input clock ICLK1, a waveform of the second input clock ICLK2, a waveform of the first output clock OCLK1, and a waveform of the first inverted output clock OCLK1B are illustrated. In Figure 12B , a graph, a horizontal direction represents time, and a vertical direction represents a logic state.

[0158] The first input clock ICLK1 can have a period Tp. The period Tp can include first to fourth time intervals Tp1 to Tp4. The phase of the second input clock ICLK2 can be delayed from the phase of the first input clock ICLK1 by up to 90 degrees. Except for the time intervals of the graph of Figure 5B and 12B The first and second input clocks ICLK1 and ICLK2 can be similar to the first and second input clocks ICLK1 and ICLK2 of Figure 5B except for the time intervals of the graph of

[0159] In an example embodiment, the voltage waveform at the first node N1 can be similar to the voltage waveform of the first inverted output clock OCLK1B. The voltage waveform at the first node N1 can be based on the falling edge of the first input clock ICLK1 and the falling edge of the second input clock ICLK2.

[0160] For example, in the first time interval Tp1, the first switch SW1 can be turned on, the first input clock ICLK1 can have a first logic state, and the third switch / SW3 can be turned off. In this case, the first node N1 can have a voltage corresponding to the first logic state. In the second time interval Tp2, the first switch SW1 can be turned on, the first input clock ICLK1 can have a second logic state, and the third switch / SW3 can be turned off. In this case, the first node N1 can have a voltage corresponding to the second logic state. In the third time interval Tp3 and the fourth time interval Tp4, the first node N1 can have a voltage corresponding to the first logic state because the power supply voltage Vdd is supplied to the first node N1 through the third switch / SW3 turned on by the second input clock ICLK2 having the second logic state.

[0161] In an example embodiment, the first inverter INV1 can generate the first output clock OCLK1 based on the voltage of the first node N1. The first output clock OCLK1 can be delayed from the first input clock ICLK1 by up to a time interval Tx5 due to the first inverter INV1. The time interval Tx5 can be an interval from a time Td1 to a time Td2.

[0162] In an example embodiment, the voltage waveform at the second node N2 can be similar to the voltage waveform of the first output clock OCLK1. The voltage waveform at the second node N2 can be based on the falling edge of the first input clock ICLK1 and the falling edge of the second input clock ICLK2.

[0163] For example, because the second switch / SW2 is turned off in the first time interval Tp1, the second node N2 can maintain the voltage formed before the first time interval Tp1. Because the first input clock ICLK1 is a periodic signal, the voltage of the second node N2 before the first time interval Tp1 can be similar to the voltage of the second node N2 in the fourth time interval Tp4 (e.g., the voltage corresponding to the second logic state). In the second time interval Tp2, the second switch / SW2 can be turned on, and the second input clock ICLK2 can have the first logic state. In this case, the second node N2 can have the voltage corresponding to the first logic state. In the third time interval Tp3, the second switch / SW2 can be turned on, and the second input clock ICLK2 can have the second logic state. In this case, the second node N2 can have the voltage corresponding to the second logic state. Because the second switch / SW2 is turned off in the fourth time interval Tp4, the second node N2 can maintain the voltage corresponding to the second logic state.

[0164] In an example embodiment, the second inverter INV2 can generate the first inverted output clock OCLK1B based on the voltage of the second node N2. Due to the second inverter INV2, the first inverted output clock OCLK1B can be delayed from the first input clock ICLK1 by up to a time interval Tx6. The time interval Tx6 can be an interval from a time Td1 to a time Td2.

[0165] As with the first clock circuit 1110 of Figure 5A the first clock circuit 2110 can be configured in such a way that the number of inverters for the first output clock OCLK1 is equal to the number of inverters for the first inverted output clock OCLK1B, and thus, the time interval Tx6 can be equal to the time interval Tx5. That is, because the first clock circuit 2110 has a symmetric structure, skew between the first output clock OCLK1 and the first inverted output clock OCLK1B can be suppressed at the first clock circuit 2110.

[0166] As described above, according to an embodiment of the disclosure, the first clock circuit 2110 that generates output clocks based on the same type of edge and has a symmetric structure is provided. However, this characteristic is also applied to the second to fourth clock circuits 2120 to 2140 of the clock conversion circuit 2100, not only to the first clock circuit 2110. The characteristics of the second to fourth clock circuits 2120 to 2140 will be described more fully with reference to Figure 12C

[0167] Figure 12C is a block diagram illustrating in detail Figure 12A the first to fourth clock circuits 2110 to 2140. In Figure 12C ​The clock conversion circuit 2100 including the first to fourth clock circuits 2110 to 2140 is shown in FIG. 21. The switches SW1, / SW2, and / SW3 and inverters INV1 and INV2 of the first clock circuit 2110 are similar to those of the first clock circuit 2100 of FIG. 20, and thus additional description will be omitted to avoid repetition. Figure 12A The switches SW1, / SW2, and / SW3 and inverters INV1 and INV2 of the first clock circuit 2110 are similar to those of the first clock circuit 2100 of FIG. 20, and thus additional description will be omitted to avoid repetition.

[0168] Referring to Figure 12C The switches SW1, / SW2, and / SW3 and inverters INV1 and INV2 of each of the second to fourth clock circuits 2120 to 2140 can be similar to those of the first clock circuit 2110. However, the second to fourth clock circuits 2120 to 2140 can differ from the first clock circuit 2110 in terms of the input clocks provided to the input nodes Nil and Ni2 and the output clocks generated at the output nodes No1 and No2.

[0169] The second clock circuit 2120 can receive a second input clock ICLK2 through the first input node Nil. The second clock circuit 2120 can receive a third input clock ICLK3 through the second input node Ni2. The second clock circuit 2120 can generate a second output clock OCLK2 and a second inverted output clock OCLK2B based on the second input clock ICLK2 and the third input clock ICLK3. The second clock circuit 2120 can output the second output clock OCLK2 through the first output node No1. The second clock circuit 2120 can output the second inverted output clock OCLK2B through the second output node No2.

[0170] The third clock circuit 2130 can receive the third input clock ICLK3 through the first input node Nil. The third clock circuit 2130 can receive a fourth input clock ICLK4 through the second input node Ni2. The third clock circuit 2130 can generate a third output clock OCLK3 and a third inverted output clock OCLK3B based on the third input clock ICLK3 and the fourth input clock ICLK4. The third clock circuit 2130 can output the third output clock OCLK3 through the first output node No1. The third clock circuit 2130 can output the third inverted output clock OCLK3B through the second output node No2.

[0171] The fourth clock circuit 2140 can receive a fourth input clock ICLK4 through a first input node Ni1. The fourth clock circuit 2140 can receive a first input clock ICLK1 through a second input node Ni2. The fourth clock circuit 2140 can generate a fourth output clock OCLK4 and a fourth inverted output clock OCLK4B based on the fourth input clock ICLK4 and the first input clock ICLK1. The fourth clock circuit 2140 can output the fourth output clock OCLK4 through a first output node No1. The fourth clock circuit 2140 can output the fourth inverted output clock OCLK4B through a second output node No2.

[0172] In an example embodiment, in the clock conversion circuit 2100, nodes for receiving the same input clock can be implemented with one node. For example, the second input node Ni2 of the first clock circuit 2110 can be the first input node Ni1 of the second clock circuit 2120. The second input node Ni2 of the second clock circuit 2120 can be the first input node Ni1 of the third clock circuit 2130. The second input node Ni2 of the third clock circuit 2130 can be the first input node Ni1 of the fourth clock circuit 2140. The second input node Ni2 of the fourth clock circuit 2140 can be the first input node Ni1 of the first clock circuit 2110.

[0173] As described above, according to an embodiment of the disclosure, an output clock is generated based on the same type of edge, and the clock conversion circuit 2100 including the first to fourth clock circuits 2110 to 2140 each having a symmetric structure is provided. Unlike the clock conversion circuit 1100 (refer to Figure 5C ) operating based on a rising edge, the clock conversion circuit 2100 can operate based on a falling edge.

[0174] Figure 13 is a block diagram illustrating a clock conversion circuit 2200 in detail according to an embodiment of the disclosure. Referring to Figure 13 , the clock conversion circuit 2200 can include first to fourth clock circuits 2210 to 2240. Each of the first to fourth clock circuits 2210 to 2240 can include switches SW1, / SW2, / SW3, and SW4 and inverters INV1 and INV2.

[0175] Referring to Figure 13 , the switches SW1, / SW2, and / SW3 and the inverters INV1 and INV2 of each of the first to fourth clock circuits 2210 to 2240 are similar to the switches SW1, / SW2, and / SW3 and the inverters INV1 and INV2 of each of the first to fourth clock circuits 2110 to 2140 of Figure 12C , and thus additional description will be omitted to avoid redundancy.

[0176] Unlike the first to fourth clock circuits 2110 to 2140 of Figure 12C , each of the first to fourth clock circuits 2210 to 2240 can further include a fourth switch SW4 connected between the second node N2 and a ground node. The ground node can be a node to which a ground GND is supplied. The fourth switch SW4 can be used to stably maintain the voltage of the second node N2. The fourth switch SW4 can operate in response to the first logic state of the input clock applied to the first input node Ni1.

[0177] In an example embodiment, the fourth switch SW4 of the first clock circuit 2210 can be connected between the second node N2 and the ground node, and can operate in response to the first logic state of the first input clock ICLK1 on the first input node Ni1.

[0178] For example, the fourth switch SW4 can be turned on in a time interval in which the first input clock ICLK1 has the first logic state (e.g., a logic high level), and can be turned off in a time interval in which the first input clock ICLK1 has the second logic state (e.g., a logic low level), but the present disclosure is not limited thereto.

[0179] As described above, according to an embodiment of the present disclosure, in a time interval in which the first input clock ICLK1 has the first logic state, the fourth switch SW4 can supply the ground GND to the second node N2, and thus, the voltage of the second node N2 can be stably maintained in a certain time interval (e.g., Tp1 and Tp4 of Figure 12B ).

[0180] Figure 14 is a block diagram illustrating in detail a clock conversion circuit 2300 according to an embodiment of the present disclosure. Referring to Figure 14 , the clock conversion circuit 2300 can include first to fourth clock circuits 2310 to 2340. The structures of the second to fourth clock circuits 2320 to 2340 can be similar to that of the first clock circuit 2310. For simplicity of explanation, the detailed structures of the second to fourth clock circuits 2320 to 2340 will be omitted.

[0181] The first clock circuit 2310 can differ from the first clock circuit 2110 of Figure 12A in that the first, second, and third switches SW1, SW2, and SW3 are implemented with transistors, and the first clock circuit 2310 further operates based on third and fourth input clocks ICLK3 and ICLK4.

[0182] The first clock circuit 2310 can include a first switch SW1, a second switch SW2, a third switch SW3, a first inverter INV1, and a second inverter INV2. The inverters INV1 and INV2 are similar to those of the first clock circuit 2110 of FIG. 21, and thus, additional description will be omitted to avoid redundancy. Figure 12A

[0183] In an example embodiment, the first switch SW1 can be implemented with a transmission gate connected between the first input node Ni1 and the first node N1 and configured to operate based on a second input clock ICLK2 and a fourth input clock ICLK4.

[0184] For example, the first switch SW1 can include a first NMOS transistor connected between the first input node Ni1 and the first node N1 and configured to operate in response to the second input clock ICLK2. The first switch SW1 can further include a first PMOS transistor connected between the first input node Ni1 and the first node N1 and configured to operate in response to the fourth input clock ICLK4. By including the first NMOS transistor and the first PMOS transistor connected in parallel, strength of the first switch SW1 can be enhanced.

[0185] In an example embodiment, the second switch SW2 can be implemented with a transmission gate connected between the second input node Ni2 and the second node N2 and configured to operate based on a first input clock ICLK1 and a third input clock ICLK3.

[0186] For example, the second switch SW2 can include a second NMOS transistor connected between the second input node Ni2 and the second node N2 and configured to operate in response to the third input clock ICLK3. The second switch SW2 can further include a second PMOS transistor connected between the second input node Ni2 and the second node N2 and configured to operate in response to the first input clock ICLK1. By including the second NMOS transistor and the second PMOS transistor connected in parallel, strength of the second switch SW2 can be enhanced.

[0187] In an example embodiment, the third switch SW3 can include a third PMOS transistor connected between the first node N1 and a power supply node and configured to operate in response to the second input clock ICLK2. The power supply node can be a node to which a power supply voltage Vdd is supplied.

[0188] ​As described above, according to embodiments of the disclosure, a clock conversion circuit 2300 including first and second switches SW1 and SW2 whose strengths are enhanced can be provided.

[0189] Figure 15 is a block diagram illustrating in detail a clock conversion circuit 2400 according to embodiments of the disclosure. Referring to Figure 15 , the clock conversion circuit 2400 can include first to fourth clock circuits 2410 to 2440. The structures of the second to fourth clock circuits 2420 to 2440 can be similar to that of the first clock circuit 2410. For simplicity of explanation, detailed structures of the second to fourth clock circuits 2420 to 2440 will be omitted.

[0190] The first clock circuit 2410 can include first and second switches SW1 and SW2, third and fourth switches SW3 and SW4, a first inverter INV1, and a second inverter INV2. The switches SW1 to SW3 and the inverters INV1 and INV2 are similar to those of the clock conversion circuit 2300 of FIG. 23, and thus additional description will be omitted to avoid redundancy. Figure 14

[0191] In an example embodiment, the fourth switch SW4 can include a third NMOS transistor connected between the second node N2 and a ground node and configured to operate in response to the first input clock ICLK1. The ground node can be a node to which a ground GND is supplied. The voltage of the second node N2 can be stably maintained by the third NMOS transistor of the fourth switch SW4.

[0192] Figure 16 is a block diagram illustrating in detail a clock conversion circuit 2500 including latch inverters LINV1 and LINV2 according to embodiments of the disclosure. Referring to Figure 16 , the clock conversion circuit 2500 can include first to fourth clock circuits 2510 to 2540. The structures of the second to fourth clock circuits 2520 to 2540 can be similar to that of the first clock circuit 2510. For simplicity of explanation, detailed structures of the second to fourth clock circuits 2520 to 2540 will be omitted.

[0193] The first clock circuit 2510 can include switches SW1, / SW2, and / SW3, inverters INV1 and INV2, and latch inverters LINV1 and LINV2. The switches SW1, / SW2, and / SW3 and the inverters INV1 and INV2 are similar to those of the clock conversion circuit 2300 of FIG. 23, and thus additional description will be omitted to avoid redundancy. Figure 12A Figure 9 ​​The latch inverters LINV1 and LINV2 of FIG. 1, and thus, additional description will be omitted to avoid redundancy.

[0194] According to embodiments of the disclosure, a clock conversion circuit 2500 can be provided in which the voltage of the second node N2 is stably maintained by the first latch inverter LINV1 and the voltage of the first node N1 is stably maintained by the second latch inverter LINV2.

[0195] Figure 17 is a block diagram illustrating in detail a clock conversion circuit 2600 including buffers BF1 and BF2 according to embodiments of the disclosure. Referring to Figure 17 , the clock conversion circuit 2600 can include first to fourth clock circuits 2610 to 2640. The structures of the second to fourth clock circuits 2620 to 2640 can be similar to that of the first clock circuit 2610. For simplicity of explanation, detailed structures of the second to fourth clock circuits 2620 to 2640 will be omitted.

[0196] The first clock circuit 2610 can include switches SW1, / SW2, and / SW3, N first buffers BF1, and M second buffers BF2. Here, "N" and "M" are natural numbers. The switches SW1, / SW2, and / SW3 are similar to those of Figure 12A , and thus, additional description will be omitted to avoid redundancy. The N first buffers BF1 and the M second buffers BF2 are similar to those of Figure 10 , and thus, additional description will be omitted to avoid redundancy.

[0197] Figure 18 is a block diagram illustrating in detail a clock conversion circuit 2700 according to embodiments of the disclosure. Referring to Figure 18 , the clock conversion circuit 2700 can include first to fourth clock circuits 2710 to 2740. The structures of the second to fourth clock circuits 2720 to 2740 can be similar to that of the first clock circuit 2710. For simplicity of explanation, detailed structures of the second to fourth clock circuits 2720 to 2740 will be omitted.

[0198] The first clock circuit 2710 can include switches SW1, / SW2, and / SW3. The switches SW1, / SW2, and / SW3 are similar to those of Figure 12A , and thus, additional description will be omitted to avoid redundancy. With Figure 12AThe first clock circuit 2710 can not include the first inverter INV1 and the second inverter INV2, unlike the first clock circuit 2110. For example, in the first clock circuit 2710, the first node N1 can be shorted to the first output node No1, and the second node N2 can be shorted to the second output node No2.

[0199] As in the first clock circuit 1710 of FIG. 17, Figure 11 As in the first clock circuit 1710 of FIG. 17, since the first inverter INV1 and the second inverter INV2 are omitted, the area of the semiconductor chip including the first clock circuit 2710 can be reduced. In addition, the power consumption of the first clock circuit 2710 can be reduced.

[0200] Figure 19 is a block diagram illustrating a memory system 10 according to an embodiment of the disclosure. Referring to Figure 19 , the memory system 10 can include a memory controller 11 and a memory device 20. The memory controller 11 can transmit a reference clock RCLK, an address ADDR, and a command CMD to the memory device 20 for the purpose of storing data in the memory device 20 or reading data stored in the memory device 20.

[0201] In an example embodiment, the address ADDR can include a row address RA and a column address CA. The command CMD can include an active command, a write command, a read command, or a precharge command. However, the disclosure is not limited thereto. For example, the address ADDR can include various forms of addresses, and the command CMD can include various forms of commands.

[0202] Under the control of the memory controller 11, the memory device 20 can store data received from the memory controller 11, or can transmit data stored therein to the memory controller 11.

[0203] In an example embodiment, the memory device 20 can be a dynamic random access memory (DRAM), and the memory controller 11 and the memory device 20 can communicate with each other based on a double data rate (DDR) interface. However, the present disclosure is not limited thereto. For example, the memory device 20 can be one of various memory devices such as a static random access memory (SRAM), a synchronous DRAM (SDRAM), a magnetic RAM (MRAM), a ferroelectric RAM (FRAM), a resistive RAM (ReRAM), and a phase change RAM (PRAM), and the memory controller 11 and the memory device 20 can communicate with each other based on one of various interfaces such as a low power DDR (LPDDR), a universal serial bus (USB), a modular multi-level converter (MMC), a peripheral component interconnect (PCI), a fast PCI (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced standard (small / system) device interface (ESDI), and an integrated drive electronics (IDE).

[0204] The memory device 20 can include a clock conversion circuit. The clock conversion circuit can include a plurality of clock circuits. In an example embodiment, the clock conversion circuit of the memory device 20 can generate first to fourth input clocks ICLK1 to ICLK4 having different phases based on a reference clock RCLK. The clock conversion circuit can generate first to fourth output clocks OCLK1 to OCLK4 and first to fourth inverted output clocks OCLK1B to OCLK4B based on the first to fourth input clocks ICLK1 to ICLK4. The first to fourth output clocks OCLK1 to OCLK4 can be clock signals having a duty cycle smaller than a duty cycle of the first to fourth input clocks ICLK1 to ICLK4. In an example embodiment, the clock conversion circuit of the memory device 20 can be one of the clock conversion circuits 1100, 1200, 1300, 1400, 1500, 1600, 1700, 2100, 2200, 2300, 2400, 2500, 2600, and 2700 described above with reference to FIGS. 11 to 18. Figure 5A 、 6 , 7, 8, 9, 10, 11, 12A, 13, 14, 15, 16, 17, and 18.

[0205] Figure 20 is a block diagram of the memory device 20 in detail according to an example embodiment of Figure 19 . Referring to Figure 19 and 20The memory device 20 may include a clock generator 21, a memory cell array 22, a command decoder 23, control logic circuitry 24, a sense amplifier and a write driver 25, and input / output (I / O) circuitry 26.

[0206] Clock generator 21 may include an input clock generator ICG and a clock conversion circuit. The input clock generator ICG may generate first to fourth input clocks ICLK1 to ICLK4 based on a reference clock RCLK. The clock conversion circuit may include multiple clock circuits. For example, the clock conversion circuit may include first to fourth clock circuits. The multiple clock circuits of the clock conversion circuit may generate first to fourth output clocks OCLK1 to OCLK4 and first to fourth inverted output clocks OCLK1B to OCLK4B based on the first to fourth input clocks ICLK1 to ICLK4.

[0207] The memory cell array 22 may include multiple memory cells. These memory cells can be connected to word lines and bit lines. The word lines can be connected to the X decoder (X-DEC), and the bit lines can be connected to the Y decoder (Y-DEC).

[0208] The control logic circuit 24 can control the components of the memory device 20 based on the decoding result from the command decoder 23. For example, if the decoding result of the command decoder 23 indicates that the received command CMD is a valid command, the control logic circuit 24 can control the X decoder X-DEC to enable the word line corresponding to the row address RA received along with the valid command. In this case, the first to fourth data D1 to D4 stored in the memory cell connected to the enabled word line can be set to the sense amplifier and write driver 25. If the decoding result of the command decoder 23 indicates that the received command CMD is a read command, the control logic circuit 24 can allow the sense amplifier and write driver 25 to sense the first to fourth data D1 to D4 from the bit line corresponding to the column address CA received along with the read command.

[0209] Input / output circuitry 26 may include a multiplexer MUX and a driver DRV. Input / output circuitry 26 can generate data signals based on first to fourth data D1 to D4, first to fourth output clocks OCLK1 to OCLK4, and first to fourth inverted output clocks OCLK1B to OCLK4B. (Refer to...) Figure 21 and 22 Describe the structure and characteristics of the input / output circuit 26.

[0210] Figure 21 It is shown in detail according to the example embodiment. Figure 20 The circuit diagram for the input / output (I / O) circuit 26 is shown below. (Refer to...) Figure 21The input / output circuit 26 can include a multiplexer MUX and a driver DRV. The multiplexer MUX can include a first MUX NMOS transistor and a first MUX PMOS transistor connected in parallel between a node for receiving first data D1 and the driver DRV. The first MUX NMOS transistor can operate in response to a first output clock OCLK1. The first MUX PMOS transistor can operate in response to a first inverted output clock OCLK1B.

[0211] The multiplexer MUX can further include a second MUX NMOS transistor and a second MUX PMOS transistor connected in parallel between a node for receiving second data D2 and the driver DRV. The second MUX NMOS transistor can operate in response to a second output clock OCLK2. The second MUX PMOS transistor can operate in response to a second inverted output clock OCLK2B.

[0212] The multiplexer MUX can further include a third MUX NMOS transistor and a third MUX PMOS transistor connected in parallel between a node for receiving third data D3 and the driver DRV. The third MUX NMOS transistor can operate in response to a third output clock OCLK3. The third MUX PMOS transistor can operate in response to a third inverted output clock OCLK3B.

[0213] The multiplexer MUX can further include a fourth MUX NMOS transistor and a fourth MUX PMOS transistor connected in parallel between a node for receiving fourth data D4 and the driver DRV. The fourth MUX NMOS transistor can operate in response to a fourth output clock OCLK4. The fourth MUX PMOS transistor can operate in response to a fourth inverted output clock OCLK4B.

[0214] The driver DRV can be connected between the multiplexer MUX and a DQ pad. The DQ pad can be a pad at which a data signal is generated. The driver DRV can generate a data signal at the DQ pad based on the first to fourth data D1 to D4 provided from the multiplexer MUX for a corresponding time interval.

[0215] Figure 22 is a graph showing a data signal generated at a DQ pad of a memory device according to an example embodiment. In Figure 21 the graph, the horizontal direction represents time, and the vertical direction represents a logic state or data. Figure 22 In the graph, the horizontal direction represents time, and the vertical direction represents a logic state or data. Figure 22 ​

[0216] The first input clock ICLK1 can have a period Tp and a duty cycle Dy1. The first output clock OCLK1 can have the period Tp and a duty cycle Dy2. The duty cycle Dy2 can be less than the duty cycle Dy1. For example, the duty cycle Dy1 can be 50%, and the duty cycle Dy2 can be 25%. The second to fourth output clocks OCLK2 to OCLK4 can be signals that are delayed by up to 90 degrees, 180 degrees, and 270 degrees, respectively, in phase with respect to the first output clock OCLK1.

[0217] In an example embodiment, the input / output circuit 26 can generate a data signal of the DQ pad based on the first to fourth output clocks OCLK1 to OCLK4 and the first to fourth data D1 to D4. For example, the period Tp can include first to fourth time intervals Tp1 to Tp4. The first to fourth time intervals Tp1 to Tp4 can correspond to the first to fourth output clocks OCLK1 to OCLK4, respectively. The input / output circuit 26 can generate a data signal based on the first to fourth output clocks OCLK1 to OCLK4 and the first to fourth data D1 to D4, the data signal including the first data D1 in the first time interval Tp1, including the second data D2 in the second time interval Tp2, including the third data D3 in the third time interval Tp3, and including the fourth data D4 in the fourth time interval Tp4.

[0218] Figure 23 is a block diagram illustrating a memory module 30 according to an embodiment of the disclosure. Referring to Figure 23 , the memory module 30 can include a register clock driver 31, a plurality of DRAMs 32a to 32h, and a plurality of data buffers DB.

[0219] The register clock driver 31 can receive a reference clock RCLK, an address ADDR, and a command CMD from an external device (e.g., a host or a memory controller). The register clock driver 31 can include a clock conversion circuit. The characteristics and structure of the clock conversion circuit are similar to those of the clock conversion circuit of the memory device 20 of Figure 19 , and thus additional description will be omitted to avoid redundancy. For example, the clock conversion circuit of the register clock driver 31 can be the clock conversion circuit described above with reference to Figure 5A , 6, 7, 8, 9, 10, 11, 12A, 13, 14, 15, 16, 17, and 18. Based on the received signals RCLK, ADDR, and CMD, the register clock driver 31 can transfer the address ADDR and the command CMD to the plurality of DRAMs 32a to 32h, and can control the plurality of data buffers DB.

[0220] The plurality of DRAMs 32a to 32h can be connected to the corresponding data buffers DB, respectively. Each of the plurality of DRAMs 32a to 32h can provide data stored therein to the corresponding data buffer DB, or can be provided with data from the corresponding data buffer DB. Each of the plurality of data buffers DB can exchange a data signal with an external device (e.g., a host or a memory controller) through a corresponding DQ pad.

[0221] Figure 24 is a block diagram illustrating an electronic system 40 according to an embodiment of the disclosure. Referring to Figure 24 The electronic system 40 can be implemented in the form of a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, or a wearable device. Alternatively, the electronic system 40 can be implemented in the form of a computing system such as a personal computer, a server, a workstation, or a notebook computer.

[0222] The electronic system 40 can include an application processor 41 (or a central processing unit), a display 42, and an image sensor 43. The application processor 41 can include a DigRF master 41a, a physical layer 41b, a display serial interface (DSI) host 41c, and a camera serial interface (CSI) host 41d.

[0223] The DSI host 41c can communicate with a DSI device 42a of the display 42 through a DSI. In an example embodiment, an optical serializer SER can be implemented in the DSI host 41c. An optical deserializer DES can be implemented in the DSI device 42a.

[0224] The CSI host 41d can communicate with the CSI device 43a of the image sensor 43 through the CSI. In an example embodiment, a deserializer DES can be implemented in the CSI host 41d. A serializer SER can be implemented in the CSI device 43a.

[0225] The electronic system 40 can further include a radio frequency (RF) chip 44 for communication with the application processor 41. The RF chip 44 can include a physical layer 44a, a DigRF slave 44b, and an antenna 44c. In an example embodiment, the physical layer 44a of the RF chip 44 and the physical layer 41b of the application processor 41 can exchange data with each other through a MIPI DigRF interface.

[0226] The electronic system 40 can further include a global positioning system (GPS) device 45 for processing location information. The electronic system 40 can further include a bridge chip 46 for managing connection between peripheral devices. The electronic system 40 can communicate with external systems through a worldwide interoperability for microwave access (WiMAX) 47a, a wireless local area network (WLAN) 47b, and an ultra wideband (UWB) 47c. The electronic system 40 can further include a speaker 48a and a microphone 48b for the purpose of processing voice information. The electronic system 40 can further include an embedded / card storage 48c for storing data of the application processor 41.

[0227] The electronic system 40 can further include a clock conversion circuit 49 that generates a clock signal to be used for data processing of the application processor 41. The clock conversion circuit 49 can be similar to the clock conversion circuit of the memory device 20 described above with reference to Figure 19 In an example embodiment, the clock conversion circuit 49 can be one of the clock conversion circuits 1100, 1200, 1300, 1400, 1500, 1600, 1700, 2100, 2200, 2300, 2400, 2500, 2600, and 2700 described above with reference to Figure 5A , 6 , 7, 8, 9, 10, 11, 12A, 13, 14, 15, 16, 17, and 18.

[0228] According to the present disclosure, a clock conversion circuit that is robust against skew and duty cycle error is provided by matching the edge type of the input clock for duty cycle conversion and designing an output stage with a symmetric structure.

[0229] Further, a clock conversion circuit that is robust against external noise is provided by adding a latch inverter. In addition, a clock conversion circuit that is reduced in power consumption and chip area is provided by removing unnecessary inverters.

[0230] While the present disclosure has been described with reference to example embodiments thereof, it will be evident that various modifications in form and details can be made therein without departing from the spirit and scope of the disclosure, which is set forth in the appended claims.

Claims

1. A clock conversion circuit, comprising: A first switch is directly connected between the first input node and the first node and is configured to operate in response to a first logic state of the first input clock. The first input node directly receives a second input clock, which is delayed by up to 90 degrees relative to the first input clock. The second switch is directly connected between the second input node and the second node and is configured to operate in response to a second logic state of the second input clock. The second input node directly receives the first input clock. and A third switch is connected between the second node and the ground node and is configured to operate in response to a first logic state that is opposite to the second logic state of the second input clock.

2. The clock conversion circuit according to claim 1 further includes: A fourth switch is connected between the first node and the power node and is configured to operate in response to a second logic state that is opposite to the first logic state of the first input clock.

3. The clock conversion circuit according to claim 1 further includes: A fourth switch is connected between a third input node and a third node for receiving a third input clock that is delayed by up to 180 degrees relative to the first input clock, and is configured to operate in response to the first logic state of the second input clock. A fifth switch is connected between the first input node and the fourth node and is configured to operate in response to a second logic state of the third input clock. A sixth switch is connected between the fourth node and the ground node and is configured to operate in response to a first logic state that is opposite to the second logic state of the third input clock. A seventh switch is connected between a fourth input node and a fifth node for receiving a fourth input clock that is delayed by up to 270 degrees relative to the first input clock, and is configured to operate in response to the first logic state of the third input clock. An eighth switch is connected between the third input node and the sixth node and is configured to operate in response to a second logic state of the fourth input clock. A ninth switch, connected between the sixth node and the ground node, is configured to operate in response to a first logic state that is opposite to the second logic state of the fourth input clock. A tenth switch, which is connected between the second input node and the seventh node, and is configured to operate in response to the first logic state of the fourth input clock; The eleventh switch is connected between the fourth input node and the eighth node and is configured to operate in response to a second logic state that is opposite to the first logic state of the first input clock. and A twelfth switch is connected between the eighth node and the ground node and is configured to operate in response to the first logic state of the first input clock.

4. The clock conversion circuit according to claim 3 further includes: The thirteenth switch is connected between the first node and the power node and is configured to operate in response to the second logic state of the first input clock. The fourteenth switch is connected between the third node and the power node and is configured to operate in response to the second logic state of the second input clock. The fifteenth switch is connected between the fifth node and the power node and is configured to operate in response to the second logic state of the third input clock. and The sixteenth switch is connected between the seventh node and the power node and is configured to operate in response to the second logic state of the fourth input clock.

5. The clock conversion circuit according to claim 1, wherein, The first switch includes a first transmission gate configured to operate in response to a first input clock and a third input clock. The second switch includes a second transmission gate configured to operate in response to a second input clock and a fourth input clock. The third input clock is delayed by 180 degrees relative to the first input clock, and The fourth input clock is delayed by 270 degrees relative to the first input clock.

6. The clock conversion circuit according to claim 5, wherein, The first transmission gate includes: A first NMOS transistor, connected between the first input node and the first node, is configured to operate in response to the first input clock; and A first PMOS transistor, connected between the first input node and the first node, is configured to operate in response to the third input clock. The second transmission gate includes: A second NMOS transistor, connected between the second input node and the second node, is configured to operate in response to the fourth input clock; and The second PMOS transistor is connected between the second input node and the second node and is configured to operate in response to the second input clock.

7. The clock conversion circuit according to claim 6 further includes: A fourth switch, connected between the first node and the power node, is configured to operate in response to a second logic state that is opposite to the first logic state of the first input clock. The third switch includes: A third NMOS transistor, connected between the second node and the ground node, is configured to operate in response to the second input clock. The fourth switch includes: A third PMOS transistor is connected between the first node and the power node and is configured to operate in response to the first input clock.

8. The clock conversion circuit according to claim 1, further comprising: A first inverter, configured to invert the voltage of the first node and output a first output clock; and The second inverter is configured to invert the voltage of the second node and output a first inverted output clock that is opposite to the first output clock.

9. The clock conversion circuit according to claim 1, further comprising: A first latch inverter is configured to invert the voltage of the first node and output the inverted voltage of the first node to the second node; and A second latch inverter is configured to invert the voltage of the second node and output the inverted voltage of the second node to the first node.

10. The clock conversion circuit according to claim 1, further comprising: N first buffers are connected in series between the first node and the first output node that generates the first inverted output clock. and M second buffers are connected in series between the second node and the second output node that generates a first output clock that is opposite to the first inverted output clock. Where "N" and "M" are natural numbers.

11. The clock conversion circuit according to claim 10, wherein, "N" is equal to "M".

12. The clock conversion circuit according to claim 10, wherein, The first time interval taken by the N first buffers to transmit the voltage of the first node to the first output node is equal to the second time interval taken by the M second buffers to transmit the voltage of the second node to the second output node.

13. A clock conversion circuit, comprising: The first to fourth clock circuits are configured to generate an output four-phase clock including the first to fourth output clocks based on an input four-phase clock including the first to fourth input clocks. The first clock circuit includes: A first switch is connected between a first input node for receiving the second input clock and a first node, and the first switch is configured to output a first pre-output clock on the first node in response to a first logic state of the first input clock. A second switch, connected between a second input node for receiving the first input clock and a second node, is configured to output a second pre-output clock on the second node in response to a second logic state of the second input clock; and A third switch, connected between the second node and the ground node, is configured to operate in response to a first logic state that is opposite to the second logic state of the second input clock. Wherein, each of the first pre-output clock and the second pre-output clock is a periodic signal, and The logic state of the first pre-output clock is opposite to that of the logic state of the second pre-output clock in one cycle.

14. The clock conversion circuit according to claim 13, wherein, The first clock circuit is configured to generate the first output clock and a first inverted output clock that is opposite to the first output clock based on the first input clock and the second input clock. The second clock circuit is configured to generate the second output clock and a second inverted output clock that is opposite to the second output clock based on the second input clock and the third input clock. The third clock circuit is configured to generate the third output clock and a third inverted output clock that is opposite to the third output clock based on the third input clock and the fourth input clock. The fourth clock circuit is configured to generate the fourth output clock and a fourth inverted output clock that is opposite to the fourth output clock based on the fourth input clock and the first input clock.

15. The clock conversion circuit according to claim 13, wherein, The second input clock is delayed by 90 degrees relative to the first input clock. The third input clock is delayed by 180 degrees relative to the first input clock, and The fourth input clock is delayed by 270 degrees relative to the first input clock.

16. A clock conversion circuit, comprising: A first switch, directly connected between the first input node and the first node, is used to directly receive the first input clock at the first input node and is configured to operate in response to a first logic state of a second input clock that is delayed by up to 90 degrees relative to the first input clock. The second switch is directly connected between the second input node and the second node, and is used to directly receive the second input clock at the second input node, and is configured to operate in response to a second logic state of the first input clock; and A third switch, connected between the first node and the power node, is configured to operate in response to a second logic state that is opposite to the first logic state of the second input clock. The power node is subjected to a voltage higher than the ground voltage.

17. The clock conversion circuit according to claim 16, further comprising: A fourth switch, connected between the second node and the ground node, is configured to operate in response to a first logic state that is opposite to the second logic state of the first input clock. The grounding node is subjected to the grounding voltage.

18. The clock conversion circuit according to claim 16, further comprising: A fourth switch is connected between the second input node and the third node and is configured to operate in response to a first logic state of a third input clock that is delayed by up to 180 degrees relative to the first input clock. The fifth switch is connected between the third input node for receiving the third input clock and the fourth node, and is configured to operate in response to the second logic state of the second input clock; A sixth switch is connected between the third node and the power node and is configured to operate in response to a second logic state that is opposite to the first logic state of the third input clock. A seventh switch is connected between the third input node and the fifth node and is configured to operate in response to a first logic state of a fourth input clock that is delayed by up to 270 degrees relative to the first input clock. An eighth switch is connected between a fourth input node for receiving the fourth input clock and a sixth node, and is configured to operate in response to the second logic state of the third input clock. A ninth switch is connected between the fifth node and the power node and is configured to operate in response to a second logic state that is opposite to the first logic state of the fourth input clock. A tenth switch is connected between the fourth input node and the seventh node and is configured to operate in response to a first logic state that is opposite to the second logic state of the first input clock. The eleventh switch is connected between the first input node and the eighth node and is configured to operate in response to the second logic state of the fourth input clock. and A twelfth switch is connected between the seventh node and the power node and is configured to operate in response to the second logic state of the first input clock.

19. The clock conversion circuit according to claim 18, further comprising: The thirteenth switch is connected between the second node and the ground node and is configured to operate in response to the first logic state of the first input clock. The fourteenth switch is connected between the fourth node and the ground node and is configured to operate in response to the first logic state of the second input clock. The fifteenth switch is connected between the sixth node and the ground node and is configured to operate in response to the first logic state of the third input clock. and A sixteenth switch, connected between the eighth node and the ground node, is configured to operate in response to the first logic state of the fourth input clock. The grounding node is subjected to the grounding voltage.

20. The clock conversion circuit according to claim 16, wherein, The first switch includes a first transmission gate configured to operate in response to a second input clock and a fourth input clock. The second switch includes a second transmission gate configured to operate in response to the first input clock and the third input clock. The third input clock is delayed by 180 degrees relative to the first input clock, and The fourth input clock is delayed by 270 degrees relative to the first input clock.

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