A capacitor structure and a method for preparing the same

Abstract

The present invention relates to the field of semiconductor manufacturing, and discloses a capacitor structure and a preparation method thereof. A preparation method of a capacitor structure comprises: depositing a first supporting layer, a first sacrificial layer, and a second supporting layer on a substrate in sequence; forming a heterogeneous region in the second supporting layer; depositing a second sacrificial layer and a third supporting layer on the second supporting layer in sequence; etching in sequence from the third supporting layer to the substrate to form a capacitor hole through an etching process, and the capacitor hole penetrates the heterogeneous region, wherein the etching selectivity ratio of the material in the heterogeneous region to the material in the second supporting layer is greater than 1; and forming a lower electrode layer on the inner surface of the capacitor hole. In the process of etching in sequence from the third supporting layer to the substrate, if the etching direction is deflected to a certain extent, due to the existence of the heterogeneous region, the heterogeneous region will be etched preferentially, that is, the etching starting point of the lower half is corrected by the heterogeneous region, and the etching direction can be corrected to a certain extent, thereby avoiding the problem of adjacent capacitor holes being interconnected due to the excessive deflection of the capacitor holes in the lower half.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a capacitor structure and a preparation method thereof. Background Art

[0002] As the feature size of dynamic random access memory (DRAM) continues to shrink, the capacitance of capacitors is also decreasing. Improving capacitance by making capacitors with high aspect ratio structures and forming double-side dielectric materials is an effective way to increase capacitance. In the application of high aspect ratio structures, it is usually necessary to prepare a sacrificial layer to etch high aspect ratio holes. In the process of etching capacitor holes, the capacitor holes may be distorted, resulting in the interconnection of the lower electrodes between multiple capacitor holes after the subsequent deposition of the lower electrode.

[0003] Therefore, there is an urgent need to provide a new capacitor structure and a method for forming the same to solve the above problems existing in the prior art. Summary of the invention

[0004] According to some embodiments, a first aspect of the present application provides a method for preparing a capacitor structure, comprising:

[0005] Depositing a first supporting layer, a first sacrificial layer, and a second supporting layer in sequence on the substrate;

[0006] forming a heterogeneous region in the second supporting layer;

[0007] sequentially depositing a second sacrificial layer and a third supporting layer on the second supporting layer;

[0008] By means of an etching process, sequentially etching along the third supporting layer toward the substrate to form capacitor holes, and the capacitor holes penetrate the heterogeneous region, wherein the etching selectivity ratio of the material of the heterogeneous region to the material of the second supporting layer is greater than 1;

[0009] A lower electrode layer is formed on the inner surface of the capacitor hole.

[0010] The embodiments of the present application have at least the following advantages:

[0011] After depositing the first supporting layer and the first sacrificial layer on the substrate in sequence, the second supporting layer is deposited on the first sacrificial layer, and a heterogeneous region is formed on the second supporting layer. The second sacrificial layer and the third supporting layer are deposited in sequence on the second supporting layer to form a basic structure of the capacitor; when etching a capacitor hole on the structure, etching is performed in sequence along the third supporting layer toward the substrate through an etching process. Since the etching selectivity ratio of the material of the heterogeneous region to the material of the second supporting layer is greater than 1, after etching the second sacrificial layer, the heterogeneous region will be etched preferentially compared with other regions of the second supporting layer. Then, the first sacrificial layer, the first supporting layer and the substrate are etched in sequence to form a complete capacitor hole, and finally a lower electrode layer is formed on the inner surface of the capacitor hole. In the process of etching from the third supporting layer to the substrate in sequence, if the etching direction is deviated to a certain extent, that is, the angle between the etching direction and the normal of the substrate exceeds the preset range, due to the existence of the heterogeneous region of the second supporting layer, the heterogeneous region will be etched preferentially, that is, the etching starting point of the lower half is corrected by the heterogeneous region, which can correct the etching direction to a certain extent, thereby avoiding the problem of adjacent capacitor holes being interconnected due to the excessive deflection of the capacitor holes in the lower half, and then causing the lower electrodes in different capacitor holes to be interconnected.

[0012] In some embodiments, forming a heterogeneous region on the second supporting layer comprises:

[0013] By means of an etching process, etching the second supporting layer to form a via hole;

[0014] The via hole is filled with a heterogeneous material to form the heterogeneous region.

[0015] In some embodiments, a cross-sectional area of ​​the via hole is greater than a cross-sectional area of ​​the capacitor hole.

[0016] In some embodiments, after the dielectric material is filled in the via hole to form the heterogeneous region, the method further includes:

[0017] The heterogeneous region is polished chemically and mechanically so that a surface of the heterogeneous region facing away from the substrate and a surface of the second supporting layer facing away from the substrate are located in the same plane.

[0018] In some embodiments, the foreign material includes hafnium oxide or aluminum oxide or tantalum oxide.

[0019] In some embodiments, the via hole is a circular hole or an elliptical hole.

[0020] In some embodiments, the via hole is a polygonal hole.

[0021] In some embodiments, the via hole is a special-shaped hole.

[0022] In some embodiments, the lower electrode layer is embedded in a groove formed by the second sacrificial layer, the second supporting layer, and the first sacrificial layer at the via hole.

[0023] In some embodiments, forming a heterogeneous region on the second supporting layer comprises:

[0024] Through an etching process, the second supporting layer is etched on a side facing away from the substrate so that the surface is recessed to form the heterogeneous region.

[0025] According to some embodiments, a second aspect of the present application provides a capacitor structure, including:

[0026] substrate;

[0027] a first supporting layer formed on the substrate;

[0028] a first sacrificial layer formed on a side of the first supporting layer facing away from the substrate;

[0029] a second supporting layer formed on a side of the first sacrificial layer away from the first supporting layer;

[0030] a second sacrificial layer formed on a side of the second supporting layer away from the first sacrificial layer;

[0031] a third supporting layer formed on a side of the second sacrificial layer away from the second supporting layer;

[0032] A capacitor hole, wherein the capacitor hole sequentially penetrates the third supporting layer, the second sacrificial layer, the second supporting layer, the first sacrificial layer, the first supporting layer and the substrate, and a limiting groove is formed on a side wall of the capacitor hole;

[0033] A lower electrode layer is formed on the side wall of the capacitor hole, and a limiting protrusion is provided on the lower electrode layer to cooperate with the limiting groove, and the limiting protrusion extends in a direction away from the axis of the capacitor hole.

[0034] In some embodiments, the limiting groove is formed at a portion of the capacitor hole that passes through the second supporting layer.

[0035] In some embodiments, the outer contour of the cross section of the limiting protrusion is circular or elliptical.

[0036] In some embodiments, the outer contour of the cross section of the limiting protrusion is a polygon.

[0037] In some embodiments, the outer contour of the cross section of the limiting protrusion is an irregular shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of a method for preparing a capacitor structure provided by an embodiment of the present invention;

[0039] Figure 2 for Figure 1A schematic diagram of a specific implementation of S102;

[0040] Figure 3a-Figure 3i for Figure 1 and Figure 2 Schematic diagram of the preparation method;

[0041] Figure 4a-4f A schematic diagram of the shape of a via provided in an embodiment of the present invention;

[0042] Figure 5 for Figure 1 A schematic diagram of another specific implementation of S102;

[0043] Figure 6 A schematic diagram of a capacitor structure provided by an embodiment of the present invention;

[0044] Figure 7 for Figure 6 Enlarged view of point A in the middle.

[0045] Icon: 1-substrate; 2-first supporting layer; 3-first sacrificial layer; 4-second supporting layer; 5-second sacrificial layer; 6-third supporting layer; 7-capacitor hole; 8-lower electrode layer; 41-heterogeneous region; 71-limiting groove; 81-limiting protrusion. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0048] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0049] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0050] According to some embodiments, a first aspect of the present application provides a method for preparing a capacitor structure, such as Figure 1 As shown, the specific steps include:

[0051] S101, depositing a first supporting layer, a first sacrificial layer, and a second supporting layer in sequence on a substrate;

[0052] S102, forming a heterogeneous region in the second supporting layer;

[0053] S103, sequentially depositing a second sacrificial layer and a third supporting layer on the second supporting layer;

[0054] S104, etching in sequence from the third supporting layer toward the substrate to form capacitor holes through an etching process, and the capacitor holes penetrate the heterogeneous region, wherein the etching selectivity ratio of the material of the heterogeneous region to the material of the second supporting layer is greater than 1;

[0055] S105, forming a lower electrode layer on the inner surface of the capacitor hole.

[0056] The embodiments of the present application have at least the following advantages:

[0057] After depositing the first supporting layer and the first sacrificial layer on the substrate in sequence, the second supporting layer is deposited on the first sacrificial layer, and a heterogeneous region is formed on the second supporting layer. The second sacrificial layer and the third supporting layer are deposited in sequence on the second supporting layer to form a basic structure of the capacitor; when etching a capacitor hole on the structure, etching is performed in sequence along the third supporting layer toward the substrate through an etching process. Since the etching selectivity ratio of the material of the heterogeneous region to the material of the second supporting layer is greater than 1, after etching the second sacrificial layer, the heterogeneous region will be etched preferentially compared with other regions of the second supporting layer. Then, the first sacrificial layer, the first supporting layer and the substrate are etched in sequence to form a complete capacitor hole, and finally a lower electrode layer is formed on the inner surface of the capacitor hole. In the process of etching from the third supporting layer to the substrate in sequence, if the etching direction is deviated to a certain extent, that is, the angle between the etching direction and the normal of the substrate exceeds the preset range, due to the existence of the heterogeneous region of the second supporting layer, the heterogeneous region will be etched preferentially, that is, the etching starting point of the lower half is corrected by the heterogeneous region, which can correct the etching direction to a certain extent, thereby avoiding the problem of adjacent capacitor holes being interconnected due to the excessive deflection of the capacitor holes in the lower half, and then causing the lower electrodes in different capacitor holes to be interconnected.

[0058] In some embodiments, reference Figure 2 In the above S102, forming a heterogeneous region on the second supporting layer includes:

[0059] S201, etching the second supporting layer to form a via hole through an etching process;

[0060] S202 , filling the via hole with a heterogeneous material to form a heterogeneous region.

[0061] In some embodiments, a cross-sectional area of ​​the via hole is larger than a cross-sectional area of ​​the capacitor hole.

[0062] It should be noted that in the process of etching from the third supporting layer to the substrate side in sequence, after the second sacrificial layer is etched, if the engraving is skewed, that is, the capacitor hole is skewed, since the cross-sectional area of ​​the via is larger than the cross-sectional area of ​​the capacitor hole, the via on the second supporting layer and the capacitor hole on the surface of the second sacrificial layer facing the second supporting layer have an overlapping part, and the heterogeneous area in the via is etched. The via can be connected to the capacitor hole on the second sacrificial layer, that is, the via can be used as a part of the capacitor hole. Since the via is formed according to the design, the via corrects the direction of the capacitor hole to a certain extent, that is, corrects the skewed etching direction, thereby avoiding the problem of adjacent capacitor holes being interconnected due to the excessive degree of deflection of the lower half of the capacitor hole, and then causing the lower electrodes in different capacitor holes to be interconnected.

[0063] In some embodiments, after the dielectric material is filled in the via hole to form the heterogeneous region, the method further includes:

[0064] S203, performing chemical mechanical polishing on the heterogeneous region so that a surface of the heterogeneous region facing away from the substrate and a surface of the second supporting layer facing away from the substrate are located in the same plane.

[0065] It should be noted that chemical mechanical polishing technology combines the advantages of chemical polishing and mechanical polishing. Pure chemical polishing has high surface accuracy, low damage, good integrity, and is not prone to surface / subsurface damage, but the polishing rate is slow, the material removal efficiency is low, the surface profile accuracy cannot be corrected, and the polishing consistency is relatively poor; pure mechanical polishing has good polishing consistency, high surface flatness, and high polishing efficiency, but it is prone to surface layer / subsurface layer damage and the surface roughness value is relatively low. Chemical mechanical polishing absorbs the advantages of both, and can obtain a more perfect surface while ensuring material removal efficiency. The flatness obtained is 1-2 orders of magnitude higher than that of the simple use of these two types of polishing, and the surface roughness can be achieved from nanometer to atomic level. Chemical mechanical polishing of heterogeneous areas can achieve global surface flattening of the surface of the second support layer facing away from the substrate, which is beneficial to the subsequent deposition process of the second sacrificial layer, so as to improve the flatness of the subsequent deposition surface.

[0066] In some embodiments, the heterogeneous region material requires a certain selectivity ratio when etching the capacitor hole, and can be easier to etch than the sacrificial layer (the second sacrificial layer or the first sacrificial layer). In the step of etching the capacitor hole, part of the heterogeneous material is retained in the via hole of the second supporting layer to prevent further oxidation of the side wall of the via hole in the second supporting layer; however, when removing the sacrificial layer, the heterogeneous region is more difficult to etch than the sacrificial layer, and the heterogeneous region material can be retained between the lower electrode and the second supporting layer.

[0067] In some embodiments, the foreign material includes hafnium oxide or aluminum oxide or tantalum oxide.

[0068] It should be noted that the general sacrificial layer material is boro-phospho-silicate glass (BPSG), and the heterogeneous material can be hafnium oxide, aluminum oxide, or tantalum oxide.

[0069] In some embodiments, the lower electrode layer is embedded in a groove formed by the second sacrificial layer, the second supporting layer, and the first sacrificial layer at the via hole.

[0070] It can be understood that since the cross-sectional area of ​​the via (or heterogeneous region) is larger than the cross-sectional area of ​​the capacitor hole, after the heterogeneous region is etched, the second sacrificial layer, the second supporting layer and the first sacrificial layer form a groove at the via so that the portion of the lower electrode layer located on the second supporting layer is embedded in the groove.

[0071] In some embodiments, the material of the lower electrode layer is TIN (nano-titanium nitride).

[0072] Figure 3a-Figure 3iThe following are some examples of the preparation method of the present invention; specifically refer to the following steps:

[0073] Reference Figure 3a , depositing a first supporting layer 2, a first sacrificial layer 3, and a second supporting layer 4 in sequence on a silicon substrate 1, and etching the second supporting layer 4 to form a plurality of via holes on the second supporting layer 4;

[0074] Reference Figure 3b , filling the via holes of the etched second support layer 4 with dielectric materials such as hafnium oxide, aluminum oxide, and tantalum oxide to form a heterogeneous region 41, and then using CMP (Chemical Mechanical Polishing) to grind the surface of the heterogeneous region 41 so that the heterogeneous region 41 and the second support layer 4 are on the same level;

[0075] Reference Figure 3c , continue to deposit a second sacrificial layer 5 and a third supporting layer 6 on the second supporting layer 4;

[0076] Reference Figure 3d , etching the third supporting layer 6, the etching method can be dry etching or wet etching; the dry etching gas can use NF3 (nitrogen trifluoride) and CF4 (carbon tetrafluoride) gas as an etchant, and the wet etching can use phosphoric acid as an etchant;

[0077] Reference Figure 3e , etching the second sacrificial layer 5, the etching method can be dry etching or wet etching; the dry etching gas can use fluorine-containing gas, such as CF4 (carbon tetrafluoride) and SF6 (sulfur hexafluoride) gas as an etchant, and the wet etching can use hydrofluoric acid as an etchant;

[0078] Reference Figure 3f , etching the second supporting layer 4 (including the heterogeneous region 41), the etching method can specifically adopt dry etching or wet etching; the dry etching gas can adopt fluorine-containing gas, such as CF4 (carbon tetrafluoride) and SF6 (sulfur hexafluoride) gas as an etchant, and the wet etching can adopt hydrofluoric acid as an etchant;

[0079] Reference Figure 3g , etching the first sacrificial layer 3, the etching method can specifically adopt dry etching or wet etching; the dry etching gas can adopt fluorine-containing gas, such as CF4 (carbon tetrafluoride) and SF6 (sulfur hexafluoride) gas as etchant, and the wet etching can adopt hydrofluoric acid as etchant;

[0080] Reference Figure 3h, etching the first support layer 2, the etching method can be dry etching or wet etching; the dry etching gas can use NF3 (nitrogen trifluoride) and CF4 (carbon tetrafluoride) gas as etchant, and the wet etching can use phosphoric acid as etchant; etching the substrate 1;

[0081] Reference Figure 3i , a CVD (Chemical Vapor Deposition) lower electrode layer 8, the lower electrode material can be TiN (nano titanium nitride), and TiN is filled into the groove formed by the second sacrificial layer 5, the second supporting layer 4 and the first sacrificial layer 3 at the via hole.

[0082] It is understandable that the cross-section of the via hole can be in various shapes, such as circular, square, oval, rectangular, pentagonal, hexagonal, octagonal, etc. Figure 4a-4f Some shapes of vias provided in the embodiments of the present application are shown below:

[0083] In some embodiments, reference Figure 4a , the via can be a circular hole.

[0084] In some embodiments, reference Figure 4b , the via hole can be an elliptical hole.

[0085] In some embodiments, reference Figure 4c-Figure 4f , the via hole can be a polygonal hole, as shown in Figure 4c The middle via is rectangular. Figure 4d The middle via is diamond-shaped. Figure 4e The vias are pentagonal and Figure 4f The middle via is hexagonal.

[0086] In some embodiments, the via hole is a special-shaped hole.

[0087] In some embodiments, reference Figure 5 , forming a heterogeneous region 41 on the second supporting layer 4, including:

[0088] S501 , etching the side of the second supporting layer 4 facing away from the substrate 1 through an etching process to make the surface concave to form a heterogeneous region 41 .

[0089] It is understandable that the second support layer 4 has a depression on its surface facing away from the substrate 1 . During etching, the area with the depression has a higher priority than the area without the depression, thereby achieving the purpose of correcting the etching direction of the capacitor hole 7 .

[0090] According to some embodiments, Figure 6 and Figure 7 As shown, the second aspect of the present application provides a capacitor structure, including:

[0091] Substrate 1;

[0092] A first supporting layer 2 formed on a substrate 1;

[0093] A first sacrificial layer 3 formed on a side of the first supporting layer 2 facing away from the substrate 1;

[0094] A second supporting layer 4 formed on a side of the first sacrificial layer 3 away from the first supporting layer 2;

[0095] A second sacrificial layer 5 formed on a side of the second supporting layer 4 away from the first sacrificial layer 3;

[0096] a third supporting layer 6 formed on a side of the second sacrificial layer 5 away from the second supporting layer 4;

[0097] The capacitor hole 7 sequentially penetrates the third support layer 6, the second sacrificial layer 5, the second support layer 4, the first sacrificial layer 3, the first support layer 2 and the substrate 1, and a limiting groove 71 is formed on the side wall of the capacitor hole 7;

[0098] The lower electrode layer 8 is formed on the side wall of the capacitor hole 7 . The lower electrode layer 8 is provided with a limiting protrusion 81 that cooperates with the limiting groove 71 . The limiting protrusion 81 extends in a direction away from the axis of the capacitor hole 7 .

[0099] The embodiments of the present application have at least the following advantages:

[0100] A limiting structure is provided between the lower electrode layer 8 and the side wall of the capacitor hole 7, which may be specifically a limiting groove 71 and a limiting protrusion 81 that cooperate with each other, wherein: the limiting groove 71 is located on the side wall of the capacitor hole 7; the limiting protrusion 81 is located on the lower electrode layer 8, and the limiting protrusion 81 of the lower electrode layer 8 is embedded in the limiting groove 71 on the side wall of the capacitor hole 7, so that the lower electrode layer 8 can increase the contact area between the supporting layer and the lower electrode, making the capacitor structure more stable.

[0101] In some embodiments, the limiting groove 71 is formed at the portion of the capacitor hole 7 that passes through the second supporting layer 4 .

[0102] Reference Figure 7 , the limiting groove 71 is formed at the second sacrificial layer 5, the second supporting layer 4 and the first sacrificial layer 3; in one possible implementation method, the method for forming the limiting groove 71 is: in the process of preparing the capacitor structure, a heterogeneous region 41 is formed on the second supporting layer 4, and the etching selectivity ratio of the material of the heterogeneous region 41 to the material of the second supporting layer 4 is greater than 1, and the cross-sectional area of ​​the heterogeneous region 41 is greater than the cross-sectional area of ​​the capacitor hole 7. Therefore, in the process of etching the capacitor hole 7, the size of the capacitor hole 7 at the second supporting layer 4 is greater than the size of the capacitor hole 7 at the second sacrificial layer 5 and the size of the capacitor hole 7 at the first sacrificial layer 3, that is, the limiting groove 71 structure is formed at the second sacrificial layer 5, the second supporting layer 4, and the first sacrificial layer 3.

[0103] It is understandable that the outer contour of the cross section of the limiting protrusion 81 can be in various shapes, such as circular, square, oval, rectangular, pentagonal, hexagonal, octagonal, etc., such as the following:

[0104] In some embodiments, the outer contour of the cross section of the limiting protrusion 81 is circular or elliptical.

[0105] In some embodiments, the outer contour of the cross section of the limiting protrusion 81 is a polygon.

[0106] In some embodiments, the outer contour of the cross section of the limiting protrusion 81 is an irregular shape.

[0107] In some embodiments, the second supporting layer 4 and the heterogeneous region 41 are deposited step by step and the second supporting layer 4 is etched step by step, which to a certain extent alleviates the problem of interconnection of the lower electrodes in the capacitor hole 7 caused by the distortion of the capacitor hole 7, and can be applied to capacitor structures with high aspect ratios.

[0108] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for preparing a capacitor structure, characterized in that: include: Depositing a first supporting layer, a first sacrificial layer, and a second supporting layer in sequence on the substrate; forming a heterogeneous region in the second supporting layer; sequentially depositing a second sacrificial layer and a third supporting layer on the second supporting layer; By means of an etching process, sequentially etching along the third supporting layer toward the substrate to form capacitor holes, and the capacitor holes penetrate the heterogeneous region, wherein the etching selectivity ratio of the material of the heterogeneous region to the material of the second supporting layer is greater than 1; A lower electrode layer is formed on the inner surface of the capacitor hole.

2. The preparation method according to claim 1, characterized in that: Forming a heterogeneous region on the second supporting layer, comprising: By means of an etching process, etching the second supporting layer to form a via hole; The via hole is filled with a heterogeneous material to form the heterogeneous region.

3. The preparation method according to claim 2, characterized in that: The cross-sectional area of ​​the via hole is greater than the cross-sectional area of ​​the capacitor hole.

4. The preparation method according to claim 2, characterized in that: After the dielectric material is filled in the via hole to form the heterogeneous region, the method further includes: The heterogeneous region is polished chemically and mechanically so that a surface of the heterogeneous region facing away from the substrate and a surface of the second supporting layer facing away from the substrate are located in the same plane.

5. The preparation method according to claim 2, characterized in that: The foreign material includes hafnium oxide or aluminum oxide or tantalum oxide.

6. The preparation method according to claim 2, characterized in that: The via hole is a circular hole or an elliptical hole.

7. The preparation method according to claim 2, characterized in that: The via hole is a polygonal hole.

8. The preparation method according to claim 2, characterized in that: The via hole is a special-shaped hole.

9. The preparation method according to claim 2, characterized in that: The lower electrode layer is embedded in a groove formed by the second sacrificial layer, the second supporting layer and the first sacrificial layer at the via hole.

10. The preparation method according to claim 2, characterized in that: Forming a heterogeneous region on the second supporting layer, comprising: Through an etching process, the second supporting layer is etched on a side facing away from the substrate so that the surface is recessed to form the heterogeneous region.

11. A capacitor structure, characterized in that: include: substrate; a first supporting layer formed on the substrate; a second supporting layer formed on a side of the first supporting layer away from the substrate, wherein a heterogeneous region is formed in the second supporting layer; a third supporting layer formed on a side of the second supporting layer facing away from the first supporting layer; A capacitor hole, wherein the capacitor hole sequentially penetrates the third supporting layer, the second supporting layer, the first supporting layer and the substrate, and the capacitor hole penetrates the heterogeneous region, wherein an etching selectivity ratio between a material of the heterogeneous region and a material of the second supporting layer is greater than 1, and a limiting groove is formed on a sidewall of the capacitor hole; A lower electrode layer is formed on the side wall of the capacitor hole, and a limiting protrusion is provided on the lower electrode layer to cooperate with the limiting groove, and the limiting protrusion extends in a direction away from the axis of the capacitor hole.

12. The capacitor structure according to claim 11, characterized in that: The limiting groove is formed at a portion of the capacitor hole that passes through the second supporting layer.

13. The capacitor structure according to claim 12, characterized in that: The outer contour of the cross section of the limiting protrusion is circular or elliptical.

14. The capacitor structure according to claim 12, characterized in that: The outer contour of the cross section of the limiting protrusion is a polygon.

15. The capacitor structure according to claim 12, characterized in that: The outer contour of the cross section of the limiting protrusion is an irregular shape.

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