An enhanced TVS structure device

Abstract

The present invention discloses an enhanced TVS structure device, including an N-type semiconductor substrate. A minority carrier injection structure region is provided on the P-type base region of the N-type semiconductor substrate. The minority carrier injection structure region is used for injecting minority carriers. The minority carrier injection structure region is a dot array structure. By providing a minority carrier injection structure region on the P-type base region of the N-type semiconductor substrate, a minority carrier injection compensation structure mechanism is added on the basis of a conventional TVS structure device. When a high-voltage surge signal passes through the TVS structure device in this case, the minority carrier injection compensation structure injects minority carriers into the P-type base region. This part of the minority carriers drifts through the P-type base region to the N-type semiconductor substrate region, reducing the overall on-resistance of the TVS structure device when it is turned on, thereby reducing the peak value of the residual voltage and enabling the protected subsequent-stage IC to be subjected to lower overvoltage interference.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip design and manufacturing, and particularly relates to an enhanced TVS structure device. Background Art

[0002] A TVS (Transient Voltage Suppressor) tube is a new product developed on the basis of the zener diode process. When a high-energy impact occurs instantaneously at both ends of the TVS tube, it can reduce its impedance suddenly at an extremely high speed, absorb a large current at the same time, and clamp the voltage between its two ends at a predetermined value, thereby ensuring that the subsequent circuit components are not damaged by the transient high-energy impact. Due to its advantages such as fast response time, high transient power, low capacitance, low leakage current, small breakdown voltage deviation, easy control of the clamping voltage, small size, and easy installation, the TVS tube has been widely used in various fields such as computer systems, communication devices, consumer electronics, power supplies, and household appliances.

[0003] With the development of integrated circuit technology, IC chips have become more and more sensitive to signal disturbances, especially the tolerance to the fluctuation amplitude of input signals is getting lower and lower. This puts higher and higher requirements on the action quality of interface overvoltage protection devices, and reducing the clamping overshoot amplitude has become the first major optimization direction for overvoltage protection devices. Summary of the Invention

[0004] The purpose of the present invention is to provide an enhanced TVS structure device. On the basis of the conventional TVS design, a minority carrier injection compensation structure is added. When a high-voltage surge signal passes through the device, this structure injects minority carriers into the base region, and these minority carriers drift through the base region to the substrate region, reducing the overall on-resistance of the device when it is turned on, thereby reducing the peak value of the residual voltage.

[0005] The technical problem solved by the present invention is:

[0006] How to reduce the residual voltage of the TVS structure device after the surge signal passes through the TVS structure device.

[0007] The purpose of the present invention can be achieved by the following technical solutions:

[0008] An enhanced TVS structure device includes an N-type semiconductor substrate, and a minority carrier injection structure region is formed on the P-type base region of the N-type semiconductor substrate, and the minority carrier injection structure region is used for injecting minority carriers.

[0009] As a further solution of the present invention: the minority carrier injection structure region is a dot array structure, the center distance between the dot array circles is 300 microns, and the diameter of the dot-shaped circular doping region is 20 microns.

[0010] As a further solution of the present invention: metal layers are provided on the upper and lower surfaces of the N-type semiconductor substrate.

[0011] As a further solution of the present invention: the metal layer is a multi-layer metal stacking structure.

[0012] As a further solution of the present invention: masking layers are provided on both sides of the P-type base region on the N-type semiconductor substrate.

[0013] As a further solution of the present invention: the metal layer consists of a contact layer as the first layer, a total of four layers, which are aluminum 1.5 μm, titanium 0.3 μm, nickel 0.7 μm, and silver 1.5 μm in sequence.

[0014] As a further solution of the present invention: a manufacturing method of an enhanced TVS structure device includes the following steps:

[0015] Step 1: Wafer preparation

[0016] Select an MCZ silicon single crystal wafer, 5-inch crystal orientation <111>, N-type, resistivity 0.03 - 0.04 Ω / cm, thickness 220 μm ± 10%;

[0017] Step 2: Primary oxidation

[0018] Under the working conditions of a furnace temperature of 1100 °C, oxygen 4 L / min, and hydrogen 5 L / min, a field oxide masking layer is fabricated, and the thickness of the oxide layer is 1.5 μm ± 10%;

[0019] Step 3: P-base region preparation

[0020] Under the working conditions of a furnace temperature of 1050 °C, oxygen 2 L / min, and nitrogen 3 L / min, boron source deposition is carried out for a deposition time of 40 min. Under the working conditions of a furnace temperature of 1260 °C, oxygen 2 L / min, and nitrogen 3 L / min, boron source push is carried out for a push time of 1500 min, and the diffusion sheet resistance is measured using a four-probe to be 22 Ω ± 10%, and the junction depth is 25 μm ± 10%;

[0021] Step 4: Diffusion of the N-type phosphorus region in the minority carrier injection structure region

[0022] Diffusion of the N-type phosphorus region to form a minority carrier injection region. Under the working conditions of a furnace temperature of 1080 °C, oxygen 2 L / min, nitrogen 3 L / min, and carrier gas nitrogen 1.2 L / min, phosphorus source deposition is carried out for a deposition time of 35 min; under the working conditions of a furnace temperature of 1150 °C, oxygen 2.5 L / min, and nitrogen 4 L / min, boron source push is carried out for a push time of 350 min, and the diffusion sheet resistance is measured using a four-probe to be 0.6 Ω ± 10%, and the junction depth is 12 μm ± 10%;

[0023] Step 5: Metal layer

[0024] Deposit a metal layer through an electron beam metal evaporation platform process.

[0025] Advantages of the present invention:

[0026] In the present invention, a minority carrier injection structure region is provided on the P-type base region of the N-type semiconductor substrate, that is, on the basis of a conventional TVS structure device, a minority carrier injection compensation structure mechanism is added. When a high-voltage surge signal passes through the TVS structure device in this case, the minority carrier injection compensation structure injects minority carriers into the P-type base region, and this part of the minority carriers will drift through the P-type base region to the N-type semiconductor substrate region, reducing the overall on-resistance of the TVS structure device when it conducts, thereby reducing the peak value of the residual voltage and enabling the protected subsequent IC to be less affected by overvoltage interference. Brief Description of the Drawings

[0027] The present invention will be further described below in conjunction with the accompanying drawings.

[0028] Figure 1 is the front view of the present invention;

[0029] Figure 2 is the schematic structural diagram of the P-type base region in the present invention;

[0030] Figure 3 is the schematic structural diagram of the minority carrier injection structure region in the present invention;

[0031] Figure 4 is the schematic structural diagram of the metallization in the present invention.

[0032] In the figure: 1, N-type semiconductor substrate; 2, P-type base region; 3, minority carrier injection structure region; 4, metal layer; 5, mask layer. Detailed Embodiments

[0033] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] Embodiment 1

[0035] Please refer to Figures 1-4 As shown, the present invention is an enhanced TVS structure device, including an N-type semiconductor substrate 1, and a minority carrier injection structure region 3 is provided on the P-type base region 2 of the N-type semiconductor substrate 1, and the minority carrier injection structure region 3 is used for injecting minority carriers.

[0036] During use, a minority carrier injection structure region 3 is formed on the P-type base region 2 of the N-type semiconductor substrate 1, that is, on the basis of a conventional TVS structure device, a minority carrier injection compensation structure mechanism is added. When a high-voltage surge signal passes through the TVS structure device in this case, the minority carrier injection compensation structure injects minority carriers into the P-type base region 2, and these minority carriers will drift through the P-type base region 2 to the N-type semiconductor substrate 1, reducing the overall on-resistance of the TVS structure device when it is turned on, thereby reducing the peak value of the residual voltage and enabling the protected subsequent-stage IC to be subjected to lower overvoltage interference.

[0037] Among them, the minority carrier injection structure region 3 is a dot array structure, but is not limited to the dot array structure, or other structures that can inject minority carriers into the P-type base region 2, so that the minority carriers will drift through the P-type base region 2 to the N-type semiconductor substrate 1;

[0038] Among them, the center distance between the dot array centers is 300 μm, and the diameter of the dot-shaped circular doping region is 20 μm.

[0039] Based on the fact that traditional overvoltage protection devices have a slow operating speed, when encountering high dv / dt signals, such as ESD spikes, the actual operating voltage of the device will be much higher than the theoretical value. For example, for a TVS product with a nominal 58V used in a 48V DC power supply, in the case of a 1.2 / 50 μs waveform, the overshoot voltage of the traditional solution may reach more than 100V, but the actual limit that the main chip can withstand is only 90V. Using traditional overvoltage protection devices will not achieve the protection effect, while the novel structure design of ours can make the typical value of the residual voltage under this waveform reach 75V, and the maximum does not exceed 80V, meeting the protection requirements of the novel whole-machine solution

[0040] Refer to Figure 1 , metal layers 4 are provided on the upper and lower surfaces of the N-type semiconductor substrate 1, the metal layer 4 is a multi-layer metal stacked structure, and the metal layer 4 consists of a contact layer and a total of four layers, which are 1.5 μm of aluminum, 0.3 μm of titanium, 0.7 μm of nickel, and 1.5 μm of silver in sequence, improving the durability and protection performance of the TVS structure device.

[0041] Among them, masking layers 5 are provided on both sides of the P-type base region 2 on the N-type semiconductor substrate 1, and the masking layers 5 play a protective role for the P-type base region 2.

[0042] A manufacturing method of an enhanced TVS structure device includes the following steps:

[0043] Step 1: Wafer preparation

[0044] Select an MCZ silicon single crystal wafer, 5 inches, crystal orientation <111>, N-type, resistivity 0.03 - 0.04 Ω / cm, thickness 220 μm ± 10%;

[0045] Step 2: Primary oxidation

[0046] Fabricate a field oxide mask layer under the conditions of a furnace temperature of 1100 °C, an oxygen flow rate of 4 L / min, and a hydrogen flow rate of 5 L / min, with the oxide layer thickness being 1.5 μm ± 10%;

[0047] Step 3: Preparation of the P-type base region

[0048] Perform boron source deposition under the conditions of a furnace temperature of 1050 °C, an oxygen flow rate of 2 L / min, and a nitrogen flow rate of 3 L / min for a deposition time of 40 min. Perform boron source drive-in under the conditions of a furnace temperature of 1260 °C, an oxygen flow rate of 2 L / min, and a nitrogen flow rate of 3 L / min for a drive-in time of 1500 min, and use a four-probe to measure the diffusion sheet resistance to be 22 Ω ± 10% and the junction depth to be 25 μm ± 10%;

[0049] Step 4: Diffusion of the N-type phosphorus region in the minority carrier injection structure region

[0050] Diffuse the N-type phosphorus region to form a minority carrier injection region. Perform phosphorus source deposition under the conditions of a furnace temperature of 1080 °C, an oxygen flow rate of 2 L / min, a nitrogen flow rate of 3 L / min, and a carrier nitrogen flow rate of 1.2 L / min for a deposition time of 35 min; perform boron source drive-in under the conditions of a furnace temperature of 1150 °C, an oxygen flow rate of 2.5 L / min, and a nitrogen flow rate of 4 L / min for a drive-in time of 350 min, and use a four-probe to measure the diffusion sheet resistance to be 0.6 Ω ± 10% and the junction depth to be 12 μm ± 10%;

[0051] Step 5: Metal layer

[0052] Deposit the metal layer through an electron beam metallization evaporation platform process.

[0053] As a further solution of the present invention: For the preparation of the P-type base region 2 in Step 3, first clean the oxide layer on the wafer surface, use spin-coated dopant as the diffusion source, and then perform boron pre-deposition diffusion doping.

[0054] Detect and test the TVS structure devices manufactured using this method. Select five groups of TVS structure devices for testing, and the test results of the breakdown voltage values are shown in the following table:

[0055]

[0056] As can be seen from the above table, based on ensuring the functions and parameters of the original product, this solution reduces the breakdown voltage by about 20%, reduces the overall on-resistance of the device when conducting, and thus reduces the breakdown voltage peak value.

[0057] Example 2

[0058] The manufacturing method of this example is exactly the same as that of Example 1, except that the N-type semiconductor substrate 1 is replaced with a P-type semiconductor substrate, and the impurity types are opposite.

[0059] In summary, based on the traditional PN junction diode, the present invention adds a layer of dot array N-type doping structure to form an NPN structure similar to a triode. When the TVS tube is in the withstand voltage state, only a very small amount of electrons will drift to the P-type base region 2 and be completely recombined in the P-type base region 2, without affecting the normal withstand voltage of the device.

[0060] When surge energy causes the device to enter the avalanche breakdown state, the electrons in the minority carrier injection structure region 3 will be accelerated by the electric field, pass through the P-type base region 2, and drift to the N-type semiconductor substrate 1. This mechanism will increase the carrier density when the device undergoes avalanche breakdown and reduce the on-resistance of the device during avalanche breakdown.

[0061] Since the residual voltage of the TVS device consists of the sum of two parts, one is the reverse withstand voltage value of the PN junction, and the other is the product of the instantaneous current and the on-resistance, that is, the on-voltage drop. Among them, the first part, the reverse withstand voltage value of the PN junction, is an inherent characteristic of the device and cannot be changed. The present invention optimizes the parameter ability of the second part through the above scheme. By reducing the on-resistance of the device, the on-voltage drop is reduced, achieving the design goal of reducing the residual voltage of the device.

[0062] This solution is based on the fact that traditional overvoltage protection devices have a slow action speed. For example, when encountering a high dv / dt signal, such as an ESD spike, the actual action voltage of the device will be much higher than the theoretical value.

[0063] Through testing, for a TVS product with a nominal 58V for a 48V DC power supply, in the case of a 1.2 / 50μs waveform, the overshoot voltage of the traditional solution may reach more than 100V, but the actual limit that the main chip can withstand is only 90V. Using the traditional overvoltage protection device will not achieve the protection effect. By adopting the technical means of this solution, the typical value of the residual voltage under this waveform can reach 75V, and the maximum does not exceed 80V, meeting the protection requirements of the new whole machine solution.

[0064] Combining Embodiment 1 and Embodiment 2, both take the planar structure PN junction as an example. The mesa structure PN junction is consistent with the key points of the present invention and will not be separately exemplified. Therefore, the structure of the present invention is also protected in mesa-type TVS.

[0065] The above has described a detailed description of an embodiment of the present invention, but the content described is only the preferred embodiment of the present invention and cannot be considered as limiting the scope of implementation of the present invention. All equivalent changes and improvements made according to the scope of the application of the present invention should still fall within the scope covered by the patent of the present invention.

Claims

1. An enhanced TVS structure device, comprising an N-type semiconductor substrate (1), characterized in that, A minority carrier injection structure region (3) is formed on the P-type base region (2) of the N-type semiconductor substrate (1), and the minority carrier injection structure region (3) is used for injecting minority carriers. The minority carrier injection structure region (3) is a dot array structure. The center distance between the dot array centers is 300 μm, and the diameter of the dot-shaped circular doping region is 20 μm. The preparation of the enhanced TVS structure device includes the following steps: Step 1: Wafer preparation Select an MCZ silicon single crystal wafer, 5 inches in <111> crystal orientation, N-type, with a resistivity of 0.03 - 0.04 Ω / cm and a thickness of 220 μm ± 10%. Step 2: First oxidation Fabricate a field oxide mask layer under the conditions of a furnace temperature of 1100 °C, oxygen flow rate of 4 L / min, and hydrogen flow rate of 5 L / min, with an oxide layer thickness of 1.5 μm ± 10%. Step 3: P-base region preparation Perform boron source deposition under the conditions of a furnace temperature of 1050 °C, oxygen flow rate of 2 L / min, and nitrogen flow rate of 3 L / min for a deposition time of 40 min. Then, perform boron source drive-in under the conditions of a furnace temperature of 1260 °C, oxygen flow rate of 2 L / min, and nitrogen flow rate of 3 L / min for a drive-in time of 1500 min. Use a four-probe to measure the sheet resistance of the diffusion to be 22 Ω ± 10% and the junction depth to be 25 μm ± 10%. Step 4: Diffusion of the N-type phosphorus region in the minority carrier injection structure region Diffuse the N-type phosphorus region to form a minority carrier injection region. Perform phosphorus source deposition under the conditions of a furnace temperature of 1080 °C, oxygen flow rate of 2 L / min, nitrogen flow rate of 3 L / min, and carrier gas nitrogen flow rate of 1.2 L / min for a deposition time of 35 min. Then, perform boron source drive-in under the conditions of a furnace temperature of 1150 °C, oxygen flow rate of 2.5 L / min, and nitrogen flow rate of 4 L / min for a drive-in time of 350 min. Use a four-probe to measure the sheet resistance of the diffusion to be 0.6 Ω ± 10% and the junction depth to be 12 μm ± 10%. Step 5: Metal layer Deposit the metal layer through an electron beam metal evaporation platform process.

2. An enhanced TVS structure device according to claim 1, wherein Metal layers (4) are provided on the upper and lower surfaces of the N-type semiconductor substrate (1).

3. An enhanced TVS structure device according to claim 2, characterized in that, The metal layer (4) is a multi-layer metal stacked structure.

4. An enhanced TVS structure device according to claim 1, characterized in that, Masking layers (5) are provided on both sides of the P-type base region (2) on the N-type semiconductor substrate (1).

5. An enhanced TVS structure device according to claim 2, characterized in that, The metal layer (4) consists of a contact layer as the first layer, a total of four layers, which are 1.5 μm of aluminum, 0.3 μm of titanium, 0.7 μm of nickel, and 1.5 μm of silver in sequence.

6. An enhanced TVS structure device according to claim 1, characterized in that: In the preparation of the P-type base region (2) in Step 3, first clean the oxide layer on the wafer surface, use a spin-coated dopant as the diffusion source, and then perform boron pre-deposition diffusion doping.

Images