Method, apparatus, electronic device, and storage medium for memory access

Abstract

The present application relates to the technical field of memory, and discloses a method for memory access, including: determining a memory access request to be executed among a number of memory access requests cached in a command pipeline; determining whether a target memory pointed to by a target memory address in the memory access request to be executed is in an idle state; determining whether a programming operation instruction is included in the memory access instruction to be executed; triggering the command pipeline to send the programming operation instruction to the target memory when the target memory is in an idle state and the memory access request to be executed includes a programming operation instruction; determining whether a flag register is included in a preset storage space; triggering the target memory to send an interrupt signal to the CPU corresponding to the memory access to be executed when the flag register is included in the preset storage space. In this way, an interrupt signal can be sent to the corresponding CPU every time a memory access request is issued. The present application also discloses a device, an electronic device and a storage medium for memory access.

Description

Technical Field

[0001] This application relates to the technical field of memory, and for example, relates to a method, device, electronic device and storage medium for memory access. Background Art

[0002] During the process of a CPU (central processing unit) accessing memory, the memory access request initiated by the CPU is stored in a command pipeline through a bus. The memory access request includes the memory address to be accessed. Then, the command pipeline issues the memory access request to the memory corresponding to the memory address to implement reading, erasing, or storing of memory data. After the memory access request is issued, that is, when there is no memory access request in the command pipeline, the memory sends an interrupt signal to the CPU to determine that the issuance of the CPU's memory access request has been completed. In the case where multiple CPUs access the same memory simultaneously, the memory access requests initiated by each CPU will go through bus arbitration and then be stored in the command pipeline in sequence. Then, the command pipeline issues the memory access requests of each CPU to the memory in the storage order, so that each CPU can implement reading, erasing, or storing of memory data in the storage order.

[0003] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0004] Since the memory sends an interrupt signal to the CPU only after the memory access request is issued, in the case where there are multiple memory access requests stored in the command pipeline, the interrupt signal can only be sent to each CPU after all memory access requests are issued, and it is impossible to send an interrupt signal to the corresponding CPU every time a memory access request is issued. Summary of the Invention

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary is not a comprehensive review, nor is it intended to identify key / important constituent elements or delineate the protection scope of these embodiments. Instead, it serves as a preface to the subsequent detailed description.

[0006] The embodiments of the present disclosure provide a method, device, electronic device and storage medium for memory access, so as to be able to send an interrupt signal to the corresponding CPU every time a memory access request is issued.

[0007] In some embodiments, the method includes: determining a memory access request to be executed among a plurality of memory access requests cached in a command pipeline; determining whether a target memory pointed to by a target memory address in the memory access request to be executed is in an idle state; determining whether the memory access instruction to be executed includes a programming operation instruction; triggering, when the target memory is in an idle state and the memory access request to be executed includes a programming operation instruction, the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory; determining whether a flag register is included in a preset storage space, where the flag register is used to represent that the command pipeline has sent the programming operation instruction to the target memory; and triggering, when the flag register is included in the preset storage space, the target memory to send an interrupt signal to the CPU.

[0008] In some embodiments, the apparatus includes: a first determination module configured to determine a memory access request to be executed among a plurality of memory access requests cached in a command pipeline; a second determination module configured to determine whether a target memory pointed to by a target memory address in the memory access request to be executed is in an idle state; determining whether the memory access instruction to be executed includes a programming operation instruction; a first trigger module configured to trigger, when the target memory is in an idle state and the memory access request to be executed includes a programming operation instruction, the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory; a third determination module configured to determine whether a flag register is included in a preset storage space, where the flag register is used to represent that the command pipeline has sent the programming operation instruction to the target memory; and a second trigger module configured to trigger, when the flag register is included in the preset storage space, the target memory to send an interrupt signal to the CPU.

[0009] In some embodiments, the apparatus includes a processor and a memory storing program instructions, where the processor is configured to execute the above method for memory access when running the program instructions.

[0010] In some embodiments, the electronic device includes the above apparatus for memory access.

[0011] In some embodiments, the storage medium stores program instructions, and when the program instructions are running, they execute the above method for memory access.

[0012] The method, apparatus, electronic device, and storage medium for memory access provided by the embodiments of the present disclosure can achieve the following technical effects: After triggering the command pipeline to send the programming operation instruction in the to-be-executed memory access request to the target memory, it is determined whether the flag register is included in the preset storage space, where the flag register is used to indicate that the command pipeline has sent the programming operation instruction to the target memory; Whether the command pipeline has sent the programming operation instruction to the target memory is determined by the presence or absence of the flag register, and in this case, the target memory is triggered to send an interrupt signal to the CPU that initiated the to-be-executed memory access request; In this way, an interrupt signal can be sent to the corresponding CPU every time a memory access request is issued.

[0013] The above general description and the following description are only exemplary and explanatory, and are not used to limit this application. Brief Description of the Drawings

[0014] One or more embodiments are exemplarily illustrated by the corresponding drawings. These exemplary illustrations and the drawings do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation, and among them:

[0015] Figure 1 is a schematic diagram of the first method for memory access provided by the embodiments of the present disclosure;

[0016] Figure 2 is a schematic diagram of the second method for memory access provided by the embodiments of the present disclosure;

[0017] Figure 3 is a schematic diagram of the third method for memory access provided by the embodiments of the present disclosure;

[0018] Figure 4 is a schematic diagram of the fourth method for memory access provided by the embodiments of the present disclosure;

[0019] Figure 5 is a schematic diagram of an apparatus for memory access provided by the embodiments of the present disclosure;

[0020] Figure 6 is a schematic diagram of another apparatus for memory access provided by the embodiments of the present disclosure. Detailed Description of the Embodiments

[0021] To more comprehensively understand the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure. In the following technical description, for the sake of explanation, numerous details are provided to enable a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be shown in a simplified manner to simplify the drawings.

[0022] In the description of the embodiments of the present disclosure, the terms "first", "second", etc. in the specification, claims and the above-mentioned drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data may be interchanged under appropriate circumstances so as to implement the embodiments of the present disclosure described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0023] Unless otherwise specified, the term "plurality" means two or more.

[0024] In the embodiments of the present disclosure, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B.

[0025] The term "and / or" is a description of the association relationship of objects, indicating that three relationships may exist. For example, A and / or B means: A or B, or, A and B these three relationships.

[0026] The term "corresponding" may refer to an association relationship or a binding relationship. A corresponding to B means that there is an association relationship or a binding relationship between A and B.

[0027] Combined with Figure 1 As shown, the embodiments of the present disclosure provide a method for memory access, including:

[0028] Step S101, determining a memory access request to be executed among several memory access requests cached in a command pipeline; the memory access request is initiated by a central processing unit (CPU);

[0029] Step S102, determining whether the target memory pointed to by the target memory address in the memory access request to be executed is in an idle state; determining whether the memory access instruction to be executed includes a programming operation instruction;

[0030] Step S103, when the target memory is in an idle state and the memory access request to be executed includes a programming operation instruction, triggering the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory;

[0031] Step S104, determine whether a flag register is included in a preset storage space, where the flag register is used to indicate that the command pipeline has sent a programming operation instruction to the target memory;

[0032] Step S105, when the flag register is included in the preset storage space, trigger the target memory to send an interrupt signal to the CPU corresponding to the memory access to be executed.

[0033] By using the method for memory access provided by the embodiments of the present disclosure, after triggering the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory, it is determined whether a flag register is included in the preset storage space. Since the flag register is used to indicate that the command pipeline has sent the programming operation instruction to the target memory, it can be determined whether the command pipeline has sent the programming operation instruction to the target memory based on the presence or absence of the flag register. And when it is determined that the flag register exists, trigger the target memory to send an interrupt signal to the CPU that initiates the memory access request to be executed. In this way, an interrupt signal can be sent to the corresponding CPU every time a memory access request is issued, so that the CPU can know the process status of the memory access.

[0034] Optionally, determining the memory access request to be executed among several memory access requests cached in the command pipeline includes: when there is one memory access request cached in the command pipeline, determining this memory access request as the memory access request to be executed; and / or, when there are multiple memory access requests cached in the command pipeline, determining the memory access request with the earliest order among the memory access requests according to the order corresponding to each memory access request as the memory access request to be executed.

[0035] Optionally, the order corresponding to each memory access request is obtained by the following method: the bus sorts multiple memory access requests initiated by the CPU in the order from the earliest initiation time to the latest initiation time.

[0036] Optionally, when multiple CPUs initiate memory access requests to the same target memory at the same time, the bus sorts the multiple received memory access requests in the order from the highest priority to the lowest priority of the CPUs corresponding to each memory access request.

[0037] Optionally, the programming operation instruction includes an erase operation on the data in the target memory; or, storing the data to be stored in the programming operation instruction into the target memory.

[0038] Optionally, after triggering the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory, it further includes: triggering the target memory to perform an erase operation on the data in the target memory according to the programming operation instruction; or, storing the data to be stored in the programming operation instruction.

[0039] Optionally, the target memory erases the data in the target memory according to the programming operation instruction; or, after the target memory stores the data to be stored in the programming operation instruction, it further includes: the target memory sends the response information indicating that the programming operation has been completed to the CPU corresponding to the pending memory access request. Optionally, the target memory sends the response information to the CPU corresponding to the pending memory access request through the response channel.

[0040] In some embodiments, the target memory sends the response information to the response channel. When the response channel receives the response information, it converts the local clock domain frequency of the response information into the high-speed clock domain frequency to obtain the high-speed response information, and sends the high-speed response information to the AXI (Advanced eXtensible Interface, bus protocol) bus. When the AXI bus receives the high-speed response information, it sends the high-speed response information to the CPU corresponding to the pending memory access request. Since the AXI bus is from the high-speed clock domain and the target memory is from the local clock domain, and at the same time, the clock domain frequency of the target memory is half of the high-speed clock domain frequency, in order for the CPU to parse the response information, it is necessary for the response channel to convert the response information into the high-speed response information.

[0041] In some embodiments, the command channel is within the controller of the target memory. The command channel is used to cache the memory access request, and the depth of the command channel is 8 and the data width is 158 bits. In some embodiments, the response channel is within the controller of the target memory, and the depth of the response channel is 16 and the data width is 94 bits.

[0042] Optionally, the pending memory access request includes multiple programming operation instructions; triggering the command pipeline to send the programming operation instructions in the pending memory access request to the target memory includes: triggering the command pipeline to send each programming operation instruction to the target memory in a preset order.

[0043] Optionally, the flag register is set in the following manner: when the command pipeline sends all the programming operation instructions in the pending memory access request to the target memory, the CPU corresponding to the pending memory access request configures the flag register in the preset storage space.

[0044] Optionally, before determining whether the target memory pointed to by the target memory address in the pending memory access request is in the idle state, it further includes: performing parity check on the target memory address, and determining whether the target memory pointed to by the target memory address is in the idle state when the check passes.

[0045] Optionally, determining whether the target memory pointed to by the target memory address in the to-be-executed memory access request is in an idle state includes: obtaining a first value at a first preset position of a status register corresponding to the target memory; the first value is used to represent the current state of the target memory; determining whether the target memory is in an idle state according to the value. In this way, it is possible to quickly determine whether the target memory is in an idle state.

[0046] Optionally, the status register stores data information with a preset number of bits, and the first value at the first preset position of the data information is used to represent the current state of the target memory. In some embodiments, when the first value is "0", it is determined that the target memory is in an idle state; in some embodiments, when the first value is "1", it is determined that the target memory is in a busy state. In some embodiments, the target memory being in a busy state is used to represent that the data stored in the target memory is being erased, or new data to be stored is being written into the target memory.

[0047] Optionally, before triggering the command pipeline to send the to-be-executed memory access request to the target memory, it further includes: determining whether the to-be-executed memory access request is actively issued by the CPU; when it is determined that the to-be-executed memory access request is actively issued by the CPU, triggering the command pipeline to send the to-be-executed memory access request to the target memory. In this way, it is possible to avoid misoperating the target memory in the case of a CPU failure.

[0048] Optionally, when it is determined that the to-be-executed memory access request is not actively issued by the CPU, the to-be-executed memory access request is deleted from the command pipeline.

[0049] Combined with Figure 2 As shown, an embodiment of the present disclosure provides a method for memory access, including:

[0050] Step S201, determining a to-be-executed memory access request from among a number of memory access requests cached in the command pipeline; the memory access request is initiated by a central processing unit CPU;

[0051] Step S202, determining whether the target memory pointed to by the target memory address in the to-be-executed memory access request is in an idle state; determining whether the to-be-executed memory access instruction includes a programming operation instruction;

[0052] Step S203, when the target memory is in an idle state and the to-be-executed memory access request includes a programming operation instruction, determining whether the to-be-executed memory access request is actively issued by the CPU; when the to-be-executed memory access request is actively issued by the CPU, performing step S204, when the to-be-executed memory access request is not actively issued by the CPU, performing step S205;

[0053] Step S204: Trigger the command pipeline to send the programming operation instruction in the to-be-executed memory access request to the target memory; then perform Step S206;

[0054] Step S205: Delete the to-be-executed memory access request from the command pipeline;

[0055] Step S206: Determine whether a flag register is included in the preset storage space;

[0056] Step S207: When the flag register is included in the preset storage space, trigger the target memory to send an interrupt signal to the CPU corresponding to the to-be-executed memory access.

[0057] By using the method for memory access provided by the embodiments of the present disclosure, it is possible to determine whether the command pipeline has sent the programming operation instruction to the target memory by determining the presence or absence of the flag register, and when it is determined that the flag register exists, trigger the target memory to send an interrupt signal to the CPU that initiates the to-be-executed memory access request; furthermore, it is possible to send an interrupt signal to the corresponding CPU every time a memory access request is issued; thus enabling the CPU to know the process status of the memory access; at the same time, by determining whether the to-be-executed memory access request is actively issued by the CPU, the present application can avoid the occurrence of the situation where the CPU misoperates the target memory due to a fault.

[0058] Optionally, determining whether the to-be-executed memory access request is actively issued by the CPU includes: obtaining a second value at a second preset position of the status register, where the second value is used to represent whether the to-be-executed memory access request is actively initiated by the CPU; determining whether the to-be-executed memory access request is actively issued by the CPU according to the second value. This can quickly determine whether the to-be-executed memory access request is actively issued by the CPU.

[0059] In some embodiments, when the CPU initiates a memory access request, it will configure a feature register in the preset space; the second value will change when the configuration of the feature register is completed. In some embodiments, after the CPU configures the feature register in the preset space, the second value changes from "0" to "1". In some embodiments, when it is detected that the second value is "1", it is determined that the to-be-executed memory access request is actively issued by the CPU.

[0060] Optionally, when the memory access request to be executed includes a programming operation instruction, the memory access request to be executed further includes the correspondence between the interrupt data and the preset address; before triggering the target memory to send an interrupt signal to the CPU, it further includes: determining whether the command pipeline sends the interrupt data to the preset address; when it is determined that the command pipeline sends the interrupt data to the preset address, triggering the target memory to send an interrupt signal to the CPU. Since the configuration of the flag register and the sending of the interrupt data are not necessarily synchronized, in order to ensure the accuracy of the interrupt signal, it is necessary to determine whether the flag register is configured and whether the interrupt data has been sent at the same time.

[0061] Combined with Figure 3 As shown, an embodiment of the present disclosure provides a method for memory access, including:

[0062] Step S301, determining a memory access request to be executed among several memory access requests cached in the command pipeline; the memory access request is initiated by a central processing unit (CPU);

[0063] Step S302, determining whether the target memory pointed to by the target memory address in the memory access request to be executed is in an idle state; determining whether the memory access instruction to be executed includes a programming operation instruction;

[0064] Step S303, when the target memory is in an idle state and the memory access request to be executed includes a programming operation instruction, triggering the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory;

[0065] Step S304, determining whether a flag register is included in the preset storage space, where the flag register is used to indicate that the command pipeline has sent the programming operation instruction to the target memory; determining whether the command pipeline sends the interrupt data in the memory access request to be executed to the preset address;

[0066] Step S305, when the flag register is included in the preset storage space and the command pipeline sends the interrupt data to the preset address, triggering the target memory to send an interrupt signal to the CPU corresponding to the memory access to be executed.

[0067] By using the method for memory access provided by the embodiment of the present disclosure, by determining whether the flag register is configured and whether the interrupt data has been sent at the same time, and when it is determined that the flag register exists and the interrupt data has been sent, triggering the target memory to send an interrupt signal to the CPU that initiates the memory access request to be executed; thus, it is possible to send an interrupt signal to the corresponding CPU more accurately every time a memory access request is issued; thereby enabling the CPU to accurately know the process status of the memory access.

[0068] Optionally, after determining whether the memory access request to be executed includes a programming operation instruction, it further includes: when the memory access request to be executed does not include a programming operation instruction and the target memory is in an idle state, triggering the command pipeline to send the memory access request to be executed to the target memory, and triggering the target memory to obtain the target data according to the memory access request to be executed and feedback the target data to the CPU corresponding to the memory access request to be executed. In this way, when the memory access request to be executed is used to read data, the target memory can be triggered to feedback the target data to the CPU corresponding to the memory access request to be executed.

[0069] As shown in combination with Figure 4 The embodiments of the present disclosure provide a method for memory access, including:

[0070] Step S401, determining a memory access request to be executed among several memory access requests cached in the command pipeline; the memory access request is initiated by a central processing unit (CPU);

[0071] Step S402, determining whether the target memory pointed to by the target memory address in the memory access request to be executed is in an idle state; determining whether the memory access instruction to be executed includes a programming operation instruction;

[0072] Step S403, when the target memory is in an idle state and the memory access request to be executed does not include a programming operation instruction, triggering the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory;

[0073] Step S404, triggering the target memory to obtain the target data according to the memory access request to be executed and feedback the target data to the CPU corresponding to the memory access request to be executed.

[0074] By using the method for memory access provided by the embodiments of the present disclosure, when the memory access request to be executed is used to read data, the target memory can be triggered to feedback the target data to the CPU corresponding to the memory access request to be executed.

[0075] In some embodiments, the target memory sends the target data to the response channel. When the response channel receives the target data, it converts the local clock domain frequency of the target data into a high-speed clock domain frequency to obtain the converted data, and sends the converted data to the AXI bus. When the AXI bus receives the converted data, it sends the converted data to the CPU corresponding to the memory access to be executed. Since the AXI bus is from the high-speed clock domain and the target memory is from the local clock domain, and at the same time, the clock domain frequency of the target memory is half of the high-speed clock domain frequency, in order for the CPU to parse the target data, the response channel needs to convert the target data into the converted data.

[0076] Optionally, the target memory address includes row address information and column address information; triggering the target memory to obtain target data according to the memory access request to be executed includes: obtaining the target data from the target memory according to the row address information and the column address information.

[0077] In some embodiments, multiple CPUs initiate memory access requests simultaneously. After sorting the memory access requests through the AXI bus, they are cached in the command pipeline. The memory access request with the earliest order in the command pipeline is determined as the memory access request to be executed. Perform parity check on the target memory address in the memory access request to be executed. When the target memory address passes the check, determine whether the target memory pointed to by the target memory address in the memory access request to be executed is in an idle state, that is, obtain a first value from the first preset position of the status register corresponding to the target memory. When the first value is "0", determine that the target memory is in an idle state; determine whether the memory access request to be executed includes a programming operation instruction. When the memory access request to be executed includes a programming operation instruction, obtain a second value from the second preset position of the status memory. When the second value is "1", determine that the memory access request to be executed is actively issued by the CPU; when the programming operation instruction includes data to be stored, perform data check on the data to be stored. When the data to be stored passes the check, trigger the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory; the target memory receives the programming operation instruction and stores the data to be stored in the programming operation instruction; determine whether the preset storage space includes a flag register; determine whether the command pipeline sends the interrupt data in the memory access request to be executed to the preset address; when the preset storage space includes a flag register and the command pipeline sends the interrupt data to the preset address, trigger the target memory to send an interrupt signal to the CPU. After the target memory stores the data to be stored, the target memory sends response information to the CPU corresponding to the memory access request to be executed through the response channel. This can send an interrupt signal to the corresponding CPU every time a memory access request is issued; thereby enabling the CPU to know the process status of the memory access.

[0078] Combined with Figure 5As shown in the figure, an embodiment of the present disclosure provides a device for memory access, including a first determination module 501, a second determination module 502, a first trigger module 503, a third determination module 504, and a second trigger module 505; the first determination module 501 is configured to determine a memory access request to be executed among several memory access requests cached in a command pipeline; the memory access request is initiated by a central processing unit (CPU); the second determination module 502 is configured to determine whether the target memory pointed to by the target memory address in the memory access request to be executed is in an idle state; and determine whether the memory access instruction to be executed includes a programming operation instruction; the first trigger module 503 is configured to, when the target memory is in an idle state and the memory access request to be executed includes a programming operation instruction, trigger the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory; the third determination module 504 is configured to determine whether a flag register is included in a preset storage space, where the flag register is used to represent that the command pipeline has sent the programming operation instruction to the target memory; the second trigger module 505 is configured to, when the flag register is included in the preset storage space, trigger the target memory to send an interrupt signal to the CPU corresponding to the memory access request to be executed.

[0079] In the device for memory access provided by the embodiment of the present disclosure, after the first trigger module triggers the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory, the third determination module determines whether a flag register is included in the preset storage space. Since the flag register is used to represent that the command pipeline has sent the programming operation instruction to the target memory, it can be determined whether the command pipeline has sent the programming operation instruction to the target memory based on the presence or absence of the flag register. When the third determination module determines that the flag register exists, the second trigger module triggers the target memory to send an interrupt signal to the CPU that initiated the memory access request to be executed. In this way, an interrupt signal can be sent to the corresponding CPU every time a memory access request is issued, so that the CPU can know the process status of the memory access.

[0080] Optionally, the second determination module is configured to determine whether the target memory pointed to by the target memory address in the memory access request to be executed is in an idle state in the following manner: obtain a first value at a first preset position of a status register corresponding to the target memory; the first value is used to represent the current state of the target memory; and determine whether the target memory is in an idle state according to the value.

[0081] Optionally, the second determination module is further configured to determine whether the memory access request to be executed is actively issued by the CPU before the first trigger module triggers the command pipeline to send the memory access request to be executed to the target memory.

[0082] Optionally, the first trigger module is configured to trigger the command pipeline to send the programming operation instruction in the to-be-executed memory access request to the target memory when the target memory is in an idle state, the to-be-executed memory access request includes a programming operation instruction, and the to-be-executed memory access request is actively issued by the CPU.

[0083] Optionally, the second determination module is configured to determine whether the to-be-executed memory access request is actively issued by the CPU in the following manner: obtain a second value at a second preset position of the status register, where the second value is used to represent whether the to-be-executed memory access request is actively initiated by the CPU; and determine whether the to-be-executed memory access request is actively issued by the CPU according to the second value.

[0084] The apparatus for memory access further includes a fourth determination module, which is configured to determine whether the command pipeline sends interrupt data to a preset address.

[0085] Optionally, the second trigger module is configured to trigger the target memory to send an interrupt signal to the CPU corresponding to the to-be-executed memory access when a flag register is included in the preset storage space and it is determined that the command pipeline sends the interrupt data to the preset address.

[0086] Optionally, the first trigger module is further configured to trigger the command pipeline to send the to-be-executed memory access request to the target memory when the to-be-executed memory access request does not include a programming operation instruction and the target memory is in an idle state; and trigger the target memory to obtain target data according to the to-be-executed memory access request and feedback the target data to the CPU corresponding to the to-be-executed memory access request.

[0087] Combined Figure 6 As shown, an embodiment of the present disclosure provides an apparatus for memory access, including a processor 600 and a memory 601. Optionally, the apparatus may further include a communication interface 602 and a bus 603. Among them, the processor 600, the communication interface 602, and the memory 601 can complete mutual communication through the bus 603. The communication interface 602 can be used for information transmission. The processor 600 can call the logical instructions in the memory 601 to execute the method for memory access in the above embodiment.

[0088] By using the device for memory access provided in the embodiments of the present disclosure, after sending the programming operation instruction in the to-be-executed memory access request to the target memory through the trigger command pipeline, it is determined whether a flag register is included in the preset storage space. Since the flag register is used to represent that the command pipeline has sent the programming operation instruction to the target memory; therefore, whether the command pipeline has sent the programming operation instruction to the target memory can be determined by the presence or absence of the flag register, and when it is determined that the flag register exists, the target memory is triggered to send an interrupt signal to the CPU that initiates the to-be-executed memory access request; in this way, an interrupt signal can be sent to the corresponding CPU every time a memory access request is issued; thereby enabling the CPU to know the process status of the memory access.

[0089] In addition, when the logical instructions in the above-mentioned memory 601 can be implemented in the form of software functional units and sold or used as an independent product, they can be stored in a computer-readable storage medium.

[0090] As a computer-readable storage medium, the memory 601 can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. The processor 600 executes functional applications and data processing by running the program instructions / modules stored in the memory 601, that is, implements the method for memory access in the above embodiments.

[0091] The memory 601 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 601 may include high-speed random access memory and may also include non-volatile memory.

[0092] The embodiments of the present disclosure provide an electronic device including the above-mentioned device for memory access.

[0093] By using the electronic device provided in the embodiments of the present disclosure, after sending the programming operation instruction in the to-be-executed memory access request to the target memory through the trigger command pipeline, it is determined whether a flag register is included in the preset storage space. Since the flag register is used to represent that the command pipeline has sent the programming operation instruction to the target memory; therefore, whether the command pipeline has sent the programming operation instruction to the target memory can be determined by the presence or absence of the flag register, and when it is determined that the flag register exists, the target memory is triggered to send an interrupt signal to the CPU that initiates the to-be-executed memory access request; in this way, an interrupt signal can be sent to the corresponding CPU every time a memory access request is issued; thereby enabling the CPU to know the process status of the memory access.

[0094] Optionally, the electronic device is a computer, a mobile phone, a tablet computer, or the like.

[0095] An embodiment of the present disclosure provides a computer-readable storage medium storing program instructions that, when running, execute the above-described method for memory access.

[0096] An embodiment of the present disclosure provides a computer program product. The computer program product includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions that, when executed by a computer, cause the computer to execute the above-described method for memory access.

[0097] The above-mentioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transient computer-readable storage medium.

[0098] The technical solution of an embodiment of the present disclosure may be embodied in the form of a software product. The computer software product is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The foregoing storage medium may be a non-transient storage medium, including: various media that can store program codes such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc, or may also be a transient storage medium.

[0099] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure, enabling those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process, and other changes. Embodiments merely represent possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terms used in this application are only for describing embodiments and do not limit the claims. As used in the description of embodiments and claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to also include the plural forms. Similarly, as used in this application, the term "and / or" refers to any and all possible combinations of one or more of the associated listed items. Additionally, when used in this application, the term "comprise" and its variants "comprises" and / or "comprising" etc. mean the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, or device comprising the element. Herein, each embodiment may focus on the differences from other embodiments, and the same or similar parts among the embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method parts disclosed in the embodiments, the relevant parts may refer to the description of the method parts.

[0100] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner may depend on the specific application and design constraints of the technical solution. The skilled person may use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the embodiments of the present disclosure. The skilled person can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0101] In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units can be merely a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Additionally, the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms. The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to implement this embodiment. Additionally, in the embodiments of the present disclosure, the various functional units can be integrated in one processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0102] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions marked in the blocks can occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks can also occur in a different order than that disclosed in the description. Sometimes, there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, which can depend on the functions involved. Each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A method for memory access, characterized in that, Including: Determine a memory access request to be executed among several memory access requests cached in a command pipeline; The memory access request is initiated by a central processing unit (CPU); Determine whether a target memory pointed to by a target memory address in the memory access request to be executed is in an idle state; Determine whether the memory access instruction to be executed includes a programming operation instruction; When the target memory is in an idle state and the memory access request to be executed includes a programming operation instruction, trigger the command pipeline to send the programming operation instruction in the memory access request to be executed to the target memory; Determine whether a flag register is included in a preset storage space, where the flag register is used to represent that the command pipeline has sent the programming operation instruction to the target memory; When the flag register is included in the preset storage space, trigger the target memory to send an interrupt signal to the CPU corresponding to the memory access request to be executed.

2. The method according to claim 1, wherein Determining whether a target memory pointed to by a target memory address in the memory access request to be executed is in an idle state includes: Obtain a first value at a first preset position of a status register corresponding to the target memory; the first value is used to represent the current state of the target memory; Determine whether the target memory is in an idle state according to the value.

3. The method according to claim 2, characterized in that, Before triggering the command pipeline to send the memory access request to be executed to the target memory, it further includes: Determine whether the memory access request to be executed is actively issued by the CPU; When it is determined that the memory access request to be executed is actively issued by the CPU, trigger the command pipeline to send the memory access request to be executed to the target memory.

4. The method according to claim 3, wherein Determining whether the memory access request to be executed is actively issued by the CPU includes: Obtain a second value at a second preset position of the status register, where the second value is used to represent whether the memory access request to be executed is actively initiated by the CPU; Determine whether the memory access request to be executed is actively issued by the CPU according to the second value.

5. The method according to claim 1, characterized in that, When the memory access request to be executed includes a programming operation instruction, the memory access request to be executed further includes a correspondence between interrupt data and a preset address; Before triggering the target memory to send an interrupt signal to the CPU, it further includes: Determine whether the command pipeline sends the interrupt data to the preset address; When it is determined that the command pipeline sends the interrupt data to the preset address, trigger the target memory to send an interrupt signal to the CPU.

6. The method according to claim 1, wherein After determining whether the memory access request to be executed includes a programming operation instruction, it further includes: When the memory access request to be executed does not include a programming operation instruction and the target memory is in an idle state, trigger the command pipeline to send the memory access request to be executed to the target memory; trigger the target memory to obtain target data according to the memory access request to be executed and feed back the target data to the CPU corresponding to the memory access request to be executed.

7. A device for memory access, characterized in that, Including: A first determination module configured to determine a memory access request to be executed among several memory access requests cached in a command pipeline; The memory access request is initiated by a central processing unit (CPU). A second determination module, configured to determine whether a target memory pointed to by a target memory address in the to-be-executed memory access request is in an idle state; Determine whether the to-be-executed memory access instruction includes a programming operation instruction; A first trigger module, configured to trigger the command pipeline to send the programming operation instruction in the to-be-executed memory access request to the target memory when the target memory is in an idle state and the to-be-executed memory access request includes a programming operation instruction; A third determination module, configured to determine whether a flag register is included in a preset storage space, where the flag register is used to represent that the command pipeline has sent the programming operation instruction to the target memory; A second trigger module, configured to trigger the target memory to send an interrupt signal to the CPU corresponding to the to-be-executed memory access when the flag register is included in the preset storage space.

8. A device for memory access, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute the method for memory access according to any one of claims 1 to 6 when running the program instruction.

9. An electronic device, characterized in that, Includes the device for memory access according to claim 8.

10. A storage medium stores program instructions, characterized in that, When the program instruction is running, it executes the method for memory access according to any one of claims 1 to 6.

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