Detection Method for N-bit Analog-to-Digital Converter

Abstract

A detection method for an N-bit analog-to-digital converter, the detection method comprising: selecting continuous M bits to be measured according to the static integral nonlinearity error requirement of the N-bit analog-to-digital converter to be measured, wherein at least one of the M bits to be measured is a non-exact bit, and determining a determination condition for the integral nonlinearity error of the M bits to be measured, where M and N are positive integers, and M < N; performing an integral nonlinearity error test on the M bits to be measured; in response to the measured integral nonlinearity error satisfying the determination condition, confirming that the N-bit analog-to-digital converter is qualified, and in response to the measured integral nonlinearity error not satisfying the determination condition, confirming that the N-bit analog-to-digital converter is unqualified.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit testing, and more particularly, to a method for detecting an N-bit analog-to-digital converter. Background Art

[0002] An analog-to-digital convertor (ADC) is a chip that converts analog signals into digital signals. Performance testing of such chips mainly includes dynamic parameters such as signal-to-noise ratio (SNR) and total harmonic distortion (THD), and static parameters such as differential non-linearity (DNL) and integral non-linearity (INL).

[0003] Testing an analog-to-digital converter is one of the most challenging tasks. The differential non-linearity (DNL) and integral non-linearity (INL) of an analog-to-digital converter are parameters used to describe the correctness of each conversion code in the static characteristics of the analog-to-digital converter, and play very important roles in various application fields. The long test time and expensive test instruments make it a difficult and costly task to test the static characteristics of high-precision analog-to-digital converters. Summary of the Invention

[0004] Some embodiments of the present disclosure provide a method for detecting an N-bit analog-to-digital converter, characterized in that the detection method includes:

[0005] Selecting M consecutive bits to be measured according to the static integral non-linearity requirement of the N-bit analog-to-digital converter to be measured, where at least one of the M bits to be measured is a non-exact bit, and determining the determination condition for the integral non-linearity of the M bits to be measured, where M and N are positive integers, and M < N;

[0006] Performing an integral non-linearity test on the M bits to be measured;

[0007] If the measured integral non-linearity meets the determination condition, it is confirmed that the N-bit analog-to-digital converter is qualified; if the measured integral non-linearity does not meet the determination condition, it is confirmed that the N-bit analog-to-digital converter is unqualified.

[0008] In some embodiments, selecting M consecutive bits to be measured according to the static integral non-linearity requirement of the N-bit analog-to-digital converter to be measured, where at least one of the M bits to be measured is a non-exact bit, and determining the determination condition for the integral non-linearity of the M bits to be measured includes:

[0009] Determining the 1st to Jth bits from low to high among the N bits as non-exact bits according to the static integral non-linearity requirement of the N-bit analog-to-digital converter to be measured;

[0010] Starting from the (J - I)-th bit, M bits are sequentially selected as the bits to be measured, where the (J - I)-th bit to the J-th bit are the non-exact bits among the M bits to be measured. Here, J is a positive integer, I is a natural number, and I < J < N, and I < M; and

[0011] The determination condition for the integral nonlinearity error of the M bits to be measured is:

[0012] INL M < (2 I+1 - 1)LSB M

[0013] where, INL M is the integral nonlinearity error of the M bits to be measured, and LSB M is the least significant bit of the M bits to be measured.

[0014] In some embodiments, the integral nonlinearity error test for the M bits to be measured includes:

[0015] Using a DC linear ramp voltage with a predetermined frequency to perform an integral nonlinearity error test on the M bits to be measured of the N-bit analog-to-digital converter. Here, the voltage range of the ramp voltage is 0 to V M where, V M = 2 M+J-I-1 / 2 N ·V N where, V N is the full-scale voltage of the N-bit analog-to-digital converter.

[0016] In some embodiments, the integral nonlinearity error test for the M bits to be measured includes:

[0017] Using a DC linear ramp voltage with a predetermined frequency to perform an integral nonlinearity error test on the M bits to be measured of the N-bit analog-to-digital converter. Here, the voltage range of the ramp voltage is V J-I to V M where, V J-I = 2 J-I / 2 N ·V N , V M = 2 M+J-I-1 / 2 N ·V N where, V N is the full-scale voltage of the N-bit analog-to-digital converter.

[0018] In some embodiments, the integral nonlinearity error test for the M bits to be measured further includes: sampling each code in the M bits to be measured once or more times.

[0019] In some embodiments, the integral non - linear error test for the M bits to be measured further includes: sampling each code in the M bits to be measured once or more times.

[0020] In some embodiments, the integral non - linear error INL of the M bits to be measured M is determined by the following formula:

[0021]

[0022] where h(i) THEORETICAL is the number of times the i - th code occurs in the ideal circuit case, h(i) THEORETICAL = MT / (2 M – 2), h(i) ACTUAL represents the actual number of times the i - th code occurs, MT represents the total number of acquisitions, and i = 1, 2, … 2 M – 2.

[0023] Some embodiments of the present disclosure provide a computer - readable storage medium, on which a computer program is stored, characterized in that when the program is executed by a processor, the detection method described in the foregoing embodiments is implemented.

[0024] Some embodiments of the present disclosure provide an electronic device, characterized in that it includes:

[0025] One or more processors;

[0026] A storage device for storing one or more programs, and when the one or more programs are executed by the one or more processors, the one or more processors implement the detection method as described in the foregoing embodiments.

[0027] The above - mentioned solution of the embodiments of the present disclosure has at least the following beneficial effects compared with the related art:

[0028] By selecting some bits of a high - precision analog - to - digital converter as test bits to detect the high - precision analog - to - digital converter, rapid detection of the high - precision analog - to - digital converter can be achieved, and the mass - production detection efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts. In the drawings:

[0030] Figure 1Flowchart of the detection method for an N-bit analog-to-digital converter provided by some embodiments of the present disclosure;

[0031] Figure 2 For Figure 1 Specific flowchart of step S10 in

[0032] Figure 3 Schematic diagram of binary digits provided by some embodiments of the present disclosure;

[0033] Figure 4 Test result graph provided by some embodiments of the present disclosure;

[0034] Figure 5 Structural diagram of an electronic device provided by some embodiments of the present disclosure. Detailed implementation manners

[0035] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings. Apparently, the described embodiments are only some of the embodiments of the present disclosure, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0036] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. The singular forms "a", "the" and "said" used in the embodiments of the present disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. "Plural" generally includes at least two.

[0037] It should be understood that the term " / and / " used herein is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0038] It should be understood that although terms such as first, second, and third may be used in the embodiments of the present disclosure, these should not be limited to these terms. These terms are only used to distinguish. For example, without departing from the scope of the embodiments of the present disclosure, the first may also be referred to as the second, and similarly, the second may also be referred to as the first.

[0039] It should also be noted that the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a commodity or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such commodity or device. Without further limitation, an element defined by the statement "including one" does not exclude the presence of additional identical elements in the commodity or device including said element.

[0040] The analog-to-digital converter is an extremely critical component module in the current two major systems of analog-digital hybrid signals and digital signal processing. In recent years, with the rapid development of SOC technology and the communication industry, the performance requirements for analog-to-digital converters have become increasingly high. Among them, the pipelined analog-to-digital converter has been widely used in various fields, such as radio frequency technology, multimedia data processing, and automated test instruments, because it can simultaneously meet the performance requirements of high speed and high precision. For analog-to-digital converter manufacturers who need to evaluate the quality of such devices, the test time is one of the most important concerns. How to quickly and effectively test high-speed and high-precision analog-to-digital converters is directly related to the production cycle and service life of the chip, and indirectly affects the market recognition of the chip. For high-speed and high-precision analog-to-digital converter chips, their design and process manufacturing costs already account for a large part. If the test time cannot be guaranteed to be short enough in the chip test process, the total cost will increase significantly. Therefore, in order to improve the reliability of the product and considering the test cost, the biggest current obstacle lies in the lack of an effective fast test method for high-speed and high-precision analog-to-digital converters.

[0041] The differential non-linearity error of the related technology analog-to-digital converter is defined as the difference between the actual quantization step and the ideal value corresponding to 1 LSB, where LSB is the least significant bit of the analog-to-digital converter. For an ideal analog-to-digital converter, its differential non-linearity error DNL = 0 LSB (each analog quantization step is equal to LSB = V FSR / 2 N , where V FSR is the full-scale voltage, N is the resolution of the analog-to-digital converter, and the interval between the jump values is 1 LSB). If the differential non-linearity error index DNL ≤ 1 LSB, it means that the transfer function has guaranteed monotonicity and no code loss. The integral non-linearity error represents the degree to which the actual transfer function deviates from a straight line, and is measured as a percentage of LSB or full-scale range (FSR). The integral non-linearity error can more truly describe the linear characteristics of the device under test.

[0042] The integral non-linearity error test is usually a full-code linear test. The test method is: by inputting a ramp wave with a low signal frequency of full scale, sampling to obtain the actual digital output signal, and determining the integral non-linearity error result by comparing the measured transfer characteristic with the ideal transfer characteristic.

[0043] Since the number of bits of a high-precision analog-to-digital converter is relatively large, usually greater than 20 bits, the number of codes needs to be at least greater than 2 N , where N is the number of bits of the high-precision analog-to-digital converter. Taking a 24-bit (bit) analog-to-digital converter as an example, the number of codes needs to be at least greater than 16777216. Moreover, the operating frequency of the high-precision analog-to-digital converter chip is relatively low, usually in the dozens of Hz. Using the above traditional integral nonlinear error parameter testing method takes dozens of hours, and the mass production testing efficiency and cost are unaffordable.

[0044] Some embodiments of the present disclosure provide a method for detecting an N-bit analog-to-digital converter. The detection method includes: selecting consecutive M bits to be measured according to the static integral nonlinearity requirement of the N-bit analog-to-digital converter to be measured, where at least one of the M bits to be measured is an inaccurate bit, and determining a determination condition for the integral nonlinearity of the M bits to be measured, where M and N are positive integers, and M < N; performing an integral nonlinearity test on the M bits to be measured; in response to the measured integral nonlinearity satisfying the determination condition, confirming that the N-bit analog-to-digital converter is qualified, and in response to the measured integral nonlinearity not satisfying the determination condition, confirming that the N-bit analog-to-digital converter is unqualified. By selecting some bits of the high-precision analog-to-digital converter as test bits to detect the high-precision analog-to-digital converter, rapid detection of the high-precision analog-to-digital converter can be achieved, and the mass production detection efficiency can be improved.

[0045] The optional embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0046] Figure 1 It is a flowchart of a method for detecting an N-bit analog-to-digital converter provided by some embodiments of the present disclosure. As Figure 1 shown, the present disclosure provides a method for detecting an N-bit analog-to-digital converter, where N is a positive integer, and the value of N is usually greater than or equal to 20, that is, the N-bit analog-to-digital converter is a high-precision analog-to-digital converter. The detection method includes the following steps:

[0047] S10: Select consecutive M bits to be measured according to the static integral nonlinear error requirement of the N-bit analog-to-digital converter to be measured, where at least one of the M bits to be measured is an inaccurate bit, and determine a determination condition for the integral nonlinear error of the M bits to be measured, where M and N are positive integers, and M < N;

[0048] S30: Perform an integral nonlinear error test on the M bits to be measured;

[0049] S50: Determine whether the N-bit analog-to-digital converter is qualified based on whether the measured integral non-linearity error meets the determination condition. Specifically, in response to the measured integral non-linearity error meeting the determination condition, confirm that the N-bit analog-to-digital converter is qualified; in response to the measured integral non-linearity error not meeting the determination condition, confirm that the N-bit analog-to-digital converter is unqualified.

[0050] As Figure 2 shown in Figure 1 is the specific flowchart of step S10. As Figure 2 shown, step S10 specifically includes the following steps:

[0051] S11: Determine that the 1st to Jth bits from low to high in the N bits are non-exact bits according to the static integral non-linearity error requirement of the N-bit analog-to-digital converter to be measured, where J is a positive integer and 0 < J < N;

[0052] Specifically, taking a 24-bit high-precision analog-to-digital converter chip as an example, that is, N = 24. From the chip's data sheet, it can be seen that the full-scale input amplitude of the chip is 5V. Under the condition that the chip operating frequency < 60Hz, the differential non-linearity error requirement is less than or equal to 1 LSB, and the integral non-linearity error requirement is "±0.0015% of FSR", where FSR represents the full scale.

[0053] From this, the integral non-linearity error INL can be calculated as INL = ±0.0015% × 2 24 = ±0.0015% × 16777216 ≈ ±256 = 512 codes. 512 is the 9th power of 2. From this, it can be known that the chip allows the 1st to 9th bits from low to high in the 24 bits to be non-exact bits. Figure 3 is a schematic diagram of binary digits provided by some embodiments of the present disclosure. As Figure 3 shown, the 1st to 24th bits are arranged in sequence from right to left. In the figure, △ and ▲ are used to represent bits, that is, each △ and ▲ represents 1 bit, ▲ represents a non-exact bit, and △ represents an exact bit. As Figure 3 shown, according to the integral non-linearity error requirement of the chip, among the 24 bits, the 1st to 9th bits are non-exact bits, and the 10th to 24th bits are exact bits.

[0054] S13: Sequentially select M bits as the bits to be measured starting from the (J - I)th bit, where the (J - I)th to Jth bits are non-exact bits among the M bits to be measured, where J is a positive integer, I is a natural number, and 0 ≤ I < J < N, and I < M.

[0055] Specifically, taking I = 1 and M = 8 as an example for explanation, sequentially select 8 bits starting from the 8th bit as the bits to be measured. As Figure 3As shown, the 8th to 15th bits enclosed are the bits to be measured. The selection of I and M is based on the actual needs of the test. The value of I determines the determination condition of the integral non - linear error of the M - bit bits to be measured mentioned later, and the value of M determines the test time. In other embodiments, I can also be, for example, 0, 2, etc., and M can be, for example, 7, 9, 10, 11, 12, etc.

[0056] S15: Determine that the determination condition for the integral non - linear error of the M - bit bits to be measured is: INL M <(2 I+1 -1)LSB M where, INL M is the integral non - linear error of the M - bit bits to be measured, and LSB M is the least significant bit of the M - bit bits to be measured.

[0057] Specifically, taking I = 1 and M = 8 as an example for explanation, since there are two non - exact bits, namely the 8th and 9th bits, and six exact bits, namely the 10th to 15th bits, among the 8 - bit bits to be measured, the determination condition for the integral non - linear error of the 8 - bit bits to be measured is: INL < 3LSB.

[0058] In step S30, specifically, in some embodiments, a DC linear ramp voltage with a predetermined frequency is used to test the integral non - linear error of the M - bit bits to be measured of the N - bit analog - to - digital converter. Among them, the voltage range of the ramp voltage is V J-I ~V M , where, V J-I = 2 J-I / 2 N ·V N , V M = 2 M+J-I-1 / 2 N ·V N , where, V N is the full - scale voltage of the N - bit analog - to - digital converter, for example, 5V. Thus, the test result (qualified / unqualified) of the M - bit bits to be measured can be equivalent to the test result (qualified / unqualified) of the N - bit analog - to - digital converter.

[0059] Taking a 24 - bit high - precision analog - to - digital converter chip as an example, that is, N = 24, M is, for example, 8, and I is, for example, 1. A DC linear ramp voltage with a predetermined frequency is used to test the integral non - linear error of the 8 - bit bits to be measured of the high - precision analog - to - digital converter. The frequency of the ramp voltage is, for example, 60Hz, and the voltage range of the ramp voltage is 0.015mV~9.8mV.

[0060] In some embodiments, a DC linear ramp voltage with a predetermined frequency is used to test the integral nonlinearity error of the M bits to be measured of the N-bit analog-to-digital converter, where the voltage range of the ramp voltage is 0 to V M , where V M = 2 M+J-I-1 / 2 N ·V N , where V N is the full-scale voltage of the N-bit analog-to-digital converter. Since the value of V J-I is very small, the starting point of the ramp voltage can be set to 0, and 0 to V J-I corresponds to the voltages corresponding to the 1st to the (J - I - 1)th bits, and the 1st to the (J - I - 1)th bits are discarded non-detected bits.

[0061] Taking a 24-bit high-precision analog-to-digital converter chip as an example, that is, N = 24, M is, for example, 8, and I is, for example, 1, a DC linear ramp voltage with a predetermined frequency is used to test the integral nonlinearity error of the 8 bits to be measured of the high-precision analog-to-digital converter. The frequency of the ramp voltage is, for example, 60 Hz, and the voltage range of the ramp voltage is 0 to 9.8 mV. Considering the actual test situation, usually the maximum value of the ramp voltage to be used is slightly enlarged to ensure meeting the test requirements. For example, the voltage range of the ramp voltage is 0 to 10 mV.

[0062] In some embodiments, each code of the M bits to be measured is sampled once or more times. For example, a digital instrument is used to collect the digital signal output by the chip. Each code uses, for example, 12 samples. When M = 8, the number of codes is 256, and the total number of samples is 3072. It takes about 52 seconds to complete the test of one chip. Compared with the full-code test of the chip, when N = 24, the number of codes is 16777216. Even if each code is collected with 1 sample, it takes about 77 hours to complete the test of one chip. Thus, it can be seen that the method of the present disclosure can significantly improve the test efficiency of the high-precision analog-to-digital converter chip.

[0063] In step S50, for example, it is determined whether the N-bit analog-to-digital converter is qualified by a chip tester collecting the digital signal output by the chip through a digitizer.

[0064] Figure 4 This is the test result diagram provided by some embodiments of the present disclosure. Taking the test of a 24-bit high-precision analog-to-digital converter chip as an example, where N = 24, M = 8, J = 9, and I = 1. As Figure 4As shown in (A) of , when the test waveform output by the chip under test is basically a continuous slanted line, and after magnification it is basically a continuous stepped shape, and the measured INL value is 1.7385 LSB, which meets the determination condition for integral non - linear error: INL < 3 LSB. Thus, it can be considered that this high - precision analog - to - digital converter chip is qualified. As Figure 4 As shown in (B) of , when the test waveform output by the chip under test is discontinuous, and the measured INL value is 121.475 LSB, which does not meet the determination condition for integral non - linear error: INL < 3 LSB. Thus, it can be considered that this high - precision analog - to - digital converter chip is unqualified.

[0065] The following specifically introduces the test principles of differential non - linear error (DNL) and integral non - linear error (INL). The linear ramp histogram test method is used to test differential non - linear error (DNL) and integral non - linear error (INL). A rising or falling linear ramp is input to the analog input of the analog - to - digital converter, and the analog - to - digital converter samples at a fixed sampling rate. Since each code has the same probability of occurrence, ideally the number of occurrences of each code should be the same (except at both ends). The number of occurrences of each code is plotted as a histogram. If the number of occurrences of a code is large, it means its quantization step is wide, otherwise it is narrow.

[0066] Let MT represent the total number of samples collected (excluding the samples at both ends), and h(i) represent the number of occurrences of the i - th code, where i = 1, 2, … 2 M -2, and M is the number of consecutive test bits. In an ideal circuit situation, the number of occurrences of the i - th code h(i) THEORETICAL = MT / (2 M – 2). If h(i) ACTUAL represents the actual number of occurrences of the i - th code, then the differential non - linear error DNL can be calculated using the following formula:

[0067]

[0068] The integral non - linear error INL M is obtained by accumulating DNL;

[0069]

[0070] Embodiments of the present disclosure provide a non - volatile computer storage medium. The computer storage medium stores computer - executable instructions, and these computer - executable instructions can execute the method steps as described in the above embodiments.

[0071] The present disclosure provides a computer program product, including a computer program, and the computer program realizes the method as described in the above embodiments when executed by a processor.

[0072] As Figure 5As shown, this embodiment provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method steps described in the above embodiment.

[0073] Refer to the following Figure 5 , which shows a schematic structural diagram of an electronic device suitable for implementing the embodiments of the present disclosure. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The electronic device shown is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0074] As Figure 5 shown, the electronic device may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 501, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 502 or the program loaded from the storage device 508 into the random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the electronic device are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. The input / output (I / O) interface 505 is also connected to the bus 504.

[0075] Generally, the following devices may be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 5011 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 508 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 509. The communication device 509 may allow the electronic device to communicate with other devices wirelessly or wirelesly to exchange data. Although Figure 5 the electronic device with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. Instead, more or fewer devices may be implemented or had.

[0076] In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, an embodiment of the present disclosure includes a computer program product that includes a computer program carried on a computer-readable medium, and the computer program includes program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device 509, or installed from a storage device 508, or installed from a ROM 502. When the computer program is executed by a processing device 501, the above functions defined in the method of the embodiment of the present disclosure are performed.

[0077] It should be noted that the above computer-readable medium in the present disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of a computer-readable storage medium can include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. And in the present disclosure, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, and the computer-readable signal medium can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0078] The above computer-readable medium can be included in the above electronic device; or it can exist separately without being assembled into the electronic device.

[0079] Computer program code for performing the operations of this disclosure may be written in one or more programming languages or combinations thereof. The foregoing programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0080] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur in a different order than noted in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0081] Finally, it should be noted that the various embodiments in this specification are described by way of examples. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments may be referred to each other. For the systems or devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference may be made to the description in the method section.

[0082] The above embodiments are only used to illustrate the technical solutions of this disclosure, rather than to limit them; although this disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of this disclosure.

Claims

1. A detection method for an N-bit analog-to-digital converter, characterized in that The detection method includes: Selecting M consecutive bits to be measured according to the static integral nonlinear error requirement of the N-bit analog-to-digital converter to be measured, where at least one of the M bits to be measured is an inaccurate bit, and determining the determination condition for the integral nonlinear error of the M bits to be measured, where M and N are positive integers and M < N; Performing an integral nonlinear error test on the M bits to be measured; In response to the measured integral nonlinear error satisfying the determination condition, it is confirmed that the N-bit analog-to-digital converter is qualified, and in response to the measured integral nonlinear error not satisfying the determination condition, it is confirmed that the N-bit analog-to-digital converter is unqualified, wherein, selecting M consecutive bits to be measured according to the static integral nonlinear error requirement of the N-bit analog-to-digital converter to be measured, where at least one of the M bits to be measured is an inaccurate bit, and determining the determination condition for the integral nonlinear error of the M bits to be measured includes; Determining the 1st to Jth bits from low to high among the N bits as inaccurate bits according to the static integral nonlinear error requirement of the N-bit analog-to-digital converter to be measured; Sequentially selecting M bits starting from the (J - I)th bit as the bits to be measured, where the (J - I)th to Jth bits are the inaccurate bits among the M bits to be measured, where J is a positive integer, I is a natural number, and I < J < N, and I < M; and Determining the determination condition for the integral nonlinear error of the M bits to be measured as: INL M <(2 I+1 -1)LSB M Among them, INL M is the integral nonlinearity error of the M bits to be measured, and LSB M is the least significant bit of the M bits to be measured.

2. The detection method according to claim 1, wherein, Performing an integral nonlinear error test on the M bits to be measured includes: Integrate the non - linear error of the M bits to be measured of the N - bit analog - to - digital converter using a DC linear ramp voltage with a predetermined frequency, where the voltage range of the ramp voltage is 0 to V M , where, V M = 2 M+J-I-1 / 2 N ·V N , where, V N is the full - scale voltage of the N - bit analog - to - digital converter.

3. The detection method according to claim 1, wherein, Performing an integral nonlinear error test on the M bits to be measured includes: Integrate and test the nonlinear error of the M bits to be measured of the N-bit analog-to-digital converter using a DC linear ramp voltage with a predetermined frequency. Among them, the voltage range of the ramp voltage is V J-I ~V M , where V J-I =2 J-I / 2 N ·V N , V M =2 M+J-I-1 / 2 N ·V N , where V N is the full-scale voltage of the N-bit analog-to-digital converter.

4. The detection method according to claim 2, wherein, Performing an integral nonlinear error test on the M bits to be measured further includes: sampling each code of the M bits to be measured once or more times.

5. The detection method according to claim 3, wherein, Performing an integral nonlinear error test on the M bits to be measured further includes: sampling each code of the M bits to be measured once or more times.

6. The detection method according to claim 1, wherein The integral nonlinearity error INL of the M bits to be measured M is determined by the following formula: Among them, h(i) THEORETICAL is the number of times the i-th code occurs in the ideal circuit case, and h(i) THEORETICAL = MT / (2 M – 2), and h(i) ACTUAL represents the actual number of times the i-th code occurs, MT represents the total number of times collected, and i = 1, 2, … 2 M – 2.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by a processor, it implements the detection method according to any one of claims 1 to 6.

8. An electronic device, characterized in that, Including: One or more processors; A storage device for storing one or more programs, which when executed by the one or more processors, cause the one or more processors to implement the detection method according to any one of claims 1 to 6.

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