Circuit testing method and apparatus

Abstract

Embodiments of the present application provide a circuit test method and device. The method comprises: compiling a to-be-tested circuit to obtain first compilation information, the first compilation information comprising a plurality of first resource positions corresponding to the to-be-tested circuit; compiling a reference circuit corresponding to the to-be-tested circuit to obtain second compilation information, the second compilation information comprising a plurality of second resource positions corresponding to the reference circuit; determining functional difference information between the to-be-tested circuit and the reference circuit according to the first compilation information and the second compilation information; and determining a test result corresponding to the to-be-tested circuit according to a target function corresponding to the to-be-tested circuit, a reference function corresponding to the reference circuit, and the functional difference information. The test result corresponding to the to-be-tested circuit can be determined only through functional simulation verification. Therefore, the verification efficiency of the to-be-tested circuit is improved and the verification period is shortened.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of automatic control, and particularly relate to a circuit testing method and device. BACKGROUND

[0002] To ensure the performance and reliability of a functional circuit implemented by a static random-access memory (SRAM) type field programmable gate array (FPGA), the functional circuit usually needs to be designed and verified before use.

[0003] In the verification process, when it is determined that the functional circuit cannot implement a preset function, the design parameters in the functional circuit usually need to be debugged and modified so that the functional circuit can implement the preset function. In the prior art, even if only one design parameter in the functional circuit is changed, the functional circuit still needs to be comprehensively verified again when the functional circuit is verified, and the comprehensive verification includes timing simulation verification and functional simulation verification.

[0004] However, since the timing simulation verification and the functional simulation verification are both needed for the functional circuit, the verification efficiency of the functional circuit is low. SUMMARY

[0005] Embodiments of the present application provide a circuit testing method and device to overcome the problem of low verification efficiency.

[0006] In a first aspect, an embodiment of the present application provides a circuit testing method, comprising:

[0007] compiling a to-be-tested circuit to obtain first compilation information, the first compilation information comprising a plurality of first resource positions corresponding to the to-be-tested circuit;

[0008] compiling a reference circuit corresponding to the to-be-tested circuit to obtain second compilation information, the second compilation information comprising a plurality of second resource positions corresponding to the reference circuit;

[0009] determining functional difference information between the to-be-tested circuit and the reference circuit according to the first compilation information and the second compilation information;

[0010] determining a test result corresponding to the to-be-tested circuit according to a target function corresponding to the to-be-tested circuit, a reference function corresponding to the reference circuit, and the functional difference information.

[0011] In a possible design, the determining the test result corresponding to the to-be-tested circuit according to the target function corresponding to the to-be-tested circuit, the reference function corresponding to the reference circuit, and the function difference information includes:

[0012] determining a test function corresponding to the to-be-tested circuit according to the reference function and the function difference information;

[0013] determining the test result of the to-be-tested circuit according to the test function and the target function.

[0014] In a possible design, the determining the test result of the to-be-tested circuit according to the test function and the target function includes:

[0015] if the test function is the same as the target function, determining that the test result is test success;

[0016] if the test function is not the same as the target function, determining that the test result is test failure.

[0017] In a possible design, the determining the function difference information between the to-be-tested circuit and the reference circuit according to the first compilation information and the second compilation information includes:

[0018] obtaining a correspondence between circuit resources and resource positions, the correspondence including a plurality of circuit resources and a resource position corresponding to each circuit resource;

[0019] determining a plurality of first circuit resources according to the first compilation information and the correspondence;

[0020] determining a plurality of second circuit resources according to the second compilation information and the correspondence;

[0021] determining function difference information according to the plurality of first circuit resources and the plurality of second circuit resources.

[0022] In a possible design, the determining the function difference information according to the plurality of first circuit resources and the plurality of second circuit resources includes:

[0023] determining resource difference information according to the plurality of first circuit resources and the plurality of second circuit resources;

[0024] determining the function difference information according to the resource difference information.

[0025] In a possible design, the obtaining the correspondence between circuit resources and resource positions includes:

[0026] obtaining a function circuit;

[0027] compile the function circuit to obtain third compilation information;

[0028] update the i th resource of the function circuit, and obtain i th compilation information of the updated function circuit, determine a resource position corresponding to the i th resource according to the third compilation information and the i th compilation information, the i th compilation information and the third compilation information are different in information at the resource position corresponding to the i th resource;

[0029] wherein, the i is 1, 2, …, N, and the N is the number of resources included in the function circuit.

[0030] In a second aspect, the embodiments of the present application provide a circuit testing device, comprising:

[0031] a first compilation module, configured to compile a to-be-tested circuit to obtain first compilation information, the first compilation information comprising a plurality of first resource positions corresponding to the to-be-tested circuit;

[0032] a second compilation module, configured to compile a reference circuit corresponding to the to-be-tested circuit to obtain second compilation information, the second compilation information comprising a plurality of second resource positions corresponding to the reference circuit;

[0033] a determination module, configured to determine function difference information between the to-be-tested circuit and the reference circuit according to the first compilation information and the second compilation information;

[0034] a processing module, configured to determine a test result corresponding to the to-be-tested circuit according to a target function corresponding to the to-be-tested circuit, a reference function corresponding to the reference circuit, and the function difference information.

[0035] In a possible design, the processing module is specifically configured to:

[0036] determine a test function corresponding to the to-be-tested circuit according to the reference function and the function difference information;

[0037] determine the test result of the to-be-tested circuit according to the test function and the target function.

[0038] In a possible design, the processing module is specifically configured to:

[0039] if the test function and the target function are the same, determine that the test result is test success;

[0040] if the test function and the target function are not the same, determine that the test result is test failure.

[0041] In a possible design, the processing module is specifically configured to:

[0042] obtain a correspondence relationship between circuit resources and resource positions, the correspondence relationship including a plurality of circuit resources and a resource position corresponding to each circuit resource;

[0043] determine a plurality of first circuit resources according to the first compilation information and the correspondence relationship;

[0044] determine a plurality of second circuit resources according to the second compilation information and the correspondence relationship;

[0045] determine function difference information according to the plurality of first circuit resources and the plurality of second circuit resources.

[0046] In a possible design, the determining module is specifically configured to:

[0047] determine resource difference information according to the plurality of first circuit resources and the plurality of second circuit resources;

[0048] determine the function difference information according to the resource difference information.

[0049] In a possible design, the determining module is specifically configured to:

[0050] obtain a function circuit;

[0051] compile the function circuit to obtain third compilation information;

[0052] update an i th resource of the function circuit, obtain i th compilation information of the updated function circuit, and determine a resource position corresponding to the i th resource according to the third compilation information and the i th compilation information, the i th compilation information and the third compilation information being different in information at the resource position corresponding to the i th resource;

[0053] wherein, the i is 1, 2, …, N, and the N is a quantity of resources included in the function circuit.

[0054] In a third aspect, an embodiment of the present application provides a circuit testing device, including:

[0055] a memory, configured to store a program;

[0056] a processor, configured to execute the program stored in the memory, and when the program is executed, the processor is configured to execute the method in the first aspect and any one of the possible designs of the first aspect.

[0057] Fourthly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the methods described in the first aspect above and any of the various possible designs of the first aspect.

[0058] Fifthly, embodiments of this application provide a computer program product comprising: a computer program stored in a readable storage medium, wherein at least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program to cause the electronic device to perform the method described in the first aspect above and any of the various possible designs of the first aspect.

[0059] This application provides a circuit testing method and apparatus. The method includes: compiling a circuit to be tested to obtain first compilation information, the first compilation information including multiple first resource locations corresponding to the circuit to be tested; compiling a reference circuit corresponding to the circuit to be tested to obtain second compilation information, the second compilation information including multiple second resource locations corresponding to the reference circuit; determining functional difference information between the circuit to be tested and the reference circuit based on the first compilation information and the second compilation information; and determining the test result corresponding to the circuit to be tested based on the target function corresponding to the circuit to be tested, the reference function corresponding to the reference circuit, and the functional difference information. The test result corresponding to the circuit to be tested can be determined based on the target function corresponding to the circuit to be tested, the reference function corresponding to the reference circuit, and the functional difference information. Therefore, when designing and verifying the circuit to be tested, only functional simulation verification is required, thereby greatly shortening the verification cycle of the circuit to be tested and significantly improving verification efficiency. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 The flowchart of the circuit testing method provided in the embodiments of this application Figure 1 ;

[0062] Figure 2 A schematic diagram illustrating some of the first compilation information provided in the embodiments of this application;

[0063] Figure 3 A schematic diagram illustrating some of the second compilation information provided in the embodiments of this application;

[0064] Figure 4A flowchart illustrating the impact of changes in SRAM-based FPGA design parameters on functional circuits is provided for embodiments of this application.

[0065] Figure 5 A schematic diagram of a multiplier provided in an embodiment of this application;

[0066] Figure 6 A schematic diagram of an odd frequency divider provided in an embodiment of this application;

[0067] Figure 7 A schematic diagram of a multi-coefficient complex synthesis circuit provided in an embodiment of this application;

[0068] Figure 8 A flowchart illustrating the correspondence between circuit resources and resource locations provided in an embodiment of this application;

[0069] Figure 9 The flowchart of the circuit testing method provided in the embodiments of this application Figure 2 ;

[0070] Figure 10 This is a schematic diagram of the circuit testing device provided in the embodiments of this application;

[0071] Figure 11 This is a schematic diagram of the hardware structure of the circuit testing equipment provided in the embodiments of this application. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0073] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0074] To facilitate understanding of the technical solution of this application, the relevant concepts involved in this application will be introduced first:

[0075] Static Random-Access Memory (SRAM) type Field Programmable Gate Array (FPGA) is a programmable device composed of various circuit resources. It features high density, high performance, and dynamic reconfiguration. These circuit resources can be strategically connected to form different circuit structures to achieve various functions, such as multipliers, registers, and address generators. Furthermore, due to its dynamic reconfiguration feature, users can remotely control its configuration to be repeatedly refreshed to obtain circuits with different functionalities.

[0076] Hardware Description Language (HDL): A text-based language used to describe the structure and behavior of digital system hardware. It can represent logic circuit diagrams, logic expressions, and the logical functions performed by a digital logic system. Examples include Very-High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) and Verilog HDL.

[0077] Next, the overall process of implementing a circuit with preset functions using an SRAM-type FPGA is introduced using hardware description languages: After completing the circuit design file with preset functions using Verilog HDL, the electronic design automation (EDA) software automatically performs synthesis, compilation, placement, and routing on the circuit design file. Then, the functional circuit implemented by the circuit design file is simulated and verified. After successful simulation verification, the circuit design file is downloaded to the SRAM-type FPGA chip, and the preset functions corresponding to the circuit design file can be implemented through the SRAM-type FPGA. The simulation verification includes functional simulation verification and timing simulation verification.

[0078] Functional simulation verification refers to testing and simulating only the logical function of a circuit and simulating the functional implementation capability of an HDL hardware design language to understand whether the function implemented by the circuit meets the requirements of the original design. In this process, no timing information is involved, and the hardware characteristics of specific components are not considered.

[0079] Timing simulation verification refers to the process of extracting relevant timing parameters such as device delays and interconnect delays after placement and routing, based on the HDL meeting the designer's functional requirements, and then performing simulations on this basis.

[0080] To ensure the performance and high reliability of the functional circuits implemented by SRAM-based FPGAs, the functional circuits must typically be designed and verified before use.

[0081] During the verification process, when it is determined that a functional circuit cannot achieve its preset function, the design parameters of the functional circuit need to be adjusted and modified to enable it to perform the preset function. In existing technologies, even if only one design parameter of a functional circuit changes, a comprehensive verification of the functional circuit is still required. However, since timing simulation verification and functional simulation verification are required for all functional circuits, the verification efficiency of functional circuits is low.

[0082] Based on the aforementioned problems, this application proposes the following technical concept: Through research on the implementation of design parameters in functional circuits, it was found that when design parameters are defined using Block Random Access Memory (BRAM), the new functional circuit after the design parameters are changed retains the configuration resources of the original functional circuit, and the circuit routing layout remains unchanged; only the configuration bits in the RAM change. These configuration bits are used to store functional circuit data. Therefore, based on this finding, and considering that the layout and routing of the new functional circuit after the design parameters are changed are consistent with the original functional circuit, only functional simulation verification is needed for the new functional circuit after the design parameters are changed; timing simulation verification is not required. That is, the timing simulation verification results of the new functional circuit are consistent with those of the original functional circuit. Since only functional simulation verification is required for the new functional circuit, this significantly shortens the simulation verification cycle and improves simulation verification efficiency.

[0083] Based on the technical concept described above, the following section combines... Figure 1 The circuit testing method provided in this application will be described in detail with specific embodiments. It is worth noting that the execution subject in each embodiment of this application is a device with testing functions, such as a processor or microprocessor. This embodiment does not limit the specific implementation of this execution subject, as long as it can perform functional testing. Figure 1 The flowchart of the circuit testing method provided in the embodiments of this application Figure 1 , Figure 2 This is a schematic diagram of some of the first compilation information provided in the embodiments of this application. Figure 3 This is a schematic diagram of some of the second compilation information provided in the embodiments of this application. Figure 4 The flowchart provided in this application illustrates the impact of changes in SRAM-based FPGA design parameters on functional circuits. Figure 5 This is a schematic diagram of a multiplier provided in an embodiment of this application. Figure 6 This is a schematic diagram of an odd frequency divider provided in an embodiment of this application. Figure 7This is a schematic diagram of a multi-coefficient complex synthesis circuit provided in an embodiment of this application. Figure 8 This is a flowchart illustrating the correspondence between circuit resources and resource locations provided in an embodiment of this application.

[0084] like Figure 1 As shown, the method includes:

[0085] S101. Compile the circuit to be tested to obtain first compilation information, which includes multiple first resource locations corresponding to the circuit to be tested.

[0086] The circuit under test is the functional circuit to be tested. For example, it can be circuit logic described using HDL, denoted as HDL functional circuit.

[0087] The compilation process includes logical synthesis, translation, mapping, placement and routing of HDL code, and configuration file generation.

[0088] Among them, logic synthesis is the process of converting HDL code into the interconnection relationship of basic logic units such as AND gates, OR gates and flip-flops (hereinafter referred to as: gate-level netlist).

[0089] Layout and routing is the process of determining the location and connection information of various logic units in the gate-level netlist.

[0090] The compilation information is the configuration file obtained after compiling the HDL code. This configuration file may be a bitstream file (hereinafter referred to as a Bit file), which includes multiple first resource locations corresponding to the HDL code. The first resource refers to the circuit resources used by the compiled HDL code, such as programmable logic, programmable I / O, IP cores, and interconnects.

[0091] An SRAM-based FPGA includes multiple circuit resources, each with a fixed corresponding bit storage location. Generally, hexadecimal address codes are used to address the bytes in the memory. The first resource location refers to the bit position occupied by the first resource in the SRAM-based FPGA.

[0092] Next, taking a portion of the bit addresses in the bit file corresponding to the circuit under test as an example, we will introduce the circuit resources included in the circuit under test, such as... Figure 2 As shown.

[0093] like Figure 2 In this representation, the leftmost column of each row represents the prefix of the bit address for that row, and the first row of each column (excluding the leftmost column) represents the suffix of the bit address for that column. Therefore, it can be seen that... Figure 2The bit addresses in the file include: 00025bd00, 00025bd01, 00025bd02, ..., 00025bd0f, 00025be00, 00025be01, 00025be02, ..., 00025be0f, and 00025bf00, 00025bf01, 00025bf02, ..., 00025bf0f. The value corresponding to each bit address in the bit file determines whether the circuit under test includes the circuit resource corresponding to that bit address. Specifically, when the value corresponding to a bit address is zero, it indicates that the circuit under test does not include the circuit resource corresponding to that bit address; when the value corresponding to a bit address is non-zero, it indicates that the circuit under test includes the circuit resource corresponding to that bit address, and different values ​​indicate different functions of the circuit resource corresponding to that bit address.

[0094] according to Figure 2 It can be deduced that the non-zero bit addresses corresponding to the specified bit addresses are, in order: 00025bd02, 00025bd05, 00025bd06, 00025bd0b, 00025bd0f, 00025bf04, and 00025bf0c. Therefore, the multiple circuit resources contained in the circuit under test are the circuit resources corresponding to the above bit addresses.

[0095] S102. Compile the reference circuit corresponding to the circuit to be tested to obtain second compilation information, which includes multiple second resource locations corresponding to the reference circuit.

[0096] In this embodiment, the reference circuit is an HDL functional circuit used for functional comparison during circuit testing.

[0097] The process of compiling the reference circuit corresponding to the circuit to be tested is similar to the specific implementation process of compiling the circuit to be tested, and will not be described in detail here.

[0098] according to Figure 3 It can be deduced that the non-zero bit addresses corresponding to the specified bit addresses are, in order: 00025bd02, 00025bd05, 00025bd06, 00025bd0b, 00025bd0f, 00025be00, 00025be04, 00025be08, 00025be0c, 00025bf04, and 00025bf0c. Therefore, the multiple circuit resources contained in the circuit under test are the circuit resources corresponding to the above bit addresses.

[0099] In addition, considering that the circuit to be tested mentioned in this application is an HDL functional circuit obtained by modifying only the design parameters on the basis of the reference circuit, in order to improve the verification efficiency of SRAM-type FPGA, it is necessary to study the implementation method of the design parameters in the SRAM-type FPGA circuit.

[0100] In one possible implementation, by comparing the bit files corresponding to the HDL functional circuits before and after the design parameter modification, and by observing the circuit placement and routing and the internal circuit structure of the configuration logic blocks in the FPGA Editor, the circuit resources corresponding to the configuration design parameters can be determined, and the implementation method of the design parameters in the SRAM-type FPGA circuit can be analyzed. This can provide a circuit description method to avoid the impact of design parameter changes on FPGA circuit placement and routing, thereby simplifying the FPGA design verification process after design parameter changes and improving the efficiency of FPGA design verification.

[0101] In another possible implementation, considering that there are two ways to define design parameters in SRAM-type FPGA circuits, namely: parameter definition method and BRAM storage method, we study the implementation of design parameters defined by the above two definition methods at the bottom layer of SRAM-type FPGA. This is the basic work for comparing the layout and routing differences of HDL functional circuits before and after the modification.

[0102] Next, we will analyze the impact of two different definitions of design parameters in the functional circuit design of SRAM-type FPGAs on the FPGA design circuit. A flowchart analyzing the impact of design parameter changes on the functional circuit of SRAM-type FPGAs is shown below. Figure 4 As shown.

[0103] First, HDL is used to describe the functional circuit of the SRAM-type FPGA. When defining design parameters, either Parameter or BRAM can be chosen. The Parameter method allows direct definition of design parameters; when using the BRAM method, the design parameters are first stored in BRAM and then retrieved when needed.

[0104] Secondly, in the process of functional circuit design, the functional purpose of the design parameters needs to be considered. These functional purposes can be divided into three types: participation in numerical calculations, logical operations, and complex synthesis operations involving multiple design parameters.

[0105] Then, for design parameters with different uses and functions, the embodiments of this application designed different FPGA functional circuits for parameters used in different functional applications. For example, a multiplier circuit was designed for numerical operations of the design parameters; an odd frequency divider circuit was designed for logical operations of the design parameters; and a 10th-order Fir filter circuit was designed for synthesis operations of multiple design parameters. After synthesizing, compiling, placing, and routing the FPGA functional circuits, bit files were generated.

[0106] Specifically, regarding the use of design parameters in numerical calculations, the multiplier circuit provided in this embodiment is as follows: Figure 5 As shown.

[0107] Figure 5 In this diagram, CLK is the input clock signal, Rst_n is the asynchronous reset signal of the circuit, X is an 8-bit input parameter, Y is a fixed-value design parameter, and Result is the output of the multiplier with a 16-bit width. The design parameter Y is modified and defined using both Parameter and BRAM.

[0108] For design parameters involved in logical operations, the odd frequency divider circuit provided in this embodiment is as follows: Figure 6 As shown.

[0109] Figure 6 In this diagram, CLK is the input clock signal, Rst_n is the off-bit reset signal, N is the division value of the odd divider, and CLK_OUT is the output clock signal. This odd divider is constructed by ANDing two counters triggered by different edges.

[0110] For complex neutralization circuits with multiple coefficients in their design parameters, this embodiment provides a 10th-order FIR low-pass filter circuit, such as... Figure 7 As shown.

[0111] Figure 7 In this circuit, CLK is the input clock signal, Rst_n is the off-bit reset signal, and FIR_OUT is the output of the filter. The filter coefficients range from h0 to h9. This FIR low-pass filter is a complex functional circuit with multiple parameters built from distributed RAM, multipliers, adders, and shift registers.

[0112] Next, the design parameters of the corresponding circuits were modified, and the circuits were placed and routed to generate new bit files. The bit files corresponding to the functional circuits before and after the design parameter modification were compared to study the impact of the design parameter changes on the SRAM-type FPGA design circuit.

[0113] Regarding the use of design parameters in numerical calculations, by comparing the bit files corresponding to the functional circuits before and after the design parameters were modified, it was found that when parameter Y was defined using Parameter and BRAM, the layout and routing of the functional circuit before parameter Y was modified were the same as those after parameter Y was modified, and no change was made. Therefore, timing simulation verification is not required.

[0114] When design parameters are involved in logic operations, the impact on the circuit is discussed by defining the frequency divider value N using both Parameter and BRAM methods, as follows:

[0115] When the frequency division value N is defined using the parameter method, after modifying N, a comparison of the bit files corresponding to the functional circuits before and after the design parameter modification reveals a total difference of 1629 bits. When the frequency division value is 5, the functional circuit uses 52 flip-flops, 85 four-input lookup tables, 43 SLICE chips, 3 I / O pins, and one clock register. When the frequency division value is 7, the circuit uses 52 flip-flops, 81 four-input lookup tables, 41 SLICE chips, 3 I / O pins, and one clock register. Analysis of these differences indicates that the different resource usage of the circuit causes these differences, which in turn alters the layout and routing of the functional circuit.

[0116] When using BRAM to store the prescaler value N, the functional circuit utilizes 61 flip-flops, 153 four-input lookup tables, 84 slices, 1 BRAM, 3 I / O pins, and a clock register. When the prescaler value N changes, comparing the bit files of the functional circuit before and after the modification reveals a total difference of 1 bit. Locating this difference bit reveals it to be a user data configuration bit in the BRAM resource used to store design parameters, caused solely by the change in the prescaler value N itself, and unrelated to other configuration circuit resources of the functional circuit.

[0117] When design parameters are involved in complex multi-coefficient synthesis calculations, the impact on the circuit is discussed by defining filter coefficients using both Parameter and BRAM methods, as follows:

[0118] When defining filter coefficients using the parameter method, a comparison of the bit files corresponding to the functional circuits before and after the filter coefficient modification revealed a total difference of 36,364 bits. Before modification, the functional circuit used 444 flip-flops, 409 four-input lookup tables, 440 SLICE chips, 22 I / O pins, 2 BRAMs, 11 Digital Signal Processing (DSP) resources, and one clock register. After modifying the filter coefficients, the functional circuit used 396 flip-flops, 378 four-input lookup tables, 395 SLICE chips, 22 I / O pins, 2 BRAMs, 9 DSP resources, and one clock register. The difference was primarily attributed to the varying amounts of configuration circuit resources used.

[0119] When using BRAM to store filter coefficients, the filter coefficients are initialized and stored in the distributed RAM for filtering operations. By comparing the bit files corresponding to the functional circuits before and after the filter coefficient modification, a total of 12 bits of difference were found. Bit location analysis of these 12 bits revealed that the difference bits are configuration bits of the BRAM resources used to store design parameters, located in the configuration data of the first, second, and third frames of that resource.

[0120] In summary, this study investigated the impact of two different methods of defining design parameters on SRAM-based FPGA circuits after parameter changes, and the following conclusions were drawn:

[0121] When design parameters are defined using parameters, these parameters are stored within slice resources. Modifying these parameters affects the configuration of the look-up table (LUT) and flip-flops (FF) within the slice, leading to significant differences in the bit files before and after the parameter modification. These differences also affect the number of slice resources used in the circuit, resulting in substantial variations in circuit routing.

[0122] When using BRAM to define design parameters, the design parameters stored in the BRAM need to be read in advance and cached in registers for subsequent calculations. There is a one-to-one correspondence between the BRAM and the register resources used for caching data. Therefore, when using BRAM to define design parameters, changes to the design parameters only affect the configuration bits of the RAM storing user data and do not affect other parts of the circuit. Consequently, changes to the design parameters do not affect other configuration logic resources of the circuit and do not lead to changes in placement and routing; they only affect the configuration bits of the RAM storing user data. Therefore, when verifying HDL functional circuits after design parameter changes, only functional verification is required, without the need for timing verification. This significantly improves the design verification efficiency of FPGA functional circuits and greatly reduces the manpower and time costs of FPGA design verification.

[0123] Therefore, in FPGA circuit design, it is preferable to use BRAM to define design parameters.

[0124] S103. Based on the first compilation information and the second compilation information, determine the functional difference information between the circuit under test and the reference circuit.

[0125] After determining the first compilation information corresponding to the circuit under test and the second compilation information corresponding to the reference circuit based on steps S101 and S102, it is necessary to determine the functional difference information between the circuit under test and the reference circuit.

[0126] Next, taking the partial bit files corresponding to the circuit under test and the partial bit files corresponding to the reference circuit as examples, we will explain how to determine the functional differences between the circuit under test and the reference circuit.

[0127] contrast Figure 2 and Figure 3 It can be seen that the difference between the circuit under test and the reference circuit is that the bit address information is: 00025bd02, 00025be00, 00025be04, 00025be08, 00025be0c.

[0128] In one possible implementation, the correspondence between circuit resources and their locations is first obtained, whereby the correspondence includes multiple circuit resources and the corresponding resource location for each circuit resource. Then, based on the first compilation information and the correspondence, multiple first circuit resources are determined, and based on the second compilation information and the correspondence, multiple second circuit resources are determined. Based on the multiple first circuit resources and the multiple second circuit resources, functional difference information is determined.

[0129] Next, we will first explain how to obtain the correspondence between circuit resources and resource locations.

[0130] In one possible implementation, a functional circuit is obtained, and the functional circuit is compiled to obtain third compilation information. Next, the i-th resource of the functional circuit is updated, and the i-th compilation information of the updated functional circuit is obtained. Based on the third compilation information and the i-th compilation information, the resource location corresponding to the i-th resource is determined. The information at the resource location corresponding to the i-th resource is different between the i-th compilation information and the third compilation information; where i takes the values ​​1, 2, ..., N, and N is the number of resources included in the functional circuit.

[0131] For example, when updating the first resource of a functional circuit (e.g., changing the first resource of the functional circuit from circuit resource 1 to circuit resource 2), and compiling the updated functional circuit to obtain the first compilation information, by comparing the third compilation information and the first compilation information, the resource position of the updated first resource in the first compilation information can be determined first.

[0132] By updating all resources of the functional circuit sequentially, the resource location corresponding to each circuit resource can be obtained using the above method, i.e., the correspondence between circuit resources and resource configuration bits.

[0133] Next, the process of obtaining the correspondence between circuit resources and resource locations will be further described. The flowchart for determining the correspondence between circuit resources and resource locations is as follows: Figure 8 As shown.

[0134] First, the functional circuits are designed, including sequential logic circuits, combinational logic circuits, and BRAM configuration circuits. The sequential logic circuits are composed of flip-flops, the combinational logic circuits are composed of lookup tables, and the BRAM configuration circuits are composed of BRAM resources.

[0135] Then, the functional circuit is placed and routed to generate the original Native Circuit Description (NCD) file. The circuit resources used by the functional circuit are placed to the target location using FPGA Editor software and compiled to obtain the Bit file.

[0136] Next, the design logic of the functional circuit is modified and synthesized, compiled, placed, and routed to generate a new NCD file. The layout of the circuit resources used by the FPGA functional circuit is modified using FPGA Editor software to make it consistent with the layout of the original functional circuit. Finally, the modified Bit file is generated using Bitgen.

[0137] Next, compare the bit files generated before and after modifying the functional circuit, map the circuit resources used to the differences in bit positions, and enter the data into the database.

[0138] The layout of the circuit resources for the functional circuit is modified again using the FPGA Editor, and a Bit file is generated for comparison to establish a mapping relationship between circuit resources and their locations. This process is repeated until all circuit resources are resolved. Furthermore, the resolution of BRAM and flip-flop resources requires the assistance of generating a readback file (.ll file) to determine the resource location of the corresponding FPGA circuit resource in the Bit file, thereby establishing the correspondence between circuit resources and their locations.

[0139] Next, based on the correspondence between the circuit resources and their locations, multiple first circuit resources are determined according to the first compilation information and the correspondence, and multiple second circuit resources are determined according to the second compilation information and the correspondence.

[0140] For example, given the first compilation information, i.e., the multiple resource addresses corresponding to the circuit under test, the multiple first circuit resources corresponding to the circuit under test can be determined based on the correspondence between circuit resources and resource addresses; similarly, given the second compilation information, i.e., the multiple resource addresses corresponding to the circuit under test, the multiple second circuit resources corresponding to the circuit under test can be determined based on the correspondence between circuit resources and resource addresses.

[0141] Therefore, based on the multiple first circuit resources corresponding to the circuit under test and the multiple second circuit resources corresponding to the reference circuit, the functional differences between the circuit under test and the second circuit resources can be determined.

[0142] S104. Based on the target function of the circuit under test, the reference function of the reference circuit, and the functional difference information, determine the test result of the circuit under test.

[0143] Based on step 103, the functional difference information between the circuit under test and the reference circuit is determined. Next, the test result corresponding to the circuit under test is determined according to the target function corresponding to the circuit under test, the reference function corresponding to the reference circuit, and the functional difference information.

[0144] In one possible implementation, the test function of the circuit under test (TBT) is first determined based on the reference function and functional difference information of the reference circuit. Then, the test result is further determined by judging whether the test function of the TBT matches the target function. If the test function matches the target function, the test result is considered successful. If the test function does not match the target function, the test result is considered unsuccessful.

[0145] The circuit testing method provided in this application includes: compiling the circuit under test to obtain first compilation information, the first compilation information including multiple first resource locations corresponding to the circuit under test; compiling a reference circuit corresponding to the circuit under test to obtain second compilation information, the second compilation information including multiple second resource locations corresponding to the reference circuit; determining functional difference information between the circuit under test and the reference circuit based on the first compilation information and the second compilation information; and determining the test result corresponding to the circuit under test based on the target function corresponding to the circuit under test, the reference function corresponding to the reference circuit, and the functional difference information. The test result corresponding to the circuit under test can be determined based on the target function corresponding to the circuit under test, the reference function corresponding to the reference circuit, and the functional difference information. Therefore, when designing and verifying the circuit under test, only functional simulation verification is required, thereby greatly shortening the verification cycle of the circuit under test and improving verification efficiency.

[0146] Based on the above embodiments, the circuit testing method provided in this application will be further described below with reference to a specific embodiment. Figure 9 To introduce, Figure 9 The flowchart of the circuit testing method provided in the embodiments of this application Figure 2 .

[0147] like Figure 9 As shown, the method includes:

[0148] S901. Compile the circuit to be tested to obtain first compilation information, which includes multiple first resource locations corresponding to the circuit to be tested.

[0149] S902. Compile the reference circuit corresponding to the circuit to be tested to obtain second compilation information, which includes multiple second resource locations corresponding to the reference circuit.

[0150] The specific implementation methods of step S901 and step S101 are similar, and the specific implementation methods of step S902 and step S102 are similar, so they will not be described again here.

[0151] S903. Obtain the correspondence between circuit resources and resource locations, including multiple circuit resources and the resource location corresponding to each circuit resource.

[0152] In one possible implementation, a functional circuit is obtained, which may be, for example, a sequential logic circuit, a combinational logic circuit, or a BRAM configuration circuit. This functional circuit is then compiled to obtain third compilation information. Next, the circuit design logic of the i-th resource in the functional circuit is modified to obtain an updated functional circuit. The resource placement and routing of the updated functional circuit are then modified using FPGA Editor software to ensure consistency between the placement and routing of the updated functional circuit and the original functional circuit. Afterward, the updated functional circuit is compiled to obtain the i-th compilation information, where i is 1, 2, ..., N, and N is the number of resources included in the functional circuit. Next, based on the third compilation information and the i-th resource, the resource location (bit address) corresponding to the i-th resource is determined, i.e., the correspondence between the i-th resource and its resource location. The above steps are repeated until the correspondence between all circuit resources and their resource locations is obtained, where each correspondence includes multiple circuit resources and their corresponding resource locations.

[0153] In addition, for the parsing of BRAM and flip-flop resources, a readback file (.ll file) needs to be generated to help determine the position of the corresponding FPGA circuit resources in the Bit file, thereby establishing the correspondence between resources and resource positions.

[0154] S904. Based on the first compilation information and the corresponding relationship, determine multiple first circuit resources.

[0155] Based on step S903, after obtaining the correspondence between circuit resources and resource locations, multiple first circuit resources can be determined according to the first compilation information and the correspondence.

[0156] The first compilation information includes multiple first resource locations corresponding to the circuit under test.

[0157] In one possible implementation, multiple first resource locations in the first compilation information are matched sequentially with a correspondence. Specifically, each first resource location is found sequentially in the correspondence, and the circuit resources corresponding to each first resource location in the correspondence are the multiple first circuit resources that constitute the circuit to be tested.

[0158] S905. Based on the second compilation information and the corresponding relationship, determine multiple second circuit resources.

[0159] Similarly, based on step S903, after obtaining the correspondence between circuit resources and resource locations, multiple second circuit resources can be determined according to the second compilation information and the correspondence.

[0160] The second compilation information includes multiple second resource locations corresponding to the reference circuit.

[0161] In one possible implementation, multiple second resource locations in the second compilation information are matched sequentially with a correspondence. Specifically, each second resource location is found sequentially in the correspondence, and the circuit resources corresponding to each second resource location in the correspondence are the multiple second circuit resources that constitute the reference circuit.

[0162] S906. Determine resource difference information based on multiple first circuit resources and multiple second circuit resources.

[0163] Based on steps S904 and S905 above, multiple first circuit resources corresponding to the circuit under test and multiple second circuit resources corresponding to the reference circuit are determined. Next, resource difference information is determined based on the multiple first circuit resources and the multiple second circuit resources. The resource difference information is the set of circuit resources that differ from those in the reference circuit.

[0164] In one possible implementation, multiple first circuit resources are compared sequentially with multiple second circuit resources. Specifically, firstly, each first circuit resource is compared sequentially with the multiple second circuit resources. If a first circuit resource is not found among the multiple second circuit resources during the comparison, it is added to a first set of differing circuit resources. Similarly, next, each second circuit resource is compared sequentially with the multiple first circuit resources. If a second circuit resource is not found among the multiple first circuit resources during the comparison, it is added to a second set of differing circuit resources. After the comparisons are complete, the sum of the first and second sets of differing circuit resources represents the resource difference information.

[0165] In this embodiment, the implementation method of determining the difference resource information is merely exemplified and is not intended to limit the implementation method of determining the difference resource information. The implementation method of determining the difference resource information can be selected according to actual needs.

[0166] S907. Determine functional difference information based on resource difference information.

[0167] Among them, the functional difference information refers to the differences in the functions implemented between the circuit under test and the reference circuit.

[0168] In one possible implementation, multiple first-difference circuit resources in the resource difference information are combined to obtain a first circuit. The function corresponding to this first circuit is the first functional difference information between the circuit under test and the reference circuit. Similarly, multiple second-difference circuit resources in the resource difference information are combined to obtain a second circuit. The function corresponding to this second circuit is the second functional difference information between the circuit under test and the reference circuit.

[0169] The first functional difference information and the second functional difference information constitute the functional difference information between the circuit under test and the reference circuit.

[0170] S908. Based on the reference function and function difference information, determine the test function corresponding to the circuit under test.

[0171] Based on the above step S907, the functional difference information consists of the first functional difference information and the second functional difference information.

[0172] In one possible implementation, the function obtained by adding the first functional difference information to the reference function corresponding to the reference circuit and subtracting the second functional difference information is determined as the test function corresponding to the circuit under test.

[0173] In this embodiment, the implementation method of determining the test function corresponding to the circuit under test is merely exemplarily introduced, and is not intended to limit the implementation method of determining the test function corresponding to the circuit under test. As long as the test function corresponding to the circuit under test is determined based on the reference function and function difference information, it is acceptable.

[0174] S909. Determine whether the test function and the target function are the same. If yes, execute S910; otherwise, execute S911.

[0175] The target function of the circuit under test is the desired function of the circuit under test obtained by modifying the design parameters of the reference circuit.

[0176] After determining the test function corresponding to the circuit under test based on the above step S908, the test result of the circuit under test is determined by judging whether the test function of the circuit under test is the same as the target function of the circuit under test.

[0177] S910. Confirm the test result as a successful test.

[0178] In this embodiment, when the test function corresponding to the circuit under test is the same as the target function, the test result of the circuit under test is determined to be a successful test, that is, the test function of the circuit under test is the expected function.

[0179] S911, The test result is determined to be a test failure.

[0180] In this embodiment, when the test function corresponding to the circuit under test is different from the target function, the test result of the circuit under test is determined to be a test failure, that is, the test function of the circuit under test is not the expected function.

[0181] The circuit testing method provided in this application includes: compiling a circuit to be tested to obtain first compilation information, the first compilation information including multiple first resource locations corresponding to the circuit to be tested; compiling a reference circuit corresponding to the circuit to be tested to obtain second compilation information, the second compilation information including multiple second resource locations corresponding to the reference circuit; obtaining a correspondence between circuit resources and resource locations, the correspondence including multiple circuit resources and the resource location corresponding to each circuit resource; determining multiple first circuit resources based on the first compilation information and the correspondence; determining multiple second circuit resources based on the second compilation information and the correspondence; determining resource difference information based on the multiple first circuit resources and the multiple second circuit resources; determining functional difference information based on the resource difference information; determining the test function corresponding to the circuit to be tested based on the reference function and the functional difference information; if the test function and the target function are the same, the test result is determined to be a test success; if the test function and the target function are different, the test result is determined to be a test failure.

[0182] Figure 10 This is a schematic diagram of the circuit testing device provided in an embodiment of this application. Figure 10 As shown, the device 1000 includes: a first compilation module 1001, a second compilation module 1002, a determination module 1003, and a processing module 1004.

[0183] The first compilation module 1001 is used to compile the circuit under test and obtain first compilation information, the first compilation information including multiple first resource locations corresponding to the circuit under test;

[0184] The second compilation module 1002 is used to compile the reference circuit corresponding to the circuit under test to obtain second compilation information, the second compilation information including multiple second resource locations corresponding to the reference circuit;

[0185] The determination module 1003 is used to determine the functional difference information between the circuit under test and the reference circuit based on the first compilation information and the second compilation information;

[0186] The processing module 1004 is used to determine the test result corresponding to the circuit under test based on the target function corresponding to the circuit under test, the reference function corresponding to the reference circuit, and the function difference information.

[0187] In one possible design, the processing module 1004 is specifically used for:

[0188] Based on the reference function and the function difference information, determine the test function corresponding to the circuit under test;

[0189] Based on the test function and the target function, the test result for the circuit under test is determined.

[0190] In one possible design, the processing module 1004 is specifically used for:

[0191] If the test function and the target function are the same, the test result is determined to be a successful test.

[0192] If the test function and the target function are not the same, the test result is determined to be a test failure.

[0193] In one possible design, the processing module 1004 is specifically used for:

[0194] Obtain the correspondence between circuit resources and resource locations, wherein the correspondence includes multiple circuit resources and the resource location corresponding to each circuit resource;

[0195] Based on the first compilation information and the correspondence, multiple first circuit resources are determined;

[0196] Based on the second compilation information and the corresponding relationship, multiple second circuit resources are determined;

[0197] Functional difference information is determined based on the plurality of first circuit resources and the plurality of second circuit resources.

[0198] In one possible design, the determining module 1003 is specifically used for:

[0199] Based on the plurality of first circuit resources and the plurality of second circuit resources, resource difference information is determined;

[0200] The functional difference information is determined based on the resource difference information.

[0201] In one possible design, the determining module 1003 is specifically used for:

[0202] Acquire functional circuit;

[0203] The functional circuit is compiled to obtain third compilation information;

[0204] The i-th resource of the functional circuit is updated, and the i-th compilation information of the updated functional circuit is obtained. Based on the third compilation information and the i-th compilation information, the resource position corresponding to the i-th resource is determined. The information of the i-th compilation information and the third compilation information at the resource position corresponding to the i-th resource is different.

[0205] Where i takes the values ​​1, 2, ..., N, and N is the number of resources included in the functional circuit.

[0206] The apparatus provided in this embodiment can be used to execute the technical solutions of the above method embodiments. Its implementation principle and technical effects are similar, and will not be described again here.

[0207] Figure 11 This is a schematic diagram of the hardware structure of the circuit testing equipment provided in the embodiments of this application, such as... Figure 11 As shown, the circuit testing device 1100 of this embodiment includes: a processor 1101 and a memory 1102; wherein

[0208] Memory 1102 is used to store computer-executed instructions;

[0209] The processor 1101 is used to execute computer execution instructions stored in the memory to implement the various steps performed by the circuit testing method in the above embodiments. For details, please refer to the relevant descriptions in the foregoing method embodiments.

[0210] Alternatively, the memory 1102 can be either standalone or integrated with the processor 1101.

[0211] When the memory 1102 is set up independently, the circuit test device also includes a bus 1103 for connecting the memory 1102 and the processor 1101.

[0212] This application provides a computer-readable storage medium storing computer-executable instructions. When a processor executes the computer-executable instructions, it implements the circuit testing method performed by the circuit testing device described above.

[0213] This application also provides a computer program product, which includes a computer program stored in a readable storage medium. At least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program to cause the electronic device to perform the solution provided in any of the above embodiments.

[0214] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0215] The integrated modules implemented as software functional modules described above can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application.

[0216] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.

[0217] The memory may include high-speed RAM, and may also include non-volatile storage (NVM), such as at least one disk storage device, and may also be a USB flash drive, external hard drive, read-only memory, disk or optical disc, etc.

[0218] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0219] The aforementioned storage medium can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.

[0220] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0221] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A circuit testing method, characterized in that, include: The circuit to be tested is compiled to obtain first compilation information, which includes multiple first resource locations corresponding to the circuit to be tested. The circuit under test is an HDL functional circuit obtained by modifying only the design parameters based on the reference circuit; the compilation includes logic synthesis, translation, mapping, placement and routing processing and configuration file generation of HDL code; the design parameters are defined through block random access memory (BRAM). Compared with the original functional circuit, the new functional circuit after the design parameters are changed will retain the configuration resources in the original functional circuit, and the circuit routing layout will not be changed, only the configuration bits in RAM will be changed. The reference circuit corresponding to the circuit under test is compiled to obtain second compilation information, which includes multiple second resource locations corresponding to the reference circuit. Obtain the correspondence between circuit resources and resource locations, wherein the correspondence includes multiple circuit resources and the resource location corresponding to each circuit resource; Based on the first compilation information and the correspondence, multiple first circuit resources are determined; Based on the second compilation information and the corresponding relationship, multiple second circuit resources are determined; Based on the plurality of first circuit resources and the plurality of second circuit resources, resource difference information is determined; Based on the resource difference information, determine the functional difference information between the circuit under test and the reference circuit; Based on the reference function corresponding to the reference circuit and the function difference information, determine the test function corresponding to the circuit under test; Based on the test function and the target function corresponding to the circuit under test, the test result of the circuit under test is determined; the target function is the expected function of the circuit under test obtained after modifying the design parameters of the reference circuit. If the test function and the target function are the same, the test result is determined to be a successful test, and the test function of the circuit under test is the expected function. If the test function and the target function are not the same, the test result is determined to be a test failure, and the test function of the circuit under test is not the expected function.

2. The method according to claim 1, characterized in that, The acquisition of the correspondence between circuit resources and resource locations includes: Acquire functional circuit; The functional circuit is compiled to obtain third compilation information; The i-th resource of the functional circuit is updated, and the i-th compilation information of the updated functional circuit is obtained. Based on the third compilation information and the i-th compilation information, the resource position corresponding to the i-th resource is determined. The information of the i-th compilation information and the third compilation information at the resource position corresponding to the i-th resource is different. Where i takes the values ​​1, 2, ..., N, and N is the number of resources included in the functional circuit.

3. A circuit testing device, characterized in that, include: The first compilation module is used to compile the circuit under test and obtain first compilation information, which includes multiple first resource locations corresponding to the circuit under test. The circuit under test is an HDL functional circuit obtained by modifying only the design parameters based on the reference circuit; the compilation includes logic synthesis, translation, mapping, placement and routing processing and configuration file generation of HDL code; the design parameters are defined through block random access memory (BRAM). Compared with the original functional circuit, the new functional circuit after the design parameters are changed will retain the configuration resources in the original functional circuit, and the circuit routing layout will not be changed, only the configuration bits in RAM will be changed. The second compilation module is used to compile the reference circuit corresponding to the circuit under test to obtain second compilation information, which includes multiple second resource locations corresponding to the reference circuit. A determination module is used to obtain the correspondence between circuit resources and resource locations, wherein the correspondence includes multiple circuit resources and the resource location corresponding to each circuit resource; and to determine multiple first circuit resources based on the first compilation information and the correspondence. Based on the second compilation information and the corresponding relationship, multiple second circuit resources are determined; Based on the plurality of first circuit resources and the plurality of second circuit resources, resource difference information is determined; Based on the resource difference information, determine the functional difference information between the circuit under test and the reference circuit; The processing module is configured to determine the test function corresponding to the circuit under test based on the reference function corresponding to the reference circuit and the function difference information; determine the test result of the circuit under test based on the test function and the target function corresponding to the circuit under test; the target function is the expected function of the circuit under test obtained by modifying the design parameters of the reference circuit; if the test function and the target function are the same, the test result is determined to be a successful test; if the test function and the target function are different, the test result is determined to be a failed test.

4. A circuit testing device, characterized in that, include: Memory, used to store programs; A processor for executing the program stored in the memory, wherein when the program is executed, the processor is configured to perform the method as described in any one of claims 1 to 2.

5. A computer-readable storage medium, characterized in that, Includes instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 2.

6. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 2.

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