Semiconductor device and method of manufacturing the same

Abstract

The present application relates to semiconductor devices and methods of manufacturing the same. A semiconductor device according to one embodiment of the present disclosure includes a conductive region, a terminal region at a termination portion of the conductive region, and a connection region between the conductive region and the terminal region. The conductive region includes an n+ type substrate, an n- type layer at a first surface of the n+ type substrate, and a p type region on the n- type layer, and a gate electrode filling an inside of a trench penetrating the p type region and located in the n- type layer, and a side wall of the trench at the termination portion of the conductive region is inclined.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefits to Korean Patent Application No. 10-2020-0164307, filed with the Korean Intellectual Property Office on November 30, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device including a trench gate and a method for manufacturing the same. Background Technology

[0004] Metal-oxide-semiconductor field-effect transistors (hereinafter referred to as "MOSFETs") are three-terminal devices that can conduct current according to the gate control, especially power semiconductor MOSFETs used for switching that requires high voltage and high current.

[0005] Meanwhile, silicon carbide (SiC) power devices outperform silicon (Si) devices in terms of high voltage and high current characteristics, so research and commercialization are actively underway. In structures that meet high current requirements, in trench-gate MOSFETs with trench gates, the polysilicon (Poly-Si) gate and the gate channel are connected through the polysilicon at the gate end, and the gate channel is again connected to the gate pad for applying voltage.

[0006] In this structure, a step exists at the gate end (trench edge portion) at the trench termination, causing electric field concentration. This concentration results in the electric field being concentrated on the oxide film at the trench edge portion, leading to oxide film damage. This phenomenon reduces the breakdown voltage in the trench gate MOSFET and is a factor that degrades the performance of high-voltage power semiconductor MOSFETs.

[0007] The information disclosed in this background section is intended only to enhance the understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0008] The purpose of this disclosure is to provide a semiconductor device that has an improved breakdown voltage by reducing the electric field concentrated at the edge portion of the trench.

[0009] Another object of this disclosure is to provide a method for manufacturing a semiconductor device that does not require the development of new process technologies.

[0010] According to one embodiment of this disclosure, a semiconductor device includes: a conductive region; an end region located at a portion terminating the conductive region; and a connection region located between the conductive region and the end region. In the semiconductor device, the conductive region includes: an n+ type substrate; an n- type layer located at a first surface of the n+ type substrate; a p- type region located on the n- type layer; and a gate electrode that fills and penetrates the p-type region and is located inside a trench in the n-type layer, wherein the sidewalls of the trench located at the terminating portion of the conductive region are inclined.

[0011] The angle between the bottom surface of the trench and the inclined sidewall can be greater than 90 degrees and less than 180 degrees.

[0012] The angle between the bottom surface of the trench and the inclined sidewall can be greater than 135 degrees and less than 160 degrees.

[0013] The area below the sloping sidewalls of the trench can be filled with insulating material.

[0014] The area below the sloping sidewalls of the trench can be where n-type layers and p-type regions are stacked.

[0015] The sloping sidewalls of the trench can have a concave shape.

[0016] The inclined sidewalls of the trench can have an upward convex shape.

[0017] The connection region may include: an n+ type substrate; an n- type layer located in a first surface of the n+ type substrate; a p- type region located on the n- type layer; a lower gate channel located on the p-type region and connected to the gate electrode; a terminal oxide layer located on the lower gate channel; and an upper gate channel located on the terminal oxide layer.

[0018] The sidewalls of the trench that connect to the bottom surface of the trench and the lower gate channel can be inclined.

[0019] The oxide layer may include contact holes that partially expose the lower gate flow channel, and the upper gate flow channel may contact the lower gate flow channel through the contact holes of the oxide layer.

[0020] The conductive region may include an oxide layer on the gate electrode and a source electrode on the oxide layer that is insulated from the gate electrode.

[0021] The conductive region, connection region, end region, or combination thereof may include a drain electrode located on the second surface of the substrate.

[0022] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming an n-type layer on a first surface of an n+ type substrate, the n+ type substrate including a conductive region, an end region located at a portion terminating the conductive region, and a connection region located between the conductive region and the end region; etching the n-type layer to form a trench; and forming a gate electrode in the trench, wherein in the formation of the trench, the sidewalls of the trench located at the portion terminating the conductive region are etched to be inclined.

[0023] The manufacturing method of semiconductor devices may also include forming a p-type region on an n-type layer.

[0024] Even after forming a p-type region in the area where the trench will form, the p-type region and the n-type layer can be etched so that the sidewalls of the trench are inclined.

[0025] The formation of trenches may include filling the etched area with an insulating material after etching the area where the trench will be formed, and wet etching the insulating material such that the sidewalls of the trench are sloping.

[0026] The manufacturing method of a semiconductor device may also include: forming an oxide layer on a gate electrode; and forming a source electrode on the oxide layer.

[0027] The manufacturing method of semiconductor devices may also include forming a drain electrode on the second surface of an n+ type substrate.

[0028] In the semiconductor device disclosed herein, the breakdown voltage is increased by reducing the electric field concentrated at the edge of the trench.

[0029] Furthermore, since the semiconductor device manufacturing method disclosed herein can be manufactured using ion implantation and epitaxial processes, the development of new process technologies is not required. Attached Figure Description

[0030] Figure 1 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0031] Figure 2 This is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0032] Figure 3 This is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0033] Figure 4 This is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0034] Figure 5 This is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0035] Figure 6 This is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0036] Figure 7 This is a view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0037] Figure 8 This is a view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0038] Figure 9 This is a view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0039] Figure 10 This is a view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0040] Figure 11 These are images showing the results of simulating the electric field distribution of semiconductor devices in the off state according to Examples 1-1 to 1-3 and Examples 2-1 to 2-3.

[0041] Figure 12 This is an image showing the results of simulating the electric field distribution of a semiconductor device in the off state according to Comparative Example 1. Detailed Implementation

[0042] Embodiments of this disclosure will be described in detail with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described herein, but may be embodied in other forms. Rather, the embodiments described herein are provided to provide a thorough and complete understanding of the disclosure and to fully convey the ideas of this disclosure to those skilled in the art.

[0043] In the accompanying drawings, the thicknesses of layers and regions are exaggerated for clarity. It should be noted that when a layer is referred to as being "on" another layer or substrate, it can be formed directly on that other layer or substrate, or it can be formed on that other layer or substrate by means of a third layer inserted therein. Throughout this specification, the same constituent elements are indicated by the same reference numerals.

[0044] Figure 1 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Figure 1 It is a cross-sectional view taken along the horizontal direction extending towards the gate electrode.

[0045] refer to Figure 1The semiconductor device includes a conductive region A, a connection region B, and a terminal region C. The conductive region A is the region through which current flows when a positive voltage is applied, the terminal region C is the region located in the portion where the conductive region A terminates, and the connection region B is the region located between the conductive region A and the terminal region C.

[0046] The semiconductor device includes an n+ type substrate 100, an n- type layer 200, a p-type region 400, a p-type end structure 450, a gate electrode 700, a lower gate channel 750, an upper gate channel 850, a source electrode 800, and a drain electrode 900.

[0047] Specifically, the n+ type substrate 100 can be an n+ type silicon carbide substrate. The n- type layer 200 is located on the first surface of the n+ type substrate 100.

[0048] The trench 210 is located in the n-type layer 200 of the conductive region A. The p-type region 400 is located on one side of the trench 210 and on the n-type layer 200.

[0049] Optionally, the n+ type region (not shown) may be located on one side of the trench 210 and may be located within the p type region 400. Alternatively, the p+ type region (not shown) may be located within the p type region 400 and may be located on one side of the n+ type region (not shown).

[0050] A gate insulating layer 610 is located inside the trench 210, and a gate electrode 700 is located on the gate insulating layer 610. The gate electrode 700 fills the inside of the trench 210 and may protrude outside the trench 210. The gate electrode 700 may comprise polysilicon or metal.

[0051] The oxide layer 630 is located on the gate electrode 700. Alternatively, the oxide layer 630 may also be located on an n+ type region (not shown), a p+ type region (not shown), or a p type region 400.

[0052] The source electrode 800 is located on the oxide layer 630. The source electrode 800 is insulated from the gate electrode 700 through the oxide layer 630. The source electrode 800 may include ohmic metal.

[0053] A p-type region 400 located on one side of the trench 210 adjacent to the terminal region C extends into the connection region B. A terminal insulating layer 620 may be located on the p-type region 400. The terminal insulating layer 620 may comprise the same material as the gate insulating layer 610.

[0054] The lower gate channel 750 is located on the end insulating layer 620. The lower gate channel 750 is connected to the gate electrode 700 disposed adjacent to the end region C, and by way of example, it can be connected to the gate electrode 700 protruding outward from the trench 210. The lower gate channel 750 can be made of the same material as the gate electrode 700, and can include polysilicon or metal.

[0055] A terminal oxide layer 640 is located on the lower gate flow channel 750 and the terminal insulating layer 620, and an upper gate flow channel 850 is located on the terminal oxide layer 640. The terminal oxide layer 640 may comprise the same material as the oxide layer 630. The upper gate flow channel 850 may comprise the same material as the source electrode 800.

[0056] The terminal oxide layer 640 includes a contact hole that partially exposes the lower gate flow channel 750, and the upper gate flow channel 850 can contact the lower gate flow channel 750 through the contact hole. The lower gate flow channel 750 and the upper gate flow channel 850 are used to rapidly apply a gate voltage to the gate electrode 700.

[0057] The p-type end structure 450 is located in the n-type layer 200 of the end region C. The p-type end structure 450 includes multiple regions injected with p-type ions, and the regions injected with p-type ions are spaced apart from each other at predetermined intervals.

[0058] The thickness of the region implanted with p-type ions to form the p-type end structure 450 is less than the depth of the trench 210. Alternatively, the thickness of the region implanted with p-type ions to form the p-type end structure 450 can be the same as the thickness of a portion of the p-type region 400.

[0059] The end insulating layer 620 and the end oxide layer 640 extend upward to the p-type end structure 450 and the n-type layer 200 of the end region C.

[0060] The drain electrode 900 is located on the second surface of the n+ type substrate 100. The drain electrode 900 may include ohmic metal. Here, the second surface of the n+ type substrate 100 is located on the side opposite to the first surface of the n+ type substrate 100.

[0061] On the other hand, the sidewall 212 of the trench 210 is inclined. That is, the angle formed by the bottom surface 211 of the trench 210 and the sidewall 212 is not perpendicular (90 degrees).

[0062] The trench 210, including the inclined sidewall 212, can be the portion terminating in the conductive region A, that is, it can be the trench 210 located closest to the end region C. Accordingly, the sidewall 212 of the trench 210, which connects to the bottom surface 211 of the trench 210 and the lower gate channel 750, is inclined.

[0063] For the gate electrode 700 formed inside the trench 210, at the trench edge portion where the trench 210 terminates, the gate electrode 700 and the upper gate channel 850 are connected through the lower gate channel 750 at the end portion of the gate electrode 700. A step is formed when the angle formed by the bottom surface 211 and the sidewall 212 of the trench 210 is perpendicular (90 degrees), and then the electric field concentrates. As a result, the electric field concentrates in the oxide layer at the trench edge portion, and the oxide layer is disrupted.

[0064] In a semiconductor device according to one embodiment, by tilting the sidewalls of the trench 210 closest to the end region C, the electric field concentrated on the trench edge portion can be reduced, thereby increasing the breakdown voltage. That is, when the tilted sidewalls 212 are introduced into the trench 210, the electric field concentrated in the vertical portion at the trench edge is dispersed in a tilted shape, thereby weakening the electric field applied to the oxide layer. At the same voltage, the electric field applied to the oxide layer is weakened, thus increasing the reliability of the oxide layer during repeated operation, and the breakdown voltage can increase with the increase of the maximum voltage to be applied.

[0065] The angle formed by the bottom surface 211 of the groove 210 and the inclined sidewall 212 can be greater than 90 degrees and less than 180 degrees, for example, greater than 135 degrees and less than 160 degrees or less.

[0066] The area 215 below the inclined sidewall 212 of the trench 210 may be filled with insulating material.

[0067] The region 215 below the inclined sidewall 212 of the trench 210 is the region surrounded by the inclined sidewall 212, a line extending horizontally at the intersection of the inclined sidewall 212 of the trench 210 and the bottom surface 211, and a line extending vertically at the intersection of the inclined sidewall 212 and the lower gate channel 750.

[0068] The insulating material can be the same as the gate insulating layer 610.

[0069] In other words, Figure 1 In this process, the inclined insulating layer is formed on the edge portion of the trench, but the insulating layer is formed thicker towards the end of the trench edge, so that the electric field increases gently along the slope, thereby reducing the electric field concentration phenomenon.

[0070] Figure 2 This is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0071] refer to Figure 2 The n-type layer 200 and the p-type region 400 are stacked in region 215 below the inclined sidewall 212 of trench 210. The gate insulating layer 610 may also be located on the inclined sidewall 212 of trench 210.

[0072] In other words, Figure 2 In this process, while keeping the thickness of the gate insulating layer 610 constant by forming the trench itself as inclined, the electric field rises gently along the inclination, thereby reducing the electric field concentration phenomenon.

[0073] Figures 3 to 6 This is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0074] The cross-sectional shape of the inclined sidewall 212 of the groove 210 is not limited to, for example Figure 1 The straight line shown can be as follows: Figure 3 and Figure 4 As shown, it bulges upwards, or as... Figure 5 and Figure 6 As shown, it is concave downwards. Here, the top of the inclined sidewall 212 of the trench 210 faces the gate electrode 700, and the bottom faces the n-type layer 200.

[0075] Figure 3 and Figure 5 As shown Figure 1 The region 215 below the inclined sidewall 212 of the trench 210 shown is filled with insulating material, and Figure 4 and Figure 6 As shown Figure 2 The n-type layer 200 and the p-type region 400 are stacked in region 215 below the inclined sidewall 212 of the trench 210.

[0076] Figure 7 and Figure 8 This is a view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0077] In the following text, see references Figure 7 and Figure 8 To describe Figure 2 The manufacturing method of the semiconductor device is shown in the figure.

[0078] After the n+ type substrate 100 is prepared, an n- type layer 200 is formed on the first surface of the n+ type substrate 100.

[0079] The n+ type substrate 100 and the n- type layer 200 include a conductive region A, a connection region B, and an end region C. The n- type layer 200 can be formed by epitaxial growth or by implantation of n-type ions.

[0080] A p-type region 400 is formed in the conductive region A and the connecting region B, and a p-type end structure 450 is formed in the end region C. The p-type region 400 is formed by implanting p-type ions into the upper part of the n-type layer 200. The p-type region 400 adjacent to the end region C is formed to extend to the connecting region B and is spaced apart from the p-type end structure 450.

[0081] The p-type end structure 450 is formed by implanting p-type ions onto the upper surface of the n-type layer 200 in the end region C. The p-type end structure 450 includes a plurality of regions implanted with p-type ions, and the regions implanted with p-type ions are spaced apart from each other at predetermined intervals.

[0082] Alternatively, a p-type region 400 can be formed in the area where the trench 210 will be formed. In this case, the trench 210 is formed by etching the n-type layer 200 and the p-type region 400 of the conductive region A. In this case, the n-type layer 200 and the p-type region 400 are etched such that the sidewalls 212 of the trench 210 are located at the terminating portion of the conductive region A. The method for etching the n-type layer 200 and the p-type region 400 can be wet etching, and it is possible to change the tilt angle, shape, and slope curvature of the sidewalls 212 of the trench 210 in various ways by changing the process conditions of the wet etching.

[0083] When trench 210 is formed, a hard mask 660 can be formed on the n-type layer 200 and the p-type region 400, in addition to the area where trench 210 is to be formed. The hard mask 660 can be formed at a point corresponding to the position of the inclined sidewall 212 of trench 210 adjacent to the bottom surface 211 of trench 210. For example, the hard mask 660 may include Si2N3.

[0084] A gate insulating layer 610 is formed inside the trench 210, and an end insulating layer 620 is formed on the p-type end structure 450 and the n-type layer 200 in the end region C. The gate insulating layer 610 and the end insulating layer 620 may comprise the same material.

[0085] Next, a gate electrode 700 is formed on the gate insulating layer 610, and a lower gate flow channel 750 is formed on the end insulating layer 620.

[0086] Next, an oxide layer 630 is formed on the gate electrode 700, and a terminal oxide layer 640 is formed on the lower gate channel 750.

[0087] After forming a contact hole in the terminal oxide layer 640, a source electrode 800 is formed in the conductive region A, and an upper gate flow channel 850 is formed in the connection region B. Next, a drain electrode 900 is formed on the second surface of the n+ type substrate 100.

[0088] Figure 9 and Figure 10 This is a view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0089] refer to Figure 9 and Figure 10 To describe Figure 1 The manufacturing method of the semiconductor device is shown in the figure.

[0090] The content regarding the formation of the n+ type substrate 100, n- type layer 200, p-type region 400 and p-type end structure 450 is the same as described above.

[0091] The n-type layer 200 and p-type region 400 of conductive region A are etched to etch the area where trench 210 will be formed. The area where trench 210 will be formed is filled with an insulating material. The insulating material 670 may be the same material as the gate insulating layer 610.

[0092] Etching the insulating material 670 causes the sidewalls 212 of the trench 210 located in the portion terminating in the conductive region A to be inclined. The method for etching the insulating material 670 can use wet etching, and it is possible to change the inclination angle, shape, and curvature of the sidewalls 212 of the trench 210 in various ways by changing the process conditions of the wet etching.

[0093] Furthermore, by leaving some insulating material 670, the gate insulating layer 610 can be formed simultaneously with the trench 210.

[0094] Subsequently, the formation of the terminal insulating layer 620, gate electrode 700, lower gate flow channel 750, oxide layer 630, terminal oxide layer 640, source electrode 800, upper gate flow channel 850 and drain electrode 900 is the same as described above.

[0095] As mentioned above, since the manufacturing methods for semiconductor devices can be performed using existing ion implantation and epitaxial processes, there is no need to develop new process technologies.

[0096] [Experimental Example 1: Measuring the breakdown voltage and maximum electric field of the oxide layer in a semiconductor device]

[0097] In Example 1, a semiconductor device is used. Figure 1 The structure shown is used for fabrication, and in this case, the tilt angle of the trench sidewalls is formed to be 160 degrees, while in embodiment 2, the semiconductor device uses... Figure 2 The structure shown is used for manufacturing, and the inclination angle of the trench sidewall is formed to be 160 degrees. Comparative Example 1 is the case where the inclination angle of the trench sidewall is 90 degrees, as in the prior art.

[0098] For the semiconductor devices of Example 1, Example 2 and Comparative Example 1, the breakdown voltage and the maximum electric field of the oxide layer were measured using Sentaurus TCAD (Synopsys), and the results are summarized in Table 1.

[0099]

[0100] Table 1

[0101] Referring to Table 1, for the semiconductor device of Example 1, the breakdown voltage of 953.1V increased by 27.2% compared with the breakdown voltage of 749.4V of the semiconductor device of Comparative Example 1, and for the semiconductor device of Example 2, the breakdown voltage of 1100V increased by 49.8% compared with the breakdown voltage of 749.4V of the semiconductor device of Comparative Example 1.

[0102] Furthermore, at the same voltage of 700V, for the semiconductor device of Example 1, 5.148V / cm 2 The electric field value of the oxide layer is compared with that of the semiconductor device in Comparative Example 1, which is 5.753 V / cm. 2 The electric field value of the oxide layer decreased by 10.5% compared to the previous example, reaching 4.433 V / cm for the semiconductor device in Example 2. 2 The electric field value of the oxide layer is compared with that of the semiconductor device in Comparative Example 1, which is 5.753 V / cm. 2 The electric field value of the oxide layer decreased by 22.9% compared to the previous value.

[0103] [Experimental Example 2: Breakdown Voltage Measurement of Semiconductor Devices Dependent on Trench Sidewall Tilt Angle Variation]

[0104] In Examples 1-1 to 1-3, semiconductor devices are used Figure 1 The structure shown is used for manufacturing, and the inclination angles of the trench sidewalls are formed to be 135 degrees, 150 degrees, and 160 degrees, respectively. Furthermore, in Examples 2-1 to 2-3, the semiconductor device... Figure 2 The structure shown is used for manufacturing, and the inclination angles of the trench sidewalls are formed to be 135 degrees, 150 degrees, and 160 degrees, respectively. Comparative Example 1 is the case where the inclination angle of the trench sidewalls is 90 degrees, as in the prior art.

[0105] For the semiconductor devices of Examples 1-1 to 1-3, Examples 2-1 to 2-3, and Comparative Example 1, the breakdown voltage and maximum electric field of the oxide layer were measured using a Sentaurus TCAD (Synopsys) instrument, and the results are summarized in Table 2. Figure 11 as well as Figure 12 middle.

[0106] Figure 11These are images showing the results of simulating the electric field distribution of semiconductor devices in the off state according to Examples 1-1 to 1-3 and Examples 2-1 to 2-3. Figure 11 In the image, the images from the top left to the right represent the results for Examples 1-1 to 1-3, and the images from the bottom left to the right represent the results for Examples 2-1 to 2-3.

[0107] Figure 12 This is an image showing the results of simulating the electric field distribution of a semiconductor device in the off state according to Comparative Example 1.

[0108] exist Figure 11 and Figure 12 In the image, red circles indicate areas where the electric field is concentrated.

[0109]

[0110]

[0111] Table 2

[0112] Refer to Table 2. Figure 11 as well as Figure 12 Compared to the 135-degree tilt angle of the trench sidewall of the semiconductor device in Example 1-1, the breakdown voltage increased by 27.6% at the 150-degree tilt angle of the trench sidewall of the semiconductor device in Example 1-2, and by 48.9% at the 160-degree tilt angle of the trench sidewall of the semiconductor device in Example 1-3.

[0113] Furthermore, compared to the 135-degree tilt angle of the trench sidewall of the semiconductor device in Example 2-1, the breakdown voltage increased by 31.3% at the 150-degree tilt angle of the trench sidewall of the semiconductor device in Example 2-2, and by 51.4% at the 160-degree tilt angle of the trench sidewall of the semiconductor device in Example 2-3.

[0114] Therefore, it can be confirmed that the electric field dispersion effect increases with the increase of the inclination angle of the trench sidewall.

[0115] While this disclosure has been described in conjunction with embodiments that are now considered practically applicable, it should be understood that this disclosure is not limited to the disclosed embodiments. Rather, this disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A conductive region, wherein the conductive region includes: n+ type substrate An n-type layer, wherein the n-type layer is located on the first surface of the n+ type substrate. p-type regions, the p-type regions being located on the n-type layer, and A gate electrode, which fills and penetrates the p-type region and is located inside the trench in the n-type layer, and The sidewalls of the trench located at the portion where the conductive region terminates are inclined; An end region, the end region being located outside the portion where the conductive region terminates; and A connection region is located between the conductive region and the end region, such that the end region is spaced apart from the conductive region by the connection region; The region below the inclined sidewalls of the trench is filled with insulating material, and the region below the inclined sidewalls of the trench is surrounded by the inclined sidewalls, a horizontally extending line at the intersection of the inclined sidewalls and the bottom surface of the trench, and a vertically extending line at the intersection of the inclined sidewalls and the lower gate channel. The p-type end structure is located within the n-type layer of the end region, and the p-type end structure includes multiple regions injected with p-type ions, the multiple regions injected with p-type ions being spaced apart from each other at predetermined intervals. The sidewall of the trench slopes from the intersection of the sidewall and the bottom surface of the trench to the intersection of the sidewall and the lower gate channel.

2. The semiconductor device according to claim 1, wherein, The angle between the bottom surface of the trench and the inclined sidewall is greater than 90 degrees and less than 180 degrees.

3. The semiconductor device according to claim 2, wherein, The angle between the bottom surface of the trench and the inclined sidewall is greater than 135 degrees and less than 160 degrees.

4. The semiconductor device according to claim 1, wherein, The inclined sidewalls of the groove have a downwardly concave shape.

5. The semiconductor device according to claim 1, wherein, The inclined sidewalls of the groove have an upwardly convex shape.

6. The semiconductor device according to claim 1, wherein, The connection area includes: The n+ type substrate The n-type layer is located on the first surface of the n+ type substrate. The p-type region is located on the n-type layer. A lower gate channel, located on the p-type region and connected to the gate electrode. A terminal oxide layer, the terminal oxide layer being located on the lower gate channel, and Upper gate channel, the upper gate channel being located on the terminal oxide layer.

7. The semiconductor device according to claim 6, wherein, The sidewalls of the trench, which are connected to the bottom surface of the trench and the lower gate channel, are inclined.

8. The semiconductor device according to claim 6, wherein, The oxide layer includes contact holes that expose a portion of the lower gate channel, and The upper gate channel contacts the lower gate channel through the contact hole in the oxide layer.

9. The semiconductor device according to claim 1, wherein, The conductive region includes: An oxide layer, the oxide layer being located on the gate electrode, and A source electrode, which is located on the oxide layer and is insulated from the gate electrode.

10. The semiconductor device according to claim 1, wherein, The conductive region, the connection region, the end region, or a combination thereof includes a drain electrode located on a second surface of the substrate.

11. A method for manufacturing a semiconductor device, the method comprising: An n-type layer is formed on a first surface of an n+ type substrate, the n+ type substrate including a conductive region, an end region located outside the portion terminating the conductive region, and a connection region located between the conductive region and the end region, such that the end region is spaced apart from the conductive region. A p-type region is formed on the n-type layer; Etch the n-type layer to form trenches; as well as A gate electrode is formed in the trench. In the formation of the trench, the sidewalls of the trench located at the portion where the conductive region terminates are etched to be inclined. The region below the inclined sidewalls of the trench is filled with insulating material, and the region below the inclined sidewalls of the trench is surrounded by the inclined sidewalls, a horizontally extending line at the intersection of the inclined sidewalls and the bottom surface of the trench, and a vertically extending line at the intersection of the inclined sidewalls and the lower gate channel. The p-type end structure is located within the n-type layer of the end region, and the p-type end structure includes multiple regions injected with p-type ions, the multiple regions injected with p-type ions being spaced apart from each other at predetermined intervals. The sidewall of the trench slopes from the intersection of the sidewall and the bottom surface of the trench to the intersection of the sidewall and the lower gate channel.

12. The method for manufacturing a semiconductor device according to claim 11, wherein, Even after the p-type region is formed in the area where the trench will be formed, the p-type region and the n-type layer are etched so that the sidewalls of the trench are inclined.

13. The method for manufacturing a semiconductor device according to claim 11, wherein, The formation of the trench includes: After etching the area where the trench will form, the etched area is filled with an insulating material, and The insulating material is wet-etched so that the sidewalls of the trench are inclined.

14. The method for manufacturing a semiconductor device according to claim 11, further comprising: An oxide layer is formed on the gate electrode; as well as A source electrode is formed on the oxide layer.

15. The method for manufacturing a semiconductor device according to claim 11, further comprising: A drain electrode is formed on the second surface of the n+ type substrate.

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