A charge pump phase-locked loop circuit with improved phase noise

Abstract

The present invention discloses a charge pump phase-locked loop circuit for improving phase noise, including a frequency detector, a charge pump, a voltage-controlled oscillator, a frequency divider and a loop filter; a frequency detector branch composed of a frequency detector is provided, and the frequency detector branch is connected in parallel between the signal input end of the frequency detector and the signal output end of the charge pump; the frequency detector branch converts the frequency difference of the two input signals to obtain a current pulse signal and connects it to the loop filter, so that a zero point is added to the loop transfer function of the charge pump phase-locked loop; thereby changing the phase noise transfer function of each component of the circuit, making the output phase noise smaller and the output signal jitter smaller. Compared with the traditional charge pump phase-locked loop under the same parameters, the output phase noise of the phase-locked loop of the present invention is smaller, and the output signal jitter of 50KHz-10MHz is reduced from 3.98pS of the traditional charge pump phase-locked loop to 2.42pS; while ensuring sufficient phase margin, the loop bandwidth is increased, thereby further suppressing phase noise and reducing locking time.

Description

Technical Field

[0001] The invention relates to the technical field of phase-locked loops, and in particular to a charge pump phase-locked loop circuit for improving phase noise. Background Art

[0002] Phase-locked loops play an important role in RF wireless communications, optical fiber communications, high-speed wired communications, etc. Phase noise is an important indicator of the phase-locked loop, which affects the purity of the generated clock signal.

[0003] The phase noise of the output signal of the phase-locked loop depends on many factors, including the phase noise of the input signal, the phase noise of the DIVIDER, the noise of the PFD / CP structure and the VCO phase noise as well as the noise transfer function of each part. In order to improve the phase noise of the output signal, it is often achieved by reducing the noise of each part, but the noise of each component cannot be reduced all the time, so the improvement of the overall noise is limited.

[0004] In order to ensure that the loop has sufficient phase margin, the loop bandwidth of the traditional charge pump phase-locked loop is set to be less than 1 / 10 of the phase-locked loop input reference signal. The locking time of the phase-locked loop circuit is often inversely proportional to the loop bandwidth. Therefore, in order to reduce the locking time of the phase-locked loop circuit, it is necessary to break through its bandwidth limitation. Summary of the invention

[0005] The present invention aims to avoid the deficiencies of the above-mentioned prior art and provides a charge pump phase-locked loop circuit with improved phase noise. By changing the noise transfer function of the loop, the noise contribution of some components is made smaller, thereby reducing the jitter of the output signal.

[0006] The present invention adopts the following technical solutions to achieve the purpose of the invention:

[0007] The charge pump phase-locked loop circuit for improving phase noise of the present invention is characterized by:

[0008] The charge pump phase-locked loop comprises a frequency detector, a charge pump, a voltage-controlled oscillator, a frequency divider and a loop filter; a frequency detector branch composed of a frequency detector is arranged in the charge pump phase-locked loop, and the frequency detector branch is connected in parallel between a signal input end of the frequency detector and a signal output end of the charge pump; the signal output end of the frequency detector is connected to a signal input end of the charge pump;

[0009] The frequency discriminator branch converts the frequency difference of the two input signals to obtain a current pulse signal, and the current pulse signal is connected to the loop filter, so that a zero point is added to the loop transfer function of the charge pump phase-locked loop; thereby changing the phase noise transfer function of each component of the circuit, making the output phase noise smaller and the output signal jitter smaller;

[0010] The current pulse signal and the output current of the charge pump are converted into a control voltage through a loop filter, and the control voltage controls the output signal f of the voltage-controlled oscillator. out The output frequency of the voltage controlled oscillator is f out The output frequency is the phase-locked loop output signal frequency;

[0011] The output signal f out The low-frequency feedback signal f is generated by the frequency divider div The two input signals are phase-locked loop input signals f ref and the low frequency feedback signal f div The phase-locked loop input signal f is input by the phase frequency detector ref and the low frequency feedback signal f div The pulse signal is converted into a pulse signal related to the phase difference of the two input signals, and the pulse signal is used to control the charge pump to generate current.

[0012] The charge pump phase-locked loop circuit for improving phase noise of the present invention is also characterized in that:

[0013] The frequency detector branch utilizes a digital logic circuit to convert the frequency difference of the two input signals into a pulse signal width difference, the pulse signal width difference is converted into a voltage difference through a voltage generating circuit, and the voltage difference is converted into the current pulse signal through a sub-sampling charge pump and a pulse generator.

[0014] The charge pump phase-locked loop circuit for improving phase noise of the present invention is also characterized in that:

[0015] The digital logic circuit uses a delay device and a NAND gate to extract the period of an input signal to generate a pulse signal. The pulse signal controls the on and off of a current source through a switch. During the on-time of the switch, the current accumulates charge on the capacitor to generate a voltage signal. After the voltage signal is maintained for a period of time, another control signal controls the capacitor through the switch to derive the charge and set the voltage signal to 0.

[0016] During the voltage signal holding period, the sub-sampling charge pump and the pulse control circuit use the pulse signal PUL generated by the pulse control circuit to turn on the upper current source and the lower current source in the charge pump, and output a current pulse signal related to the frequency difference of the input signal.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0018] 1. The present invention adds a discriminator branch on the basis of the charge pump phase-locked loop. The output current of the discriminator branch depends on the frequency difference of the two input signals, and introduces a zero point for the phase transfer function of the overall loop, thereby changing the noise transfer function of the loop, effectively improving the noise transfer function of the charge pump CP and the voltage-controlled oscillator VCO, reducing the phase noise of the output signal, and reducing signal jitter. Compared with the traditional charge pump phase-locked loop under the same parameters, the output phase noise of the phase-locked loop of the present invention is smaller, and the output signal jitter of 50KHz-10MHz is reduced from 3.98pS of the traditional charge pump phase-locked loop to 2.42pS.

[0019] 2. The present invention introduces a zero point into the phase transfer function of the overall loop by adding a frequency discriminator branch, so that the phase-locked loop can increase the loop bandwidth while ensuring sufficient phase margin, and is not limited by 1 / 10 of the input reference frequency, thereby further suppressing phase noise and reducing the locking time. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a circuit structure diagram of a phase-locked loop circuit of the present invention;

[0021] Figure 2 It is a circuit diagram of a discriminator branch in a phase-locked loop circuit of the present invention;

[0022] Figure 3 It is a timing diagram of each signal in the phase-locked loop circuit of the present invention;

[0023] Figure 4 A comparison of charge pump noise transfer functions between the phase-locked loop circuit of the present invention and a conventional charge pump phase-locked loop circuit;

[0024] Figure 5 A comparison of the voltage controlled oscillator noise transfer function between the phase-locked loop circuit of the present invention and the conventional charge pump phase-locked loop circuit;

[0025] Figure 6 The output signal phase noise comparison between the phase-locked loop circuit of the present invention and the conventional charge pump phase-locked loop circuit is shown; DETAILED DESCRIPTION

[0026] See also Figure 1 , Figure 2 and Figure 3 In this embodiment, the charge pump phase-locked loop circuit for improving phase noise includes a phase frequency detector PFD, a charge pump CP, a voltage-controlled oscillator VCO, a frequency divider N and a loop filter LPF; a frequency detector branch composed of a frequency detector FD is arranged in the charge pump phase-locked loop, and the frequency detector branch is connected in parallel between a signal input end of the phase frequency detector PFD and a signal output end of the charge pump CP; the signal output end of the phase frequency detector PFD is connected to a signal input end of the charge pump CP.

[0027] The frequency discriminator branch FD converts the frequency difference of the two input signals to obtain a current pulse signal, and the current pulse signal is connected to the loop filter LPF, so that a zero point is added to the loop transfer function of the charge pump phase-locked loop; thereby changing the phase noise transfer function of each component of the circuit, reducing the output phase noise and the output signal jitter.

[0028] The current pulse signal and the output current of the charge pump CP are converted into a control voltage through the loop filter LPF, and the control voltage controls the output signal f of the voltage controlled oscillator VCO. out The output frequency of the voltage controlled oscillator VCO is f out The output frequency is the phase-locked loop output signal frequency; the output signal f out The low-frequency feedback signal f is generated by the frequency divider N div ; The two input signals are the phase-locked loop input signal f ref and the low frequency feedback signal f div ; The phase frequency detector PFD converts the phase-locked loop input signal f ref and the low frequency feedback signal f div It is converted into a pulse signal related to the phase difference of the two input signals, and the pulse signal is used to control the charge pump CP to generate current.

[0029] like Figure 2 As shown, in this embodiment, the frequency detector branch FD uses a digital logic circuit 1 to convert the frequency difference of two input signals into a pulse signal width difference, the pulse signal width difference is converted into a voltage difference through a voltage generating circuit 2, and the voltage difference is converted into a current pulse signal through a sub-sampling charge pump SSCP and a pulse generator 3.

[0030] Figure 2 The digital logic circuit 1 shown uses a delay device and a NAND gate to extract the period of an input signal to generate a pulse signal. The pulse signal controls the on and off of a current source through a switch. During the on-time of the switch, the current accumulates charge on the capacitor to generate a voltage signal. After the voltage signal is maintained for a period of time, it is controlled by another control signal to derive the charge through the switch to control the capacitor to set the voltage signal to 0; the sub-sampling charge pump SSCP and the pulse control circuit use the pulse signal PUL generated by the pulse control circuit to turn on the upper current source and the lower current source in the charge pump during the voltage signal holding period, and output a current pulse signal related to the frequency difference of the input signal.

[0031] Figure 2 The digital logic circuit 1 and the voltage generating circuit 2 shown correspond to the phase-locked loop input signal f ref and the low frequency feedback signal f div Set as two independent branches with the same structure; where the phase-locked loop input signal f refAfter flowing into the two branches of the inverter and the delay device, two signals are generated, and the two signals generate a pulse signal REF1 through the NAND gate; the voltage generating circuit 2 is composed of a first current source and a first switch S1 to form a charging circuit of the capacitor C11, the capacitor C11 is connected to the ground, and a second switch S2 is arranged in parallel at both ends of the capacitor C11 to form a discharge circuit of the capacitor C11. The pulse signal REF1 generated by the digital logic circuit 1 is used to control the opening and closing of the first switch S1; the digital logic circuit 1 also generates another control signal to control the opening and closing of the second switch S2; the low-frequency feedback signal f div The digital logic circuit 1 and the voltage generating circuit 2 use the phase-locked loop input signal f ref Same signal processing.

[0032] In the sub-sampling charge pump SSCP and the pulse generator 3, the input signal f ref The two signals generated after passing through the inverter and the delayer generate a pulse signal PUL after passing through the NAND gate. The pulse signal PUL is used to control the switch and then control the on and off of the upper and lower current sources. One end of the upper current source is connected to the power supply, and the other end is connected to the upper switch. Its current is I 0up +gm up ×(Vref-V dc ), where I 0up When the input signal Vref=V dc The current value of the current source, gm up is the transconductance of the upper current source, Vref is the voltage after the capacitor C11 is charged; one end of the lower current source is connected to the ground potential, and the other end is connected to the lower switch, and its current is I 0dn +gm dn ×(Vdiv-V dc ), where I 0dn When the input signal Vdiv=V dc The current value of the current source, and I 0dn =I 0up =I0, gm dn is the transconductance of the lower current source, and gm dn =gm up =gm, Vdiv is the voltage after capacitor C22 is charged;

[0033] Preferred technical solution: Phase-locked loop reference input square wave signal f ref The frequency is selected as 25MHz, and the phase-locked loop outputs a square wave signal f outThe frequency is selected as 2250MHz, the division ratio of the divider is 90, the charge pump CP current is 145uA, and the VCO adopts a ring oscillator circuit with a gain of Kvco=2300MHz / V, loop filter parameters R1=3.23kΩ, C1=103pF, C2=10.3pF; the discriminator branch parameters are set to: I / C=300pA / 500fF, gm=3mS, tpul=300pS.

[0034] Figure 4 The figure shows the comparison of the charge pump noise transfer function of the phase-locked loop circuit of the present invention and the traditional charge pump phase-locked loop circuit; wherein the dotted line is the charge pump noise transfer function of the phase-locked loop circuit of the present invention, and the solid line is the charge pump noise transfer function of the traditional charge pump phase-locked loop circuit; compared with the traditional charge pump phase-locked loop circuit, the parallel discriminator structure has an improved charge pump noise transfer function, and at a loop bandwidth of 2M, the noise transfer function is reduced by 7dB.

[0035] Figure 5 The figure shows the comparison of the voltage controlled oscillator noise transfer function of the phase-locked loop circuit of the present invention and the traditional charge pump phase-locked loop circuit. The dotted line is the voltage controlled oscillator noise transfer function of the phase-locked loop circuit of the present invention, and the solid line is the voltage controlled oscillator noise transfer function of the traditional charge pump phase-locked loop circuit. Compared with the traditional charge pump phase-locked loop circuit, after the parallel frequency discriminator structure is connected, the noise transfer function of the voltage controlled oscillator is improved, and the noise transfer function decreases by 10dB at the loop bandwidth of 2M.

[0036] Figure 6 The figure shows the output signal phase noise comparison between the phase-locked loop circuit of the present invention and the conventional charge pump phase-locked loop circuit. The dotted line is the output signal phase noise of the phase-locked loop circuit of the present invention, and the solid line is the output signal phase noise of the conventional charge pump phase-locked loop circuit. The output signal phase noise of the conventional charge pump is obtained by extracting the noise of each component and performing noise fitting through matlab. By adding a frequency discriminator branch, the output signal phase noise is improved, and the output signal jitter is reduced from 3.98pS to 2.42pS (50KHz-10MHz).

[0037] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments, and the above embodiments and descriptions are only preferred examples of the present invention, and are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. A charge pump phase-locked loop circuit for improving phase noise, characterized in that: The charge pump phase-locked loop comprises a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a frequency divider (N) and a loop filter (LPF); a frequency detector branch composed of a frequency detector (FD) is arranged in the charge pump phase-locked loop, and the frequency detector branch is connected in parallel between a signal input end of the phase frequency detector (PFD) and a signal output end of the charge pump (CP); the signal output end of the phase frequency detector (PFD) is connected to a signal input end of the charge pump (CP); The frequency discriminator branch (FD) converts the frequency difference of the two input signals into a current pulse signal, and the current pulse signal is connected to a loop filter (LPF) so that a zero point is added to the loop transfer function of the charge pump phase-locked loop; thereby changing the phase noise transfer function of each component of the circuit, reducing the output phase noise and the output signal jitter; the frequency discriminator branch (FD) uses a digital logic circuit (1) to convert the frequency difference of the two input signals into a pulse signal width difference, the pulse signal width difference is converted into a voltage difference through a voltage generating circuit (2), and the voltage difference is converted into the current pulse signal through a sub-sampling charge pump (SSCP) and a pulse generator (Pulser); The current pulse signal and the output current of the charge pump (CP) are converted into a control voltage through a loop filter (LPF), and the control voltage controls the output signal f of the voltage controlled oscillator (VCO). out The output frequency of the voltage controlled oscillator (VCO) is out The output frequency is the phase-locked loop output signal frequency; The output signal f out The low frequency feedback signal f is generated by the frequency divider (N) div The two input signals are phase-locked loop input signals f ref and the low frequency feedback signal f div The phase frequency detector (PFD) inputs the phase-locked loop input signal f ref and the low frequency feedback signal f div The pulse signal is converted into a pulse signal related to the phase difference of the two input signals, and the pulse signal is used to control a charge pump (CP) to generate current.

2. The charge pump phase-locked loop circuit for improving phase noise according to claim 1, characterized in that: The digital logic circuit (1) uses a delay device and a NAND gate to extract the period of an input signal to generate a pulse signal. The pulse signal controls the on and off of a current source through a switch. During the on-time of the switch, the current accumulates charge on a capacitor to generate a voltage signal. After the voltage signal is maintained for a period of time, another control signal is used to control the capacitor through the switch to derive the charge and set the voltage signal to 0. During the voltage signal holding period, the sub-sampling charge pump (SSCP) and the pulse control circuit (Pulser) use the pulse signal PUL generated by the pulse control circuit to turn on the upper current source and the lower current source in the charge pump, and output a current pulse signal related to the frequency difference of the input signal.

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