LED chip and preparation method thereof

Abstract

The application provides an LED chip and a preparation method thereof. A first current blocking layer and a current spreading layer are sequentially formed on a mesa of an epitaxial stack, and a P-type electrode comprises an interconnected P-type connecting part and a P-type spreading part. The P-type connecting part is laminated on a surface of the first current blocking layer and connected with the P-type semiconductor layer by embedding the first current blocking layer through a through hole. The P-type spreading part extends to the edge of the mesa from the periphery of the P-type connecting part by being laminated on the surface of the current spreading layer. In this way, the current crowding phenomenon caused by a large driving current is solved, and the external quantum efficiency of the LED is effectively improved. Meanwhile, the P-type connecting part is laminated on the surface of the first current blocking layer and connected with the P-type semiconductor layer by embedding the first current blocking layer through a through hole, so that the falling-off problem of the electrode is effectively solved, and the reliability of the LED chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of light emitting diode, in particular to a LED chip and a preparation method thereof. BACKGROUND

[0002] With the rapid development of LED technology and the gradual improvement of LED light efficiency, the application of LED is more and more extensive, and people pay more and more attention to the development prospect of LED in display screen. LED chip, as the core component of LED lamp, its function is to convert electrical energy into light energy, specifically, including an epitaxial wafer and N-type electrode and P-type electrode arranged on the epitaxial wafer. The epitaxial wafer includes a P-type semiconductor layer, an N-type semiconductor layer and an active layer between the N-type semiconductor layer and the P-type semiconductor layer. When current passes through the LED chip, the holes in the P-type semiconductor and the electrons in the N-type semiconductor will move to the active layer, and recombine in the active layer, so that the LED chip emits light.

[0003] With the market demand for the brightness of light emitting diode is higher and higher, the size of the chip is made bigger and bigger, the driving current is also bigger, and the high-power LED is obtained. The chip structure needs to be continuously improved and optimized; at present, various electrode optimized chip structures become the mainstream structure of super brightness chip; however, there are still problems of electrode current congestion and poor reliability.

[0004] Therefore, in order to overcome the above defects of the prior art LED chip, the present application is designed, and the present application is produced. SUMMARY

[0005] The purpose of the present application is to provide a LED chip and a preparation method thereof, to solve the problems of LED chip current congestion and electrode reliability.

[0006] In order to achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0007] A LED chip, comprising:

[0008] a substrate;

[0009] an epitaxial stack arranged on the surface of the substrate, the epitaxial stack at least comprising an N-type semiconductor layer, an active region and a P-type semiconductor layer stacked in a first direction in sequence, and a local area of the epitaxial stack is etched to part of the N-type semiconductor layer to form a groove and a mesa; the first direction is perpendicular to the substrate and points from the substrate to the epitaxial stack;

[0010] a first current blocking layer laminated on part of the surface of the mesa;

[0011] a current spreading layer laminated on the mesa and covering at least part of the first current blocking layer;

[0012] a P-type electrode comprising a P-type connecting portion and a P-type spreading portion interconnected; wherein the P-type connecting portion is laminated on a surface of the first current blocking layer and forms a connection with the P-type semiconductor layer by means of embedding the first current blocking layer through a via; the P-type spreading portion extends to the edge of the mesa from the periphery of the P-type connecting portion by means of lamination on the surface of the current spreading layer; and the P-type spreading portion overlaps the projection of the first current blocking layer on the surface of the substrate;

[0013] an N-type electrode laminated on the recess;

[0014] a passivation layer covering the P-type spreading portion and the exposed part of the epitaxial stack.

[0015] Preferably, the projected area of the P-type spreading portion on the surface of the substrate is less than the projected area of the first current blocking layer on the surface of the substrate.

[0016] Preferably, a second current blocking layer is provided on the bottom surface of the recess, and the N-type electrode comprises an N-type connecting portion and an N-type spreading portion interconnected;

[0017] wherein the N-type connecting portion is laminated on a surface of the second current blocking layer and forms a connection with the N-type semiconductor layer by means of embedding the second current blocking layer through a via; the N-type spreading portion extends to the direction of the mesa from the periphery of the N-type connecting portion by means of lamination on the surface of the second current blocking layer, and the N-type connecting portion is arranged away from the sidewall of the recess;

[0018] and the passivation layer also covers the N-type spreading portion.

[0019] Preferably, the N-type semiconductor layer comprises a first N-type semiconductor layer and a second N-type semiconductor layer stacked in sequence along the surface of the substrate, and the N-type doping concentration of the second N-type semiconductor layer is greater than that of the first N-type semiconductor layer.

[0020] Preferably, the recess has an inclined bottom surface, and the inclined bottom surface exposes the second N-type semiconductor layer near one end of the sidewall of the recess, exposes the first N-type semiconductor layer at the other end of the inclined bottom surface, and at least part of the N-type spreading portion is formed corresponding to the exposed part of the second N-type semiconductor layer.

[0021] Preferably, the groove has a stepped bottom surface, and the stepped bottom surface exposes the second N-type semiconductor layer at one end close to the side wall of the groove, exposes the first N-type semiconductor layer at the opposite end, and at least part of the N-type extension part is formed corresponding to the exposed part of the second N-type semiconductor layer.

[0022] Preferably, at least part of the N-type connecting part is laminated on the exposed part of the first N-type semiconductor layer.

[0023] Preferably, the area of the N-type extension part provided on the exposed part of the first N-type semiconductor layer is S1, the area of the N-type extension part provided on the exposed part of the second N-type semiconductor layer is S2, and S2≥S1.

[0024] Preferably, the current expansion layer is a transparent conductive material, and specifically can include one or more of ITO transparent conductive layer, IZO transparent conductive layer.

[0025] The application also provides a preparation method of an LED chip, which comprises the following steps:

[0026] Step S01, providing a substrate;

[0027] Step S02, laminating an epitaxial layer on the surface of the substrate, the epitaxial layer comprising an N-type semiconductor layer, an active region and a second-type semiconductor layer stacked in sequence along a first direction, the first direction being perpendicular to the substrate and pointing from the substrate to the epitaxial layer;

[0028] Step S03, etching part of the epitaxial layer to part of the N-type semiconductor layer to form a groove and a mesa;

[0029] Step S04, depositing a current blocking layer, so that the mesa forms a first current blocking layer and the groove forms a second current blocking layer;

[0030] Step S05, making a current expansion layer laminated on the mesa and covering the first current blocking layer;

[0031] Step S06, etching the current expansion layer and the first current blocking layer to form a through hole with the P-type semiconductor layer exposed;

[0032] Etching the second current blocking layer to form a through hole with the N-type semiconductor layer exposed;

[0033] Step S07, evaporation to form a P-type electrode and an N-type electrode;

[0034] The P-type electrode comprises an interconnected P-type connecting portion and a P-type extending portion; wherein the P-type connecting portion is laminated on the surface of the first current blocking layer and is connected with the P-type semiconductor layer by embedding the first current blocking layer through a via hole; the P-type extending portion extends to the edge of the mesa from the periphery of the P-type connecting portion by laminating on the surface of the current extending layer; and the P-type extending portion and the first current blocking layer overlap in the projection on the surface of the substrate;

[0035] The N-type electrode comprises an interconnected N-type connecting portion and an N-type extending portion; wherein the N-type connecting portion is laminated on the surface of the second current blocking layer and is connected with the N-type semiconductor layer by embedding the second current blocking layer through a via hole; the N-type extending portion extends to the mesa direction from the periphery of the N-type connecting portion by laminating on the surface of the second current blocking layer, and the N-type connecting portion is arranged away from the sidewall of the groove;

[0036] Step S08, a passivation layer is made to cover the N-type extending portion, the P-type extending portion and the exposed part of the epitaxial stack.

[0037] Preferably, the N-type semiconductor layer comprises a first N-type semiconductor layer and a second N-type semiconductor layer stacked in sequence along the surface of the substrate, and the N-type doping concentration of the second N-type semiconductor layer is greater than that of the first N-type semiconductor layer.

[0038] Preferably, the groove has an inclined bottom surface, and the inclined bottom surface exposes the second N-type semiconductor layer near one end of the sidewall of the groove, the other end of the inclined bottom surface exposes the first N-type semiconductor layer, and at least part of the N-type extending portion is formed corresponding to the exposed part of the second N-type semiconductor layer, and at least part of the N-type connecting portion is laminated on the exposed part of the first N-type semiconductor layer.

[0039] Preferably, the groove has a stepped bottom surface, and the stepped bottom surface exposes the second N-type semiconductor layer near one end of the sidewall of the groove, and exposes the first N-type semiconductor layer at the opposite end, and at least part of the N-type extending portion is formed corresponding to the exposed part of the second N-type semiconductor layer.

[0040] Preferably, the area of the N-type extending portion arranged on the exposed part of the first N-type semiconductor layer is S1, the area of the N-type extending portion arranged on the exposed part of the second N-type semiconductor layer is S2, and S2≥S1.

[0041] The LED chip provided by the technical scheme has the first current blocking layer and the current spreading layer formed in sequence on the mesa of the epitaxial stack, and the P-type electrode comprises the interconnected P-type connecting part and P-type spreading part; the P-type connecting part is stacked on the surface of the first current blocking layer and connected with the P-type semiconductor layer by embedding the first current blocking layer through the via hole; the P-type spreading part extends to the edge of the mesa from the periphery of the P-type connecting part by being stacked on the surface of the current spreading layer; and the projection of the P-type spreading part and the first current blocking layer on the surface of the substrate is overlapped. Thus, the current flowing through the P-type spreading part is blocked by the first current blocking layer below the P-type spreading part, spreads to the edge of the mesa through the current spreading layer, and then diffuses uniformly on the light-emitting mesa (i.e. P surface). Therefore, based on the above structure, the current crowding phenomenon caused by the large driving current is solved, and the external quantum efficiency of the LED is effectively improved. Meanwhile, the P-type connecting part is stacked on the surface of the first current blocking layer and connected with the P-type semiconductor layer by embedding the first current blocking layer through the via hole, which can effectively solve the problem of electrode falling off and improve the reliability of the LED chip.

[0042] Similarly, the N-type electrode comprises the interconnected N-type connecting part and N-type spreading part; the N-type connecting part is stacked on the surface of the second current blocking layer and connected with the N-type semiconductor layer by embedding the second current blocking layer through the via hole; the N-type spreading part extends to the mesa direction from the periphery of the N-type connecting part by being stacked on the surface of the second current blocking layer, and the N-type connecting part is arranged away from the side wall of the groove. The current can also be diffused uniformly on the light-emitting N surface, and the problem of electrode falling off is also effectively solved, and the reliability of the LED chip is improved.

[0043] Secondly, the N-type semiconductor layer comprises the first N-type semiconductor layer and the second N-type semiconductor layer stacked in sequence along the surface of the substrate, and the N-type doping concentration of the second N-type semiconductor layer is greater than that of the first N-type semiconductor layer. Further, the groove has an inclined bottom surface, the second N-type semiconductor layer is exposed at one end of the inclined bottom surface close to the side wall of the groove, the first N-type semiconductor layer is exposed at the other end of the inclined bottom surface, and at least part of the N-type spreading part is formed corresponding to the exposed part of the second N-type semiconductor layer. Since the N-type spreading part is arranged on the surface of the low-doped N-type semiconductor layer at the side close to the N-type connecting part, the resistance value thereof is relatively large; and the N-type spreading part is arranged on the surface of the high-doped N-type semiconductor layer away from the N-type connecting part (i.e. the tail end of the N-type connecting part), and the resistance value thereof is relatively small; thus, the current on the N surface is guided to spread to the tail end of the N-type connecting part (i.e. the end close to the side wall of the groove) after being introduced through the N-type electrode, and then diffuses more uniformly on the N surface.

[0044] Then, the area of the N-type extension part arranged at the first N-type semiconductor layer exposed part is S1, the area of the N-type extension part arranged at the second N-type semiconductor layer exposed part is S2, and S2≥S1. Thus, the current distribution ratio of the head and tail of the N-type connecting part is effectively adjusted, and the current distribution of the tail of the N-type connecting part (i.e., the end close to the groove sidewall) is fully ensured, so that the current is more uniformly diffused on the N surface.

[0045] Via the technical solution described above, the preparation method of the LED chip provided by the application can achieve the beneficial effects of the LED chip, and the process is simple and convenient for production. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0047] Figure 1 The structure schematic diagram of the LED chip provided by the embodiment 1 of the present application;

[0048] Figures 2.1 to 2.8 The structure schematic diagram corresponding to the manufacturing method steps of the LED chip provided by the embodiment 1 of the present application;

[0049] Figure 3 The structure schematic diagram of the LED chip provided by the embodiment 2 of the present application;

[0050] Figures 4.1 to 4.8 The structure schematic diagram corresponding to the manufacturing method steps of the LED chip provided by the embodiment 2 of the present application;

[0051] Figure 5 The structure schematic diagram of the LED chip provided by the embodiment 3 of the present application;

[0052] Symbol explanation in the figure: 1, substrate, 2, N-type semiconductor layer, 2.1, first N-type semiconductor layer, 2.2, second N-type semiconductor layer, 3, active region, 4, P-type semiconductor layer, 5.1, first current blocking layer, 5.2, second current blocking layer, 6, current expansion layer, 7.1, P-type connecting part, 7.2, P-type extension part, 8.1, N-type connecting part, 8.2, N-type extension part, 9, passivation layer, 10, mesa, 11, groove, 12, via hole. DETAILED DESCRIPTION

[0053] In order to make the content of the present application more clear, the content of the present application is further explained below in combination with the drawings. The present application is not limited to this specific embodiment. Based on the embodiment in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of the present application.

[0054] Embodiment 1

[0055] As shown in FIG. 1, an LED chip comprises: Figure 1

[0056] a substrate 1;

[0057] an epitaxial stack arranged on the surface of the substrate 1, the epitaxial stack comprising at least an N-type semiconductor layer 2, an active region 3 and a P-type semiconductor layer 4 stacked in sequence along a first direction, and a partial region of the epitaxial stack is etched to form a mesa 10 and a groove 11 in part of the N-type semiconductor layer 2; the first direction is perpendicular to the substrate 1 and points from the substrate 1 to the epitaxial stack;

[0058] a first current blocking layer 5.1 laminated on part of the surface of the mesa 10;

[0059] a current spreading layer 6 laminated on the mesa 10 and covering at least part of the first current blocking layer 5.1;

[0060] a P-type electrode comprising an interconnected P-type connecting part 7.1 and a P-type spreading part 7.2; wherein the P-type connecting part 7.1 is laminated on the surface of the first current blocking layer 5.1 and forms a connection with the P-type semiconductor layer 4 by embedding the first current blocking layer 5.1 through the via hole 12; the P-type spreading part 7.2 extends to the edge of the mesa 10 from the periphery of the P-type connecting part 7.1 by laminating on the surface of the current spreading layer 6; and the projection of the P-type spreading part 7.2 and the first current blocking layer 5.1 on the surface of the substrate 1 overlaps;

[0061] an N-type electrode laminated on the groove 11;

[0062] a passivation layer 9 covering the P-type spreading part 7.2 and the exposed part of the epitaxial stack.

[0063] It is worth mentioning that the type of the substrate 1 is not limited in the LED chip of the present embodiment, for example, the substrate 1 can be but is not limited to a sapphire substrate 1, a silicon substrate 1, etc. In addition, the materials of the N-type semiconductor layer 2, the active region 3 and the P-type semiconductor layer 4 of the epitaxial stack in the LED chip of the present embodiment can also be unlimited, for example, the N-type semiconductor layer 2 can be but is not limited to an N-type gallium nitride layer, and accordingly, the P-type semiconductor layer 4 can be but is not limited to a P-type gallium nitride layer;

[0064] ​It should be noted that the embodiments of the present invention do not limit the number and distribution of the P-type extensions 7.2, and can be adaptively adjusted according to product requirements (including size, light emission parameters, etc.).

[0065] Similarly, the material of passivation layer 9 can be, but is not limited to, SiO2 (silicon dioxide).

[0066] In addition, P-type and N-type electrodes can be, but are not limited to, gold-tin electrodes.

[0067] In this embodiment of the invention, the projected area of ​​the P-type extension 7.2 on the surface of the substrate 1 is smaller than the projected area of ​​the first current blocking layer 5.1 on the surface of the substrate 1.

[0068] In this embodiment of the invention, a second current blocking layer 5.2 is provided on the bottom surface of the groove 11, and the N-type electrode includes an interconnected N-type connection portion 8.1 and an N-type extension portion 8.2;

[0069] The N-type connection portion 8.1 is stacked on the surface of the second current blocking layer 5.2 and is connected to the N-type semiconductor layer 2 by being embedded in the second current blocking layer 5.2 through the through hole 12; the N-type extension portion 8.2 extends from the periphery of the N-type connection portion 8.1 towards the mesa 10 by being stacked on the surface of the second current blocking layer 5.2, and the N-type connection portion 8.1 is disposed away from the sidewall of the groove 11;

[0070] Furthermore, the passivation layer 9 also covers the N-type extension portion 8.2.

[0071] It should be noted that the embodiments of the present invention do not limit the number and distribution of the N-type extensions 8.2. The number and relative positions of the N-type extensions 8.2 and the P-type extensions 7.2 can be adaptively adjusted according to product requirements (including size, light emission parameters, etc.).

[0072] In this embodiment of the invention, the current spreading layer 6 is a transparent conductive material, which may specifically include one or more of ITO transparent conductive layers and IZO transparent conductive layers.

[0073] This invention also provides a method for fabricating an LED chip, the method comprising the following steps:

[0074] Step S01, as follows Figure 2.1 As shown, a substrate 1 is provided;

[0075] Step S02, as follows Figure 2.2 As shown, an epitaxial stack is stacked on the surface of substrate 1. The epitaxial stack includes an N-type semiconductor layer 2, an active region 3, and a second-type semiconductor layer stacked sequentially along a first direction. The first direction is perpendicular to substrate 1 and points from substrate 1 to the epitaxial stack.

[0076] Step S03, as followsFigure 2.3 As shown, a local region of the epitaxial stack is etched to part of the N-type semiconductor layer 2 to form a recess 11 and a mesa 10;

[0077] Step S04, as shown in the figure, a current blocking layer is deposited to form a first current blocking layer 5.1 for the mesa 10 and a second current blocking layer 5.2 for the recess 11; Figure 2.4

[0078] Step S05, as shown in the figure, a current spreading layer 6 is made to be laminated on the mesa 10 and cover the first current blocking layer 5.1; Figure 2.5

[0079] Step S06, as shown in the figure, the current spreading layer 6 and the first current blocking layer 5.1 are etched to form a via 12 with exposed P-type semiconductor layer 4; Figure 2.6

[0080] The second current blocking layer 5.2 is etched to form a via 12 with exposed N-type semiconductor layer 2;

[0081] Step S07, as shown in the figure, a P-type electrode and an N-type electrode are formed by evaporation; Figure 2.7

[0082] The P-type electrode includes an interconnected P-type connecting part 7.1 and a P-type spreading part 7.2; wherein the P-type connecting part 7.1 is laminated on the surface of the first current blocking layer 5.1 and is embedded into the first current blocking layer 5.1 through the via 12 to form a connection with the P-type semiconductor layer 4; the P-type spreading part 7.2 extends to the edge of the mesa 10 from the periphery of the P-type connecting part 7.1 by being laminated on the surface of the current spreading layer 6; and the projection of the P-type spreading part 7.2 and the first current blocking layer 5.1 on the surface of the substrate 1 overlaps;

[0083] The N-type electrode includes an interconnected N-type connecting part 8.1 and an N-type spreading part 8.2; wherein the N-type connecting part 8.1 is laminated on the surface of the second current blocking layer 5.2 and is embedded into the second current blocking layer 5.2 through the via 12 to form a connection with the N-type semiconductor layer 2; the N-type spreading part 8.2 extends to the direction of the mesa 10 from the periphery of the N-type connecting part 8.1 by being laminated on the surface of the second current blocking layer 5.2, and the N-type connecting part 8.1 is arranged away from the sidewall of the recess 11;

[0084] Step S08, as shown in the figure, a passivation layer 9 is made to cover the N-type spreading part 8.2, the P-type spreading part 7.2 and the exposed part of the epitaxial stack. Figure 2.8

[0085] ​​​​​Via the technical solution, the LED chip provided by the application is characterized in that the first current blocking layer 5.1 and the current spreading layer 6 are sequentially formed on the mesa 10 of the epitaxial stack, and the P-type electrode comprises the interconnected P-type connecting part 7.1 and the P-type spreading part 7.2; the P-type connecting part 7.1 is laminated on the surface of the first current blocking layer 5.1 and is connected with the P-type semiconductor layer 4 by being embedded in the first current blocking layer 5.1 through the via hole 12; the P-type spreading part 7.2 extends to the edge of the mesa 10 from the periphery of the P-type connecting part 7.1 by being laminated on the surface of the current spreading layer 6; and the projection of the P-type spreading part 7.2 and the first current blocking layer 5.1 on the surface of the substrate 1 overlaps. Thus, the current flowing through the P-type spreading part 7.2 is blocked by the first current blocking layer 5.1 below the P-type spreading part 7.2, and then spreads to the edge of the mesa 10 through the current spreading layer 6, so that the current is uniformly diffused on the light-emitting mesa 10 (i.e. the P surface). Therefore, based on the above structure, the current crowding phenomenon caused by a large driving current is solved, and the external quantum efficiency of the LED is effectively improved. Meanwhile, the P-type connecting part 7.1 is laminated on the surface of the first current blocking layer 5.1 and is connected with the P-type semiconductor layer 4 by being embedded in the first current blocking layer 5.1 through the via hole 12, so that the falling-off problem of the electrode is effectively solved, and the reliability of the LED chip is improved.

[0086] Similarly, the N-type electrode comprises the interconnected N-type connecting part 8.1 and the N-type spreading part 8.2; the N-type connecting part 8.1 is laminated on the surface of the second current blocking layer 5.2 and is connected with the N-type semiconductor layer 2 by being embedded in the second current blocking layer 5.2 through the via hole 12; the N-type spreading part 8.2 extends to the mesa 10 from the periphery of the N-type connecting part 8.1 by being laminated on the surface of the second current blocking layer 5.2, and the N-type connecting part 8.1 is arranged away from the side wall of the groove 11. Thus, the current is uniformly diffused on the light-emitting N surface, and the falling-off problem of the electrode is effectively solved, and the reliability of the LED chip is improved.

[0087] Via the technical solution, the LED chip provided by the application is characterized in that the first current blocking layer 5.1 and the current spreading layer 6 are sequentially formed on the mesa 10 of the epitaxial stack, and the P-type electrode comprises the interconnected P-type connecting part 7.1 and the P-type spreading part 7.2; the P-type connecting part 7.1 is laminated on the surface of the first current blocking layer 5.1 and is connected with the P-type semiconductor layer 4 by being embedded in the first current blocking layer 5.1 through the via hole 12; the P-type spreading part 7.2 extends to the edge of the mesa 10 from the periphery of the P-type connecting part 7.1 by being laminated on the surface of the current spreading layer 6; and the projection of the P-type spreading part 7.2 and the first current blocking layer 5.1 on the surface of the substrate 1 overlaps. Thus, the current flowing through the P-type spreading part 7.2 is blocked by the first current blocking layer 5.1 below the P-type spreading part 7.2, and then spreads to the edge of the mesa 10 through the current spreading layer 6, so that the current is uniformly diffused on the light-emitting mesa 10 (i.e. the P surface). Therefore, based on the above structure, the current crowding phenomenon caused by a large driving current is solved, and the external quantum efficiency of the LED is effectively improved. Meanwhile, the P-type connecting part 7.1 is laminated on the surface of the first current blocking layer 5.1 and is connected with the P-type semiconductor layer 4 by being embedded in the first current blocking layer 5.1 through the via hole 12, so that the falling-off problem of the electrode is effectively solved, and the reliability of the LED chip is improved.

[0088] Example 2

[0089] As Figure 3 shown, an LED chip comprises:

[0090] a substrate 1;

[0091] An epitaxial stack is arranged on a surface of a substrate 1, the epitaxial stack at least comprising an N-type semiconductor layer 2, an active region 3 and a P-type semiconductor layer 4 stacked in a first direction in sequence, and a partial region of the epitaxial stack is etched to form a recess 11 and a mesa 10 by exposing a part of the N-type semiconductor layer 2; the first direction is perpendicular to the substrate 1 and points from the substrate 1 to the epitaxial stack; wherein the N-type doping concentration of a second N-type semiconductor layer 2.2 is greater than that of a first N-type semiconductor layer 2.1; the recess 11 has an inclined bottom surface, and an end of the inclined bottom surface close to a side wall of the recess 11 exposes the second N-type semiconductor layer 2.2, and the other end of the inclined bottom surface exposes the first N-type semiconductor layer 2.1;

[0092] A first current blocking layer 5.1 is laminated on a part of the surface of the mesa 10;

[0093] A current spreading layer 6 is laminated on the mesa 10 and covers at least a part of the first current blocking layer 5.1;

[0094] A P-type electrode comprising an interconnected P-type connecting part 7.1 and a P-type spreading part 7.2; wherein the P-type connecting part 7.1 is laminated on the surface of the first current blocking layer 5.1 and forms a connection with the P-type semiconductor layer 4 by embedding the first current blocking layer 5.1 through the via hole 12; the P-type spreading part 7.2 extends to the edge of the mesa 10 from the periphery of the P-type connecting part 7.1 by laminating on the surface of the current spreading layer 6; and the projection of the P-type spreading part 7.2 and the first current blocking layer 5.1 on the surface of the substrate 1 overlaps;

[0095] An N-type electrode laminated on the recess 11;

[0096] A passivation layer 9 covering the P-type spreading part 7.2 and the exposed part of the epitaxial stack.

[0097] It is worth mentioning that the type of the substrate 1 is not limited in the LED chip of the embodiment, for example, the substrate 1 can be but is not limited to a sapphire substrate 1, a silicon substrate 1, etc. In addition, the materials of the N-type semiconductor layer 2, the active region 3 and the P-type semiconductor layer 4 of the epitaxial stack in the LED chip of the embodiment can also be not limited, for example, the N-type semiconductor layer 2 can be but is not limited to an N-type gallium nitride layer, and correspondingly, the P-type semiconductor layer 4 can be but is not limited to a P-type gallium nitride layer;

[0098] It should be noted that the number and distribution state of the P-type spreading part 7.2 are not limited in the embodiment of the application, and can be adaptively adjusted according to product requirements (including size, light emitting parameters, etc.).

[0099] It should be noted that the embodiment of the present application does not limit the first N-type semiconductor layer 2.1 and the second N-type semiconductor layer 2.2, as long as the N-type doping concentration of the second N-type semiconductor layer 2.2 is greater than the N-type doping concentration of the first N-type semiconductor layer 2.1, and the N-type semiconductor layer 2 can cooperate with the active region 3 and the P-type semiconductor layer 4 to realize the light-emitting requirement of the LED.

[0100] Similarly, the material of the passivation layer 9 can be, but is not limited to, SiO2 (silicon dioxide).

[0101] In addition, the P-type electrode and the N-type electrode can be, but are not limited to, gold-tin electrodes.

[0102] In the embodiment of the present application, the projection area of the P-type extension part 7.2 on the surface of the substrate 1 is smaller than the projection area of the first current blocking layer 5.1 on the surface of the substrate 1.

[0103] In the embodiment of the present application, the second current blocking layer 5.2 is arranged on the bottom surface of the groove 11, and the N-type electrode comprises an interconnected N-type connecting part 8.1 and an N-type extension part 8.2.

[0104] The N-type connecting part 8.1 is stacked on the surface of the second current blocking layer 5.2 and is connected with the N-type semiconductor layer 2 by being embedded into the second current blocking layer 5.2 through the via hole 12; the N-type extension part 8.2 extends from the periphery of the N-type connecting part 8.1 to the mesa 10 by being stacked on the surface of the second current blocking layer 5.2, and at least part of the N-type connecting part 8.1 is stacked on the exposed part of the first N-type semiconductor layer 2.1, and at least part of the N-type extension part 8.2 is formed corresponding to the exposed part of the second N-type semiconductor layer 2.2; and the N-type connecting part 8.1 is arranged away from the sidewall of the groove 11.

[0105] In addition, the passivation layer 9 also covers the N-type extension part 8.2.

[0106] It should be noted that the embodiment of the present application does not limit the number and distribution state of the N-type extension part 8.2, and the number and mutual position relationship of the N-type extension part 8.2 and the P-type extension part 7.2 can be adaptively adjusted according to product requirements (including size, light-emitting parameters, etc.).

[0107] In the embodiment of the present application, the area of the N-type extension part 8.2 arranged on the exposed part of the first N-type semiconductor layer 2.1 is S1, the area of the N-type extension part 8.2 arranged on the exposed part of the second N-type semiconductor layer 2.2 is S2, and S2≥S1.

[0108] The embodiment of the present application also provides a preparation method of an LED chip, and the preparation method comprises the following steps:

[0109] Step S01, as shown in Figure 4.1 Fig. 1, a substrate 1 is provided.

[0110] Step S02, as shown in the figure, laminates an epitaxial stack on the surface of the substrate 1, the epitaxial stack includes N-type semiconductor layer 2, active region 3 and second-type semiconductor layer stacked in turn along the first direction, the first direction is perpendicular to the substrate 1, and is directed from the substrate 1 to the epitaxial stack; and the N-type semiconductor layer 2 includes the first N-type semiconductor layer 2.1 and the second N-type semiconductor layer 2.2 stacked in turn along the surface of the substrate 1, and the N-type doping concentration of the second N-type semiconductor layer 2.2 is greater than that of the first N-type semiconductor layer 2.1; Figure 4.2 Step S03, as shown in the figure, etches a partial region of the epitaxial stack to part of the N-type semiconductor layer 2 to form a mesa 10 and a groove 11; wherein the groove 11 has an inclined bottom surface, and the inclined bottom surface exposes the second N-type semiconductor layer 2.2 at one end close to the side wall of the groove 11, and exposes the first N-type semiconductor layer 2.1 at the other end;

[0111] Figure 4.3 Step S04, as shown in the figure, deposits a current blocking layer, so that the mesa 10 forms a first current blocking layer 5.1, and the groove 11 forms a second current blocking layer 5.2;

[0112] Step S05, as shown in the figure, makes a current spreading layer 6, which is laminated on the mesa 10 and covers the first current blocking layer 5.1; Figure 4.4 Step S06, as shown in the figure, etches the current spreading layer 6 and the first current blocking layer 5.1 to form a via hole 12 with the P-type semiconductor layer 4 exposed;

[0113] Figure 4.5 Etch the second current blocking layer 5.2 to form a via hole 12 with the N-type semiconductor layer 2 exposed;

[0114] Step S07, as shown in the figure, vapor deposition forms a P-type electrode and an N-type electrode; Figure 4.6 The P-type electrode includes an interconnected P-type connecting part 7.1 and a P-type spreading part 7.2; wherein the P-type connecting part 7.1 is laminated on the surface of the first current blocking layer 5.1, and is embedded in the first current blocking layer 5.1 in a manner through the via hole 12 to form a connection with the P-type semiconductor layer 4; the P-type spreading part 7.2 extends to the edge of the mesa 10 from the periphery of the P-type connecting part 7.1 in a manner laminated on the surface of the current spreading layer 6; and the P-type spreading part 7.2 and the first current blocking layer 5.1 overlap in projection on the surface of the substrate 1;

[0115] The N-type electrode includes an interconnected N-type connecting part 8.1 and an N-type spreading part 8.2; wherein the N-type connecting part 8.1 is laminated on the surface of the second current blocking layer 5.2, and is embedded in the second current blocking layer 5.2 in a manner through the via hole 12 to form a connection with the N-type semiconductor layer 2; the N-type spreading part 8.2 extends to the edge of the mesa 10 from the periphery of the N-type connecting part 8.1 in a manner laminated on the surface of the current spreading layer 6; and the N-type spreading part 8.2 and the second current blocking layer 5.2 overlap in projection on the surface of the substrate 1;

[0116] Figure 4.7 Step S08, as shown in the figure, forms a P-type electrode and an N-type electrode by vapor deposition;

[0117] The P-type electrode includes an interconnected P-type connecting part 7.1 and a P-type spreading part 7.2; wherein the P-type connecting part 7.1 is laminated on the surface of the first current blocking layer 5.1, and is embedded in the first current blocking layer 5.1 in a manner through the via hole 12 to form a connection with the P-type semiconductor layer 4; the P-type spreading part 7.2 extends to the edge of the mesa 10 from the periphery of the P-type connecting part 7.1 in a manner laminated on the surface of the current spreading layer 6; and the P-type spreading part 7.2 and the first current blocking layer 5.1 overlap in projection on the surface of the substrate 1;

[0118] ​​​The N-type electrode includes interconnected N-type connection portions 8.1 and N-type extension portions 8.2; wherein, the N-type connection portion 8.1 is stacked on the surface of the second current blocking layer 5.2 and is connected to the N-type semiconductor layer 2 by being embedded in the second current blocking layer 5.2 through a through-hole 12; the N-type extension portion 8.2 extends from the periphery of the N-type connection portion 8.1 toward the mesa 10 by being stacked on the surface of the second current blocking layer 5.2; and at least a portion of the N-type connection portion 8.1 is stacked on the exposed portion of the first N-type semiconductor layer 2.1, and at least a portion of the N-type extension portion 8.2 is formed corresponding to the exposed portion of the second N-type semiconductor layer 2.2; and the N-type connection portion 8.1 is disposed away from the sidewall of the groove 11;

[0119] Step S08, as follows Figure 4.8 As shown, a passivation layer 9 is fabricated, which covers the N-type extension portion 8.2, the P-type extension portion 7.2, and the exposed portion of the epitaxial stack.

[0120] Preferably, the area of ​​the N-type extension portion 8.2 disposed on the exposed portion of the first N-type semiconductor layer 2.1 is S1, and the area of ​​the N-type extension portion 8.2 disposed on the exposed portion of the second N-type semiconductor layer 2.2 is S2, then S2≥S1.

[0121] As can be seen from the above technical solution, the LED chip provided by the present invention has a first current blocking layer 5.1 and a current spreading layer 6 sequentially formed on the mesa 10 of the epitaxial stack, and the P-type electrode includes interconnected P-type connection portions 7.1 and P-type spreading portions 7.2; wherein, the P-type connection portion 7.1 is stacked on the surface of the first current blocking layer 5.1 and is connected to the P-type semiconductor layer 4 by embedding the first current blocking layer 5.1 through a via 12; the P-type spreading portion 7.2 extends from the periphery of the P-type connection portion 7.1 to the edge of the mesa 10 by being stacked on the surface of the current spreading layer 6; and the projection of the P-type spreading portion 7.2 and the first current blocking layer 5.1 on the surface of the substrate 1 overlaps. Thus, the current flowing through the P-type spreading portion 7.2 is blocked by the first current blocking layer 5.1 below it and spreads to the edge of the mesa 10 through the current spreading layer 6, thereby making the current diffuse uniformly on the light-emitting mesa 10 (i.e., the P-plane); therefore, based on the above structure, the current congestion phenomenon caused by large driving current is solved, and the external quantum efficiency of the LED is effectively improved. Meanwhile, the P-type connection portion 7.1 is stacked on the surface of the first current blocking layer 5.1 and is connected to the P-type semiconductor layer 4 by embedding the first current blocking layer 5.1 through the through hole 12, which can effectively solve the problem of electrode detachment and improve the reliability of the LED chip.

[0122] Similarly, the N-type electrode comprises an N-type connecting part 8.1 and an N-type extending part 8.2 which are interconnected; the N-type connecting part 8.1 is laminated on the surface of the second current blocking layer 5.2 and is connected with the N-type semiconductor layer 2 by embedding the second current blocking layer 5.2 through the via hole 12; the N-type extending part 8.2 extends from the periphery of the N-type connecting part 8.1 to the mesa 10 by laminating on the surface of the second current blocking layer 5.2, and the N-type connecting part 8.1 is arranged away from the side wall of the groove 11. The current can be uniformly diffused on the light-emitting N surface, and the problem of electrode falling off is effectively solved, and the reliability of the LED chip is improved.

[0123] Secondly, the N-type semiconductor layer 2 comprises a first N-type semiconductor layer 2.1 and a second N-type semiconductor layer 2.2 which are stacked in sequence along the surface of the substrate 1, and the N-type doping concentration of the second N-type semiconductor layer 2.2 is greater than that of the first N-type semiconductor layer 2.1. Further, the groove 11 has an inclined bottom surface, one end of the inclined bottom surface near the side wall of the groove 11 exposes the second N-type semiconductor layer 2.2, the other end of the inclined bottom surface exposes the first N-type semiconductor layer 2.1, and at least part of the N-type extending part 8.2 is formed corresponding to the exposed part of the second N-type semiconductor layer 2.2. Since the N-type extending part 8.2 is arranged on the surface of the low-doped N-type semiconductor layer 2 near the N-type connecting part 8.1, the resistance value thereof is relatively large; and the N-type extending part 8.2 is arranged on the surface of the high-doped N-type semiconductor layer 2 away from the N-type connecting part 8.1 (i.e. the tail end of the N-type connecting part 8.1), and the resistance value thereof is relatively small; thereby guiding the current on the N surface to be introduced through the N-type electrode and then extended to the tail end of the N-type connecting part 8.1 (i.e. the end near the side wall of the groove 11), and further making the current more uniformly diffused on the N surface.

[0124] Then, the area of the N-type extending part 8.2 arranged on the exposed part of the first N-type semiconductor layer 2.1 is S1, the area of the N-type extending part 8.2 arranged on the exposed part of the second N-type semiconductor layer 2.2 is S2, and S2≥S1. Thus, the current distribution ratio of the head and tail ends of the N-type connecting part 8.1 is effectively adjusted, and the current distribution of the tail end of the N-type connecting part 8.1 (i.e. the end near the side wall of the groove 11) is sufficiently ensured, so that the current is more uniformly diffused on the N surface.

[0125] According to the technical scheme, the preparation method of the LED chip is simple and convenient in process, and is easy to produce.

[0126] Embodiment 3

[0127] The difference between this embodiment and embodiment 2 is only that Figure 5As shown, in this embodiment, the groove has a stepped bottom surface, and the stepped bottom surface exposes the second N-type semiconductor layer at one end close to the side wall of the groove and exposes the first N-type semiconductor layer at the opposite end, so that the N-type extension portion extends in the mesa direction from the periphery of the N-type connection portion in a manner of being laminated on the surface of the second current blocking layer; and at least part of the N-type connection portion is laminated on the exposed part of the first N-type semiconductor layer, and at least part of the N-type extension portion is formed corresponding to the exposed part of the second N-type semiconductor layer; and the N-type connection portion is arranged away from the side wall of the groove.

[0128] As to the preparation method, the preparation method described in Embodiment 2 is correspondingly adjusted, and this embodiment will not be repeated here.

[0129] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between each embodiment can be referred to each other.

[0130] It should also be noted that the relational terms herein such as first and second and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any such actual relationship or order between such entities or actions. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises a list of elements does not include only those elements recited, but also other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus including the recited element.

[0131] The above description of disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized in that, include: Substrate; An epitaxial stack disposed on the surface of the substrate includes at least an N-type semiconductor layer, an active region, and a P-type semiconductor layer stacked sequentially along a first direction, and a local area of ​​the epitaxial stack is etched to a portion of the N-type semiconductor layer to form a groove and a mesa. The first direction is perpendicular to the substrate and extends from the substrate toward the epitaxial stack; A first current blocking layer is stacked on a portion of the surface of the platform; A current spreading layer is stacked on the platform and at least partially covers the first current blocking layer; A P-type electrode includes interconnected P-type connection portions and P-type extension portions; wherein, the P-type connection portions are stacked on the surface of the first current blocking layer and are connected to the P-type semiconductor layer by means of embedding the first current blocking layer through vias; the P-type extension portions extend from the periphery of the P-type connection portions to the edge of the mesa by means of being stacked on the surface of the current extension layer; and the P-type extension portions overlap with the projection of the first current blocking layer on the substrate surface; An N-type electrode is stacked in the groove; A passivation layer that covers the P-type extension and the exposed portion of the epitaxial stack; Wherein, the projected area of ​​the P-type extension on the substrate surface is smaller than the projected area of ​​the first current blocking layer on the substrate surface; A second current blocking layer is provided on the bottom surface of the groove, and the N-type electrode includes interconnected N-type connection portions and N-type extension portions.

2. The LED chip according to claim 1, characterized in that, The N-type connection portion is stacked on the surface of the second current blocking layer and is connected to the N-type semiconductor layer by embedding it into the second current blocking layer through a through-hole; the N-type extension portion extends from the periphery of the N-type connection portion toward the mesa by being stacked on the surface of the second current blocking layer, and the N-type connection portion is disposed away from the sidewall of the groove; Furthermore, the passivation layer also covers the N-type extension.

3. The LED chip according to claim 1, characterized in that, The N-type semiconductor layer includes a first N-type semiconductor layer and a second N-type semiconductor layer stacked sequentially along the surface of the substrate, wherein the N-type doping concentration of the second N-type semiconductor layer is greater than the N-type doping concentration of the first N-type semiconductor layer.

4. The LED chip according to claim 3, characterized in that, The groove has an inclined bottom surface, and one end of the inclined bottom surface near the sidewall of the groove exposes the second N-type semiconductor layer, while the other end of the inclined bottom surface exposes the first N-type semiconductor layer. At least a portion of the N-type extension is formed corresponding to the exposed portion of the second N-type semiconductor layer.

5. The LED chip according to claim 3, characterized in that, The groove has a stepped bottom surface, and the stepped bottom surface exposes the second N-type semiconductor layer at one end near the sidewall of the groove, exposes the first N-type semiconductor layer at the opposite end, and at least a portion of the N-type extension is formed corresponding to the exposed portion of the second N-type semiconductor layer.

6. The LED chip according to claim 4 or 5, characterized in that, At least a portion of the N-type interconnect is stacked on the exposed portion of the first N-type semiconductor layer.

7. The LED chip according to claim 6, characterized in that, If the area of ​​the N-type extension portion disposed on the first N-type semiconductor layer exposed portion is S1, and the area of ​​the N-type extension portion disposed on the second N-type semiconductor layer exposed portion is S2, then S2≥S1.

8. A method for fabricating an LED chip, characterized in that, The preparation method includes the following steps: Step S01: Provide a substrate; Step S02: Stack an epitaxial layer on the surface of the substrate. The epitaxial layer includes an N-type semiconductor layer, an active region, and a second-type semiconductor layer stacked sequentially along a first direction. The first direction is perpendicular to the substrate and extends from the substrate to the epitaxial layer. Step S03: Etch a portion of the epitaxial stack to a portion of the N-type semiconductor layer to form a groove and a mesa; Step S04: Deposit a current blocking layer to form a first current blocking layer on the platform and a second current blocking layer on the groove; Step S05: Fabricate a current spreading layer, which is stacked on the platform and covers the first current blocking layer; Step S06: Etch the current spreading layer and the first current blocking layer to form a via with an exposed P-type semiconductor layer; The second current blocking layer is etched to form a via with an exposed N-type semiconductor layer; Step S07: Evaporation to form P-type and N-type electrodes; The P-type electrode includes interconnected P-type connection portions and P-type extension portions; wherein, the P-type connection portions are stacked on the surface of the first current blocking layer and are connected to the P-type semiconductor layer by means of embedding the first current blocking layer through vias; the P-type extension portions extend from the periphery of the P-type connection portions to the edge of the mesa by means of being stacked on the surface of the current extension layer; and the P-type extension portions overlap with the projection of the first current blocking layer on the substrate surface; The N-type electrode includes interconnected N-type connection portions and N-type extension portions; wherein, the N-type connection portions are stacked on the surface of the second current blocking layer and are connected to the N-type semiconductor layer by means of embedding the second current blocking layer through through holes; the N-type extension portions extend from the periphery of the N-type connection portions toward the mesa by means of being stacked on the surface of the second current blocking layer, and the N-type connection portions are disposed away from the sidewalls of the groove; Step S08: Create a passivation layer that covers the N-type extension, the P-type extension, and the exposed portion of the epitaxial stack.

9. The method for preparing an LED chip according to claim 8, characterized in that, The N-type semiconductor layer includes a first N-type semiconductor layer and a second N-type semiconductor layer stacked sequentially along the surface of the substrate, wherein the N-type doping concentration of the second N-type semiconductor layer is greater than the N-type doping concentration of the first N-type semiconductor layer.

10. The method for preparing an LED chip according to claim 9, characterized in that, The groove has an inclined bottom surface, and one end of the inclined bottom surface near the sidewall of the groove exposes the second N-type semiconductor layer, the other end of the inclined bottom surface exposes the first N-type semiconductor layer, and at least a portion of the N-type extension is formed corresponding to the exposed portion of the second N-type semiconductor layer, and at least a portion of the N-type connection is stacked on the exposed portion of the first N-type semiconductor layer.

11. The method for preparing an LED chip according to claim 9, characterized in that, The groove has a stepped bottom surface, and the stepped bottom surface exposes the second N-type semiconductor layer at one end near the sidewall of the groove, exposes the first N-type semiconductor layer at the opposite end, and at least a portion of the N-type extension is formed corresponding to the exposed portion of the second N-type semiconductor layer.

12. The method for preparing an LED chip according to claim 10 or 11, characterized in that, If the area of ​​the N-type extension portion disposed on the first N-type semiconductor layer exposed portion is S1, and the area of ​​the N-type extension portion disposed on the second N-type semiconductor layer exposed portion is S2, then S2≥S1.

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