An artificial neuron with leak-integrate-fire functionality

Abstract

The application introduces an artificial neuron with a leak-integrate-fire function, which comprises a membrane potential accumulation unit, a leak unit and a pulse generation unit; the membrane potential accumulation unit is connected with the leak unit, and the pulse generation unit is connected with the membrane potential accumulation unit and the leak unit simultaneously; the membrane potential accumulation unit is a transistor; the source end thereof is connected with the input end of the pulse generation unit and the fixed resistor of the leak unit respectively, the gate thereof is connected with the fixed resistor of the leak unit, and the drain end thereof is connected with a constant voltage or a pulse end; the pulse generation unit is a volatile threshold transition memristor; the leak unit is composed of one end of a fixed resistor connected with the gate and the source of the transistor respectively; the artificial neuron designed by the application realizes the generation of analog pulses; realizes the compatibility of electronic components and CMOS process, can work under low power voltage, greatly reduces the preparation cost of the circuit, simplifies the integration difficulty, and reduces the occupied area.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of artificial intelligence design, and particularly relates to an artificial neuron with a leaky-integrate-fire function. BACKGROUND

[0002] As the brain of the biological nervous system, the brain can efficiently and energy-efficiently perform the biological behavior control and thinking function. The brain is composed of hundreds of millions of neuron cells, each of which is composed of a basic unit of multiple synapses and a neuron. When they are integrated into the brain structure composed of interacting neurons, they can solve complex tasks and perform complex behaviors in real time with high precision and at very low power consumption. There are 10 11 billion neurons and 10 15 billion synapses in the human brain, and the energy consumption is extremely low. However, to simulate the state of a large number of neurons and synapses in the brain to process information in parallel, the designed circuit needs to have the performance of ultra-low power consumption and a small occupied area.

[0003] Chinese patent CN207319273U discloses an artificial neuron device and an integrated circuit, wherein an artificial neuron device includes a refractory circuit configured to inhibit signal integration for an inhibition duration after passing an output signal. The refractory circuit includes a first MOS transistor coupled between an input node and a reference node and having a gate connected to an output node through a second MOS transistor having a first electrode coupled to a power node and a gate coupled to the output node. The refractory circuit also includes a resistive-capacitive circuit coupled between the power node, the reference node, and the gate of the second MOS transistor. The inhibition duration depends on a time constant of the resistive-capacitive circuit. However, it uses MOS transistors, which results in a large volume and further causes energy waste.

[0004] Chinese patent CN207302125U discloses an integrated artificial neuron device and an integrated circuit, the integrated artificial neuron device comprising an input signal node, an output signal node and a reference power supply node. An integrator circuit receives an input signal and integrates the input signal to generate an integrated signal; a generator circuit receives the integrated signal and transmits an output signal when the integrated signal exceeds a threshold value. The integrator circuit comprises a main capacitor coupled between the input signal node and the reference power supply node. The integrator circuit comprises a main MOS transistor coupled between the input signal node and the output signal node; the main MOS transistor has a gate coupled to the output signal node and a substrate mutually coupled with the gate. However, the current hardware approach to simulating the operation mode of the human brain by neural networks mainly realizes the neuron function through a complex CMOS-compatible circuit design, which increases the preparation cost and the complexity of integrated design. Another way is to construct an LIF model by connecting a volatile memristor and a capacitor in parallel. This model can realize the basic function of the neuron and the circuit implementation is relatively simple, which can greatly reduce the power consumption of the circuit. However, the capacitor is difficult to be integrated with the traditional CMOS process, and occupies a large area, which brings great challenges to the design and preparation of ultra-compact circuits. SUMMARY

[0005] To solve the above problems, the electronic element is compatible with the CMOS process, and the technical problems of high complexity of the electronic system, large device size, large area occupation and large energy consumption are overcome.

[0006] To achieve the above effects, the application designs an artificial neuron with leakage-integration-emission function.

[0007] An artificial neuron with leakage-integration-emission function comprises a membrane potential accumulation unit, a leakage unit and a pulse generation unit.

[0008] The membrane potential accumulation unit is connected with the leakage unit.

[0009] The pulse generation unit is connected with the membrane potential accumulation unit and the leakage unit at the same time.

[0010] Preferably, the membrane potential accumulation unit is a transistor with double-layer effect and plasticity adjustment.

[0011] The source end of the transistor is connected with the input end of the pulse generation unit as an output end.

[0012] The gate of the transistor is connected with the fixed resistance of the leakage unit.

[0013] The drain end of the transistor is connected with a constant voltage or a constant pulse end VDD.

[0014] Preferably, the pulse generation unit is a volatile threshold transition memristor, and input ends of the volatile threshold transition memristor are connected with source ends of the membrane potential accumulation unit and the discharge unit respectively.

[0015] Preferably, the discharge unit is composed of a constant resistance and a gate and a source of the membrane potential accumulation unit; one end of the constant resistance is connected with the gate and the source of the membrane potential accumulation unit respectively; the other end of the constant resistance is connected with a constant voltage or a constant pulse end V in Preferably, the constant voltage or the constant pulse end V

[0016] Preferably, the transistor has the following characteristics: after a signal is applied to the gate, the equivalent resistance of the channel is reduced, and after the signal is removed from the gate, the equivalent resistance of the channel of the transistor does not immediately rise to the initial value, but slowly rises to the initial value.

[0017] In an embodiment, the membrane potential accumulation unit is a multi-gate transistor with a plurality of side gate electrodes, and the side gate electrodes serve as presynaptic input ends on dendrites of neurons.

[0018] Preferably, the electrode material of the transistor is selected from indium tin oxide, gold, silver, copper, titanium, platinum, aluminum and other metal electrodes or conductive polymers.

[0019] The channel material of the transistor is selected from indium gallium zinc oxide, indium tungsten oxide, graphene, molybdenum disulfide, indium zinc oxide, carbon nanotubes, lithium silicon oxide and other semiconductor oxides or two-dimensional materials; and the gate dielectric material is selected from chitosan, low-temperature silicon oxide, polyvinyl alcohol, polyethylene oxide and niobium pentoxide.

[0020] Preferably, the volatile threshold transition memristor has the following characteristics: after a voltage or a current is applied across the volatile threshold transition memristor, the resistance state of the volatile threshold transition memristor changes, and after the voltage or the current is removed, the resistance of the volatile threshold transition memristor can spontaneously recover.

[0021] Preferably, the resistance value of the constant resistance is limited between the high and low resistance states of the volatile threshold transition memristor.

[0022] Preferably, the volatile threshold transition memristor can also be replaced by a diffusion-type memristor.

[0023] The advantages and effects of the present application are as follows:

[0024] 1. The present application provides an artificial neuron with a leaky-integrate-fire function, and a neuron core circuit adopts a dynamic voltage division circuit of a double-layer transistor and a memristor to simulate accumulation and discharge of a membrane potential of a neuron, and a volatile threshold transition characteristic of the memristor to simulate generation of a pulse, so that the effect of simulating a neuron is realized.

[0025] 2. The double-electric-layer transistor can not only adopt a top gate structure, a bottom gate structure, but also a multi-side gate structure, adopt multiple side gate electrodes of the transistor as multiple presynaptic input ends on neuron dendrites, adjust excitatory postsynaptic current of source-drain electrodes, realize multi-signal input and integration of time and space signals, and finally transmit to a memristor to simulate the neuron dendrite time and space signal processing function; when multiple gate electrodes are input, one of the gate electrodes can be grounded to realize faster discharge of the double-electric-layer capacitor, thereby improving system stability.

[0026] 3. The electronic components required by the design of the application are compatible with the CMOS process, and only one double-electric-layer transistor, one memristor and two fixed-value resistors are required to realize the design, which greatly reduces the preparation cost of the circuit, simplifies the integration difficulty and reduces the occupied area.

[0027] 4. The neuron circuit designed in the application only includes a membrane potential accumulation unit, a discharge unit and a pulse generation unit; the problem of high complexity of the electronic system is overcome, the neuron circuit can work in a low-voltage environment, and power consumption is saved.

[0028] The above description is only a summary of the technical solutions of the application. In order to more clearly understand the technical means of the application, the content of the description can be implemented, and in order to make the above and other purposes, characteristics and advantages of the application more obvious and easy to understand, the following will be described in detail with the preferred embodiments of the application and the accompanying drawings.

[0029] According to the detailed description of the specific embodiments of the application in the following text combined with the drawings, those skilled in the art will more clearly understand the above and other purposes, advantages and characteristics of the application. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual proportion.

[0031] Figure 1 A circuit diagram of an artificial neuron with leakage-integration-emission function provided by the application;

[0032] Figure 2 The LIF model neuron circuit provided by the application is used for inputting a fixed frequency pulse signal, and the membrane voltage V in When the membrane voltage V out and the output current Iout a schematic diagram of the double-electric-layer transistor and the memristor provided by the present application;

[0033] Figure 3 The double-electric-layer transistor and the memristor provided by the present application adopt an integrated preparation design diagram based on a thin film process;

[0034] Figure 4 The double-electric-layer transistor and the memristor provided by the present application adopt an integrated preparation design diagram based on a MOSFET design structure. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. In the following description, specific details such as specific configurations and components are provided only to help a comprehensive understanding of the embodiments of the present application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. In addition, in order to be clear and concise, the description of known functions and structures is omitted in the embodiments.

[0036] It should be understood that the "one embodiment" or "the embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "one embodiment" or "the embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0037] In addition, reference numerals and / or letters can be repeated in different examples in the present application. Such repetition is for the purpose of simplification and clarity, and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0038] The term "and / or" herein is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, B exists alone, and A and B exist simultaneously. The term "and" herein is a description of another association relationship of the associated objects, which means that there can be two relationships, for example, A and B can mean that A exists alone and A and B exist simultaneously. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after it.

[0039] The term "at least one" herein is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, at least one of A and B can mean that A exists alone, A and B exist simultaneously, and B exists alone.

[0040] It is also need to point out that, in this article, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations.

[0041] Embodiment 1

[0042] This embodiment mainly introduces a design of artificial neuron with leaky-integrate-fire function.

[0043] A design of artificial neuron with leaky-integrate-fire function, comprising a membrane potential accumulation unit, a leak unit and a pulse generation unit;

[0044] The membrane potential accumulation unit is connected with the leak unit;

[0045] The pulse generation unit is connected with the membrane potential accumulation unit and the leak unit simultaneously.

[0046] Further, the membrane potential accumulation unit is a transistor with double-layer effect and plasticity adjustment;

[0047] The source end of the transistor is connected with the input end of the pulse generation unit as an output end;

[0048] The gate of the transistor is connected with a fixed resistance of the leak unit;

[0049] The drain end of the transistor is connected with a constant voltage or constant pulse end VDD.

[0050] Further, the pulse generation unit is a volatile threshold transition memristor, and the input end thereof is connected with the source end of the membrane potential accumulation unit and the leak unit respectively.

[0051] Further, the leak unit is composed of a fixed resistance, one end of which is connected with the gate and source of the membrane potential accumulation unit respectively;

[0052] The other end of the fixed resistance is connected with a constant voltage or constant pulse end V in .

[0053] Further, the transistor has the following characteristics: after a signal is applied on the gate, the equivalent resistance of the channel is reduced, and after the signal is removed from the gate, the equivalent resistance of the channel of the transistor does not immediately rise to the initial value, but slowly rises to the initial value.

[0054] In one embodiment, the membrane potential accumulation unit is a multi-gate transistor with multiple side gate electrode structures, the side gate electrodes serving as presynaptic inputs on neuron dendrites.

[0055] Further, the electrode material of the transistor is selected from indium tin oxide, gold, silver, copper, titanium, platinum, aluminum and other metal electrodes or conductive polymers.

[0056] The channel material of the transistor is selected from indium gallium zinc oxide, indium tungsten oxide, graphene, molybdenum disulfide, indium zinc oxide, carbon nanotubes, lithium silicon oxide and other semiconductor oxides or two-dimensional materials; the gate dielectric material is selected from chitosan, low-temperature silicon oxide, polyvinyl alcohol, polyethylene oxide and niobium pentoxide.

[0057] Further, the volatile threshold transition memristor characteristic is that after a voltage or current is applied across the volatile threshold transition memristor, the resistance state of the memristor changes, and after the voltage or current is removed, the resistance of the volatile threshold transition memristor can spontaneously recover.

[0058] Further, the resistance value of the fixed value resistor is limited between the high and low resistance states of the volatile threshold transition memristor. The high resistance state of the memristor: the resistance value of the device before the resistance value jumps to a low resistance value (for the TaOx memristor in this design, the high resistance state is 10 11 -10 9 Ω); the low resistance state of the memristor: the resistance value of the device after the resistance value jumps to a low resistance value (for the TaOx memristor in this design, the low resistance state is 10 7 -10 2 Ω).

[0059] In one embodiment, the volatile threshold transition memristor can be replaced by a diffusion type memristor.

[0060] The double-electric-layer transistor can not only adopt a top gate structure, a bottom gate structure, but also a multi-side gate structure, and the multiple side gate electrodes of the transistor serve as multiple presynaptic inputs on neuron dendrites, adjust the excitatory postsynaptic current of the source and drain electrodes, realize multi-signal input and integration of spatial and temporal signals, and finally deliver the signals to the memristor for simulation of the neuron dendrite spatial and temporal signal processing function; when multiple gate electrodes are input, one of the gate electrodes can be grounded to realize faster discharge of the double-electric-layer capacitor of the transistor, thereby improving system stability.

[0061] As Figure 1 the circuit design, the double-electric-layer transistor source is connected to the volatile memristor, and the gate is short-circuited to the source, thereby constituting an artificial neuron unit with leakage-integration-emission function, and the voltage division of the series resistance end is used as the output unit.

[0062] The electronic element required by the application is compatible with the CMOS process, and can be realized by only one double-layer transistor, one memristor and two constant resistors, so that the preparation cost of the circuit is greatly reduced, the integration difficulty is simplified, and the occupied area is reduced.

[0063] The neuron circuit designed in the application only includes a membrane potential accumulation unit, a discharge unit and a pulse generation unit, and can work in a low voltage environment and save power consumption by overcoming the problem of high complexity of an electronic system.

[0064] Embodiment 2

[0065] Figure 2 The LIF model neuron circuit providing the preferred embodiment of the application is illustrated in the following table, in which V in is the input voltage, V out is the membrane voltage, I out is the output current, and V in is the bias voltage. Figure 2 out Figure 2 out g

[0066] out out out

[0067] Embodiment 3

[0068] Based on the above embodiment 1, this embodiment mainly introduces a first design of an artificial neuron with a leakage-integration-emission function.​​​​​​​​​

[0069] right Figure 1 The core components of the designed circuit, the electric double-layer transistor and the memristor, are integrated and fabricated using a thin-film process. For example... Figure 3 The transistor employs a top-gate design, fabricating source and drain electrodes and an IGZO channel material on a substrate. A low-temperature silicon oxide gate dielectric material is then fabricated on top of the channel material, and the gate electrode is fabricated on the gate dielectric material and connected to the source. From bottom to top, the memristor's upper electrode, active layer, and lower electrode are fabricated on the gate electrode. A voltage divider resistor R1 is fabricated on the gate for connection. Using the voltage divider resistor R1 on the transistor's gate as the input terminal, a constant bias voltage is applied to the drain terminal, and the voltage division at the lower electrode of the memristor becomes the output voltage V. out Meanwhile, the lower electrode of the memristor is connected to the voltage divider resistor R2 to ground. Figure 3 To deposit IGZO channel material on a silicon substrate, metal electrodes are deposited on both sides of the IGZO for the source and drain. The drain is connected to a bias voltage VDD. Low-temperature grown SiO2 is deposited on the IGZO and extends to cover the source and drain electrodes. A metal electrode is deposited on the SiO2 as the gate and extends to the source to ensure its connection to the source. A metal oxide is deposited on one side of the gate as a resistor (R1), and the input signal VIN is connected at R1. On the other side, the memristor upper electrode Ag, active layer TaO, and lower electrode ITO are fabricated sequentially from bottom to top. A resistor (R2) is connected in series to ground. The voltage division between R2 and ITO is the output signal VOUT of the device.

[0070] Example 4

[0071] Based on the above embodiment 1, this embodiment mainly introduces a second design of an artificial neuron with leakage-integration-emission function.

[0072] right Figure 1 The core components of the designed circuit, the double-layer transistor and memristor, are fabricated using an integrated approach based on a MOSFET design structure. For example... Figure 4 Using P-Si as the substrate, Si as the channel layer, and low-temperature silicon oxide as the gate dielectric layer, a gate electrode is fabricated on the gate dielectric material and connected to the source. From bottom to top, a memristor upper electrode, active layer, and lower electrode are fabricated on the gate electrode. A voltage divider resistor R1 is fabricated on the gate for connection. Using the voltage divider resistor R1 on the transistor gate as the input terminal, a constant bias voltage is applied to the drain terminal, and the voltage division at the lower electrode of the memristor becomes the output voltage V. out Meanwhile, the lower electrode of the memristor is connected to the voltage divider resistor R2 to ground. Figure 4For using a piece of P-type silicon semiconductor material as a substrate, two N-type regions are diffused on the surface, then a layer of silicon dioxide (SiO2) insulating layer is covered on the surface, finally two holes are made on the N regions by etching method, and S (source) and D (drain) are formed by metallization method; G (gate) is formed on the insulating layer by metallization method and extends to the source end to ensure that it is connected with the source end; one side of the gate is deposited with metal oxide as resistance (R1), R1 is connected with input signal VIN, and the other side is prepared from bottom to top in turn with memory resistor upper electrode Ag, active layer TaO and lower electrode ITO; and a resistance (R2) is connected in series to ground, and the voltage division of R2 and ITO is the output signal VOUT of the device.

[0073] The preferred embodiments of the present application have been described above with the aid of drawings and are not intended to limit the scope of the application. Various alternatives, modifications and equivalents can be used. It should be understood by those skilled in the art that the present application can be varied in a variety of ways. Any modification and change within the spirit and principle of the present application will be included in the scope of the present application.

Claims

1. An artificial neuron having a leak-integrate-fire function, characterized by, It includes a membrane potential accumulation unit, a discharge unit, and a pulse generation unit; The membrane potential accumulation unit is connected to the discharge unit; The pulse generation unit is simultaneously connected to the membrane potential accumulation unit and the discharge unit; The membrane potential accumulation unit is a transistor, which is a transistor with double-layer effect and plastic regulation capability or a multi-gate transistor with multiple side gate electrode structures. The source terminal of the transistor is connected to the input terminal of the pulse generation unit as the output terminal; The gate of the transistor is connected to a fixed resistor in the bleeder unit; The drain of the transistor is connected to a constant voltage or a constant pulse terminal VDD. The discharge unit consists of a fixed resistor and the gate and source of a film potential accumulation unit; One end of the fixed resistor is connected to the gate and source of the membrane potential accumulation unit, respectively. The constant value resistor is connected to a constant voltage or constant pulse end V in Connected; The side gate electrode serves as the presynaptic input terminal on the neuronal dendrite.

2. The artificial neuron with leaky-integrate-fire functionality according to claim 1, wherein The pulse generation unit is a volatile threshold switching memristor, and its input terminal is connected to the source terminal of the membrane potential accumulation unit and the discharge unit, respectively. The integrated fabrication method of the membrane potential accumulation unit and the pulse generation unit is as follows: a gate electrode is fabricated on the gate dielectric material and connected to the source terminal; the memristor upper electrode, active layer and lower electrode are fabricated sequentially from bottom to top on the gate electrode; A voltage divider resistor R1 is prepared on the gate for connection; the voltage divider resistor R1 on the gate of the transistor is used as the input terminal, a constant bias voltage is applied to the drain terminal, the voltage divider at the lower electrode of the memristor is the output terminal Vout, and the lower electrode of the memristor is connected to the voltage divider resistor R2 to ground.

3. An artificial neuron with leakage-integration-emission function according to claim 1, characterized in that, The transistor has the following characteristics: after a signal is applied to the gate, the channel equivalent resistance decreases, and after the signal is removed from the gate, the equivalent resistance of the transistor channel does not immediately rise to the initial value, but slowly rises to the initial value.

4. An artificial neuron with leakage-integration-emission function according to claim 2, characterized in that, The electrode material of the transistor is selected from indium tin oxide, gold, silver, copper, titanium, platinum, aluminum, or conductive polymer; The channel material of the transistor is selected from indium gallium zinc oxide, indium tungsten oxide, graphene, molybdenum disulfide, indium zinc oxide, carbon nanotubes, lithium silicon oxide, or two-dimensional materials; the gate dielectric material is selected from chitosan, low-temperature silicon oxide, polyvinyl alcohol, polyethylene oxide, and niobium pentoxide.

5. An artificial neuron with leakage-integration-emission function according to claim 2, characterized in that, The volatile threshold switching memristor is characterized in that when a voltage or current is applied across its terminals, its resistance changes, and when the voltage or current is removed, the resistance of the volatile threshold switching memristor can spontaneously recover.

6. An artificial neuron with leakage-integration-emission function according to claim 1, characterized in that, The value of the fixed resistor is limited to the high and low resistance states of the volatile threshold switching memristor.

7. An artificial neuron with leakage-integration-emission function according to claim 2, characterized in that, The volatile threshold switching memristor is replaced with a diffused memristor.

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