Extracting resistor-capacitor time constants of electronic circuits

Abstract

A resistor-capacitor (RC) sensor circuit of an electronic device drives a representative copy of a current driving an electronic circuit line of the electronic device to a drive voltage. The RC sensor circuit is to sample a voltage indicative of an RC time constant of the electronic circuit line. A first sample voltage is determined by sampling a first representative voltage generated at the RC sensor circuit by driving the RC sensor circuit with the representative copy of the current for a first period of time. A second sample voltage is determined by sampling a second representative voltage generated at the RC sensor circuit by driving the RC sensor circuit with the representative copy of the current for a second period of time. A ratio of the first sample voltage to the second sample voltage is indicative of the RC time constant of the electronic circuit line.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to electronic circuit lines, and more specifically, to extracting resistor-capacitor time constants of electronic circuit lines. BACKGROUND

[0002] The propagation of signals across electrical lines or other circuitry can be dominated by resistor-capacitor effects. Resistor-capacitor delay, or RC delay, can impede the speed of electronic devices, such as microelectronic integrated circuits. RC delay can become a significant obstacle to performance improvement, especially considering the continued feature example scaling and feature density of electronic devices. BRIEF DESCRIPTION OF DRAWINGS

[0003] The present disclosure will become more fully understood from the detailed description given herein and from the accompanying drawings, wherein: FIG. 1 is a block diagram illustrating an example computing environment including a memory sub-system in accordance with some embodiments of the present disclosure.

[0004] Figure 1 FIG. 1 is a block diagram illustrating an example computing environment including a memory sub-system in accordance with some embodiments of the present disclosure.

[0005] Figure 2 FIG. 1 is a block diagram illustrating an example computing environment including a memory sub-system in accordance with some embodiments of the present disclosure.

[0006] Figure 3 FIG. 1 is a block diagram illustrating an example computing environment including a memory sub-system in accordance with some embodiments of the present disclosure.

[0007] Figure 4 FIG. 1 is a block diagram illustrating an example computing environment including a memory sub-system in accordance with some embodiments of the present disclosure.

[0008] Figure 5 FIG. 1 is a block diagram illustrating an example computing environment including a memory sub-system in accordance with some embodiments of the present disclosure.

[0009] Figure 6 FIG. 1 is a block diagram illustrating an example computing environment including a memory sub-system in accordance with some embodiments of the present disclosure.

[0010] Figure 7 FIG. 1 is a block diagram illustrating an example computing environment including a memory sub-system in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] An electronic circuit line can refer to a physical line or wire of some length, through which a signal, such as a voltage signal or a current signal, can be conducted. Examples of electronic circuit lines can include, but are not limited to, a word line of a memory device, a transmission line, a circuit interconnect, or any signal line of an electronic device. A circuit line can be associated with some amount of resistance and capacitance, such as parasitic resistance and parasitic capacitance, which can contribute to a resistance-capacitance (RC) delay of a signal transmitted or propagated across the electronic circuit line. The RC delay can be characterized by an RC time constant, in units of seconds. The RC time constant is equal to the product of the resistance and the capacitance. For example, an electronic circuit line can include at least two terminals: a near terminal and a far terminal opposite the near terminal. When a voltage signal is driven at the near terminal of the electronic circuit line, the propagation of the signal to the far terminal of the electronic circuit line can be delayed in proportion to the RC time constant of the electronic circuit line.

[0012] The RC delay of an electronic circuit line can inhibit the performance of many electronic devices. For example, in a memory device, a voltage signal can be applied to a word line to perform a memory operation, such as a read operation or a program operation. If the RC delay is large and the magnitude or duration of the voltage signal is insufficient to account for the RC delay, a significant latency can be introduced when performing the memory operation.

[0013] In some systems, the RC time constant and the RC delay of an electronic circuit line can be obtained by making direct measurements at the near and far terminals of the electronic circuit line. Using the known RC time constant, the driving voltage of the electronic circuit line can be adjusted to account for the problem of the associated RC delay.

[0014] As feature sizes continue to shrink and feature densities increase for electronic devices, making direct measurements at an electronic circuit line to obtain the RC time constant and the RC delay of the electronic circuit line is not feasible. Furthermore, the distribution of the RC time constant across electronic circuit lines of the same electronic device and across electronic circuit lines of different electronic devices of the same device type can be random, which makes compensating for the RC delay of an electronic circuit line particularly challenging.

[0015] Aspects of the present disclosure address the above-referenced and other shortcomings by implementing an RC sensor circuit that can extract or extrapolate RC time constant information of an electronic circuit line using a representative copy of a current driving the electronic circuit line.

[0016] In some embodiments, an RC sensor circuit can be driven to a particular voltage using a representative copy of the current driving the electronic circuit line. The representative copy of the current can be integrated at an integration capacitor of the RC sensor circuit. At various times, the voltage at the integration capacitor can be sampled to obtain at least two sample voltages. For example, the integration capacitor can be sampled at a first time (ti) before the voltage at the integration capacitor reaches a steady state voltage and at a second time (t2) when the voltage at the integration capacitor is at or near the steady state voltage. The sampled voltages obtained at the RC sensor circuit can be indicative of the voltages that would have been generated at the far end of the electronic circuit line at respective times ti and t2 if the electronic circuit line was driven to the drive voltage using a similar current. A ratio of the first sampled voltage to the second sampled voltage obtained at the RC sensor circuit can have a one-to-one mapping with the RC time constant of the electronic circuit line. In some embodiments, the ratio can be used to select or adjust an operating voltage that can be used to drive the electronic circuit line and compensate for the extracted RC delay of the electronic circuit line.

[0017] Advantages of the present disclosure include, but are not limited to, determining RC information, such as an RC time constant or an RC delay, of an electronic circuit line where direct measurement of the RC time constant or the RC delay at the electronic circuit line is not feasible. In addition, the RC information can be used to improve performance of electronic devices, such as memory devices, etc. For example, an RC information drive signal of the electronic circuit line can be adjusted to compensate for the RC delay, which improves latency and performance in many electronic devices.

[0018] Figure 1 An example computing environment 100 including a memory sub-system 110 is described in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such devices.

[0019] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include a solid state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and a non-volatile dual in-line memory module (NVDIMM).

[0020] The computing environment 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1An example of a host system 120 coupled to a memory sub-system 110 is described. The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., no intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0021] The host system 120 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing device including memory and a processing device. The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further access a memory component (e.g., the memory device 130) utilizing an NVM Express (NVMe) interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120.

[0022] The memory devices can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory device 140) can be, but are not limited to, random access memories (RAMs) such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0023] Examples of non-volatile memory devices (e.g., the memory device 130) include “not- and” (NAND) type flash memories. Each of the memory devices 130 can include one or more arrays of memory cells, such as single-level cells (SLCs) or multi-level cells (MLCs) (e.g., triple-level cells (TLCs) or quad-level cells (QLCs)). In some embodiments, a particular memory component can include SLC portions and MLC portions, TLC portions, or QLC portions of memory cells. Each of the memory cells can store one or more bits of data used by the host system 120. Furthermore, the memory cells of the memory device 130 can be grouped into memory pages or memory blocks, which can refer to units of memory components used to store data.

[0024] Although a non-volatile memory component (e.g., NAND-type flash memory) is described, the memory device 130 can be based on any other type of non-volatile memory, such as read only memory (ROM), phase change memory (PCM), magnetic random access memory (MRAM), “not -or” (NOR) flash memory, electrically erasable programmable read only memory (EEPROM), and cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on bulk resistance changes along with a stacked cross-grid data access array. Additionally, in contrast to many flash-based memories, a cross-point non-volatile memory can perform in-situ write operations, where a non-volatile memory cell can be programmed without requiring a prior erasure of the non-volatile memory cell.

[0025] The memory sub-system controller 115 can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0026] The memory sub-system controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0027] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although the example memory sub-system 110 in Figure 1 In another embodiment of the disclosure, the memory sub-system 110 can not include the memory sub-system controller 115, and can instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

[0028] In general, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130. Memory sub-system controller 115 can be responsible for other operations associated with memory devices 130, such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translation between a logical block address and a physical block address. Memory sub-system controller 115 can further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from a host system into command instructions to access memory devices 130, and also convert responses associated with memory devices 130 into information for host system 120.

[0029] Memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130.

[0030] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130.

[0031] In some embodiments, memory operations can include, but are not limited to, program operations (e.g., write operations), read operations, or erase operations. In some embodiments, program operations can include multiple sub-operations, such as program sub-operations, read sub-operations, and verify sub-operations. Program sub-operations program data to memory cells. The data to be programmed can also be stored in one or more registers of memory devices 130. Read operations read data programmed at memory cells. Verify operations confirm that the input data is correctly programmed (e.g., written) at memory cells. For example, to perform a verify operation, read data from a read operation is compared to original data stored in a register.

[0032] In some embodiments, memory sub-system 110 includes an RC time constant manager 113. In some embodiments, RC time constant manager 113 of memory sub-system controller 115 performs the operations described herein. In some embodiments, RC time constant manager 113 of local media controller 135 performs the operations described herein. In some embodiments, RC time constant managers 113 of memory sub-system controller 115 and local media controller 135 work together to perform the operations described herein. In some embodiments, any component of a computer environment can include RC time constant manager 113. For example, RC time constant manager 113 can be part of host system 120, memory device 140, memory device 130, or an operating system (OS), such as an OS of host system 120. In another example, memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 to perform the operations described herein.

[0033] In some embodiments, memory device 130 can include one or more of driver circuitry 118 (also referred to herein as “drivers”), decoder circuitry 124 (also referred to herein as “decoders”), and RC sensor circuitry 122. In some embodiments, RC sensor circuitry 122 can be part of driver circuitry 118. In some embodiments, memory device 130 can include one or more electronic circuit lines 137, such as word lines. A word line can refer to one or more rows of memory cells of a memory device, which, along with one or more bit lines, are used to generate an address for each of the memory cells. Driver circuitry 118, decoder circuitry 124, RC sensor circuitry 122, electronic circuit lines 137, and RC time constant manager 113 are further described with respect to the following figures. Figure 1 The components of FIG. 1 are used to help describe the following figures.

[0034] It should be noted that aspects of the present disclosure are described with respect to memory sub-system 110 and memory device 130 for illustrative and not limiting purposes. It should be noted that aspects of the present disclosure can be applied to any electronic circuit line, including electronic circuit lines included in or coupled to any type of electronic device, such as, but not limited to, memory device 130, memory device 140, and processing devices. Additionally, for illustrative and not limiting purposes, RC time constant manager 113 is illustrated as part of memory sub-system controller 115 and memory device 130, and it can be part of another component or a separate module executed at, for example, a processing device. Additional details regarding RC time constant manager 113 are described below.

[0035] Figure 2is a diagram illustrating an RC sensor circuit and an example electronic circuit line in accordance with some embodiments of the present disclosure. Diagram 200 illustrates an RC sensor circuit 222 (also referred to herein as an “RC sensor”) and an electronic circuit line 237.

[0036] Electronic circuit line 237 is represented by a resistor and capacitor network. The resistors and capacitors illustrated in the RC network can include one or more of a parasitic resistance of electronic circuit line 237, a parasitic capacitance of electronic circuit line 237, a resistance of an electronic component of electronic circuit line 237, or a capacitance of an electronic component of electronic circuit line 237.

[0037] In some embodiments, electronic circuit line 237 has a physical layout that includes two ends: a near end (e.g., a source end) and a far end (e.g., a load end) opposite the near end. The far end can be some point at electronic circuit line 237 that is any distance or length away from the near end. For example, electronic circuit line 237 can be a word line of memory device 130. The word line can include a first end (e.g., a near end) coupled to driver circuit 218. The first end can be associated with an initial memory cell of the word line of memory device 130. A second end (e.g., a far end) can be a portion of the word line that is the farthest distance (or length) away from the first end. The second end can be associated with a last memory cell of the word line of memory device 130.

[0038] In some embodiments, the near end is driven by a signal such as a drive voltage or current 240. For example, an input voltage (e.g., Vin) can be supplied to an input of driver circuit 218, and an output of driver circuit 218 drives electronic circuit line 237 to some drive voltage based on the input voltage. Current 240 represents the current that drives electronic circuit line 237 to the drive voltage. In this example, driver circuit 218 drives electronic circuit line 237 to a voltage equal to the input voltage.

[0039] Due to the resistance and capacitance of electronic circuit line 237, a signal at the far end of electronic circuit line 237 is delayed (e.g., an RC delay). For example, a voltage at the near end of electronic circuit line 237 (e.g., Vnear) can be driven to the drive voltage almost instantaneously, but a voltage at the far end of electronic circuit line 237 (e.g., Vfar) is driven to the drive voltage more slowly due to the RC delay. The delay of a signal between an input at one end (e.g., the near end) and an output at the other end (e.g., the far end) can be referred to as an RC delay. As noted above, an RC delay can be characterized by an RC time constant (in seconds). The RC time constant is equal to the product of the circuit resistance and the circuit capacitance, and indicates the time it takes for a capacitor to charge from an initial voltage of zero volts to approximately 63.2% of the voltage value of an applied direct current (DC) voltage through a resistor.

[0040] In some embodiments, the far end of the electronic circuit line 237 cannot be measured. For example, the far end of the word line can not have a conductive pad accessible by a probe or have an electrical coupling to an electronic circuit that can measure the voltage (Vfar) at the far end of the word line.

[0041] In some embodiments, the RC sensor circuit 222 can be used to extract the RC time constant of the electronic circuit line 237 and estimate the RC delay of the electronic circuit line 237. In some embodiments, a representative copy of the current 240 (hereinafter referred to as the representative copy of current 242) driven at the electronic circuit line 237 is driven at the RC sensor circuit 222. The representative copy of current 242 can approximate (or substantially resemble) the current 240 driven at the electronic circuit line 237 at any given time. The accuracy of the representative copy of current 242 in approximating the current 240 can be based on design considerations. For example, the accuracy of the representative copy of current 242 is roughly linearly proportional to the estimated RC. If the allowable error in the estimated RC time constant is 10%, then the accuracy of the representative copy of current 242 can be equal to or greater than 90%. In some embodiments, the driver circuit 218 can drive both the electronic circuit line 237 and the RC sensor circuit 222. For example, the driver circuit 218 can supply the current 240 at the electronic circuit line 237 and the representative copy of current 242 at the RC sensor circuit 222. In some embodiments, the driver circuit 218 can include a current mirror circuit. The current mirror circuit can supply the current 240 to the electronic circuit line 237 and mirror the current 240 by providing the representative copy of current 242 to the RC sensor circuit 222. As illustrated, two p-channel metal-oxide-semiconductor (PMOS) transistors each represent half of the current mirror circuit. The gates of the PMOS transistors are coupled and the two PMOS transistors are turned on in response to the application of an input voltage (Vin). In some embodiments, various techniques can be implemented to reduce current mismatch of the current mirror. For example, the transistors can be long channel devices or matched (e.g., layout matched) to reduce current mismatch.

[0042] It should be noted that the driver circuit 218 is provided for illustrative and not limiting purposes. In other embodiments, different circuit types can be implemented to provide the current 240 and the representative copy of current 242. In yet further embodiments, separate driver circuits can drive the electronic circuit line 237 and the sensor circuit 222 with the current 240 and the representative copy of current 242, respectively.

[0043] In some embodiments, the RC sensor circuit 222 can include an integration capacitor 244. In some embodiments, a representative copy 242 of the current can be integrated at the integration capacitor 244. The integration capacitor 244 can have two terminals. One terminal is coupled to the output of the driver circuit 218. The other terminal can be coupled to a ground potential, such as a device ground or a ground ground.

[0044] In some embodiments, the RC sensor circuit 222 can include an amplifier 246. In some embodiments, the amplifier 246 can include a unity gain amplifier. In other embodiments, the amplifier 246 can include an amplifier that amplifies a received signal by any factor. In some embodiments, the amplifier 246 includes an input and an output. The input of the amplifier 246 can be coupled to the integration capacitor 244 and the output of the driver circuit 218. The output of the amplifier 246 can be coupled to a sampling capacitor 250 via a switch 248. In some embodiments, the amplifier 246 can isolate the signal at the input side of the amplifier 246 from the signal at the output side of the amplifier 246. In some embodiments, the amplifier 246 amplifies the voltage (e.g., Vx) stored at the integration capacitor 244 to generate a corresponding voltage at the output of the amplifier 246.

[0045] In some embodiments, the RC sensor circuit 222 includes a sampling circuit to sample the signal (e.g., voltage (Vx)) stored at the integration capacitor 244. The sampling circuit can sample the signal at different times such that the signal generated at the integration capacitor 244 over different time periods can be sampled at different times. In some embodiments, the sampling circuit includes the switch 248 and the sampling capacitor 250. The switch 248 can be a voltage controlled switch that opens (e.g., illustrated) and closes in response to an applied voltage. In some embodiments, the switch 248 can include a complementary metal-oxide-semiconductor (CMOS) switch or other type of switch. The switch 248 can include at least two terminals. One terminal can be coupled to the output of the amplifier 246. The other terminal can be coupled to a terminal of the sampling capacitor 250. In some embodiments, the sampling capacitor 250 can include two terminals. One terminal can be coupled to the terminal of the switch 248 and an analog-to-digital converter (ADC) 252. The other terminal can be coupled to a ground potential.

[0046] In some embodiments, switch 248 can be controlled such that the amplified signal from the output of amplifier 246 can be stored at sample capacitor 250. For example, during a first time period (e.g., 0 to 2 microseconds (μβ)), a voltage can be charged at integration capacitor 244 in response to representative copy of current 242. For instance, the voltage (Vx) generated at integration capacitor 244 during the first time period can be a voltage that is prior to the steady state voltage being generated at integration capacitor 244 (e.g., a transient). In some embodiments, to sample the voltage (Vx) stored at integration capacitor 244, switch 248 can be closed and cause amplifier 246 to charge sample capacitor 250 to a voltage (e.g., Vsmpl) that represents the voltage (e.g., Vx) stored at integration capacitor 244 at a particular time. Switch 248 can be opened when the desired voltage (e.g., Vsmpl) is stored at sample capacitor 250. In some embodiments, the above operation can be repeated to sample another voltage. For example, during a second time period (e.g., 0 to 20 μβ), a new higher voltage can be charged at integration capacitor 244 in response to representative copy of current 242. For instance, the voltage (Vx) generated at integration capacitor 244 during the second time period can reach the steady state voltage. Switch 248 can be closed and amplifier 246 charges sample capacitor 250 to a new voltage that represents the voltage (Vx) generated at integration capacitor 244 during the second time period. It should be noted that the first time period and the second time period can overlap.

[0047] In some embodiments, RC sensor circuit 222 can include ADC 252. ADC 252 can include an input and an output. The input can be coupled to sample capacitor 250 and the output can be coupled to look-up table (LUT) 256. ADC 252 can convert an analog signal to a digital code. In some embodiments, the sampled voltage at sample capacitor 250 can be converted to a digital code by ADC 252. For example, a first sampled voltage representing the voltage (e.g., Vx) generated at integration capacitor 244 during the first time period can be converted to a first digital code by ADC 252. A second sampled voltage representing the voltage generated at integration capacitor 244 during the second time period can be converted to a second digital code by ADC 252.

[0048] In some embodiments, the ratio of the two sampled voltages (e.g., Vsmpl) indicates the RC time constant of electronic circuit line 237. In some embodiments, the ratio can be the ratio 254 of the respective digital codes. Equation 1 illustrates the ratio relationship to the RC time constant. "r" represents the ratio, "V x (t)" represents the voltage at integration capacitor 244 at a particular time, "ti" and "t2" represent two different times or time periods, and RC represents a lumped estimate of the RC time constant of electronic circuit line 237.

[0049]

[0050] In some embodiments, the ratio 254 can be used as an input to a lookup table (LUT) 256. The LUT 256 can map the ratio 254 to an operating voltage 258 for driving the electronic circuit line 237 in view of the extracted RC time constant of the electronic circuit line 237. For example, different ratios can be mapped to different RC time constants or RC delays of the electronic circuit line 237 via testing or simulation. Using the estimated RC time constant, the ratio can be further mapped to an operating voltage that can sufficiently drive the electronic circuit line 237 to a particular voltage in a desired amount of time. The LUT 256 can store information that maps a determined ratio to a corresponding operating voltage. The operating voltage can be a voltage for driving the electronic circuit line 237 to perform a particular operation.

[0051] In some embodiments, the operating voltage can represent an overdrive voltage for driving the electronic circuit line 237. In some embodiments, the operating voltage can be associated with one or more of a voltage trim or a program time. The voltage trim can refer to a digital code that can identify a voltage level at which the electronic circuit line 237 is to be driven. In some embodiments, the program time can indicate a length of time in which the electronic circuit line 237 is to be driven at the voltage level identified by the voltage trim. For example, the voltage trim can identify an operating voltage of 5V and a program time of 10us. The electronic circuit line 237 can be driven at 5V for 10us (after which the voltage can be reduced to the original operating voltage, e.g., 2.5V).

[0052] In an illustrative example, the electronic circuit line 237 is a word line of the memory device 130. The RC of the word line can be estimated using the operations described above. The ratio of the sampled voltage can be used as an input to the LUT 256. The output of the LUT 256 can provide a trim voltage and a program time for performing a memory operation, such as a program operation or a read operation, at the word line of the memory device 130. The operations can be repeated for one or more word lines of the memory device 130.

[0053] In some embodiments, the electronic circuit line 237 and one or more components of the RC sensor circuit 222 can be part of an electronic device. In other embodiments, the electronic circuit line 237 and one or more components of the RC sensor circuit 222 can be part of a different electronic device. In some embodiments, one or more components of the RC sensor circuit 222 can be part of a different electronic device or the same electronic device. In an illustrative example, the electronic circuit line 237, the driver circuit 218, the integration capacitor 244, the amplifier 246, the switch 248, and the sampling capacitor 250 can be on an electronic circuit, and the ADC 252 and the LUT 256 can be part of one or more different electronic circuits.

[0054] Figure 3 A voltage waveform graph illustrating example waveforms at an electronic circuit line and an RC sensor circuit is described in accordance with some embodiments of the disclosure. Figure 2 The components of FIG. 400 are used to help illustrate Figure 3 .

[0055] Waveform graph 300 shows waveforms for Vnear 305, Vfar 310, Vx 315, and Vsmpl 320. The voltages mentioned earlier correspond to the voltages and nodes shown in Figure 2 Vnear 305 of electronic circuit line 237 reaches a steady state voltage quickly, and Vfar 310 of electronic circuit line 237 reaches a steady state voltage with a delay due to the RC delay of electronic circuit line 237. As illustrated, the voltage waveform of Vx 315 at the integrating capacitor 244 of RC sensor circuit 222 is similar to the voltage waveform of Vfar 310, and mimics the RC delay of electronic circuit line 237. Vsmpl 320 shows two samples of Vx 315 at two different times, e.g., ti and t2.

[0056] Figure 4 is a block diagram illustrating circuitry for implementing an RC sensor circuit at multiple electronic circuit lines in accordance with some embodiments of the disclosure. FIG. 400 includes an electronic circuit that includes a driver circuit 418, a decoder 424, and multiple electronic circuit lines 437A-437N (also collectively referred to as “electronic circuit lines 437”). In some embodiments, driver circuit 418 can include RC sensor circuit 422. In other embodiments, RC sensor circuit 422 can be separate from driver circuit 418. In the current example, driver circuit 418, decoder 424, and electronic circuit lines 237 are part of an electronic device 430. In other embodiments, one or more of driver circuit 218, decoder 424, or electronic circuit lines 237 can be part of one or more different electronic devices. For example, electronic circuit lines 237 can be included in a discrete semiconductor package, and driver circuit 218 and decoder 424 can be included in one or more different discrete semiconductor packages.

[0057] In some embodiments, the RC time constant of different electronic circuit lines 437 can be extracted (e.g., estimated) by implementing the decoder 424. For example, the decoder 424 can operate to select a first electronic circuit line, such as electronic circuit line 437A. Operations to determine a ratio indicative of the RC time constant of the electronic circuit line 437A can be performed as described herein. An appropriate operating voltage can be selected based on the ratio, and operations performed on the electronic device 430 at the electronic circuit line 437A can be performed using the selected operating voltage. The decoder 424 can select a second electronic circuit line, such as electronic circuit line 437B (not shown). Operations to determine a ratio indicative of the RC time constant of the electronic circuit line 437B can be performed. An appropriate operating voltage can be selected based on the new ratio, and operations performed on the electronic device 430 at the electronic circuit line 437B can be performed using the selected operating voltage.

[0058] In other embodiments, one or more of the multiple RC sensor circuits or multiple decoders can be implemented to perform RC time constant extraction of electronic circuit lines in parallel.

[0059] Figure 5 is a diagram illustrating an RC sensor circuit and an example electronic circuit line in accordance with some embodiments of the present disclosure. FIG. 500 illustrates an RC sensor circuit 522 and an electronic circuit line 537. Some components of the RC sensor circuit 522 are similar to those of the RC sensor circuit 222 of FIG. 2, and will not be described again with respect to FIG. 2 for purposes of clarity. Figure 2 Figure 5 Some components of the electronic circuit line 537 are similar to those of the electronic circuit line 237 of FIG. 2, and will not be described again with respect to FIG. 2 for purposes of clarity. Figure 2 Figure 5 Some components of the electronic circuit line 537 are similar to those of the electronic circuit line 237 of FIG. 2, and will not be described again with respect to FIG. 2 for purposes of clarity.

[0060] The RC sensor circuit 522 includes a sampling circuit that includes a plurality of sampling capacitors 550A-N, a plurality of switches 548A-N before the sampling capacitors 550A-N, and a plurality of switches 560A-N after the sampling capacitors 550A-N. Each row of the sampling circuit (e.g., switches 548A, sampling capacitors 550, and switches 560A) can sample a voltage (e.g., Vx) at the integration capacitor (Cx) at different times. In some embodiments, the sampling times can be relatively close such that the voltage (e.g., Vx) at the integration capacitor can be sampled multiple times before the voltage (e.g., Vx) reaches a steady state voltage. A plurality of sampled voltages can be stored at respective sampling capacitors 550A-N. Thus, the stored voltages can be sent to the ADC in a serial fashion by operating the switches 560A-N. In some embodiments, at least one of the sampled voltages can be a voltage (Vx) at or near a steady state voltage (e.g., t is large).

[0061] ​​In some embodiments, a plurality of sample voltages can be used to generate a plurality of ratios. For example, a ratio between each of the sampled voltages and a last sampled voltage (e.g., a sampled voltage at or near a steady state voltage) can be generated. The ratios can be used as points in a fitted curve. One or more best fit curve techniques, such as best least squares curve fitting, can be used. The RC time constant can be extrapolated from the fitted curve.

[0062] Figure 6 is a flowchart of an example method of extracting an RC time constant of an electronic circuit line according to embodiments of the present disclosure. The method 600 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by the RC time constant manager 113 of Figure 1 is a flowchart of an example method of extracting an RC time constant of an electronic circuit line according to embodiments of the present disclosure. The method 600 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by the RC time constant manager 113 of

[0063] At operation 605, the processing device drives a resistor-capacitor (RC) sensor of the electronic device to a drive voltage using a representative copy of the current. The current can drive an electronic circuit line of the electronic device. The RC sensor circuit can sample a voltage indicative of an RC time constant of the electronic circuit line.

[0064] In some embodiments, the electronic circuit line includes a first end and a second end opposite the first end. A driver circuit is coupled to the first end to drive the second end to the drive voltage using the current. The second end is inaccessible for measurement of the drive voltage.

[0065] At operation 610, the processing logic drives an electronic circuit line of the electronic device to a drive voltage using the current. In some embodiments, the processing logic drives the electronic circuit line concurrently with driving the RC sensor circuit. In other embodiments, the processing logic does not drive the electronic circuit line and the RC sensor circuit concurrently. In yet other embodiments, the processing logic does not drive the electronic circuit line.

[0066] At operation 615, the processing logic integrates the representative copy of the current at an integrating capacitor of the RC sensor circuit for a first time period to generate a first representative voltage.

[0067] At operation 620, processing logic determines a first sample voltage by sampling a first representative voltage generated at the RC sensor circuit. Sampling the first representative voltage can be performed at least in part by driving the RC sensor circuit with the representative copy of current for a first time period. The representative voltage can represent a voltage generated at a distal end of the electronic circuit line.

[0068] At operation 625, processing logic integrates the representative copy of current at an integration capacitor of the RC sensor circuit for a second time period to generate a second representative voltage. In some embodiments, the second time period overlaps the first time period.

[0069] In some embodiments, to determine the first sample voltage by sampling the first representative voltage generated at the RC sensor circuit, processing logic can amplify the first representative voltage at the integration capacitor to generate the first sample voltage at a sampling capacitor of the RC sensor circuit.

[0070] In some embodiments, to determine the second sample voltage by sampling the second representative voltage generated at the RC sensor circuit, processing logic can amplify the second representative voltage at the integration capacitor to generate the second sample voltage at the sampling capacitor of the RC sensor circuit.

[0071] At operation 630, processing logic determines a second sample voltage by sampling a second representative voltage generated at the RC sensor circuit. Sampling the second representative voltage can be performed at least in part by driving the RC sensor circuit with the representative copy of current for a second time period. A ratio of the first sample voltage to the second sample voltage indicates an RC time constant of the electronic circuit line.

[0072] In some embodiments, the first sample voltage is converted into a first digital code representing the first sample voltage. The second sample voltage is converted into a second digital code representing the second sample voltage. The ratio of the first sample voltage to the second sample voltage is determined using the first digital code and the second digital code.

[0073] In some embodiments, the ratio is mapped to a trim voltage (e.g., an operating voltage) selected to drive the electronic circuit line in view of the RC time constant of the electronic circuit line. In some embodiments, the electronic circuit line includes a word line of a memory device. The trim voltage is selected to drive the word line when performing a memory operation.

[0074] At operation 635, processing logic performs an operation at an electronic circuit line of an electronic device using an operating voltage selected from a plurality of operating voltages. The operating voltage can be selected based on the ratio indicating the RC time constant of the electronic circuit line.

[0075] Figure 7An example machine of the computer system 700 is illustrated and described in FIG. 1. The machine includes instructions for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 700 can correspond to a host system (e.g., host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to RC time constant manager 113 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment. Figure 1 Figure 1 Figure 1 The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform the methodologies discussed herein.

[0076] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform the methodologies discussed herein.

[0077] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 718, which communicate with each other via a bus 730.

[0078] ​​Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations thereof. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0079] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which one or more sets of instructions 726 or software embodying any one or more methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially in main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage media. The machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0080] In one embodiment, instruction 726 includes instructions for implementing the corresponding Figure 1 The RC time constant manager 113 provides functional instructions. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methodologies of this disclosure. The term "machine-readable storage medium" should be understood accordingly to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0081] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0082] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0083] The disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0084] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as follows from the description of the detailed description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure described herein.

[0085] The disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0086] The word "example" or "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words "example" or "exemplary" is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing instances. Also, as used in this application, the articles "a," "an," and "the" can connote the meaning of "one or more" unless otherwise specified or clear from the context to be directed to a singular form. Additionally, the use of terms "implementation" or "one implementation" or "an implementation" or "one embodiment" or similar throughout is not intended to mean the same implementation or embodiment, unless otherwise specifically so stated. One or more implementations or embodiments described herein can be combined in a particular implementation or embodiment. As used herein, the terms "first," "second," "third," "fourth," etc. are used as labels for different elements, and are not intended to mean a sequential or chronological order, unless so specified.

[0087] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples thereof. It is evident, however, that various modifications can be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method of extracting a resistor-capacitor time constant of an electronic circuit line, comprising: driving a resistor-capacitor (RC) sensor circuit of an electronic device to a drive voltage using a mirror current of an electronic circuit line of the electronic device, wherein the RC sensor circuit is configured to sample a voltage indicative of an RC time constant of the electronic circuit line; determining a first sample voltage by sampling a first representative voltage generated at the RC sensor circuit, wherein sampling the first representative voltage comprises driving the RC sensor circuit with the mirror current for a first time period; and determining a second sample voltage by sampling a second representative voltage generated at the RC sensor circuit, wherein sampling the second representative voltage comprises driving the RC sensor circuit with the mirror current for a second time period, and wherein a ratio of the first sample voltage to the second sample voltage is indicative of the RC time constant of the electronic circuit line.

2. The method of claim 1, further comprising: performing an operation at the electronic circuit line of the electronic device using an operating voltage selected from a plurality of operating voltages, wherein the operating voltage is selected based on the ratio indicative of the RC time constant.

3. The method of claim 1, further comprising: integrating the mirror current at an integration capacitor of the RC sensor circuit to generate the first representative voltage for the first time period.

4. The method of claim 3, wherein determining the first sample voltage by sampling the first representative voltage generated at the RC sensor circuit comprises: amplifying the first representative voltage at the integration capacitor to generate the first sample voltage at a sampling capacitor of the RC sensor circuit.

5. The method of claim 4, further comprising: integrating the mirror current at the integration capacitor of the RC sensor circuit to generate the second representative voltage for the second time period; and wherein determining the second sample voltage by sampling the second representative voltage generated at the RC sensor circuit comprises amplifying the second representative voltage at the integration capacitor to generate the second sample voltage at the sampling capacitor of the RC sensor circuit.

6. The method of claim 1, further comprising: driving the electronic circuit line of the electronic device to the drive voltage using the current concurrently with driving the RC sensor circuit.

7. The method of claim 1, wherein the ratio is mapped to a trim voltage, the trim voltage selected to drive the electronic circuit line in view of the RC time constant of the electronic circuit line.

8. The method of claim 7, wherein the electronic circuit line comprises a word line of a memory device, wherein the trim voltage is selected to drive the word line when performing a memory operation.

9. The method of claim 1, wherein the first sample voltage is converted to a first digital code representative of the first sample voltage, wherein the second sample voltage is converted to a second digital code representative of the second sample voltage, and wherein the ratio of the first sample voltage to the second sample voltage is determined using the first digital code and the second digital code.

10. The method of claim 1, wherein the electronic circuit line includes a first end and a second end opposite the first end, wherein a driver circuit is coupled to the first end to drive the second end to the drive voltage using the current, and wherein the second end is inaccessible for measurement of the drive voltage.

11. A non-transitory computer-readable medium comprising instructions that, in response to execution by a processing device, cause the processing device to perform operations comprising: driving, by the processing device, a resistor-capacitor (RC) sensor circuit of an electronic device to a drive voltage using a mirror current of an electronic circuit line of the electronic device, wherein the RC sensor circuit is configured to sample a voltage indicative of an RC time constant of the electronic circuit line; determining a first sample voltage by sampling a first representative voltage generated at the RC sensor circuit, wherein sampling the first representative voltage comprises driving the RC sensor circuit with the mirror current for a first time period; and determining a second sample voltage by sampling a second representative voltage generated at the RC sensor circuit, wherein sampling the second representative voltage comprises driving the RC sensor circuit with the mirror current for a second time period, and wherein a ratio of the first sample voltage to the second sample voltage is indicative of the RC time constant of the electronic circuit line.

12. The non-transitory computer-readable medium of claim 11, further comprising: performing an operation at the electronic circuit line of the electronic device using an operating voltage selected from a plurality of operating voltages, wherein the operating voltage is selected based on the ratio indicative of the RC time constant.

13. The non-transitory computer-readable medium of claim 11, further comprising: integrating the mirror current at an integration capacitor of the RC sensor circuit for the first time period to generate the first representative voltage.

14. The non-transitory computer-readable medium of claim 13, wherein determining the first sample voltage by sampling the first representative voltage generated at the RC sensor circuit comprises: amplifying the first representative voltage at the integration capacitor to generate the first sample voltage at a sampling capacitor of the RC sensor circuit.

15. The non-transitory computer-readable medium of claim 14, further comprising: integrating the mirror current at the integration capacitor of the RC sensor circuit for the second time period to generate the second representative voltage; and wherein determining the second sample voltage by sampling the second representative voltage generated at the RC sensor circuit comprises amplifying the second representative voltage at the integration capacitor to generate the second sample voltage at the sampling capacitor of the RC sensor circuit.

16. The non-transitory computer-readable medium of claim 11, further comprising: driving the electronic circuit line of the electronic device to the drive voltage using the current concurrently with driving the RC sensor circuit.

17. The non-transitory computer-readable medium of claim 11, wherein the ratio is mapped to a trim voltage selected to drive the electronic circuit line in view of the RC time constant of the electronic circuit line, wherein the electronic circuit line comprises a first end and a second end opposite the first end, wherein a driver circuit is coupled to the first end to drive the second end to the drive voltage using the current, and wherein the second end is inaccessible for measurement of the drive voltage.

18. A memory sub-system, comprising: a memory device; and a processing device coupled to the memory device, the processing device to: drive a resistor-capacitor (RC) sensor circuit to a drive voltage using a mirror current that drives an electronic circuit line of the memory device, wherein the RC sensor circuit is configured to sample a voltage indicative of an RC time constant of the electronic circuit line; determine a first sample voltage by sampling a first representative voltage generated at the RC sensor circuit, wherein sampling the first representative voltage comprises driving the RC sensor circuit with the mirror current for a first period of time; and determine a second sample voltage by sampling a second representative voltage generated at the RC sensor circuit, wherein sampling the second representative voltage comprises driving the RC sensor circuit with the mirror current for a second period of time, and wherein a ratio of the first sample voltage to the second sample voltage is indicative of the RC time constant of the electronic circuit line.

19. The memory sub-system of claim 18, the processing device further to: perform an operation at the electronic circuit line of the memory device using an operating voltage selected from a plurality of operating voltages, wherein the operating voltage is selected based on the ratio indicative of the RC time constant.

20. The memory sub-system of claim 19, wherein the electronic circuit line comprises a word line of a memory device, wherein the operating voltage is selected to drive the word line when performing a memory operation, wherein the word line comprises a first end and a second end opposite the first end, wherein a driver circuit is coupled to the first end to drive the second end to the drive voltage using the current, and wherein the second end is inaccessible for measurement of the drive voltage.

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