Instruction transmission method, processor, chip and electronic device

Abstract

The embodiment of the present application provides an instruction emission method, processor, chip and electronic device, wherein the method includes: in the current clock cycle, adding the instruction to be added to the instruction queue to the mobile queue in the instruction queue; wherein the instruction queue includes a mobile queue and a static queue, and the entry of the instruction queue is divided into an entry of the mobile queue and an entry of the static queue; in the current clock cycle, determining the candidate instructions in the mobile queue and the static queue that meet the instruction ready condition; based on the candidate instructions, selecting the instruction to be emitted in the current clock cycle and emitting it; moving the instructions in the mobile queue that have not been emitted in the current clock cycle to the head of the mobile queue as the goal, and moving them forward in sequence in the mobile queue; and adding the instructions that are at the head of the mobile queue and have not been emitted in the current clock cycle to the static queue. The embodiment of the present application can reduce the power consumption of instruction emission and improve the performance of the processor while meeting the timing requirements of the processor.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of processor technology, and specifically to an instruction transmission method, a processor, a chip, and an electronic device. Background Art

[0002] High-performance processors typically use superscalar out-of-order execution technology to improve instruction processing efficiency. During out-of-order instruction execution, instructions are sent to the pipeline through an instruction issue queue (instruction queue for short), a process known as instruction issue. As processor performance requirements continue to increase, reducing the power consumption of instruction issue has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0003] In view of this, embodiments of the present application provide an instruction transmission method, a processor, a chip, and an electronic device to reduce power consumption of instruction transmission and improve processor performance.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0005] In a first aspect, an embodiment of the present application provides a method for transmitting an instruction, comprising:

[0006] In a current clock cycle, adding an instruction to be added to the instruction queue to a mobile queue in the instruction queue; wherein the instruction queue includes a mobile queue and a static queue, and entries in the instruction queue are divided into entries in the mobile queue and entries in the static queue, wherein one entry stores one instruction;

[0007] and, in the current clock cycle, determining candidate instructions in the mobile queue and the static queue that meet the instruction ready condition; and selecting an instruction to be issued in the current clock cycle based on the candidate instructions and issuing the instruction;

[0008] Also, instructions in the mobile queue that have not been issued in the current clock cycle are moved forward sequentially in the mobile queue with the goal of being moved to the head of the mobile queue; and instructions that are at the head of the mobile queue and have not been issued in the current clock cycle are added to the static queue.

[0009] In a second aspect, an embodiment of the present application provides a processor, comprising: an instruction queue, instruction ready judgment logic, and a data selector; wherein the instruction queue comprises a mobile queue and a static queue, entries of the instruction queue are divided into entries of the mobile queue and entries of the static queue, and each entry stores one instruction;

[0010] The instruction ready judgment logic is used to determine the candidate instructions that meet the instruction ready condition in the mobile queue and the static queue in the current clock cycle;

[0011] The data selector is configured to select and transmit an instruction to be transmitted in the current clock cycle based on the candidate instructions;

[0012] Among them, the instructions expected to be added to the instruction queue in the current clock cycle are first added to the mobile queue; the instructions in the mobile queue that have not been issued in the current clock cycle are moved forward sequentially in the mobile queue with the goal of moving to the head of the mobile queue; and the instructions that are at the head of the mobile queue and have not been issued in the current clock cycle are added to the static queue.

[0013] In a third aspect, an embodiment of the present application provides a processor, which is configured to execute the instruction transmission method provided in the embodiment of the present application.

[0014] In a fourth aspect, an embodiment of the present application provides a chip, which includes the processor as described in the second aspect, or the processor as described in the third aspect.

[0015] In a fifth aspect, an embodiment of the present application provides an electronic device, which includes a chip provided in an embodiment of the present application.

[0016] The instruction emission method provided by the embodiment of the present application can divide the entries for storing instructions in the instruction queue into entries of the mobile queue and entries of the static queue, thereby mixing the mobile queue and the static queue for instruction storage and emission; in the current clock cycle, the instructions to be added to the instruction queue can be added to the mobile queue first, and the instructions in the mobile queue that have not been emitted in the current clock cycle are moved forward in sequence in the mobile queue with the goal of moving to the head of the mobile queue; at the same time, the instructions that are at the head of the mobile queue and have not been emitted in the current clock cycle can be added to the static queue. For the instructions stored in the mobile queue and the static queue, the embodiment of the present application can determine the candidate instructions in the mobile queue and the static queue that meet the instruction ready conditions in the current clock cycle; thus, based on the candidate instructions, the instruction to be emitted in the current clock cycle is selected and emitted, so that the mobile queue has an idle entry to add new instructions, and the static queue has an idle entry to store the instructions added from the mobile queue to the static queue. It can be seen that in the embodiment of the present application, when the entries of the instruction queue are divided into mobile queue type entries and static queue type entries, the mobile queue is first used to store and transmit instructions, which can meet the timing requirements of the processor through the characteristics of the mobile queue, and then the instructions at the head of the mobile queue and not transmitted in the current clock cycle are transferred to the static queue for storage and transmission, which can greatly reduce the dynamic power consumption of instruction transmission through the characteristics of the static queue; therefore, the embodiment of the present application uses a mixture of mobile queues and static queues to store and transmit instructions, which can reduce the power consumption of instruction transmission while meeting the timing requirements of the processor, thereby improving the performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0018] Figure 1A This is a simplified example diagram of the process of out-of-order instruction execution.

[0019] Figure 1B This is an example diagram of the instruction queue.

[0020] Figure 2A An example diagram of instruction issuance for a move queue.

[0021] Figure 2B This is an example diagram of instruction issuance for a static queue.

[0022] Figure 3AAn example diagram of an instruction queue provided in an embodiment of the present application.

[0023] Figure 3B A flowchart of the instruction transmission method provided in an embodiment of the present application.

[0024] Figure 3C This is an example diagram of an implementation of the instruction transmission method provided in an embodiment of the present application.

[0025] Figure 4 This is an example diagram of an implementation of a processor provided in an embodiment of the present application.

[0026] Figure 5A Another example diagram of an instruction queue provided in an embodiment of the present application.

[0027] Figure 5B Another flowchart of the instruction transmission method provided in an embodiment of the present application.

[0028] Figure 6 A flow chart of a method for determining readiness information for a command.

[0029] Figure 7 This is another example diagram of an implementation of the processor provided in an embodiment of the present application.

[0030] Figure 8 This is an example diagram of the tag comparison process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] Figure 1A An example diagram of a simplified process of out-of-order execution of instructions is shown as an example. As shown in Figure 1, the out-of-order execution process of instructions mainly includes the following stages: instruction decoding stage 110, register renaming stage 120, instruction issuance stage 130, instruction execution stage 140, and instruction submission stage 150.

[0033] In the instruction decoding stage 110 , the processor may decode the instruction fetched from the cache or main memory to obtain a decoded instruction, thereby determining information such as an operation code and / or an address code of the instruction.

[0034] During the register renaming stage 120, the processor may rename the registers of the decoded instructions, mapping the architectural register numbers of the instructions to physical register numbers, thereby eliminating register dependencies between the previous and next instructions. Furthermore, during register renaming, the processor may also eliminate register dependencies between the previous and next instructions through related processing logic. After eliminating register dependencies between the previous and next instructions, the instructions may enter the instruction queue (IQ), which may store instructions that the processor needs to execute out of order, and then issue the instructions during the instruction issue stage 130.

[0035] In the instruction emission stage 130, for the instructions stored in the instruction queue, the processor may emit the instructions from the instruction queue to the corresponding pipeline when the instructions meet the instruction ready condition. For example, any instruction in the instruction queue can be emitted when the source operand is ready and the corresponding pipeline is ready. The instructions in the instruction queue can support out-of-order emission and do not need to be emitted in the order in which the instructions enter the instruction queue. It should be noted that multiple pipelines for executing instructions can be set in the processor, and for any instruction, the instruction may not necessarily enter all pipelines for execution, so the pipeline that the instruction may enter can be called the pipeline corresponding to the instruction.

[0036] In the instruction execution stage 140, for the instructions issued from the instruction queue, the processor can read the source operands of the instructions from the register file and enter the pipeline corresponding to the instruction to execute the instructions; based on the out-of-order issuance of instructions, the processor can realize out-of-order execution of instructions.

[0037] In the instruction submission stage 150, for the executed instructions, the processor can write the execution results into the register file and save the instructions into the submission queue. The instructions in the submission queue can be submitted sequentially.

[0038] It should be noted that Figure 1 is only an example of an optional process for a processor to execute instructions out of order. The processor can also adjust or replace one or more of the above stages as needed. However, regardless of the adjustment or replacement, the current processor still needs to go through the instruction issue stage to send instructions from the instruction queue to the corresponding pipeline for execution. Therefore, it is particularly necessary to optimize the technical solution of the instruction issue stage.

[0039] Figure 1B An example diagram of an optional instruction queue is shown as follows: Figure 1B As shown, the instruction queue may include multiple entries, for example Figure 1BEntry 1 through entry n are shown. An entry can be considered a storage unit for instructions in an instruction queue. An instruction queue can have multiple entries, each storing a single instruction. Instruction queues can be divided into two types: shift queues and static queues, depending on whether the instructions stored in the entry are dynamically moved. These two types are described below.

[0040] For mobile queues, unissued instructions in the queue aim to move to the head of the queue, and are dynamically moved forward in sequence during each clock cycle (the head of the mobile queue can be considered the front of the mobile queue). Specifically, during each clock cycle, instructions can enter the mobile queue sequentially from the tail of the mobile queue, and unissued instructions in the mobile queue are sequentially moved forward during each clock cycle until they reach the head of the mobile queue. It should be noted that the number of entries that instructions sequentially move forward in one clock cycle can be set based on actual conditions and algorithms, and is subject to the condition that it does not exceed the number of unissued instructions at the front of the queue.

[0041] For ease of understanding, let's take the number of entries n in the instruction queue as 10 as an example. Figure 2A The following example shows an example diagram of the instruction issuance of the mobile queue. Figure 2A As shown, the mobile queue has 10 entries that can store 10 instructions (it should be noted that the specific number of entries in the instruction queue can be determined according to actual conditions. Here, for the sake of convenience of example, it is assumed that the number of entries is 10). In one clock cycle, assuming that entries 1 to 10 in the mobile queue store instructions A1 to A10 respectively, and instructions A2, A4, and A8 meet the instruction ready condition, and other instructions do not meet the instruction ready condition, then instructions A2, A4, and A8 are emitted from the mobile queue, and other instructions move forward sequentially in the mobile queue (instruction A10 is already at the head of the queue, so instruction A10 no longer moves); based on the movement of instructions in the mobile queue, entry 8 in the mobile queue stores instruction A7, entry 7 stores instruction A6, entry 6 stores instruction A5, entry 5 stores instruction A3, entry 4 stores instruction A1, and entry 3, entry 2, and entry 1 respectively store instructions A11, A12, and A13 newly added to the mobile queue in the current clock cycle. In the next clock cycle, instructions are still added to the mobile queue in sequence from the end of the mobile queue. Instructions in the mobile queue that meet the instruction ready conditions are selected and issued, while unissued instructions are moved to the front of the mobile queue with the goal of moving to the head of the queue and without exceeding the unissued instructions in front of the queue.

[0042] It can be seen that in terms of microstructure, the logic of the mobile queue is relatively simple, and the fan-out of each entry is small. Therefore, when the instruction queue uses a mobile queue to store and transmit instructions, the timing is easy to converge, especially when the processor frequency is high. However, in each clock cycle, the unissued instructions in the mobile queue need to be dynamically moved forward, which causes the mobile queue to consume higher dynamic power, resulting in higher power consumption for the processor to transmit instructions. It should be noted that for the signal line of the processor, the fan-out corresponds to the output of the signal line (for example, the size of the fan-out corresponds to the number of outputs of the signal line). If the fan-out is larger, the more outputs the signal line has. Correspondingly, the signal line is heavier in load, the signal flipping speed is slower, and the signal line transmission delay is longer.

[0043] For static queues, in each clock cycle, instructions that meet the instruction ready condition in the queue are selected and issued, and unissued instructions are kept at the stored entry. New instructions added to the static queue are inserted into the static queue in the order of the free entries in the static queue. For ease of understanding, take the example of the number of entries n in the instruction queue being 10. Figure 2B This diagram illustrates an example of instruction issuance from a static queue. During a clock cycle, entries 1 through 10 in the static queue store instructions A1 through A10, respectively. If instructions A2, A4, and A8 meet the instruction-ready condition, while other instructions do not, instructions A2, A4, and A8 are issued from the static queue, while the other instructions retain their stored entries in the static queue. During the issuance of instructions A2, A4, and A8, entries 2, 4, and 8 in the static queue are idle. Instructions A11, A12, and A13, newly added to the static queue, can be stored in entries 8, 4, and 2, respectively.

[0044] It can be seen that the instructions in the static queue do not move, so the dynamic power consumption of the instruction queue is low when using a static queue to store and issue instructions. However, since the idle entries in the static queue are uncertain, new instructions may be added to any position in the static queue, which leads to a large fan-out of the static queue entrance, so the timing of the static queue is relatively tight. One way to alleviate the tight timing of the static queue is to insert an additional pipeline stage at the entrance, but the introduction of additional pipeline stages will result in performance loss of the processor.

[0045] As can be seen from the above description, different problems exist when using either a mobile queue or a static queue for instruction queues. Specifically, using a mobile queue to store and issue instructions will result in higher power consumption for instruction issuance; using a static queue to store and issue instructions will result in failure to meet timing requirements. Based on this, the embodiments of the present application provide an improved instruction issuance scheme that stores and issues instructions using a hybrid mobile queue and static queue to reduce power consumption for instruction issuance while meeting processor timing requirements, thereby improving processor performance.

[0046] As an optional implementation, Figure 3A An optional example diagram of the instruction queue provided in the embodiment of the present application is shown as an example. Figure 3A As shown, the instruction queue may include a mobile queue 310 and a static queue 320; wherein, the entries of the instruction queue are divided into entries of the mobile queue 310 and entries of the static queue 320. As an optional implementation, the embodiment of the present application may treat some entries in the instruction queue as mobile queue type entries (in each clock cycle, if the instruction stored in the entry is not issued, it is dynamically moved forward), while treating another part of the entries in the instruction queue as static queue type entries (the instructions stored in the entry are not moved). Therefore, from a performance perspective, the total number of entries in the instruction queue = the number of entries in the mobile queue + the number of entries in the static queue.

[0047] In one example, combining Figure 3A As shown, assuming that the instruction queue has n entries from entry 1 to entry n; then the m entries from entry 1 to entry m can be used as entries of the mobile queue 310 (i.e., the mobile queue 310 has entry 1 to entry m), and the nm entries from entry m+1 to entry n can be used as entries of the static queue 320 (i.e., the static queue 320 has entry m+1 to entry n). Among them, m can be regarded as the number of entries in the instruction queue allocated to the mobile queue 310, and its specific value can be set according to actual conditions. As an optional implementation, since the mobile queue 310 is mainly used to solve the timing problem at the entrance of the instruction queue, the depth of the mobile queue 310 can be designed to be shallower; for example, the number of entries in the mobile queue 310 can be less than the number of entries in the static queue 320. In one example, the number of entries in the mobile queue 310 (e.g., the value of m) can be set according to the instruction issuance width of the instruction queue in each clock cycle. For example, the value of m is set to be the same as the instruction issuance width. The instruction issuance width can be regarded as the upper limit of the number of instructions issued by the instruction queue in each clock cycle.

[0048] pass Figure 3A The instruction queue structure shown in the embodiment of the present application can, without increasing the number of entries in the instruction queue, divide the entries in the instruction queue into mobile queue type entries and static queue type entries, and use a mixed mobile queue and static queue for storage and transmission of instructions, thereby combining the advantages of mobile queues and static queues to achieve the purpose of meeting processor timing requirements and reducing power consumption when issuing instructions.

[0049] In an optional implementation idea of ​​mixed use of mobile queues and static queues, for instructions to be added to the instruction queue in any clock cycle, the embodiment of the present application can first use the mobile queue to store the instructions, thereby meeting the timing requirements of the high-frequency processor through the characteristics of the mobile queue; in any clock cycle, when the unissued instructions in the mobile queue are at or move to the head of the mobile queue, the embodiment of the present application can add the unissued instructions at the head of the mobile queue to the static queue, thereby utilizing the characteristics of the static queue to reduce the transmission power consumption of the instructions in the static queue, and thus achieve the purpose of using a mixed use of mobile queues and static queues to meet the processor timing requirements and reduce power consumption.

[0050] Based on the above ideas, as an optional implementation, Figure 3B The optional flow chart of the instruction transmission method provided by the embodiment of the present application is shown as an example. The method flow can be implemented by the processor, such as Figure 3B As shown, the method flow may include the following steps.

[0051] In step S31, in the current clock cycle, the instruction to be added to the instruction queue is added to the mobile queue in the instruction queue; wherein the instruction queue includes a mobile queue and a static queue, and the entry of the instruction queue is divided into an entry of the mobile queue and an entry of the static queue, wherein one entry stores one instruction.

[0052] based on Figure 3A As shown in the instruction queue structure, in the current clock cycle of the processor, the embodiment of the present application can determine the instruction to be added to the instruction queue and first use the mobile queue to store the instruction.

[0053] In some embodiments, based on the characteristic that unissued instructions in the mobile queue dynamically move forward in each clock cycle, embodiments of the present application can sequentially add instructions to be added to the instruction queue from the end of the mobile queue to the mobile queue. In one example, the instruction to be added to the instruction queue in the current clock cycle can be an instruction that completes register renaming in the current clock cycle. For example, an instruction that completes the register renaming stage in the current clock cycle can be sequentially added to the mobile queue from the end of the mobile queue.

[0054] As an optional implementation, the current clock cycle can be any clock cycle of the processor. In any clock cycle of the processor, the embodiment of the present application can add the instruction that completes register renaming to the instruction queue and select instructions from the instruction queue (including the mobile queue and the static queue) for emission; at the same time, the unemitted instructions in the mobile queue are sequentially moved forward in the mobile queue, and the unemitted instructions stored at the head of the mobile queue can be added to the static queue. The above process will be described in detail below.

[0055] In step S32, in the current clock cycle, candidate instructions in the mobile queue and the static queue that meet the instruction ready condition are determined.

[0056] In an embodiment of the present application, the instruction stored in the mobile queue is derived from the instruction added to the instruction queue after completing register renaming, and the instruction stored in the static queue is derived from the instruction transferred from the mobile queue to the static queue (i.e., the instruction at the head of the mobile queue and not emitted is transferred to the static queue for storage). For the instructions stored in the mobile queue and the static queue, the embodiment of the present application needs to determine the instructions that meet the instruction ready condition and the instructions that do not meet the instruction ready condition, so as to carry out the instruction emission of the current clock cycle based on the instructions that meet the instruction ready condition in the mobile queue and the static queue. For ease of explanation, the embodiment of the present application may refer to the instruction that meets the instruction ready condition as a candidate instruction.

[0057] In some embodiments, instruction readiness may include the source operands of the instruction being ready and the pipeline corresponding to the instruction being ready (for example, the pipeline corresponding to the instruction is able to receive the instruction). Accordingly, an instruction meeting the instruction ready condition may include: the source operands of the instruction are ready, and the pipeline corresponding to the instruction is ready. Based on this, as an optional implementation, for any instruction stored in the mobile queue and the static queue, the embodiment of the present application may determine whether the source operands of the instruction are ready in the current clock cycle, and whether the pipeline corresponding to the instruction is ready in the current clock cycle; if the source operands of the instruction are ready in the current clock cycle, and the pipeline corresponding to the instruction is ready in the current clock cycle, then the instruction may be determined to be a candidate instruction that meets the instruction ready condition; if the source operands of the instruction are not ready in the current clock cycle, or the pipeline corresponding to the instruction is not ready (for example, the pipeline corresponding to the instruction is not able to receive the instruction), then it may be determined that the instruction does not meet the instruction ready condition in the current clock cycle. Further, in one example, the pipeline corresponding to the instruction is able to receive the instruction may include: the pipeline corresponding to the instruction does not have functional unit conflicts, write port conflicts, etc.

[0058] In an optional implementation, the embodiment of the present application may also determine whether the instruction meets the instruction ready condition before the instruction is added to the instruction queue (for example, the instruction is added to the mobile queue), rather than necessarily determining whether the instruction meets the instruction ready condition after the instruction is added to the instruction queue. For example, the embodiment of the present application may set the readiness information of the instruction. Before adding the instruction to the instruction queue, the embodiment of the present application may obtain the readiness information of whether the instruction meets the instruction ready condition by determining whether the source operand of the instruction is ready and whether the corresponding pipeline is ready, and add the readiness information of the instruction together with the instruction to the instruction queue; thus, for the instruction in the instruction queue, if the readiness information of the instruction indicates that the instruction meets the instruction ready condition, the embodiment of the present application may determine that the instruction is a candidate instruction; if the readiness information of the instruction indicates that the instruction does not meet the instruction ready condition (for example, the source operand of the instruction is not ready and / or the corresponding pipeline is not ready), the embodiment of the present application needs to further determine whether the instruction meets the instruction ready condition in the current clock cycle.

[0059] In step S33, based on the candidate instructions, an instruction to be issued in the current clock cycle is selected and issued.

[0060] After determining the candidate instructions that meet the instruction readiness conditions from the mobile queue and static queue respectively, based on whether the instructions are emitted to the corresponding pipeline for execution, the embodiment of the present application needs to select the candidate instructions in the mobile queue and static queue based on the situation of the pipeline corresponding to the instruction, and whether they can be emitted in the current clock cycle. Based on this, the embodiment of the present application can introduce an instruction selection mechanism for selecting the instruction to be emitted in the current clock cycle from the candidate instructions in the mobile queue and static queue based on the situation of the pipeline corresponding to the candidate instruction.

[0061] In some embodiments, since the instructions in the static queue come from the mobile queue, and the unissued instructions in the mobile queue need to be dynamically moved in each clock cycle, while the unissued instructions in the static queue remain stationary, based on the different characteristics of the mobile queue and the static queue, the embodiments of the present application can select different instruction selection mechanisms for the candidate instructions in the mobile queue and the static queue.

[0062] As an optional implementation, for any candidate instruction in the mobile queue, if the pipeline corresponding to the candidate instruction is not occupied by the static queue, the embodiment of the present application may select the candidate instruction as the instruction to be emitted in the current clock cycle, thereby ensuring that the candidate instruction in the mobile queue is preferentially emitted when the pipeline is not occupied. In one example, the pipeline corresponding to the candidate instruction is not occupied by the static queue can be: in the current clock cycle, no instruction in the static queue is selected and emitted to the pipeline corresponding to the candidate instruction.

[0063] As an optional implementation, based on the fact that instructions are emitted to the corresponding pipeline for execution, if a pipeline corresponds to multiple candidate instructions that meet the instruction ready condition in the current clock cycle, the pipeline may not be able to support the execution of the multiple candidate instructions. Therefore, when multiple candidate instructions in the static queue correspond to the same pipeline, the embodiment of the present application can select the instruction to be emitted in the current clock cycle based on the age (age, indicating the time when the instruction is added to the instruction queue) of the multiple candidate instructions corresponding to the same pipeline in the static queue. For example, the embodiment of the present application can select the instruction to be emitted in the current clock cycle from the multiple candidate instructions corresponding to the same pipeline in the static queue according to the principle that the age of the instruction is positively correlated with the emission priority (that is, the older the age of the instruction, the higher the priority of the instruction emission).

[0064] In an example, assume that in the current clock cycle, there are 5 candidate instructions that meet the instruction ready condition in the static queue: instructions B1, B2, B3, B4 and B5; if instructions B1, B3 and B4 correspond to the same pipeline (that is, instructions B1, B3 and B4 need to be issued to the same pipeline for execution), and instructions B2 and B5 are different from the pipelines corresponding to other instructions, then instructions B2 and B5 can be issued directly, while instructions B1, B3 and B4 need to be based on the age of the instructions, and the instruction with the oldest age (that is, the longest time to join the instruction queue) needs to be selected for priority issuance; assuming that instruction B4 among instructions B1, B3 and B4 has the oldest age, then instruction B4 will be issued first in the current clock cycle, and instructions B1 and B3 will not be issued, and will wait for the next clock cycle to be selected.

[0065] It should be noted that the use of different instruction selection mechanisms for candidate instructions in the mobile queue and the static queue is only an optional implementation. The embodiments of the present application may also use the same instruction selection mechanism for candidate instructions in the mobile queue and the static queue; for example, both the mobile queue and the static queue select the instruction to be emitted in the current clock cycle based on the age of the candidate instruction. Of course, selecting the instruction to be emitted first based on the age of the instruction is also only an optional implementation. In other possible implementations, without exceeding the emission width of the instruction queue, the embodiments of the present application may also select the instruction to be emitted in the current clock cycle from the candidate instructions based on the type of instruction (for example, different emission priorities are divided according to the type of instruction), or directly select all candidate instructions as the instructions to be emitted in the current clock cycle. The embodiments of the present application do not limit the specific implementation of the instruction selection mechanism.

[0066] In step S34, the instructions in the mobile queue that have not been issued in the current clock cycle are moved forward sequentially in the mobile queue with the goal of being moved to the head of the mobile queue; and the instructions that are at the head of the mobile queue and have not been issued in the current clock cycle are added to the static queue.

[0067] After selecting an instruction from the mobile queue for transmission, based on the idle entry of the mobile queue for transmitting the instruction, the embodiment of the present application can move the position of the instructions that have not been transmitted in the current clock cycle in the mobile queue according to the instruction movement characteristics of the mobile queue. It should be noted that the instructions that have not been transmitted in the current clock cycle in the mobile queue include: instructions that do not meet the instruction ready condition in the current clock cycle in the mobile queue, and / or candidate instructions that meet the instruction ready condition in the current clock cycle in the mobile queue but are not selected for transmission. As an optional implementation, the instructions that have not been transmitted by the mobile queue in the current clock cycle are moved to the front of the mobile queue with the goal of moving to the head of the mobile queue and without exceeding the untransmitted instructions in front of the mobile queue.

[0068] It should be noted that in the embodiment of the present application, although the unissued instructions in the mobile queue are still dynamically moved forward in each clock cycle, the entries in the mobile queue are only part of the entries that constitute the instruction queue. Therefore, the range in which the instructions can move in the mobile queue is greatly reduced. Therefore, when the timing of the mobile queue is easy to converge and the instruction movement range of the mobile queue is reduced, the instructions can be stored in the mobile queue first, so as to meet the timing requirements of the processor and reduce the power consumption of instruction issuance to a certain extent.

[0069] Furthermore, based on the mixed use of mobile queues and static queues in the embodiments of the present application, when the mobile queue is first used to store instructions, the embodiments of the present application need to consider a mechanism for transferring instructions in the mobile queue to the static queue. As an optional implementation, in the current clock cycle, the embodiments of the present application can add instructions that are at the head of the mobile queue and have not been issued in the current clock cycle to the static queue for storage. For example, based on the idle entries in the static queue, instructions that are at the head of the mobile queue and have not been issued in the current clock cycle can be sequentially added to the idle entries in the static queue. Optionally, the instructions that are at the head of the mobile queue and have not been issued in the current clock cycle can include: instructions that are at the head of the mobile queue and have not met the instruction ready condition in the current clock cycle, or candidate instructions that are at the head of the mobile queue and have met the instruction ready condition in the current clock cycle but have not been selected for issuance. The instruction at the head of the mobile queue may be the instruction that was originally at the head of the mobile queue at the beginning of the current clock cycle, or the instruction that was moved to the head of the mobile queue during the current clock cycle.

[0070] As can be seen, in this embodiment of the present application, the idle entries in the mobile queue in the current clock cycle come from two sources: 1. The entries idled by the mobile queue when instructions were issued in the current clock cycle; 2. The entries idled by the unissued instructions at the head of the mobile queue after being added to the static queue. Based on the idle entries in the mobile queue in the current clock cycle, this embodiment of the present application can add instructions to be added to the instruction queue in the current clock cycle to the idle entries in the mobile queue, starting from the end of the mobile queue.

[0071] Furthermore, after selecting an instruction from the static queue for transmission, instructions in the static queue that have not been transmitted in the current clock cycle (instructions in the static queue that do not meet the instruction ready condition in the current clock cycle, and / or candidate instructions in the static queue that meet the instruction ready condition in the current clock cycle but have not been selected for transmission) are stored in the original entry of the static queue. Since instructions in the static queue are not moved every clock cycle, moving instructions from the mobile queue into the static queue for storage and transmission can significantly reduce the dynamic power consumption of instruction transmission.

[0072] It can be seen that in the embodiment of the present application, the idle entries of the static queue in the current clock cycle mainly come from: the idle entries of the static queue for issuing instructions in the current clock cycle. Based on this, as an optional implementation, when adding the instructions that are at the head of the mobile queue and have not been issued to the static queue, the embodiment of the present application can, based on the idle entries in the static queue, sequentially add the instructions that are at the head of the mobile queue and have not been issued in the current clock cycle to the idle entries of the static queue. For example, after adding the instruction that is currently at the head of the mobile queue and has not been issued to an idle entry in the static queue, if there are still idle entries in the static queue, the instructions that are located after the head of the mobile queue and have not been issued can be moved to the head of the mobile queue and then added to the idle entries of the static queue; this is repeated until there are no idle entries in the static queue; at this time, since there are no idle entries in the static queue, the subsequent instructions that are moved to the head of the mobile queue and have not been issued will be added to the static queue in the next clock cycle.

[0073] To facilitate understanding of the instruction transmission scheme provided in the embodiment of the present application, Figure 3C The following is an example diagram showing an implementation example of the instruction transmission method provided in the embodiment of the present application. Figure 3CAs shown in the figure, taking the number of entries n in the instruction queue as 10, in one example, 4 entries in the instruction queue can be allocated to the mobile queue, and the other 6 entries can be allocated to the static queue. In one clock cycle, assume that instructions A1 to A4 are stored in the mobile queue, and instructions A5 to A10 are stored in the static queue; and assume that instructions A1, A2, and A3 in the mobile queue meet the instruction ready condition, while instruction A4 does not meet the instruction ready condition. At the same time, assume that instructions A7, A8, and A10 in the static queue meet the instruction ready condition, while instructions A5, A6, and A9 do not meet the instruction ready condition.

[0074] Furthermore, assuming that the pipelines corresponding to instructions A1 and A3 in the mobile queue are not occupied by the static queue, and the pipeline of instruction A2 is occupied by the static queue, then instructions A1 and A3 can be selected as instructions to be issued in the current clock cycle and are issued, and instruction A2 is not issued in the current clock cycle; assuming that instructions A7 and A8 in the static queue correspond to the same pipeline, and instruction A10 and other instructions that meet the instruction ready conditions do not correspond to the same pipeline, then instruction A10 is directly issued, and instructions A7 and A8 select the older instruction A8 for issuance based on the age of the instructions.

[0075] After instructions A8 and A10 in the static queue are issued, entries 8 and 10 in the static queue are idle. The mobile queue can add the two unissued instructions to the static queue. Specifically, after instructions A1 and A3 in the mobile queue are issued, instruction A4 at the head of the queue does not meet the instruction ready condition, so instruction A4 is added to entry 10 of the static queue. At the same time, the unissued instruction A2 in the mobile queue moves forward sequentially in the mobile queue, and instruction A2 moves to entry 4 of the mobile queue. At this time, since there is still an idle entry 8 in the static queue, instruction A2 is added to entry 8 of the static queue. At this time, there is no idle entry in the static queue.

[0076] During the instruction issuance and instruction movement of the mobile queue, entries 4 to 1 of the mobile queue are idle, so new instructions A11 to A14 can be added to entries 4 to 1 of the mobile queue respectively; if instructions A11 to A14 do not meet the instruction ready condition in the current clock cycle, the instruction issuance of the current clock cycle ends; if there are instructions among instructions A11 to A14 that meet the instruction ready condition and can be selected for issuance (the pipeline corresponding to the instruction is not occupied by the static queue), then after the instructions selected for issuance among instructions A11 to A14 are issued, the remaining instructions continue to move forward sequentially in the mobile queue, and new instructions continue to be added to the mobile queue until the instructions stored in the mobile queue do not meet the instruction ready condition in the current clock cycle, or cannot be selected as instructions to be issued, or the issued instructions reach the instruction issuance width of one clock cycle, and the instruction issuance of the current clock cycle ends.

[0077] The instruction emission method provided by the embodiment of the present application can divide the entries for storing instructions in the instruction queue into entries of the mobile queue and entries of the static queue, thereby mixing the mobile queue and the static queue for instruction storage and emission; in the current clock cycle, the instructions to be added to the instruction queue can be added to the mobile queue first, and the instructions in the mobile queue that have not been emitted in the current clock cycle are moved forward in sequence in the mobile queue with the goal of moving to the head of the mobile queue; at the same time, the instructions that are at the head of the mobile queue and have not been emitted in the current clock cycle can be added to the static queue. For the instructions stored in the mobile queue and the static queue, the embodiment of the present application can determine the candidate instructions in the mobile queue and the static queue that meet the instruction ready conditions in the current clock cycle; thus, based on the candidate instructions, the instruction to be emitted in the current clock cycle is selected and emitted, so that the mobile queue has an idle entry to add new instructions, and the static queue has an idle entry to store the instructions added from the mobile queue to the static queue. It can be seen that in the embodiment of the present application, when the entries of the instruction queue are divided into mobile queue type entries and static queue type entries, the mobile queue is first used to store and transmit instructions, which can meet the timing requirements of the processor through the characteristics of the mobile queue, and then the instructions at the head of the mobile queue and not transmitted in the current clock cycle are transferred to the static queue for storage and transmission, which can greatly reduce the dynamic power consumption of instruction transmission through the characteristics of the static queue; therefore, the embodiment of the present application uses a mixture of mobile queues and static queues to store and transmit instructions, which can reduce the power consumption of instruction transmission while meeting the timing requirements of the processor, thereby improving the performance of the processor.

[0078] based on Figure 3A The instruction queue structure shown and Figure 3B The instruction transmission method flow shown is an optional implementation. Figure 4 An exemplary implementation diagram of a processor provided in an embodiment of the present application is shown. Figure 4 As shown, the processor may include: a mobile queue 310 , a static queue 320 , an instruction ready judgment logic 410 and a data selector 420 .

[0079] In an embodiment of the present application, after the instruction is fetched and decoded by the processor front end, it can enter the register renaming and related processing logic stage, and then the instruction becomes an instruction to be added to the instruction queue; the instruction to be added to the instruction queue can first be added to the mobile queue 310.

[0080] The instruction ready determination logic 410 may be used to determine candidate instructions that meet instruction ready conditions and instructions that do not meet instruction ready conditions in the mobile queue 310 and the static queue 320 in the current clock cycle.

[0081] The data selector 420 may be used to select and issue an instruction to be issued in the current clock cycle based on the candidate instructions in the mobile queue 310 and the static queue 320 .

[0082] Among them, after the instructions in the mobile queue 310 and the static queue 320 are selected for issuance, the instructions in the mobile queue 310 that have not been issued in the current clock cycle are moved forward sequentially in the mobile queue with the goal of moving to the head of the mobile queue; and the instructions that are at the head of the mobile queue and have not been issued in the current clock cycle can be added to the static queue.

[0083] In some embodiments, instruction readiness determination logic 410 may include source operand readiness determination logic 411 and pipeline readiness determination logic 412. Source operand readiness determination logic 411 is used to determine whether the source operand of the instruction is ready in the current clock cycle; pipeline readiness determination logic 412 is used to determine whether the pipeline corresponding to the instruction is ready in the current clock cycle. The methods for determining whether the source operand of the instruction is ready and whether the pipeline corresponding to the instruction is ready can be found in the description of the corresponding sections of the document and will not be expanded here.

[0084] It should be further explained that the more specific implementation method of the instruction ready judgment logic 410 for judging the instruction ready condition, the implementation method of selecting the instruction to be issued in the current clock cycle from the candidate instructions, the instruction movement method of the mobile queue, and the implementation method of transferring the instructions in the mobile queue to the static queue, etc., can be referred to the description of the corresponding part of the previous text and will not be expanded here.

[0085] In some further embodiments, based on the fact that the instruction satisfies the instruction ready condition, which may include the source operand of the instruction being ready and the pipeline corresponding to the instruction being ready, the embodiment of the present application may further subdivide the structure of the static queue. As an optional implementation, Figure 5A Another optional example diagram of the instruction queue provided by the embodiment of the present application is shown as an example. Figure 3A and Figure 5A As shown, in Figure 5A In the embodiment, the static queue 320 in the instruction queue may further include: a ready static queue (RQ) 510 and an unready static queue (URQ) 520. Among them, for an instruction added to the static queue by the mobile queue, if the source operand of the instruction is ready, the instruction may be added to the ready static queue 510; if the source operand of the instruction is not ready, the instruction may be added to the unready static queue 520. In other words, the ready static queue is used to store instructions added to the static queue by the mobile queue whose source operands are ready, and the unready static queue is used to store instructions added to the static queue by the mobile queue whose source operands are not ready. Therefore, when judging the instruction readiness condition of the instruction in the ready static queue, it is no longer necessary to judge whether the source operand is ready, which can further reduce the power consumption of instruction issuance.

[0086] based on Figure 5A The instruction queue structure shown in the figure is described below. The instruction transmission method provided by the embodiment of the present application is introduced below. As an optional implementation, Figure 5B Another optional flow chart of the instruction transmission method provided by the embodiment of the present application is shown as an example. The method flow can be executed by a processor. For the convenience of explanation, the method flow is described from the perspective of a mobile queue and a static queue (including a ready static queue and an unready static queue). Figure 5B The method flow may include the following steps.

[0087] In step S51 , in the current clock cycle, for the instruction to be added to the instruction queue, the instruction and the readiness information of the instruction are added to the mobile queue.

[0088] In some embodiments, the processor may determine the readiness information of the instruction before adding the instruction to the instruction queue, so that when the instruction is added to the move queue within the instruction queue, the readiness information of the instruction may also be added to the move queue. For example, the move queue entry may store the readiness information of the instruction in addition to the instruction.

[0089] As an optional implementation, the readiness information of the instruction can indicate whether the instruction meets the instruction readiness condition, such as whether the source operand of the instruction is ready, whether the corresponding pipeline is ready, etc. As an optional implementation, before adding the instruction to the instruction queue, the embodiment of the present application can first determine whether the source operand of the instruction is ready by reading the MBV (Matched Bit Vector, matching vector of the physical register) corresponding to the instruction; if the source operand of the instruction is not ready, it can also be determined whether the source operand of the instruction is ready by comparing the Tag of the source operand of the instruction (the Tag in the embodiment of the present application represents the physical register number, that is, the physical register number corresponding to the source operand) with the Tag broadcast in the current clock cycle. Thus, the embodiment of the present application can obtain the readiness information of the instruction based at least on the result of whether the source operand of the instruction is ready. Furthermore, after obtaining the result of whether the source operand of the instruction is ready, the embodiment of the present application can also determine whether the pipeline of the instruction is ready, thereby obtaining readiness information indicating whether the instruction is finally ready.

[0090] As an optional implementation, Figure 6 The flowchart of an optional method for determining the readiness information of an instruction is shown as an example. Figure 6 The method flow may include the following steps.

[0091] In step S61, the MBV corresponding to the instruction is read.

[0092] In step S62, it is determined whether the source operand of the instruction is ready in the current clock cycle according to the MBV. If so, step S63 is executed; if not, step S64 is executed.

[0093] MBV represents a matching vector of physical registers. MBV can have multiple bits, one bit corresponding to a physical register of the source operand of the instruction. When a physical register is written with a value, the position (bit) corresponding to the physical register in the MBV is set to the first value (the first value is, for example, 1), otherwise it is set to the second value (the second value is, for example, 0). Therefore, the embodiment of the present application can determine whether the source operand of the instruction is ready by reading the MBV corresponding to the instruction; for example, if the bit values ​​in the MBV are all 1, it means that the physical registers corresponding to the instruction are all written with values, and the source operand of the instruction is ready. The embodiment of the present application can obtain the readiness information of the source operand of the instruction; and if the bit values ​​in the MBV are partially the first value or not the first value, it means that the source operand of the instruction is partially ready (considered not ready) or not ready at all. At this time, the embodiment of the present application needs to further determine whether the source operand of the instruction is ready through the Tag comparison mechanism of step S64.

[0094] In step S63, readiness information indicating whether the source operand of the instruction is ready is determined.

[0095] In step S64, the physical register number of the source operand of the instruction is compared with the physical register number broadcast in the current clock cycle to see if they are consistent. If so, step S63 is executed; if not, step S65 is executed.

[0096] When judging that the source operand of an instruction is not ready based on MBV, an embodiment of the present application can also judge whether the source operand of the instruction is ready by comparing the physical register number of the source operand of the instruction to see whether it is consistent with the physical register number broadcast in the current clock cycle; if the physical register number of the source operand of the instruction is consistent with the physical register number broadcast in the current clock cycle, the source operand of the instruction is ready, and the embodiment of the present application can obtain the readiness information that the source operand of the instruction is ready; if the physical register number of the source operand of the instruction is inconsistent with the physical register number broadcast in the current clock cycle, it can be determined that the source operand of the instruction is not ready, and the embodiment of the present application can obtain the readiness information that the source operand of the instruction is not ready.

[0097] It should be noted that the processor can broadcast the physical register number of the current clock cycle through Tag Broadcast; specifically, when an instruction in an instruction queue (including the mobile queue and static queue in the embodiment of the present application) is selected for transmission, the processor can broadcast the physical register number of the transmitted instruction, thereby waking up subsequent instructions that depend on the physical register. Therefore, if the physical register number of the source operand of the instruction is consistent with the physical register number broadcast by the Tag in the current clock cycle, it means that the physical register number corresponding to the source operand can be relied upon, and it can be determined that the source operand of the instruction is ready.

[0098] In step S65, readiness information indicating that the source operand of the instruction is not ready is determined.

[0099] Furthermore, in addition to determining instruction readiness information through MBV and Tag broadcast, embodiments of the present application may also further combine the readiness of the pipeline corresponding to the instruction to comprehensively determine whether the instruction is ultimately ready. Of course, embodiments of the present application may also configure the instruction readiness information to only indicate the readiness of the instruction's source operands.

[0100] Back to Figure 5B As shown, in step S52, in the current clock cycle, if the source operand of the instruction in the move queue is ready and the pipeline corresponding to the instruction is ready, the instruction is determined to be a candidate instruction that meets the instruction ready condition.

[0101] In step S53, if the pipeline corresponding to the candidate instruction of the mobile queue is not occupied by the static queue, the candidate instruction is selected as the instruction to be issued in the current clock cycle and is issued.

[0102] For instructions stored in the mobile queue, if the readiness information of the instruction indicates that the source operand is ready and the pipeline corresponding to the instruction is ready, it can be determined that the instruction meets the instruction ready condition, and the instruction meeting the instruction ready condition can be used as a candidate instruction.

[0103] After determining the candidate instructions that meet the instruction ready conditions in the current clock cycle from the mobile queue, for any candidate instruction, the embodiment of the present application can determine whether the pipeline corresponding to the candidate instruction is occupied by the static queue (including the ready static queue and the not ready static queue) in the current clock cycle; if not, the candidate instruction can be directly selected as the instruction to be emitted in the current clock cycle and emitted; if so, the candidate instruction is not emitted in the current clock cycle.

[0104] In step S54, in the current clock cycle, the unissued instructions in the mobile queue are moved forward sequentially in the mobile queue with the goal of being moved to the head of the mobile queue.

[0105] For instructions in the move queue that haven't been issued in the current clock cycle, they can be moved forward sequentially within the move queue, aiming to reach the head of the queue. The method for sequentially moving instructions forward within the move queue is described previously and will not be elaborated on here.

[0106] In step S55 , if the source operand of the unissued instruction at the head of the mobile queue is ready, the instruction is added to the ready static queue.

[0107] In step S56 , if the source operand of the unissued instruction at the head of the mobile queue is not ready, the instruction is added to the unready static queue.

[0108] For instructions that are at the head of the mobile queue and have not been issued in the current clock cycle, an embodiment of the present application can add the instructions to the ready static queue or the not ready static queue based on whether the source operand of the instruction is ready; specifically, if the source operand of the instruction is ready, the instruction can be added to the ready static queue when it is added from the mobile queue to the static queue; if the source operand of the instruction is not ready, the instruction can be added to the not ready static queue.

[0109] In some embodiments, the embodiments of the present application can determine the idle entries of the ready static queue in the current clock cycle, and thus, based on the idle entries of the ready static queue in the current clock cycle, the unissued instructions at the head of the mobile queue and whose source operands are ready are sequentially added to the idle entries of the ready static queue. Further, the embodiments of the present application can determine the idle entries of the unready static queue in the current clock cycle, and thus, based on the idle entries of the unready static queue in the current clock cycle, the unissued instructions at the head of the mobile queue and whose source operands are not ready are sequentially added to the idle entries of the unready static queue. That is, in the current clock cycle, the number of instructions with ready source operands added by the mobile queue to the static queue is consistent with the number of idle entries of the ready static queue in the current clock cycle, and the number of instructions with unready source operands added by the mobile queue to the static queue is consistent with the number of idle entries of the unready static queue in the current clock cycle.

[0110] In step S57, in the current clock cycle, if the source operands of the instructions in the ready static queue and the not-ready static queue are ready, and the pipeline corresponding to the instruction is ready, the instruction is determined to be a candidate instruction that meets the instruction ready condition.

[0111] In step S58, if there are multiple candidate instructions corresponding to the same pipeline in the ready static queue and the not ready static queue, an instruction to be issued in the current clock cycle is selected from the multiple candidate instructions according to their ages and is issued.

[0112] In step S59, if there is a candidate instruction that does not correspond to the same pipeline in the ready static queue and the not-ready static queue, the candidate instruction is selected as the instruction to be issued in the current clock cycle and is issued.

[0113] For the instructions stored in the ready static queue and the not-ready static queue, the embodiment of the present application can determine the candidate instructions that meet the instruction ready condition in the current clock cycle, as well as the instructions that do not meet the instruction ready condition. For the case where the source operand of the instruction in the ready static queue is ready, if the pipeline corresponding to the instruction can receive the instruction in the current clock cycle, it is determined that the instruction meets the instruction ready condition; otherwise, the instruction does not meet the instruction ready condition. For the case where the source operand of the instruction in the not-ready static queue is not ready, if the source operand of the instruction is adjusted to ready in the current clock cycle, and the pipeline corresponding to the instruction can receive the instruction, then the instruction meets the instruction ready condition.

[0114] After determining the candidate instructions that meet the instruction ready conditions in the current clock cycle from the ready static queue and the not ready static queue, the embodiment of the present application can determine whether there are multiple candidate instructions corresponding to the same pipeline in the ready static queue and the not ready static queue (that is, determine whether multiple candidate instructions need to be emitted to the same pipeline); for candidate instructions that do not correspond to the same pipeline in the ready static queue and the not ready static queue, the candidate instruction can be directly selected as the instruction emitted in the current clock cycle and emitted; and for multiple candidate instructions corresponding to the same pipeline in the ready static queue and the not ready static queue, the embodiment of the present application can select the instruction emitted in the current clock cycle and emit it based on the age of the multiple candidate instructions, according to the principle that the older the instruction, the higher the emission priority.

[0115] Furthermore, after selecting and issuing a candidate instruction from the ready static queue, unissued instructions whose source operands are ready and whose entries are freed by instruction issuance in the ready static queue are located at the head of the mobile queue and whose source operands are ready, can be added to the ready static queue. After selecting and issuing a candidate instruction from the not-ready static queue, unissued instructions whose source operands are not ready and whose entries are freed by instruction issuance in the not-ready static queue are located at the head of the mobile queue and whose source operands are not ready can be added to the not-ready static queue.

[0116] In some further embodiments, in a manner where instructions to be emitted are selected based on the age of the instructions, the instructions added to the ready static queue and the not-ready static queue can simultaneously update the age matrix (age matrix) to mark the age information of the instructions; thus, in the current clock cycle, if a pipeline capable of receiving instructions has multiple instructions with ready source operands in the ready static queue and the not-ready static queue, the embodiments of the present application can select the instructions to be emitted with priority based on the marked instruction ages. In other words, when instructions from the mobile queue are added to the ready static queue or the not-ready static queue, the age information can be updated at the same time; then, in each clock cycle, for the instructions in the ready static queue and the not-ready static queue that meet the instruction readiness condition, the embodiments of the present application can use the age information of the instructions and select the instructions to be emitted with priority according to the principle that the age of the instructions is positively correlated with the emission priority.

[0117] In some further embodiments, for the instructions emitted in the current clock cycle selected from the mobile queue and the static queue (including the ready static queue and the not-ready static queue) in the current clock cycle, the embodiments of the present application may broadcast the physical register number of the instruction (i.e., perform tag broadcasting) so as to compare the physical register numbers (i.e., tag comparison) of the instructions whose source operands are not ready in the mobile queue and the not-ready static queue. Specifically, if the physical register number of the instruction whose source operand is not ready is consistent with the broadcast physical register number, it is determined that the original instruction whose source operand is not ready is adjusted to ready, that is, the physical register corresponding to the instruction has data ready. Furthermore, the embodiments of the present application may also update the bit value corresponding to the physical register in the MBV based on the physical register number broadcast in the current clock cycle.

[0118] It should be noted that the embodiment of the present application further divides the static queue into a ready static queue and an unready static queue, which is only an optional implementation method. The embodiment of the present application can also implement instruction storage and transmission by mixing mobile queues and static queues without further dividing the static queue, and achieve the purpose of meeting processor timing requirements and reducing power consumption. For example, the embodiment of the present application can directly add the untransmitted instructions stored at the head of the mobile queue to the static queue without having to identify whether the source operand of the instruction is ready. It should also be noted that Figure 5B The steps of the process shown are not necessarily executed in sequence, and some steps can be executed in parallel; for example, in the current clock cycle, the steps of determining the instructions that meet the instruction ready conditions in the mobile queue and the static queue (including the ready static queue and the not ready static queue) and selecting the steps of issuing the instructions can be executed in parallel.

[0119] based on Figure 5A The instruction queue structure shown and Figure 5B The instruction transmission method flow shown is an optional implementation. Figure 7 Another example diagram of implementing the processor provided in the embodiment of the present application is shown as an example. Figure 7 As shown, the processor may include: a mobile queue 310, a ready static queue 510, an unready static queue 520, an instruction ready judgment logic 410, a first data selector 710, a second data selector 720 and a broadcast logic 730. The first data selector 710 and the second data selector 720 may be Figure 4 An optional implementation of the data selector 420 is shown, for example, the data selector 420 may include a first data selector 710 and a second data selector 720 .

[0120] In an embodiment of the present application, after the instruction is fetched and decoded by the processor front end, it can enter the register renaming and related processing logic stage, after which the instruction becomes an instruction to be added to the instruction queue.

[0121] Before the instruction to be added to the instruction queue is added to the move queue 310, the instruction ready judgment logic 410 can be used to determine whether the source operand of the instruction is ready. Figure 7 As shown, the instruction readiness determination logic 410 can be configured to: before an instruction is added to the move queue 310, read the MBV corresponding to the instruction and determine whether the instruction's source operands are ready based on the MBV; if the instruction's source operands are ready, determine readiness information indicating the source operands are ready; if the instruction's source operands are not ready, compare the tag of the instruction's source operands with the tag broadcast by the broadcast logic 720 in the current clock cycle; if the comparison results are consistent, determine readiness information indicating the instruction's source operands are ready; if the comparison results are inconsistent, determine readiness information indicating the instruction's source operands are not ready. Based on the instruction's readiness information determined by the instruction readiness determination logic 410, when the instruction is added to the move queue 310, the instruction and its readiness information can be added together. Furthermore, the instruction readiness determination logic 410 can also determine whether the pipeline corresponding to the instruction is ready before the instruction is added to the move queue 310, thereby including the pipeline readiness result in the instruction's readiness information.

[0122] For instructions stored in the move queue 310, the instruction readiness determination logic 410 can determine whether the source operands of the instruction are ready and whether the pipeline corresponding to the instruction is ready in the current clock cycle. Specifically, if the instruction readiness information indicates that the source operands of the instruction are ready, the instruction readiness determination logic 410 can determine whether the pipeline corresponding to the instruction can receive the instruction; if the instruction readiness information indicates that the source operands of the instruction are not ready, the instruction readiness determination logic 410 can determine whether the source operands of the instruction are ready through MBV and Tag comparison, and at the same time determine whether the pipeline corresponding to the instruction can receive the instruction.

[0123] If the instruction ready determination logic 410 determines that the source operand of an instruction stored in the move queue is ready and the pipeline corresponding to the instruction is able to receive the instruction, the instruction becomes a candidate instruction and can wait for instruction selection processing by the first data selector 710. If the instruction ready determination logic 410 determines that the source operand of an instruction stored in the move queue is not ready and / or the pipeline corresponding to the instruction is unable to receive the instruction, the instruction does not meet the instruction ready condition. Instructions that do not meet the instruction ready condition are not emitted in the current clock cycle and, along with candidate instructions not selected by the first data selector, are moved forward sequentially in the move queue with the goal of being moved to the head of the move queue. At the same time, instructions at the head of the move queue 310 that have not been emitted in the current clock cycle can be added to the ready static queue 510 or the not ready static queue 520 based on whether the source operand is ready.

[0124] The first data selector 710 can be used to determine whether the pipeline corresponding to the candidate instruction in the mobile queue is occupied by the ready static queue 510 and the not-ready static queue 520; if the pipeline corresponding to the candidate instruction is not occupied by the ready static queue 510 and the not-ready static queue 520, the candidate instruction is selected as the instruction to be emitted in the current clock cycle and emitted; if the pipeline corresponding to the candidate instruction is occupied by the ready static queue 510 and the not-ready static queue 520, the candidate instruction is not emitted in the current clock cycle.

[0125] For the instructions stored in the ready static queue 510, the instruction ready judgment logic 410 can judge whether the pipeline corresponding to the instruction can receive the instruction in the current clock cycle; if so, the instruction becomes a candidate instruction, and the candidate instruction can wait for the instruction selection processing of the second data selector 720; if not, the instruction does not meet the instruction ready condition and remains in the entry stored in the ready static queue 510.

[0126] For the instructions stored in the not-ready static queue 520, the instruction ready judgment logic 410 can judge whether the source operand of the instruction is ready and whether the pipeline corresponding to the instruction can receive the instruction in the current clock cycle; if the judgment results are all yes, the instruction becomes a candidate instruction, and the candidate instruction can wait for the instruction selection processing of the second data selector 720; if any of the judgment results is no, the instruction does not meet the instruction ready condition and remains in the entry stored in the not-ready static queue 520.

[0127] The second data selector 720 can be used to select and transmit instructions from the candidate instructions in the ready static queue 510 and the not ready static queue 520; specifically, if there are multiple candidate instructions corresponding to the same pipeline in the ready static queue and the not ready static queue, the second data selector 720 can select and transmit the instruction to be transmitted in the current clock cycle from the multiple candidate instructions based on the ages of the multiple candidate instructions; if there are candidate instructions that do not correspond to the same pipeline in the ready static queue and the not ready static queue, the second data selector 720 can select the candidate instruction as the instruction to be transmitted in the current clock cycle and transmit it.

[0128] After selecting the instruction to be issued in the current clock cycle from the move queue, the ready static queue, and the not-ready static queue, the broadcast logic 730 broadcasts the physical register number of the instruction selected for issuance so as to compare the physical register numbers with the instructions whose source operands are not ready in the move queue and the not-ready static queue.

[0129] In some further embodiments, based on the target physical register number broadcasted by the broadcast logic 730 , the processor may update the bit value corresponding to the physical register in the MBV.

[0130] The embodiment of the present application further divides the static queue into a ready static queue and a not-ready static queue, and transfers the unissued instructions at the head of the mobile queue and whose source operands are ready to the ready static queue, and transfers the unissued instructions at the head of the mobile queue and whose source operands are not ready to the not-ready static queue; thus, when subsequently determining the instruction readiness condition of the instructions in the static queue, the embodiment of the present application no longer determines whether the source operands are ready for the instructions in the ready static queue, thereby further reducing the power consumption of instruction issuance.

[0131] Furthermore, for the unready static queue, the source operand of the instruction in the unready static queue may be unready, that is, part of the source operands of the instruction may be unready; that is, an instruction in the unready static queue may have part of its source operands ready, and another part of its source operands not ready. If all the source operands of the instruction are ready, then the source operands of the instruction are considered to be ready. Based on the ready part of the source operands of the instructions in the unready static queue, the embodiment of the present application can broadcast the physical register number of the ready part of the source operand with a set value (for example, 0) in the current clock cycle, so that when performing tag comparison on the instructions in the unready static queue, the embodiment of the present application can stop tag comparison on the ready part of the source operand, thereby further reducing the power consumption of the source operand readiness judgment.

[0132] As an optional implementation, Figure 8 The following is an example diagram of the Tag comparison process provided by the embodiment of the present application, as shown in FIG. Figure 8 As shown, for any instruction stored in the unready static queue, assuming that the instruction has not been issued and some source operands are ready, for example, the source operands of the instruction include some source operands s and some source operands m (wherein some source operands s are ready and some source operands m are not ready), then based on the partial source operands s of the instruction that are ready, the embodiment of the present application can generate a partial source operand ready signal (Src_rdy signal, Src represents the source operand) of the instruction; and in the current clock cycle, the physical register number of the partial source operand s of the instruction that is ready is broadcast with a set value, thereby realizing the closing of the tag comparison of the partial source operand s, thereby saving power consumption.

[0133] Specifically, when some source operands of an instruction are ready, the processor can generate a partial source operand ready signal (Src_rdy signal) for the instruction. On the one hand, this signal will cause the instruction ready judgment logic to stop accepting the tag comparison results corresponding to the partial source operands of the instruction that are ready, and the partial source operand ready signal will be in a continuously pulled-up state; on the other hand, it can change the tag of the partial source operands that are ready to be broadcast in the current clock cycle to a set value (for example, 0), so that the input of the instruction ready judgment logic when performing tag comparison will continue to be the set value. This is because the partial source operand ready signal is from the register, and the tag of the partial source operand that is broadcast is derived from the broadcast logic. Therefore, the source operand ready judgment logic receives the partial source operand ready signal earlier than the broadcast tag, so that the partial source operand ready signal can block the broadcast tag, so that the broadcast tag signal is pulled to the set value early in a clock cycle. In this way, when the instruction ready judgment logic performs tag comparison on the ready partial source operand, one input is stabilized to the set value, and the other input is the stable partial source operand ready signal output from the register, thereby reducing dynamic flipping of the tag comparison circuit and thus reducing power consumption.

[0134] The embodiment of the present application uses a mixture of mobile queues and static queues, and uses the mobile queue to store instructions newly added to the instruction queue, which can meet the timing requirements of the processor at the entrance of the instruction queue; on the other hand, the instructions at the head of the mobile queue and not emitted in the current clock cycle are transferred to the static queue for storage and emission, and the characteristics of the static queue can be used to reduce the dynamic power consumption during the instruction emission process. Furthermore, the static queue can be divided into a ready static queue and an unready static queue, thereby reducing the power consumption of the instructions stored in the static queue when making instruction readiness judgments. Furthermore, for instructions in the unready static queue where some source operands are ready, the embodiment of the present application can turn off the tag comparison of the ready source operands, thereby reducing the dynamic flipping of the circuit during tag comparison and further reducing power consumption. It can be seen that the embodiment of the present application can reduce the power consumption of instruction emission and improve the performance of the processor while meeting the timing requirements of the processor.

[0135] An embodiment of the present application also provides a processor, which can be configured to execute the instruction transmission method provided in the embodiment of the present application.

[0136] Furthermore, an embodiment of the present application also provides a chip, which may include the processor provided in the embodiment of the present application.

[0137] Furthermore, an embodiment of the present application also provides an electronic device (eg, a terminal device or a server device), which may include the chip provided above.

[0138] The above describes multiple embodiment schemes provided by the embodiments of the present application. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present application.

[0139] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A method for transmitting an instruction, characterized in that: include: In a current clock cycle, adding an instruction to be added to the instruction queue to a mobile queue in the instruction queue; wherein the instruction queue includes a mobile queue and a static queue, and entries in the instruction queue are divided into entries in the mobile queue and entries in the static queue, wherein one entry stores one instruction; and, in the current clock cycle, determining candidate instructions in the mobile queue and the static queue that meet the instruction ready condition; and selecting an instruction to be issued in the current clock cycle based on the candidate instructions and issuing the instruction; Furthermore, instructions in the mobile queue that have not been issued in the current clock cycle are moved forward sequentially in the mobile queue with the goal of being moved to the head of the mobile queue; and instructions that are at the head of the mobile queue and have not been issued in the current clock cycle are added to the static queue; The step of adding the instruction to be added to the instruction queue to the mobile queue in the instruction queue includes: Based on the idle entries in the mobile queue in the current clock cycle, instructions are sequentially added from the end of the mobile queue to the mobile queue. The idle entries in the mobile queue in the current clock cycle include: idle entries for instructions issued by the mobile queue in the current clock cycle, and / or idle entries for instructions transferred from the mobile queue to the static queue.

2. The method according to claim 1, characterized in that The selecting, based on the candidate instructions, an instruction to be emitted in the current clock cycle comprises: Based on the pipeline conditions corresponding to the candidate instructions, an instruction to be issued in the current clock cycle is selected from the candidate instructions.

3. The method according to claim 2, characterized in that The selecting, based on the pipeline conditions corresponding to the candidate instructions, an instruction to be emitted in the current clock cycle from the candidate instructions comprises: For any candidate instruction in the mobile queue, if the pipeline corresponding to the candidate instruction is not occupied by the static queue, the candidate instruction is selected as the instruction to be issued in the current clock cycle; For multiple candidate instructions corresponding to the same pipeline in the static queue, the instruction to be issued in the current clock cycle is selected according to the ages of the multiple candidate instructions; wherein the age of the instruction is the time when the instruction is added to the instruction queue.

4. The method according to claim 1, wherein The determining of candidate instructions in the mobile queue and the static queue that meet the instruction ready condition includes: For any instruction stored in the mobile queue and the static queue, if the source operand of the instruction is ready in the current clock cycle and the pipeline corresponding to the instruction is ready in the current clock cycle, the instruction is determined to be a candidate instruction that meets the instruction ready condition.

5. The method according to claim 1, wherein Also includes: Before adding the instruction to the move queue, determining whether a source operand of the instruction is ready in the current clock cycle, and determining readiness information of the instruction based on at least the determination result; When an instruction is added to the mobile queue, the readiness information of the instruction is also added to the mobile queue.

6. The method according to claim 5, characterized in that The step of determining whether the source operand of the instruction is ready in the current clock cycle includes: Read the matching vector MBV of the physical register corresponding to the instruction, and determine whether the source operand of the instruction is ready in the current clock cycle according to the MBV; If it is determined according to the MBV that the source operand of the instruction is not ready in the current clock cycle, the physical register number of the source operand of the instruction is compared with the physical register number broadcast in the current clock cycle to see whether they are consistent.

7. The method according to claim 6, characterized in that The MBV has a plurality of bits, each bit corresponding to a physical register of an instruction; and determining whether a source operand of the instruction is ready in a current clock cycle according to the MBV includes: If the bits corresponding to the physical register in the MBV corresponding to the instruction are all the first value, it is determined that the source operand of the instruction is ready; If the bits corresponding to all physical registers in the MBV corresponding to the instruction are not the first value, or the bits corresponding to some physical registers are the first value, it is determined that the source operand of the instruction is not ready.

8. The method according to claim 1, characterized in that Also includes: For the instruction issued in the current clock cycle, the physical register number of the instruction is broadcasted so as to compare the physical register numbers of the instructions whose source operands are not ready in the mobile queue and the static queue.

9. The method according to any one of claims 1 to 8, characterized in that The static queue includes a ready static queue and an unready static queue; The step of adding the instruction at the head of the mobile queue and not issued in the current clock cycle to the static queue includes: In the current clock cycle, adding the unissued instruction at the head of the mobile queue and with ready source operands to the ready static queue; Furthermore, the unissued instruction at the head of the mobile queue and whose source operand is not ready is added to the unready static queue.

10. The method according to claim 9, characterized in that The step of adding the unissued instruction at the head of the mobile queue and with ready source operands to the ready static queue comprises: Based on the idle entries of the ready static queue in the current clock cycle, the unissued instructions at the head of the mobile queue and with ready source operands are sequentially added to the idle entries of the ready static queue; The step of adding the unissued instruction at the head of the mobile queue and having a source operand that is not ready to be issued to the unready static queue comprises: Based on the idle entries of the not-ready static queue in the current clock cycle, the unissued instructions at the head of the mobile queue and whose source operands are not ready are sequentially added to the idle entries of the not-ready static queue.

11. The method according to claim 9, characterized in that If multiple candidate instructions in the ready static queue and the not-ready static queue correspond to the same pipeline, the instruction to be issued in the current clock cycle is selected according to the ages of the multiple candidate instructions.

12. The method according to claim 9, characterized in that Also includes: For any instruction stored in the unready static queue, if part of the source operands of the instruction are ready, a part of the source operands of the instruction are ready signal is generated based on the part of the source operands that are ready for the instruction; and the physical register number of the part of the source operands that are ready for the instruction is broadcast with a set value.

13. A processor, characterized in that: include: An instruction queue, an instruction ready judgment logic, and a data selector; wherein the instruction queue includes a mobile queue and a static queue, and entries of the instruction queue are divided into entries of the mobile queue and entries of the static queue, and one entry stores one instruction; The instruction ready judgment logic is used to determine the candidate instructions that meet the instruction ready condition in the mobile queue and the static queue in the current clock cycle; The data selector is configured to select and transmit an instruction to be transmitted in the current clock cycle based on the candidate instructions; Among them, the instructions to be added to the instruction queue in the current clock cycle are first added to the mobile queue; the instructions in the mobile queue that have not been issued in the current clock cycle are moved forward in sequence in the mobile queue with the goal of moving to the head of the mobile queue; and the instructions that are at the head of the mobile queue and have not been issued in the current clock cycle are added to the static queue; the instructions to be added to the instruction queue are added to the mobile queue, including: based on the idle entries of the mobile queue in the current clock cycle, the instructions are added to the mobile queue from the tail of the mobile queue in sequence; wherein, the idle entries of the mobile queue in the current clock cycle include: in the current clock cycle, the idle entries of the mobile queue for issuing instructions, and / or, the idle entries of the mobile queue for instructions transferred to the static queue.

14. The processor according to claim 13, wherein: The instruction readiness judgment logic includes: source operand readiness judgment logic and pipeline readiness judgment logic; The source operand ready judgment logic is used to judge whether the source operand of the instruction is ready in the current clock cycle; The pipeline readiness judgment logic is used to judge whether the pipeline corresponding to the instruction is ready in the current clock cycle; Among them, if the source operand corresponding to the instruction is ready in the current clock cycle, and the pipeline corresponding to the instruction is ready in the current clock cycle, then the instruction meets the instruction ready condition.

15. The processor according to claim 13, wherein: Also includes: The broadcast logic is used to broadcast the physical register number of the instruction for the instruction issued in the current clock cycle, so as to compare the physical register numbers of the instructions whose source operands are not ready in the mobile queue and the static queue.

16. The processor according to any one of claims 13 to 15, characterized in that: The static queue includes a ready static queue and a not-ready static queue; among them, the instructions that are located at the head of the mobile queue and whose source operands are ready but not issued in the current clock cycle are added to the ready static queue; the instructions that are located at the head of the mobile queue and whose source operands are not ready but not issued in the current clock cycle are added to the not-ready static queue.

17. The processor according to claim 16, wherein: The data selector includes a first data selector and a second data selector; The first data selector is configured to select any candidate instruction in the mobile queue as the instruction to be issued in the current clock cycle and issue the candidate instruction if the pipeline corresponding to the candidate instruction is not occupied by the static queue; The second data selector is used to select and transmit the instruction to be transmitted in the current clock cycle according to the ages of multiple candidate instructions corresponding to the same pipeline in the ready static queue and the not ready static queue; wherein the age of the instruction is the time when the instruction is added to the instruction queue.

18. The processor according to claim 16, wherein: For any instruction stored in the unready static queue, if part of the source operands of the instruction are ready, the processor generates a partial source operand ready signal of the instruction based on the partial source operands that are ready for the instruction; and broadcasts the physical register number of the partial source operand that is ready for the instruction with a set value.

19. A processor, characterized in that: The processor is configured to execute the instruction transmitting method according to any one of claims 1 to 12.

20. A chip, characterized in that: The chip includes the processor according to any one of claims 13 to 18, or the processor according to claim 19.

21. An electronic device, characterized in that: The electronic device comprises the chip according to claim 20.

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