A digital integrating pixel circuit for photodetectors

Abstract

The present invention discloses a photodetector digital integration pixel circuit, specifically a digital integration charge-to-digital conversion circuit that increases charge storage capacity and improves linearity. The circuit comprises a photodetector, an injection tube, an integration capacitor, a reset switch, a comparator, a monostable circuit, a counter, a control signal generating circuit, a charge storage switch, a charge transfer switch, and a unit charge storage capacitor. By using a unit charge storage capacitor and two switches connected thereto, when current integration triggers comparator flipping, the unit charge Qo is used to replenish the charge discharged from the integration capacitor, replacing the traditional digital integration method of resetting voltage. This avoids the influence of the comparator's decision voltage and delay time, and improves the linearity of the charge-to-digital conversion.

Description

Technical Field

[0001] The present invention belongs to the field of electronic circuits and relates to a digital integrating pixel circuit for a photoelectric detector. The present invention is suitable for use in readout circuits including photoelectric detectors such as CMOS image sensors, infrared detectors, and capacitive sensors. Background Art

[0002] In photodetectors such as image sensors and infrared detectors, the pixels of the readout circuit are interconnected with the photodetector units in a one-to-one correspondence. Its main task is to extract, amplify, integrate and convert the photocurrent generated by the detector into a voltage signal for output. The working principle of the pixel circuit is that the signal current I p The integrating capacitor C int On the integral, after a certain integration time T int , the voltage across the capacitor V int Output through multiple switches, the charge stored in the capacitor is Q , is given by:

[0003] (1)

[0004] After integration by the pixel circuit, the signal accumulates linearly, while the noise accumulates as RMS. The signal-to-noise ratio of the output signal is proportional to the square root of the integration time. Increasing the integration time can improve the signal-to-noise ratio and dynamic range of the detector output signal. However, the extension of the integration time is limited by the charge storage capacity Qmax of the readout circuit pixel, which is given by the following formula:

[0005] (2)

[0006] The maximum output voltage of the pixel circuit V int_max is limited by the supply voltage, so the charge storage capacity Q max The capacity of the integrating capacitor is the main limitation, that is, the dynamic range of the readout circuit is limited by the capacity of the integrating capacitor. To increase the integration time of the detector output photocurrent, the capacity of the integrating capacitor must be increased.

[0007] Because the integrating capacitor must be integrated within the area of ​​each pixel, the unit capacitance of the capacitor that can be integrated under current silicon CMOS process conditions is several femtofarads per square micron. Assuming a pixel area of ​​20μm × 20μm, the maximum capacitance that can be integrated within the pixel is only 2pF. Assuming an integrating capacitor of 2pF and a power supply voltage of 3.3V, the charge storage capacity of the pixel circuit is approximately 41Me-. At a maximum output voltage of 3.3V and a photocurrent of 10nA, the maximum integration time is:

[0008] (3)

[0009] If the photodetector's dark current and background current are taken into account, the maximum integration time is even shorter. Compared to the 20ms frame time of a typical image sensor or infrared detector, less than 4% of this time is dedicated to photocurrent integration, with the rest being unused, limiting further improvements in photodetector performance.

[0010] As the number of detector pixels continues to increase, the pixel size continues to shrink, and the integral capacitance integrated in the pixel continues to decrease, resulting in the charge storage capacity limitation of the readout circuit becoming one of the most important factors affecting the performance of the photodetector.

[0011] In order to break through the charge storage capacity limitation of pixel circuits, the literature [1] uses digital integration technology to increase the charge storage capacity. Its working principle is that the integral capacitor C int The voltage V int Every time the comparator threshold voltage V th When the voltage reaches 0, the circuit automatically resets, clearing the charge on the integrating capacitor and incrementing the counter by 1. This process is repeated multiple times within the integration time. Digital integration technology changes the measurement of the absolute value of the single-integrated voltage on the capacitor to a count of multiple integration times, N. This avoids the limitations of the integrating capacitor and voltage on a single integration, and increases the equivalent charge storage capacity by N times.

[0012] (4)

[0013] Because the integration time is extended, digital integration technology improves the signal-to-noise ratio and dynamic range of the detector output signal. At the same time, the output value N is a quantized result of the photocurrent, so digital integration technology also completes the conversion of charge into digital signal.

[0014] Another commonly used pixel circuit uses a capacitive transimpedance amplifier (CTIA) to improve the signal-to-noise ratio and linearity. However, this comes at the cost of adding an amplifier to each pixel. This not only occupies the limited pixel area, resulting in a reduction in the integral capacitance, but also significantly increases the power consumption of the readout circuit.

[0015] The above-mentioned pixel circuit for integrating the photodetector and measuring its photocurrent can be extended to a charge-to-digital conversion circuit for measuring current. The only difference is that the device under test is changed from a photodetector to other devices that generate the current to be measured. Its integration and charge-to-digital conversion also have problems with dynamic range and signal-to-noise ratio.

[0016] In addition, capacitive sensors also require a similar readout circuit to complete charge-to-digital conversion, except that the object of measurement is changed from current to capacitance. By simply replacing the photodetector of the pixel circuit with a current source that provides a fixed current, the measured capacitance can be integrated and quantified. Its dynamic range and signal-to-noise ratio are also important performance features that need to be improved.

[0017] Although digital integration technology can increase the charge storage capacity of the pixel circuit, since it uses a voltage reset method, the delay time of the comparator circuit will cause integral nonlinearity.

[0018] Ideally, each count represents a unit charge of

[0019] (5)

[0020] Where V rst is the reset voltage, V th is the comparator threshold voltage. The pixel output count value is

[0021] (6)

[0022] Count value N and photocurrent I p It is linearly proportional and can quantify the photocurrent generated by the detector.

[0023] However, due to the inevitable delay time T of the comparator d , during this period the photocurrent is still discharging, resulting in the effective unit charge becoming

[0024] (7)

[0025] The actual integrated voltage change is determined by V rst -V th becomes

[0026] (8)

[0027] So the actual output count value is

[0028] (9)

[0029] Comparator delay T d A nonlinear term I is introduced into the denominator of the count value expression p T d , that is, the count value N is no longer related to the photocurrent I p The linear proportional relationship causes the output of the photodetector to become a nonlinear response affected by the input signal, which affects the performance of the photodetector and brings difficulties to the design and processing of the imaging system.

[0030] References [1] Sylvette Bisottoa, et al. "A 25μm pitch LWIR staringfocal plane array with pixel-level 15-bit ADC ROIC achieving 2mK NETD". Proceding of SPIE, 2010, 7834: 78340J. Summary of the Invention

[0031] The present invention aims to provide a digital integration pixel circuit for a photodetector, particularly a digital integration charge-to-digital conversion circuit that increases charge storage capacity and improves linearity. The circuit employs digital integration technology to overcome the limited charge storage capacity problem of conventional analog integration, while also addressing the nonlinear output response defect of existing digital integration technology with a voltage reset structure. This improves the signal-to-noise ratio and dynamic range of charge-to-digital conversion while ensuring output linearity, thereby enhancing the performance of photodetectors, current measurement sensors, and capacitance measurement sensors.

[0032] The overall concept of the present invention includes:

[0033] (1) Using a unit charge storage capacitor Co and two switches connected to it, when the current integration triggers the comparator flip, the unit charge Qo is used to supplement the discharged charge on the integration capacitor, replacing the traditional digital integration method of voltage reset, avoiding the influence of the comparator judgment voltage and delay time, and improving the linearity of charge-to-digital conversion.

[0034] (2) The switch control signals S1 and S2 that control the unit charge storage capacitor or the measured capacitor Co to store and transfer charge have non-overlapping effective levels to avoid errors caused by charge leakage.

[0035] (3) The control signal generation circuit and the input of the counter are generated by a monostable circuit. The characteristic is that each time the comparator output flips during each integration process, only one pulse Vp is generated, and its effective level width is determined by the monostable circuit and is not affected by other circuits such as the comparator. The purpose is to avoid the generation of multiple erroneous pulses during a single integration process due to interference from non-ideal factors such as the power supply voltage, which may cause miscounting of the counter and erroneous operation of unit capacitance storage and transfer.

[0036] (4) The present invention is not only aimed at Figure 1 and Figure 2 The integral of the current Ip discharging the integral capacitor shown is also applicable to the integral of the current Ip charging the integral capacitor.

[0037] The technical solution adopted by the present invention to achieve the above-mentioned purpose is:

[0038] First, the present invention provides a digital integration charge-to-digital conversion circuit for measuring current, which is composed of an injection tube, an integration capacitor, a reset switch, a comparator, a monostable circuit, a counter, a control signal generating circuit, a charge storage switch, a charge transfer switch, and a unit charge storage capacitor, wherein:

[0039] One end of the injection tube is connected to a device that generates a measured current, and the other end is connected to the upper plate of the integrating capacitor and an input end of a comparator; the lower plate of the integrating capacitor is connected to a common voltage Vcom; the other input end of the comparator is connected to a judgment voltage Vth, and the output end is connected to the input of a monostable circuit, and the output of the monostable circuit is connected to the input of a counter and an input of a control signal generating circuit; a first output signal S1 of the control signal generating circuit controls a charge storage switch, and a second output signal S2 controls a charge transfer switch; one plate of the unit charge storage capacitor is connected to the charge storage switch and the charge transfer switch, and the other plate is connected to a reference voltage Vref; the other end of the charge storage switch is connected to a reset voltage Vrst; the other end of the charge transfer switch is connected to the upper plate of the integrating capacitor; one end of the reset switch is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor.

[0040] Furthermore, the current-to-digital integral conversion is completed through the timing relationship of the RST, Vp, S1, and S2 signals, where:

[0041] The voltage VB provides appropriate bias conditions for the device that generates the measured current through the injection tube; first, the reset signal RST is valid, the reset switch is turned on, the voltage Vint on the integration capacitor Cint is reset to Vrst, and the counter is reset at the same time; then the reset signal RST is invalid, the reset switch is turned off, and integration begins, that is, the measured current Ip discharges the charge on the integration capacitor Cint. When the integration voltage Vint drops below the comparator judgment voltage Vth, the comparator output Vout flips, and a pulse signal Vp is generated through the monostable circuit, and the counter output Do is increased by 1; the pulse signal Vp is generated through the control signal generating circuit to generate two control signals S1 and S2, where S1 controls the charge storage switch and S2 controls the charge transfer switch; during the reset and integration period of the integration capacitor Cint, S1 is valid, the charge storage switch is closed, and the unit charge storage capacitor Co is connected to the reset voltage Vrst, thereby The unit charge Qo is stored on the charge storage capacitor Co. During this period, S2 is invalid and the charge transfer switch is disconnected. When the pulse signal Vp output by the monostable circuit is valid, S1 is invalid and the charge storage switch is disconnected. After a certain time interval, S2 is valid, the charge transfer switch is closed, and the unit charge Qo is transferred to the integration capacitor Cint. The voltage Vint on the capacitor is restored to a level higher than the judgment level Vth, so that the comparator output is restored. After the pulse signal Vp is invalid, a new integration begins, that is, the measured current Ip discharges the integration capacitor Cint again. After a certain time interval, S1 is valid, the charge storage switch is closed, and the unit charge storage capacitor Co is connected to the reset voltage Vrst. The above-mentioned process of integration and unit charge storage, transfer and integration voltage recovery is repeated until it stops at the specified integration time Tint. The value N of the counter output Do is the quantized result of the measured current Ip.

[0042] Secondly, the present invention also provides a digital integral charge-to-digital conversion circuit for measuring capacitance, which is composed of a current source, an integral capacitor, a reset switch, a comparator, a monostable circuit, a counter, a control signal generating circuit, a charge storage switch, and a charge transfer switch, wherein:

[0043] The upper plate of the integrating capacitor is connected to the current source and an input end of the comparator, and the lower plate of the integrating capacitor is connected to the common voltage Vcom; the other input end of the comparator is connected to the judgment voltage Vth, and the output end is connected to the input of the monostable circuit, and the output of the monostable circuit is connected to the input of the counter and the input of the control signal generating circuit; the first output signal S1 of the control signal generating circuit controls the charge storage switch, and the second output signal S2 controls the charge transfer switch; one plate of the measured capacitor is connected to the charge storage switch and the charge transfer switch, and the other plate is connected to the reference voltage Vref; the other end of the charge storage switch is connected to the reset voltage Vrst; the other end of the charge transfer switch is connected to the upper plate of the integrating capacitor; one end of the reset switch is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor.

[0044] Furthermore, the capacitance-to-digital integral conversion is completed through the timing relationship of the RST, Vp, S1, and S2 signals, where:

[0045] First, the reset signal RST is valid, the reset switch is turned on, the voltage on the integrating capacitor Cint is reset to Vrst, and the counter is reset at the same time; then the reset signal RST is invalid, the reset switch is turned off, and integration begins, that is, the current Ip of the current source discharges the charge on the integrating capacitor. When the integrated voltage Vint drops below the comparator judgment voltage Vth, the comparator output Vout flips, and a pulse signal Vp is generated through the monostable circuit, and the counter output Do is increased by 1; the pulse signal Vp is generated through the control signal generating circuit to generate two control signals S1 and S2, where S1 controls the charge storage switch and S2 controls the charge transfer switch; during the reset and integration period of the integrating capacitor Cint, S1 is valid, the charge storage switch is closed, and the measured capacitor Co is connected to the reset voltage Vrst, so that the unit charge Qo is stored in the measured capacitor Co, during this period S2 is invalid, and the charge transfer switch is disconnected; when the monostable circuit output pulse signal Vp is valid, S1 is invalid, and the charge storage switch is disconnected. After a certain time interval, S2 is valid, and the charge transfer switch is closed, and the unit charge Qo is transferred to the integration capacitor Cint. The voltage on the capacitor is restored to be higher than the judgment level Vth, so that the comparator output is restored; after the pulse signal Vp is invalid, a new integration starts, that is, the current Ip discharges the integration capacitor Cint again; after a certain time interval, S1 is valid, and the charge storage switch is closed, connecting the measured capacitor Co to the reset voltage Vrst; the above-mentioned integration and unit charge storage, transfer and integration voltage recovery process are repeated until it stops at the specified integration time Tint. The value N of the counter output Do is the quantized result of the measured capacitor Co.

[0046] The ultimate goal of the present invention is to provide a photodetector digital integration pixel circuit, which is composed of a photodetector, an injection tube, an integration capacitor, a reset switch, a comparator, a monostable circuit, a counter, a clock generation circuit, a charge storage switch, a charge transfer switch and a unit charge storage capacitor.

[0047] One end of the injection tube is connected to the photodetector, and the other end is connected to the upper plate of the integrating capacitor and an input end of the comparator; the other input end of the comparator is connected to the judgment voltage Vth, and the output end is connected to the input of the monostable circuit, and the output of the monostable circuit is connected to the input of the counter and the input of the clock generation circuit; the first output signal S1 of the clock generation circuit controls the charge storage switch, and the second output signal S2 controls the charge transfer switch; one plate of the unit charge storage capacitor is connected to the charge storage switch and the charge transfer switch, and the other plate is connected to the reference voltage Vref; the other end of the charge storage switch is connected to the reset voltage Vrst; the other end of the charge transfer switch is connected to the upper plate of the integrating capacitor; one end of the reset switch is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor.

[0048] The principle of the present invention is:

[0049] The principle of the present invention is explained by taking the integration process of the measured current (or current source current) Ip to the discharge of the integration capacitor as an example. All control signals are high level valid. The working timing of the relevant signals is shown in Figure 2 .

[0050] During the reset phase, when RST is valid, the integrating capacitor Cint is connected to the reset voltage Vrst, and the voltage on the capacitor Vint = Vrst. Since Vint is greater than the comparator judgment voltage Vth, the comparator output Vout is low, the monostable circuit output Vp is low, and the counter output is reset to 0. During the reset period, the output signal S1 of the control signal generating circuit is valid and S2 is invalid, that is, the unit charge storage capacitor (or the measured capacitor) Co is connected to Vrst through the charge storage switch, allowing it to store charge:

[0051] (10)

[0052] After the reset signal RST is deactivated, current Ip discharges the integrating capacitor Cint until its voltage Vint falls below Vth, causing the comparator output Vout to increase, triggering the monostable circuit output Vp to increase. This pulse persists for a certain period, forming a narrow pulse and incrementing the counter's count by 1. Vp's high level triggers the control signal generation circuit's output signal S1 to become deactivated, disconnecting capacitor Co from the reset voltage Vrst. After a certain time interval, S2 becomes active, transferring the charge Qo on capacitor Co to integrating capacitor Cint, restoring the voltage Vint to a value above Vth. S2 is then deactivated, disconnecting capacitor Co from integrating capacitor Cint, and current Ip begins a new integration of integrating capacitor Cint. After a certain time interval, S1 becomes active, connecting capacitor Co to Vrst, and re-storing the charge Qo on capacitor Co.

[0053] In order to prevent errors caused by charge leakage on the capacitor Co, the outputs S1 and S2 of the control signal generating circuit cannot be valid at the same time, that is, there must be a certain time interval between their high levels to form non-overlapping valid levels.

[0054] The above process of integration, charge storage Qo, and charge transfer Qo is repeated until the specified integration time Tint. The counter counts the number of pulses Vp and obtains the value N:

[0055] (11)

[0056] Since the unit charge Qo is determined by the capacitor Co, the reset voltage Vrst, and the reference voltage Vref, and is not affected by the comparator decision voltage Vth and the delay time Td, the count value N is linearly proportional to the current Ip and linearly inversely proportional to the capacitor Co. Therefore, the count value N can linearly quantize the current Ip or the capacitance Co to achieve charge-to-digital conversion.

[0057] The total charge storage capacity is

[0058] (12)

[0059] Since the charge storage capacity is increased N times from Qo, the integration time is extended, which can improve the dynamic range and signal-to-noise ratio.

[0060] The present invention is also applicable to the integration process of the current Ip charging the integration capacitor. The same function can be achieved to measure the current Ip or capacitance Co by simply setting the Vrst voltage value lower than Vref and Vcom, changing the polarity of the input signal that triggers the monostable circuit to output Vp from a low level to a high level, or inserting an inverter between the comparator and the monostable circuit to invert the signal.

[0061] According to the specific circuit implementation requirements, the circuit of the present invention can be configured so that the control signal is valid at a low level. The connection method of the upper and lower plates of the relevant capacitors can also be adjusted according to the actual circuit requirements.

[0062] The beneficial effects of the present invention are:

[0063] The existing voltage reset digital integration circuit is a voltage reset operation, so the unit charge counted each time (Formula (7)) is affected by the comparator judgment voltage Vth and delay time Td, resulting in a nonlinear relationship between the count value (i.e., Formula (9)) and the current to be measured. The technical solution provided by the present invention improves the charge storage capacity to obtain dynamic range and signal-to-noise ratio while adopting charge storage and transfer operations to avoid the nonlinearity introduced by non-ideal factors such as comparators in voltage operations. The output result can linearly convert the current or capacitance into a digital value, reducing the requirements for comparator circuit design. That is, high-quality charge quantization can be achieved without a low delay time and high-precision comparator, thereby reducing the power consumption and area of ​​the charge-to-digital conversion circuit. At the same time, since the output result is a linear conversion of current or capacitance, there is no need for complex subsequent circuit processing to improve the linearity of current or capacitance measurement, reducing the design complexity of the entire sensor system. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 This is a schematic diagram of the digital integral charge-to-digital conversion circuit for measuring current according to the present invention; Figure 1 middle:

[0065] 300 - Digital integration charge-to-digital conversion circuit for measuring current, 301 - Device for generating measured current, 302 - Injection tube, 303 - Integrating capacitor, 304 - Reset switch, 305 - Comparator, 306 - Monostable circuit, 307 - Counter, 308 - Control signal generating circuit, 309 - Charge storage switch, 310 - Charge transfer switch, 311 - Unit charge storage capacitor.

[0066] Figure 2 This is a signal diagram of the digital integration charge-to-digital conversion circuit for measuring current or capacitance according to the present invention.

[0067] Figure 3 This is a schematic diagram of the digital integral charge-to-digital conversion circuit for measuring capacitance according to the present invention. Figure 3 middle:

[0068] 500 - digital integration charge-to-digital conversion circuit for measuring capacitance, 501 - measured capacitance, 502 - current source, 503 - integrating capacitor, 504 - reset switch, 505 - comparator, 506 - monostable circuit, 507 - counter, 508 - control signal generating circuit, 509 - charge storage switch, 510 - charge transfer switch.

[0069] Figure 4 This is a schematic diagram of the digital pixel circuit of the photodetector according to the present invention. Figure 4 middle:

[0070] 600-photodetector digital pixel circuit, 601-photodetector, 602-injection tube, 603-integrating capacitor, 604-reset switch, 605-comparator, 606-monostable circuit, 607-counter, 608-clock generation circuit, 609-charge storage switch, 610-charge transfer switch, 611-unit charge storage capacitor. DETAILED DESCRIPTION

[0071] The present invention will be further described in detail below through embodiments in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following embodiments. Example 1

[0072] like Figure 1 As shown, a digital integration charge-to-digital conversion circuit 300 for measuring current is composed of an injection tube 302, an integration capacitor 303, a reset switch 304, a comparator 305, a monostable circuit 306, a counter 307, a control signal generating circuit 308, a charge storage switch 309, a charge transfer switch 310, and a unit charge storage capacitor 311, wherein:

[0073] One end of the injection tube 302 is connected to the device 301 that generates the measured current, and the other end is connected to the upper plate of the integrating capacitor 303 and an input end of the comparator 305; the lower plate of the integrating capacitor 303 is connected to the common voltage Vcom; the other input end of the comparator 305 is connected to the judgment voltage Vth, and the output end is connected to the input of the monostable circuit 306, and the output of the monostable circuit 306 is connected to the input of the counter 307 and the input of the control signal generating circuit 308; the first output signal S1 of the control signal generating circuit 308 controls the charge storage switch 309, and the second output signal S2 controls the charge transfer switch 310; one plate of the unit charge storage capacitor 311 is connected to the charge storage switch 309 and the charge transfer switch 310, and the other plate is connected to the reference voltage Vref; the other end of the charge storage switch 309 is connected to the reset voltage Vrst; the other end of the charge transfer switch 310 is connected to the upper plate of the integrating capacitor 303; one end of the reset switch 304 is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor 303.

[0074] The function of the comparator 305 is to compare the input voltage with the judgment voltage Vth. If the input voltage is higher than the judgment voltage, the comparator 305 outputs a high level. If the input voltage is lower than the judgment voltage, the comparator 305 outputs a low level. The monostable circuit 306 is used to generate a pulse with a certain width when the output of the comparator 305 flips, to avoid power supply interference, noise, etc. from falsely triggering multiple pulses. The counter 307 and the control signal generating circuit 308 are both digital circuits. The former realizes counting accumulation, and the latter generates Figure 2 Non-overlapping control signals S1 and S2 are shown.

[0075] Further, refer to Figure 2 , the current-to-digital integral conversion is completed through the timing relationship of signals such as RST, Vp, S1, and S2, where:

[0076] The voltage VB provides a suitable bias condition for the device 301 generating the measured current through the injection tube 302. First, the reset signal RST is valid, the reset switch 304 is opened, and the voltage Vint on the integrating capacitor 303 is reset to Vrst, and the counter 307 is reset at the same time. Then the reset signal RST is invalid, the reset switch 304 is turned off, and integration begins. That is, the measured current Ip discharges the charge on the integrating capacitor 303. When the integrated voltage Vint drops below the judgment voltage Vth of the comparator 305, the comparator output Vout flips, and a pulse signal Vp is generated through the monostable circuit 306. The counter 307 outputs Do plus 1. The pulse signal Vp is generated by the control signal generating circuit 308. Two control signals S1 and S2 are generated, where S1 controls the charge storage switch 309 and S2 controls the charge transfer switch 310. During the reset and integration period of the integrating capacitor 303, S1 is valid, closing the charge storage switch 309, connecting the unit charge storage capacitor Co 311 to the reset voltage Vrst, so that the unit charge Qo is stored in the capacitor Co. 311, during this period S2 is invalid, and the charge transfer switch 310 is disconnected; when the pulse signal Vp output by the monostable circuit 306 is valid, S1 is invalid, and the charge storage switch 309 is disconnected. After a certain time interval, S2 is valid, and the charge transfer switch 310 is closed, and the unit charge Qo is transferred to the integration capacitor Cint 303. The voltage Vint on the capacitor is restored to be higher than the judgment level Vth, so that the output of the comparator 305 is restored; after the pulse signal Vp is invalid, a new integration begins, that is, the measured current Ip discharges the integration capacitor Cint again; after a certain time interval, S1 is valid, and the charge storage switch 309 is closed, and the unit charge storage capacitor Co 311 is connected to the reset voltage Vrst; the above-mentioned integration and unit charge storage, transfer and integration voltage recovery process are repeated until it stops at the specified integration time Tint. The value N of Do output by the counter 307 is the quantized result of the measured current Ip. Example 2

[0077] like Figure 3 As shown, a digital integration charge-to-digital conversion circuit 500 for measuring capacitance is composed of a current source 502, an integrating capacitor 503, a reset switch 504, a comparator 505, a monostable circuit 506, a counter 507, a control signal generating circuit 508, a charge storage switch 509, and a charge transfer switch 510, wherein:

[0078] The upper plate of the integrating capacitor 503 is connected to the current source 502 and an input terminal of the comparator 505, and the lower plate of the integrating capacitor 503 is connected to the common voltage Vcom; the other input terminal of the comparator 505 is connected to the judgment voltage Vth, and the output terminal is connected to the input of the monostable circuit 506, and the output of the monostable circuit 506 is connected to the input of the counter 507 and the input of the control signal generating circuit 508; the first output signal S1 of the control signal generating circuit 508 controls the charge storage switch 509, and the second output signal S2 controls the charge transfer switch 510; one plate of the measured capacitor 501 is connected to the charge storage switch 509 and the charge transfer switch 510, and the other plate is connected to the reference voltage Vref; the other end of the charge storage switch 509 is connected to the reset voltage Vrst; the other end of the charge transfer switch 510 is connected to the upper plate of the integrating capacitor 503; one end of the reset switch 504 is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor 503.

[0079] Further, refer to Figure 2 , the capacitance-to-digital integral conversion is completed through the timing relationship of signals such as RST, Vp, S1, and S2, where:

[0080] First, the reset signal RST is valid, and the reset switch 504 is turned on, so that the voltage on the integrating capacitor 503 is reset to Vrst, and the counter 507 is reset at the same time; then the reset signal RST is invalid, and the reset switch 504 is turned off, and integration begins, that is, the current Ip of the current source discharges the charge on the integrating capacitor 503. When the integrated voltage Vint drops below the judgment voltage Vth of the comparator 505, the comparator output Vout flips, and a pulse signal Vp is generated through the monostable circuit 506, and the counter 507 output Do is increased by 1; the pulse signal Vp is generated through the control signal generating circuit 508 to generate two control signals S1 and S2, where S1 controls the charge storage switch 509, and S2 controls the charge transfer switch 510. During the reset and integration period of the integrating capacitor Cint503, S1 is valid, closing the charge storage switch 509 and connecting the measured capacitor Co501 to the reset voltage Vrst, thereby storing the unit charge Qo on the measured capacitor Co501. During this period, S2 is invalid, and the charge transfer switch 510 is disconnected. When the output pulse signal Vp of the monostable circuit 506 is valid, S1 is invalid, disconnecting the charge storage switch 509. After a certain time interval, S2 is valid, closing the charge transfer switch 510, and transferring the unit charge Qo to the integrating capacitor Cint. 503, the voltage on the capacitor recovers to be higher than the judgment level Vth, so that the output of the comparator 505 is restored; a new integration starts after the pulse signal Vp is invalid, that is, the current Ip discharges the integration capacitor Cint again; after a certain time interval, S1 is valid, and the charge storage switch 509 is closed, connecting the measured capacitor Co 501 to the reset voltage Vrst; repeat the above-mentioned integration and unit charge storage, transfer and integration voltage recovery process until it stops at the specified integration time Tint, and the value N of Do output by the counter 507 is the quantized result of the measured capacitor Co. Example 3

[0081] like Figure 4 As shown, a photodetector digital pixel circuit 600 is composed of a photodetector 601, an injection tube 602, an integrating capacitor 603, a reset switch 604, a comparator 605, a monostable circuit 606, a counter 607, a clock generation circuit 608, a charge storage switch 609, a charge transfer switch 610 and a unit charge storage capacitor 611.

[0082] One end of the injection tube 602 is connected to the photodetector 601, and the other end is connected to the upper plate of the integrating capacitor 603 and an input end of the comparator 605; the other input end of the comparator 605 is connected to the judgment voltage Vth, and the output end is connected to the input of the monostable circuit 606, and the output of the monostable circuit 606 is connected to the input of the counter 607 and the input of the clock generation circuit 608; the first output signal S1 of the clock generation circuit 608 controls the charge storage switch 609, and the second output signal S2 controls the charge transfer switch 610; one plate of the unit charge storage capacitor 611 is connected to the charge storage switch 609 and the charge transfer switch 610, and the other plate is connected to the reference voltage Vref; the other end of the charge storage switch 609 is connected to the reset voltage Vrst; the other end of the charge transfer switch 610 is connected to the upper plate of the integrating capacitor 603; one end of the reset switch 604 is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor 603.

[0083] Further, refer to Figure 2 This embodiment completes digital integration and measures the current generated by the detector through the timing relationship of the following signals, and converts and outputs digital values:

[0084] The voltage VB provides a suitable bias condition for the photodetector 601 through the injection tube 602. First, the reset signal RST is valid, and the reset switch 604 is turned on, so that the voltage on the integration capacitor 603 is reset to Vrst, and the counter 607 is reset at the same time. Then the reset signal RST is invalid, and the reset switch 604 is turned off, and integration begins. That is, the current Ip generated by the detector 601 discharges the charge on the integration capacitor 603. When the integrated voltage Vint drops below the judgment voltage Vth of the comparator 605, the comparator output Vout flips, and the counter 607 is reset. The monostable circuit 606 generates a pulse signal Vp, and the counter 607 outputs Do plus 1; the pulse signal Vp passes through the control signal generating circuit 608 to generate two control signals S1 and S2, where S1 controls the charge storage switch 609 and S2 controls the charge transfer switch 610; during the reset and integration period of the integrating capacitor 603, S1 closes the charge storage switch 609, connects the unit charge storage capacitor 611 to the reset voltage Vrst, and stores the unit charge Qo on the capacitor 611. During this period, S2 opens the charge transfer switch 610. The unit charge Qo is

[0085] (13)

[0086] When the pulse signal Vp output by the monostable circuit 606 is valid, S1 disconnects the charge storage switch 609. After a certain time interval, the S2 signal closes the charge transfer switch 610, transferring the unit charge Qo to the integration capacitor 603. The voltage on the capacitor recovers to a level higher than the decision level Vth, causing the output of the comparator 605 to recover. A new integration begins after the pulse signal Vp becomes invalid. After a certain time interval, S1 closes the charge storage switch 609, connecting the unit charge storage capacitor 611 to the reset voltage Vrst. The above integration, unit charge storage, transfer, and voltage recovery processes are repeated until the specified integration time Tint is reached. The value N of the Do output by the counter 607 is the quantized result of the detector current Ip, which is linearly proportional to the current Ip:

[0087] (14)

[0088] It should be pointed out that Figure 4 The photodetector digital pixel circuit according to the embodiment of the present invention is not limited to measuring the N-on-P type photodetector 601 shown in the figure, that is, the situation where the current generated by the detector discharges the integral capacitor, but is also applicable to P-on-N type photodetectors, that is, the situation where the current generated by the detector charges the integral capacitor.

[0089] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A photodetector digital integrating pixel circuit, comprising a photodetector, characterized in that: The digital integration pixel circuit is composed of an injection tube, an integration capacitor, a reset switch, a comparator, a monostable circuit, a counter, a clock generation circuit, a charge storage switch, a charge transfer switch and a unit charge storage capacitor; wherein: One end of the injection tube is connected to the photodetector, and the other end is connected to the upper plate of the integrating capacitor and an input end of the comparator; the other input end of the comparator is connected to the judgment voltage Vth, and the output end is connected to the input of the monostable circuit, and the output of the monostable circuit is connected to the input of the counter and the input of the clock generating circuit; the first output signal S1 of the clock generating circuit controls the charge storage switch, and the second output signal S2 controls the charge transfer switch; one plate of the unit charge storage capacitor is connected to the charge storage switch and the charge transfer switch, and the other plate is connected to the reference voltage Vref; the other end of the charge storage switch is connected to the reset voltage Vrst; the other end of the charge transfer switch is connected to the upper plate of the integrating capacitor; one end of the reset switch is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor; The current-to-digital integral conversion is completed through the timing relationship of the reset signal RST, the pulse signal Vp generated by the monostable circuit, the first output signal S1 of the clock generating circuit, and the second output signal S2 of the clock generating circuit, including: (1) The voltage VB provides appropriate bias conditions for the device that generates the measured current through the injection tube; (2) The reset signal RST is valid, the reset switch is turned on, and the voltage Vint on the integral capacitor Cint is reset to Vrst, and the counter is reset at the same time; (3) The reset signal RST is invalid, the reset switch is turned off, and integration begins. That is, the measured current Ip discharges the charge on the integration capacitor Cint. When the integrated voltage Vint drops below the comparator judgment voltage Vth, the comparator output Vout flips, and a pulse signal Vp is generated through the monostable circuit, and the counter output Do is incremented by 1. (4) The pulse signal Vp generates two output signals S1 and S2 through the control signal generating circuit, wherein the output signal S1 controls the charge storage switch and the output signal S2 controls the charge transfer switch; during the reset and integration period of the integration capacitor Cint, the output signal S1 is valid, closing the charge storage switch and connecting the unit charge storage capacitor Co to the reset voltage Vrst, so that the unit charge Qo is stored on the charge storage capacitor Co. During this period, the output signal S2 is invalid, opening the charge transfer switch; (5) When the output pulse signal Vp of the monostable circuit is valid, the output signal S1 is invalid, and the charge storage switch is disconnected. After a certain time interval, the output signal S2 is valid, and the charge transfer switch is closed, and the unit charge Qo is transferred to the integration capacitor Cint. The voltage Vint on the capacitor recovers to a level higher than the decision level Vth, and the comparator output is restored; (6) After the pulse signal Vp becomes invalid, a new integration begins, that is, the measured current Ip discharges the integration capacitor Cint again; (7) After a certain time interval, the output signal S1 is valid, closing the charge storage switch and connecting the unit charge storage capacitor Co to the reset voltage Vrst; (8) Repeat the above integration and unit charge storage, transfer and integrated voltage recovery process of (3)-(7) until the specified integration time Tint is reached. The value N of the counter output Do is the quantized result of the measured current Ip. The charge Qo stored in the unit charge storage capacitor Co and transferred to the integration capacitor Cint is Qo=Co(Vrst-Vref).

2. The photodetector digital integration pixel circuit according to claim 1, characterized in that: The effective levels of the output signals S1 and S2 of the control signal generating circuit do not overlap, that is, when the output signal S1 is effective, the output signal S2 is ineffective, and when the output signal S2 is effective, the output signal S1 is ineffective.

3. The photodetector digital integration pixel circuit according to claim 2, characterized in that: The effective levels of the output signal S1 and the output signal S2 are high levels.

4. The photodetector digital integration pixel circuit according to claim 2, wherein: The effective levels of the output signal S1 and the output signal S2 are low levels.

5. The photodetector digital integration pixel circuit according to any one of claims 1 to 4, characterized in that: The photoelectric detector is an N-on-P type photoelectric detector.

6. The photodetector digital integrating pixel circuit according to any one of claims 1 to 4, characterized in that: The photoelectric detector is a P-on-N type photoelectric detector.

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