GaN field effect transistor

Abstract

This invention discloses a GaN field-effect transistor, comprising a substrate; an epitaxial layer having a source, a drain, and an epitaxial trench near the source; and a gate structure disposed within the epitaxial trench, the gate structure comprising: a heavily doped p-GaN layer deposited at the bottom of the epitaxial trench for conducting a two-dimensional electron gas channel for depleting the gate structure; a lightly doped p-GaN layer deposited on the heavily doped p-GaN layer, with trench structures formed on both sides of the lightly doped p-GaN layer; a gate dielectric layer covering the sidewalls of the lightly doped p-GaN layer and the trench structures, and the sidewalls of the heavily doped p-GaN layer; and a gate metal layer in contact with the top of the lightly doped p-GaN layer for forming a gate Schottky contact with the lightly doped p-GaN layer. This invention overcomes the problem that the gate breakdown voltage of traditional p-GaN gate HEMT devices is generally less than 10V, significantly improving the gate forward breakdown voltage of GaNHEMT devices and reducing the gate leakage current.

Description

Technical Field

[0001] This invention relates to the field of transistor technology, and more specifically to a GaN field-effect transistor. Background Technology

[0002] Energy has become a major problem plaguing humanity. With the dwindling supply of fossil fuels, transportation systems are increasingly moving towards electrification. Therefore, the design of high-efficiency, lightweight, and reliable power devices is urgently needed. Silicon-based devices have reached the theoretical limits of Si materials. Compared to first-generation semiconductors like Si and second-generation semiconductors like gallium arsenide, third-generation semiconductors have larger band gaps, higher breakdown field strengths, and faster electron saturation migration speeds, making them ideal for applications in high-temperature, high-voltage, high-frequency, and high-power fields.

[0003] GaN transistors have always been a research hotspot in GaN power devices. Due to the polarization effect, a high concentration of two-dimensional electron gas (2DEG) exists at the AlGaN / GaN interface, making GaN high electron mobility transistors (HEMTs) naturally normally-on devices. To achieve normally-off operation, growing a p-GaN layer between the gate metal and AlGaN is a relatively reliable method. Currently, p-GaN gate enhancement type HEMTs are widely used in high-frequency and low-to-medium power applications. Summary of the Invention

[0004] Based on this, the present invention proposes a GaN field-effect transistor that effectively improves the gate forward breakdown voltage of GaN HEMT devices and reduces the gate leakage current.

[0005] According to one aspect of the present invention, a GaN field-effect transistor is provided, comprising:

[0006] Substrate;

[0007] The epitaxial layer has a source electrode, a drain electrode, and an epitaxial trench near the source electrode.

[0008] A gate structure is disposed within the aforementioned epitaxial trench, the gate structure comprising:

[0009] A heavily doped p-GaN layer is deposited at the bottom of the epitaxial trench to deplete the two-dimensional electron gas conductive channel of the gate structure.

[0010] A lightly doped p-GaN layer is deposited on the above-mentioned heavily doped p-GaN layer, and a trench structure is formed on both sides of the lightly doped p-GaN layer.

[0011] A gate dielectric layer, covering the sidewalls and trench structure of the lightly doped p-GaN layer, and the sidewalls of the heavily doped p-GaN layer; and

[0012] A gate metal layer is in contact with the top of the lightly doped p-GaN layer to form a gate Schottky contact with the lightly doped p-GaN layer.

[0013] According to an embodiment of the present invention, the epitaxial layer comprises a buffer layer, a barrier layer, and a passivation layer stacked sequentially.

[0014] According to an embodiment of the present invention, the epitaxial trench is formed in the passivation layer, and the bottom of the epitaxial trench extends to contact the barrier layer.

[0015] According to an embodiment of the present invention, the source and drain are in direct contact with the barrier layer to form an ohmic contact.

[0016] According to an embodiment of the present invention, the barrier layer and the passivation layer are isolated by the gate dielectric layer.

[0017] According to an embodiment of the present invention, the gate dielectric layer is a metal oxide dielectric layer, and the thickness of the gate dielectric layer is 0.1-10 nm.

[0018] According to an embodiment of the present invention, the sidewalls of the trench structure and the gate dielectric layer are used to form a metal-insulator-semiconductor structure with the gate metal layer.

[0019] According to an embodiment of the present invention, the buffer layer is a GaN or AlGaN buffer layer.

[0020] According to an embodiment of the present invention, the barrier layer is Al. x Ga 1-x N-barrier layer.

[0021] According to an embodiment of the present invention, the passivation layer is one of SiO2, Al2O3, or SiN.

[0022] As can be seen from the above technical solution, the GaN field-effect transistor provided by the present invention has the following beneficial effects:

[0023] This invention is based on a specific gate structure, which forms a Schottky contact between the gate metal and the p-type gate. The Schottky contact is optimized based on the trench structure of the lightly doped region. Combined with the heavily doped p-GaN depletion 2DEG channel to provide a higher threshold voltage, this invention overcomes the problem that the gate breakdown voltage of traditional p-GaN gate HEMT devices is generally less than 10V. It significantly improves the gate forward breakdown voltage of GaNHEMT devices and reduces the gate leakage current.

[0024] GaN HEMT devices with this gate structure have lower on-resistance and significantly improved gate control capability. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a GaN field-effect transistor according to an embodiment of the present invention;

[0026] Figure 2 This is a comparison diagram of the near-Schottky junction interface electric field intensity between a conventional p-type gate structure and the p-trench MIS Schottky gate structure of the present invention, as shown in the embodiment of the present invention.

[0027] Figure 3 The following are gate current curves corresponding to different trench depths in embodiments of the present invention;

[0028] Figure 4 The embodiments of the present invention show the gate current curves corresponding to different dielectric layer thicknesses;

[0029] Figure 5 The embodiments of the present invention show the gate current curves corresponding to different trench spacings;

[0030] Figure 6 This is the gate current curve corresponding to a light doping concentration in an embodiment of the present invention;

[0031] Figure 7 The figures show the gate current curves for materials with different dielectric constants in embodiments of the present invention.

[0032] Figure reference numerals: 101-substrate layer; 102-buffer layer; 103-barrier layer; 104-drain; 105-passivation layer; 106-heavily doped p-GaN layer; 107-lightly doped p-GaN layer; 108-gate dielectric layer; 109-gate metal layer; 110-source. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0034] Currently, although p-GaN gate-enhanced HEMTs exhibit superior performance, significant reliability issues remain. Low gate forward breakdown voltage (<10V) and high gate leakage current are the main factors limiting the application scenarios of p-GaN gate GaN HEMTs.

[0035] Large gate leakage current limits the gate voltage swing and also causes losses in the drive circuit; while small gate breakdown voltage also puts a burden on the design of the gate drive.

[0036] Therefore, it is essential to develop a gate structure that improves gate breakdown voltage and reduces gate leakage current, thereby ensuring more stable device operation.

[0037] Figure 1This is a schematic diagram of the structure of a GaN field-effect transistor according to an embodiment of the present invention.

[0038] According to one aspect of the invention, such as Figure 1 As shown, a GaN field-effect transistor is provided, which mainly includes a substrate 101, an epitaxial layer and a gate structure.

[0039] According to an embodiment of the present invention, the transistor includes a substrate 101;

[0040] According to an embodiment of the present invention, the transistor includes an epitaxial layer, wherein a source 110, a drain 104, and an epitaxial trench near the source 110 are disposed on the epitaxial layer.

[0041] According to an embodiment of the present invention, the transistor includes a gate structure disposed in an epitaxial trench. The gate structure includes a heavily doped p-GaN layer 106, a lightly doped p-GaN layer 107, a gate dielectric layer 108, and a gate metal layer 109.

[0042] Among them, the heavily doped p-GaN layer 106 is deposited at the bottom of the epitaxial trench and is used as a two-dimensional electron gas conductive channel for the depletion gate structure;

[0043] A lightly doped p-GaN layer 107 is deposited on a heavily doped p-GaN layer 106, and trench structures are formed on both sides of the lightly doped p-GaN layer 107.

[0044] Gate dielectric layer 108 covers the sidewalls and trench structure of lightly doped p-GaN layer 107 and the sidewalls of heavily doped p-GaN layer 106; and

[0045] The gate metal layer 109 is in contact with the top of the lightly doped p-GaN layer 107 to form a gate Schottky contact with the lightly doped p-GaN layer 107.

[0046] The gate structure is located closer to the source 110, with a larger distance from the drain 104. The position of the gate structure can be moved to change the distance between it and the source 110 and the drain 104, but it is generally closer to the source 110 because a large voltage is applied to the drain 104 in actual applications. This would cause leakage current to occur on the sidewall of the heavily doped p-GaN layer 106 near the drain 104, affecting the lateral breakdown voltage of the device.

[0047] When a metal and a semiconductor come into contact, depletion occurs, forming a depletion region on the semiconductor surface. Within a certain width, there are almost no mobile electrons. Therefore, electrons do not easily travel between the semiconductor and the metal, forming a gate Schottky contact.

[0048] The gate dielectric layer 108 completely covers the bottom and sidewalls of the trench structures on both sides of the lightly doped p-GaN layer 107, but does not cover the top of the lightly doped p-GaN layer 107. There are two reasons for setting this shape: First, to optimize the distribution of mirror charges generated inside the semiconductor due to the contact between the metal and the semiconductor, and reduce the influence of the increased gate current caused by the Schottky barrier reduction effect. Second, to optimize the electric field distribution of the Schottky junction. Since there is a large peak electric field at the gold semiconductor interface, this setting can reduce the peak electric field at the gold semiconductor interface, that is, at the direct contact between the gate metal layer 109 and the lightly doped p-GaN layer 107, and improve the gate breakdown voltage.

[0049] When a forward gate voltage is applied, the Schottky junction is reverse biased. The heavily doped p-GaN layer 106 can deplete the 2DEG channel, providing a higher threshold voltage. The lightly doped p-GaN layer 107, which is in direct contact with the gate metal layer 109, can reduce the peak electric field at the metal-semiconductor interface and improve interface stability. Trenching the lightly doped p-GaN layer 107 changes the distribution of mirrored charges within the metal, increasing the amount of mirrored charges within the trench. The trench sidewalls and the bottom dielectric layer form the transistor structure, generating charge coupling when a forward gate voltage is applied, further optimizing the electric field distribution of the Schottky junction formed by the gate metal layer 109 and the lightly doped p-GaN layer 107, and reducing the peak electric field. This improves the forward breakdown voltage of the gate, limits the gate current, improves the gate reliability, and prevents gate breakdown caused by voltage overshoot in the gate drive circuit.

[0050] This invention overcomes the problems of low gate forward breakdown voltage and high gate leakage current in traditional Schottky p-GaN HEMTs, and can significantly improve the gate breakdown voltage of GaN HEMTs and suppress gate leakage current.

[0051] According to an embodiment of the present invention, the epitaxial layer includes a buffer layer 102, a barrier layer 103, and a passivation layer 105 stacked sequentially.

[0052] Epitaxy can meet the requirements for manufacturing future high-performance integrated circuits (ICs). For example, it can be used to achieve raised source / drain structures with low contact resistance.

[0053] According to an embodiment of the present invention, an epitaxial trench is formed in a passivation layer 105, and the bottom of the epitaxial trench extends to contact the barrier layer 103.

[0054] According to an embodiment of the present invention, the source 110 and the drain 104 are in direct contact with the barrier layer 103 to form an ohmic contact.

[0055] Electrons are highly concentrated near the conduction band, making it easy for them to travel between metals and semiconductors. There is no barrier between electrons in a semiconductor and metals, and the barrier height between metals and semiconductors is very small. In actual operation of the device, the current is also bidirectional, thus forming an ohmic contact. The source and drain electrodes form an ohmic contact with the barrier layer 103 to reduce the channel resistance. The electrical properties of the channel determine the on-resistance and output characteristics of the device.

[0056] According to an embodiment of the present invention, the barrier layer 103 and the passivation layer 105 are isolated by the gate dielectric layer 108.

[0057] According to an embodiment of the present invention, the gate dielectric layer 108 is a metal oxide dielectric layer, and the thickness of the gate dielectric layer 108 is 0.1-10 nm.

[0058] The gate dielectric layer 108 can be an oxide layer with a thickness of less than 10 nm that can be grown in actual production, such as H. f O2 metal oxide layer.

[0059] According to an embodiment of the present invention, the sidewalls of the trench structure formed in the lightly doped p-GaN layer 107 and the gate dielectric layer 108 are used to form a metal-insulator-semiconductor structure with the gate metal layer 109.

[0060] This invention addresses the problem of low forward breakdown voltage in p-GaN gate HEMTs by modifying the gate structure and fully utilizing the advantages of the Schottky contact formed between the gate metal and the p-type gate. Parameters such as trench depth, trench width, gate dielectric layer thickness, gate dielectric layer dielectric constant, and doping concentration in the lightly doped region can be controlled to manage the magnitude of the increase in forward breakdown voltage and the decrease in gate control capability.

[0061] According to an embodiment of the present invention, the buffer layer 102 is a GaN or AlGaN buffer layer.

[0062] According to an embodiment of the present invention, the barrier layer 103 is Al x Ga 1-x N-barrier layer.

[0063] Since barrier height is difficult to control, why not control barrier width to allow electrons or holes to tunnel? In a PN junction, the width of the space charge region depends on the doping concentration. Therefore, similarly, the ohmic contact region can be heavily doped. After heavy doping, the barrier width narrows, making it easier for electrons or holes to tunnel or be thermally excited under voltage.

[0064] According to an embodiment of the present invention, the passivation layer 105 is one of SiO2, Al2O3, or SiN.

[0065] According to an embodiment of the present invention, the trench depth and width, the gate dielectric layer 108 thickness and dielectric constant, the heavily doped region 106 thickness and doping concentration, and the lightly doped region 107 thickness and doping concentration can all be adjusted.

[0066] Performance testing

[0067] Using the GaN field-effect transistor provided in this application, the change in the transistor's electrical performance under no-current conditions was detected.

[0068] Figure 2 The diagram shows a comparison of the near-Schottky junction interface electric field strength between a conventional p-type gate structure and the p-trench MIS Schottky gate structure of the present invention, as shown in the embodiment of the present invention.

[0069] like Figure 2 The figure shows a comparison of the electric field strength near the Schottky junction interface between the traditional p-type gate structure and the p-trench MIS Schottky gate structure of the present invention. It can be seen that the trench MIS Schottky gate structure of the present invention can significantly reduce the electric field strength at the gate Schottky junction interface of the device, thereby improving the gate forward breakdown voltage.

[0070] Figure 3 The following are gate current curves corresponding to different trench depths in embodiments of the present invention.

[0071] like Figure 3 As shown, the gate current curves are for different trench depths. It can be seen that the gate leakage current gradually decreases as the trench depth increases.

[0072] Figure 4 The examples provided are gate current curves for different dielectric layer thicknesses in this invention.

[0073] like Figure 4 As shown, the gate current curves are for different dielectric layer thicknesses. It can be seen that as the dielectric layer thickness increases, the gate current does not simply decrease, but rather there is an extreme value.

[0074] Figure 5 The following are gate current curves for different trench spacings in embodiments of the present invention.

[0075] like Figure 5 As shown, the gate current curves are for different trench spacings. It can be seen that the gate leakage current gradually decreases as the trench spacing increases.

[0076] Figure 6 This is the gate current curve corresponding to a light doping concentration in an embodiment of the present invention.

[0077] like Figure 6 As shown, the gate current curves are for lightly doped concentrations. It can be seen that the gate leakage current decreases slightly as the doping concentration decreases.

[0078] Figure 7 The figures show the gate current curves for materials with different dielectric constants in embodiments of the present invention.

[0079] like Figure 7 As shown, the gate current curves for materials with different dielectric constants are displayed. It can be seen that when the gate voltage is greater than 3V, the gate leakage current of HfO2 material is significantly lower than that of Al2O3 material.

[0080] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A GaN field effect transistor, comprising: a substrate; an epitaxial layer comprising a buffer layer, a barrier layer and a passivation layer stacked in sequence, the epitaxial layer being provided with a source, a drain, and an epitaxial trench close to the source, the epitaxial trench being formed in the passivation layer and the bottom of the epitaxial trench extending to contact the barrier layer; a gate structure disposed in the epitaxial trench, the gate structure comprising: a heavily doped p-GaN layer deposited at the bottom of the epitaxial trench for depleting a two-dimensional electron gas conduction channel of the gate structure; a lightly doped p-GaN layer deposited on the heavily doped p-GaN layer, the lightly doped p-GaN layer being flanked by a trench structure; a gate dielectric layer covering the sidewalls of the lightly doped p-GaN layer and the bottom of the trench structure, and the sidewalls of the heavily doped p-GaN layer, wherein the gate dielectric layer does not cover the top of the lightly doped p-GaN layer, the gate dielectric layer isolating the barrier layer from the passivation layer; and a gate metal layer in contact with the top of the lightly doped p-GaN layer for forming a gate Schottky contact with the lightly doped p-GaN layer; wherein the sidewalls of the trench structure of the lightly doped p-GaN layer and the gate dielectric layer covering the sidewalls of the lightly doped p-GaN layer and the bottom of the trench structure are for forming a metal-insulator-semiconductor structure with the gate metal layer.

2. The transistor of claim 1, wherein, The source and drain are in direct contact with the barrier layer to form an ohmic contact.

3. The transistor of claim 1, wherein, The gate dielectric layer is a metal-oxide dielectric layer, and the thickness of the gate dielectric layer is 0.1-10 nm.

4. The transistor of claim 1, wherein, The buffer layer is a GaN or AlGaN buffer layer.

5. The transistor of claim 1, wherein, The barrier layer is Al x Ga 1－x N barrier layer.

6. The transistor of claim 1, wherein, The passivation layer is one of SiO2, Al2O3 and SiN.

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