Thin film transistor, array substrate, display panel and display device

Abstract

The present disclosure relates to the technical field of display, and discloses a thin film transistor, an array substrate, a display panel and a display device. The thin film transistor is located on one side of a substrate, and comprises a channel part, a first electrode and a second electrode. The channel part is arranged on one side of the substrate. The first electrode comprises a first surface, the first surface is in contact with the channel part, and the first surface comprises a first edge line. The second electrode is arranged separately from the first electrode, and comprises a second surface, the second surface is in contact with the channel part, and the second surface comprises a second edge line. The second edge line is located on the side of the second surface close to the first electrode, and the orthographic projection of the second edge line on the substrate is located within the orthographic projection of the channel part on the substrate. The first edge line is located on the side of the first surface close to the second electrode. The voltage applied to the second electrode is higher than the voltage applied to the first electrode, and the length of the second edge line is greater than the length of the first edge line. The thin film transistor is not easy to be damaged, and the display device can display normally.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a thin film transistor, an array substrate comprising the thin film transistor, a display panel comprising the array substrate and a display device comprising the array substrate. BACKGROUND

[0002] With the development of display technology, liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices have become mainstream in display devices.

[0003] However, the current display device is prone to reliability defects such as horizontal lines.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to overcome the shortcomings of the prior art that are prone to reliability defects such as horizontal lines, and to provide a thin film transistor, an array substrate comprising the thin film transistor, a display panel comprising the array substrate and a display device comprising the array substrate.

[0006] According to one aspect of the present disclosure, a thin film transistor is provided on one side of a substrate, the thin film transistor comprising:

[0007] a channel portion provided on one side of the substrate;

[0008] a first electrode comprising a first surface, the first surface being in contact with the channel portion, the first surface comprising a first edge line;

[0009] a second electrode provided separately from the first electrode, the second electrode comprising a second surface, the second surface being in contact with the channel portion, the second surface comprising a second edge line, a normal projection of the second edge line on the substrate being located within a normal projection of the channel portion on the substrate;

[0010] wherein the first edge line is located on a side of the first surface close to the second electrode, a voltage applied to the second electrode is higher than a voltage applied to the first electrode, and a length of the second edge line is greater than a length of the first edge line.

[0011] In an example embodiment of the present disclosure, a distance between a start point and an end point of the first edge line is equal to a distance between a start point and an end point of the second edge line, the first edge line is a straight line, and the second edge line is a curved line.

[0012] In an example embodiment of the present disclosure, the second edge line includes one or both of an arc line and a broken line.

[0013] In an example embodiment of the present disclosure, a side of the first electrode close to the second electrode is a first side, the first side is configured as a flat surface, and a connecting line between the first side and the first surface is the first edge line.

[0014] In an example embodiment of the present disclosure, a side of the second electrode close to the first electrode is a second side, the second side is configured as a curved surface, and a connecting line between the second side and the second surface is the second edge line.

[0015] In an example embodiment of the present disclosure, the first electrode includes a first portion on a side of the channel portion away from the substrate, the second electrode includes a second portion on a side of the channel portion away from the substrate, and an area of a projection of the first portion on the substrate is less than or equal to an area of a projection of the second portion on the substrate.

[0016] In an example embodiment of the present disclosure, the first surface is a surface of the first portion close to the channel portion, and the second surface is a surface of the second portion close to the channel portion.

[0017] In an example embodiment of the present disclosure, the second electrode includes:

[0018] a first layer in contact with the channel portion, the second edge line being provided on the first layer;

[0019] a second layer provided on a side of the first layer away from the substrate, a projection of the second layer on the substrate overlapping a part of the second edge line or a projection of the second layer on the substrate not overlapping the second edge line.

[0020] In an example embodiment of the present disclosure, the thin film transistor further includes:

[0021] a gate electrode provided on a side of the substrate;

[0022] a gate insulating layer provided on a side of the gate electrode away from the substrate, and the channel portion being provided on a side of the gate insulating layer away from the substrate.

[0023] In one example embodiment of the present disclosure, the material of the channel portion is an oxide semiconductor.

[0024] In one example embodiment of the present disclosure, the first electrode is a source electrode and the second electrode is a drain electrode.

[0025] According to another aspect of the present disclosure, there is provided an array substrate, comprising the thin film transistor as described above.

[0026] According to still another aspect of the present disclosure, there is provided a display panel, comprising the array substrate as described above.

[0027] According to yet another aspect of the present disclosure, there is provided a display device, comprising the display panel as described above.

[0028] The thin film transistor of the present disclosure, the voltage applied to the second electrode is higher than the voltage applied to the first electrode, the length of the second edge line is greater than the length of the first edge line, so that the area S2 of the high resistance region near the second electrode increases, and the ratio of the resistance R2 of the high resistance region to the resistance R1 of the low resistance region is fixed, that is, R2 is fixed, and according to the calculation formula of the resistance R2 = p2 x d2 / S2, p2 is the resistivity of the high resistance region, d2 is the length of the critical voltage position from the second electrode 72, and the increase of S2 will lead to the proportional increase of d2, thereby reducing the electric field E = (Vpu-Uc) / d2 of the high resistance region in proportion, Vpu is the voltage applied to the second electrode, Uc is the critical potential of the high resistance region and the low resistance region, the reduction of the electric field reduces the impact of the hot carrier on the chemical bond of the oxide of the channel portion (semiconductor), avoids the damage of the thin film transistor at a higher voltage, can normally output current, and the output current is basically not attenuated, the PU point can be normally reset, and the display device can display normally.

[0029] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0030] The drawings herein are incorporated into the specification and form a part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0031] Figure 1 It is a schematic diagram of the circuit structure of the driving circuit in the GOA structure.

[0032] Figures 2-4 It is a schematic diagram of the working timing of the driving circuit in Figure 1 .

[0033] Figure 5 A schematic diagram of the potential distribution and carrier distribution in the channel of a thin-film transistor when discharging at the PU point in related technologies.

[0034] Figure 6 for Figure 5 A top-view schematic diagram showing the distribution of low-resistance and high-resistance regions in the channel section of a thin-film transistor.

[0035] Figure 7 for Figure 5 A three-dimensional structural diagram showing the main current path through the high-resistivity region.

[0036] Figure 8 This is a schematic diagram of the current transfer characteristics before and after the device is damaged due to the voltage increase of the second electrode.

[0037] Figure 9 This is a schematic diagram of an example embodiment of the thin-film transistor disclosed herein, and a schematic diagram of the potential distribution and carrier distribution in the channel when the PU point is discharged.

[0038] Figure 10 This is a schematic diagram of another example embodiment of the thin-film transistor of this disclosure.

[0039] Figure 11 for Figure 10 A schematic diagram comparing the withstand voltage test of the first and second electrodes of the thin-film transistor.

[0040] Figure 12 for Figure 9 A top-view schematic diagram showing the distribution of low-resistance and high-resistance regions in the channel section of a thin-film transistor.

[0041] Figure 13 for Figure 12 A three-dimensional structural diagram showing the main current path through the high-resistivity region.

[0042] Figure 14 This is a schematic diagram of another exemplary embodiment of the thin-film transistor disclosed herein.

[0043] Explanation of reference numerals in the attached figures:

[0044] 1. Substrate; 2. Light-shielding layer; 3. Buffer layer; 4. Gate; 5. Gate insulating layer;

[0045] 6. Channel section; 61. Low-resistivity region; 62. High-resistivity region;

[0046] 71. First electrode; 71a. First part; 711. First surface; 7111. First edge line; 712. First side surface;

[0047] 72, second electrode; 72a, second portion; 721, second surface; 7211, second edge line; 722, second side surface; 723, first layer; 724, second layer. DETAILED DESCRIPTION

[0048] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided as non-limiting examples so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus description of the same will be omitted. In addition, the drawings are to be considered in the illustrative mode, and not necessarily to scale.

[0049] Although relative terms are used herein, such as "upper", "lower", to describe one component's relative position to another component of a figure, these terms are used herein for convenience only and are not necessarily carried into the claims. As will be understood by persons of skill in the art, if the figure is flipped upside down, then the component described as being "on top" would become the component described as being "on the bottom". When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is "directly" on the other structure or that the structure is "indirectly" on the other structure via another structure.

[0050] The terms "one", "a", "an", "the", and "at least one" are used to mean that "one or more" of something is present; the term "or" is used to mean, and is used interchangeably with, the term "and / or"; the term "comprising" is used to mean "including, but not limited to"; and the term "first", "second", and "third" are used only as labels, and do not mean "one or more" or "at least one".

[0051] In the present application, unless specifically stated and limited otherwise, the term "connected" is used broadly and encompasses direct connections, indirect connections (for example, via another intervening medium), fixed connections and removable connections, and combinations thereof. The term "and / or" is used to mean "and", "or", or both, for example, "A and / or B" means "A and B", "A or B", or "A and B".

[0052] GOA is the abbreviation of Gate Driven on Array, which means gate driving integrated on array substrate; refer to Figure 1As shown, the GOA unit can include four thin film transistors, M1, M2, M3 and M4 respectively; M1 is used for charging the PU point, M2 is used for discharging reset of the PU point, M3 is used for charging the Gout, and M4 is used for discharging reset of the Gout.

[0053] Input is the carry signal input end; CLK is the clock signal input end, including phase opposite CLK and CLKB, wherein CLK can be used for odd level, and CLKB can be used for even level; V GL is a low voltage input end; Reset is the PU point and Gout reset signal input end; Gout-N-1 is the output end of the previous row, Gout-N is the Nth row output end, and Gout-N+1 is the output end of the next row; the PU point is the gate point of M3 controlling the Gout output high level.

[0054] Referring to Figure 1 and Figure 2 , in the first step, before the output signal of the previous GOA unit arrives, although the CLK signal line has a high potential input to the source of M3, the PU point is at a low potential, and M3 is in an off state, at this time, the Gout has no output high potential.

[0055] In the second step, the GoutN-1 of the previous GOA unit provides an input signal for the GOA unit, M1 is turned on, the potential of the PU point is raised to V1, and M3 is also in an on state, but since the CLK signal connected to the source of M3 is still low at this time, the Gout-N of the GOA unit still has no output high potential.

[0056] Referring to Figure 1 and Figure 3 , in the third step, the CLK signal outputs a high potential at this moment, under the action of the capacitor C, the potential of the PU point is also pulled up synchronously, that is, the potential of the PU point is raised from V1 to V2, at this time, the conduction ability of M3 is also greatly increased, the output current is increased, and the Gout-N outputs a high potential.

[0057] Referring to Figure 1 and Figure 4 , in the fourth step, since the Gout-N of the current GOA unit is the input signal of the next level GOA unit, as shown, during the output of the Gout-N, the next level is also pre-charged. With the potential of the CLK signal changing from high potential to low potential, the high potential signal Gout-N+1 of the next level is input to the current level as a reset signal, then M2 and M4 are turned on, so that the two ends of the capacitor C are connected to the low potential V GL and discharge, and the Gout-N is also connected to the low potential V GL , so that the TFT of this row is turned off.

[0058] The inventors found through various analyses and numerous experiments that the main cause of the display device's reliability problems, such as horizontal lines, is that the thin film transistor (M2) is damaged and cannot normally output, and the PU point cannot be normally reset. Referring to Figures 5-7 the drawing, the arrow indicates the direction of current flow, and the cause of the thin film transistor's damage is that when the thin film transistor discharges the PU point, the Reset voltage of the gate 4 of the thin film transistor is high Vgh=20V, the source (first electrode 71) is connected to low V GL =-14V, and the drain (second electrode 72) is connected to the PU point Vpu=40V. Since the voltage difference between the source and the drain of M2 is the largest, M2 is most likely to be damaged. In the channel region 6 (semiconductor), the carriers gather to form an electron channel in the region where the channel potential U

[0059] The main current flows from the high resistance region 62 of the semiconductor through the contact surface between the second electrode 72 (metal) and the channel region 6 (semiconductor) to the low resistance region 61 of the semiconductor. Referring to Figure 5 the drawing, the potential distribution in the direction from the first electrode 71 to the second electrode 72, in the overlapping region between the first electrode 71 (metal) and the channel region 6 (semiconductor), the potential is basically unchanged because the resistance of the metal is much smaller than that of the semiconductor; in the overlapping region between the second electrode 72 (metal) and the channel region 6 (semiconductor), the potential is also basically unchanged because the resistance of the metal is much smaller than that of the semiconductor; the low resistance region 61 and the high resistance region 62 are similar to a series structure of resistors, and the voltage at the junction between the low resistance region 61 and the high resistance region 62 is the critical potential Uc=Vgh+Vth; assuming that Vth=2V, the critical potential Uc is 22V. In the direction from the first electrode 71 to the second electrode 72, the higher the potential of the low resistance region 61, the narrower the electron channel, the greater the resistivity, and the faster the potential rises, until the critical potential is reached and the channel is pinched off. Considering that the series current is constant, the resistance of the low resistance region 61 R1 and the resistance of the high resistance region 62 R2 are in the following relationship: (Uc-V GL ) / R1=(VPU-Uc) / R2, and by introducing the aforementioned voltages, R1 / R2=36 / 18=2.

[0060] As the resistivity p2 of the high-resistance region 62 is much greater than the resistivity p1 of the low-resistance region 61, only the low-resistance region 61 with the minimum resistance and the high-resistance region 62 are considered, the length d1 of the channel position of the critical potential from the first electrode 71, and the length d2 of the channel position of the critical potential from the second electrode 72, R1 = p1 x d1 / S1, R2 = p2 x d2 / S2, p1 / S1 << p2 / S2 is considered, so d1 >> d2, the position of the critical potential will be very close to the second electrode 72, resulting in a very large electric field E = (VPU - Uc) / d2 near the second electrode 72, and the chemical bonds of the oxide of the channel portion 6 (semiconductor) are damaged under the impact of hot carriers accelerated by a large electric field, thereby damaging the thin film transistor and causing the thin film transistor to not output normally, and the PU point cannot be reset normally; and causing the display device to have reliability problems such as horizontal lines.

[0061] Referring to Figure 8 As shown in the figure, the horizontal coordinate is the gate voltage, and the vertical coordinate is the output current, L1 is the current transmission curve of the thin film transistor when the voltage difference between the second electrode and the first electrode is 37V, L2 is the current transmission curve of the thin film transistor when the voltage difference between the second electrode and the first electrode is 38V, L3 is the current transmission curve of the thin film transistor when the voltage difference between the second electrode and the first electrode is 39V, and L4 is the current transmission curve of the thin film transistor when the voltage difference between the second electrode and the first electrode is 40V; it can be seen from the figure that when the voltage difference between the second electrode and the first electrode is 37V, the current transmission of the thin film transistor remains normal; when the voltage difference between the second electrode and the first electrode is 38V, 39V and 40V, the current transmission of the thin film transistor is not normal, and all has attenuation; and the greater the voltage difference between the second electrode and the first electrode, the more serious the attenuation.

[0062] The example embodiments of the present disclosure provide a thin film transistor, referring to Figures 9-13 As shown in the figure, the thin film transistor is located on the substrate 1, and can include a channel portion 6, a first electrode 71 and a second electrode 72; the channel portion 6 is arranged on one side of the substrate 1; the first electrode 71 can include a first surface 711, the first surface 711 is in contact with the channel portion 6, and the first surface 711 includes a first edge line 7111; the second electrode 72 is arranged separately from the first electrode 71, and the second electrode 72 can include a second surface 721, the second surface 721 is in contact with the channel portion 6, and the second surface 721 includes a second edge line 7211, the second edge line 7211 is located on the side of the second surface 721 close to the first electrode 71, and the orthographic projection of the second edge line 7211 on the substrate 1 is located within the orthographic projection of the channel portion 6 on the substrate 1; wherein the first edge line 7111 is located on the side of the first surface 711 close to the second electrode 72, the voltage applied to the second electrode 72 is higher than the voltage applied to the first electrode 71, and the length of the second edge line 7211 is greater than the length of the first edge line 7111.

[0063] The thin film transistor of the present disclosure increases the area S2 of the high resistance region 62 near the second electrode 72, and the ratio of the resistance R2 of the high resistance region 62 to the resistance R1 of the low resistance region 61 is fixed, that is, R2 is fixed, and according to the calculation formula of resistance R2 = p2 x d2 / S2, the increase of S2 will cause the proportional increase of d2, thereby proportionally reducing the electric field E = (Vpu-Uc) / d2 of the high resistance region 62, and the reduction of the electric field reduces the impact of the hot carrier on the chemical bond of the oxide of the channel part 6 (semiconductor), avoiding damage to the thin film transistor at a higher voltage, enabling normal output, and the output current is basically not attenuated, the PU point can be normally reset, and the display device displays normally.

[0064] In the present example embodiment, the material of the substrate 1 can include an inorganic material, for example, the inorganic material can be glass, quartz or metal, etc. The material of the substrate 1 can also include an organic material, for example, the organic material can be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate, etc. The substrate 1 can be formed by multiple layers of materials, for example, the substrate 1 can include multiple base layers, and the material of the base layer can be any of the above materials. Of course, the substrate 1 can also be provided as a single layer, which can be any of the above materials.

[0065] An optical shielding layer 2 can also be provided on one side of the substrate 1. Light rays entering the active layer from the substrate 1 can generate photo-generated carriers in the active layer, which can greatly affect the characteristics of the thin film transistor and ultimately affect the display quality of the display device. The optical shielding layer 2 can block the light rays entering from the substrate 1, thereby avoiding affecting the characteristics of the thin film transistor and avoiding affecting the display quality of the display device.

[0066] A buffer layer 3 can also be formed on the side of the optical shielding layer 2 away from the substrate 1. The buffer layer 3 can block water vapor and impurity ions in the substrate 1 (especially organic materials), and can also increase the hydrogen ions for the subsequent formation of the active layer. The buffer layer 3 is made of an insulating material, which can insulate and separate the optical shielding layer 2 and the active layer. Of course, in some example embodiments of the present disclosure, the optical shielding layer 2 and the buffer layer 3 can not be provided.

[0067] The gate 4 is provided on the side of the buffer layer 3 away from the substrate 1. The gate 4 can include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The gate 4 can be a single layer or a multi-layer film.

[0068] A gate insulating layer 5 is provided on the side of the gate electrode 4 facing away from the substrate 1. The gate insulating layer 5 can include a silicon compound, a metal oxide, or the like. For example, the gate insulating layer 5 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These can be used alone or in combination with one another. The gate insulating layer 5 can be a single layer film or a multilayer film formed as a layered structure of different materials. The gate insulating layer 5 can be provided only on the side of the gate electrode 4 facing away from the substrate 1, or the gate insulating layer 5 can be provided over the entire surface of the substrate 1.

[0069] A channel portion 6 is provided on the side of the gate insulating layer 5 facing away from the substrate 1. The channel portion 6 has a projection on the substrate 1 which at least partially overlaps a projection of the gate electrode 4 on the substrate 1. For example, the projection of the channel portion 6 on the substrate 1 can be positioned within the projection of the gate electrode 4 on the substrate 1, or a part of the projection of the channel portion 6 on the substrate 1 can overlap a part of the projection of the gate electrode 4 on the substrate 1. Alternatively, the projection of the gate electrode 4 on the substrate 1 can be positioned within the projection of the channel portion 6 on the substrate 1.

[0070] The channel portion 6 can include an oxide semiconductor. The channel portion 6 can include amorphous silicon, low-temperature polysilicon, or the like.

[0071] In addition, the thin film transistor described above is of a bottom-gate type, and in another example embodiment of the present disclosure, the thin film transistor can be of a top-gate type. Specifically, the channel portion 6 can be provided on the side of the buffer layer 3 facing away from the substrate 1, the gate insulating layer 5 can be provided on the side of the channel portion 6 facing away from the substrate 1, and the gate electrode 4 can be provided on the side of the gate insulating layer 5 facing away from the substrate 1.

[0072] An electrode layer is provided on the side of the channel portion 6 facing away from the substrate 1. The electrode layer can include at least one metal selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The electrode layer can be a single layer film or a multilayer film. For example, the electrode layer can be formed to have a layered structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or MoNb / Cu. The electrode layer can include a first electrode 71 and a second electrode 72. The first electrode 71 can be a source electrode, and the second electrode 72 can be a drain electrode.

[0073] Reference Signs List Figure 9As shown, the first electrode 71 can include a first portion 71a located on the side of the channel portion 6 facing away from the substrate 1; that is, at least part of the first electrode 71 is located on the side of the channel portion 6 facing away from the substrate 1. The second electrode 72 can include a second portion 72a located on the side of the channel portion 6 facing away from the substrate 1; that is, at least part of the second electrode 72 is located on the side of the channel portion 6 facing away from the substrate 1. The first face 711 is the face of the first portion 71a close to the channel portion 6, and further, the first face 711 is the face of the first portion 71a adhering to the channel portion 6; the second face 721 is the face of the second portion 72a adhering to the channel portion 6. The edge line of the first face 711 close to the second electrode 72 is the first edge line 7111, and the edge line of the second face 721 close to the first electrode 71 is the second edge line 7211.

[0074] In the present example embodiment, the first electrode 71 can further include a third portion connected to the first portion 71a and located on the side of the sidewall of the channel portion 6 and the gate insulating layer 5 facing away from the substrate 1. The second electrode 72 can further include a fourth portion connected to the second portion 72a and located on the side of the sidewall of the channel portion 6 and the gate insulating layer 5 facing away from the substrate 1.

[0075] Of course, in another example embodiment of the present disclosure, the third portion and the fourth portion can not be provided, and only the first portion 71a and the second portion 72a are provided.

[0076] Reference is made to Figure 10 As shown, the first electrode 71 and the second electrode 72 are asymmetrically arranged, specifically, the area of the orthographic projection of the first portion 71a on the substrate 1 is smaller than the area of the orthographic projection of the second portion 72a on the substrate 1, that is, the area of the first face 711 is smaller than the area of the second face 721. Moreover, the length of the second edge line 7211 is greater than the length of the first edge line 7111.

[0077] The voltage of 42V, 45V, 46V is respectively applied to the second electrode 72, while the voltage of 0V is applied to the first electrode 71; then, the voltage of 40V, 41V is respectively applied to the first electrode 71, while the voltage of 0V is applied to the second electrode 72, and the output current is obtained as Figure 11 As shown in the curve diagram, the horizontal coordinate is the gate voltage, and the vertical coordinate is the output current. In the diagram, L5 is the current transfer characteristic curve when the voltage of 40V is applied to the first electrode 71, L6 is the current transfer characteristic curve when the voltage of 41V is applied to the first electrode 71, L7 is the current transfer characteristic curve when the voltage of 42V is applied to the second electrode 72, L7 is the current transfer characteristic curve when the voltage of 45V is applied to the second electrode 72, and L8 is the current transfer characteristic curve when the voltage of 46V is applied to the second electrode 72. From Figure 11The transmission characteristic curve appears slight current attenuation when the gate 4 is opened when a high voltage of 40 V or more is applied to the first electrode 71, and large current attenuation occurs at the second electrode 72 voltage of 41 V. The transmission characteristic curve is completely normal when a high voltage of 42 V or more is applied to the second electrode 72; slight current attenuation occurs when a voltage of 45 V is applied to the second electrode 72; and the output current attenuates when a voltage of 46 V is applied to the second electrode 72, but is still better than when a voltage of 41 V is applied to the first electrode 71.

[0078] Therefore, in the case where the area of the second face 721 is greater than the area of the first face 711, and the length of the second edge line 7211 is greater than the length of the first edge line 7111, the transmission of the current is facilitated, and abnormal phenomena do not occur.

[0079] However, in some example embodiments, the first electrode 71 and the second electrode 72 are required to be symmetrically arranged, that is, the first part 71a and the second part 72a are also substantially symmetrically arranged, and the first face 711 and the second face 721 are also substantially symmetrically arranged, so that the distance between the starting point and the ending point of the first edge line 7111 is equal to the distance between the starting point and the ending point of the second edge line 7211, and in this case, it is difficult to increase the length of the second edge line 7211.

[0080] Referring to Figure 12 and Figure 13 It is shown that the second edge line 7211 is arranged as a curve, and the first edge line 7111 is arranged as a straight line, which can increase the length of the second edge line 7211.

[0081] It should be noted that the curve is relative to the straight line, and as long as it is not a straight line, it is a curve, that is, the curve can include not only an arc line but also a broken line.

[0082] Specifically, the second edge line 7211 can be arranged as a rectangular sawtooth line, that is, the second edge line 7211 can include a plurality of rectangular broken lines, and the plurality of rectangular broken lines are sequentially connected to form the second edge line 7211. Of course, in some other example embodiments of the present disclosure, the second edge line 7211 can also include a plurality of circular arc lines, and the plurality of circular arc lines are sequentially connected to form the second edge line 7211; the second edge line 7211 can also include a plurality of circular arc lines and a plurality of rectangular broken lines, and the circular arc lines and the rectangular broken lines can be alternately arranged and then sequentially connected; or the plurality of circular arc lines are sequentially connected, the plurality of rectangular broken lines are sequentially connected, and then the adjacent circular arc lines and the rectangular broken lines are connected.

[0083] It should be further noted that the second edge line 7211 can also include a plurality of triangular sawtooth lines, elliptical arc lines, and the like, various shapes of curves. Here, they will not be described one by one.

[0084] In the case where the size of the channel portion 6 is not changed, the length of the second edge line 7211 of the boundary between the second electrode 72 (metal) and the channel portion 6 (semiconductor) is increased because the main current passes through the second electrode 72 and then passes through the high-resistance region 62 near the second electrode 72 and then passes through the low-resistance region 61. Since the height H2 of the high-resistance region 62 of the channel portion 6 is equal to the height H1 of the channel portion 6, which is a fixed value, after the second edge line 7211 is set as a curve, the width of the high-resistance region 62 is increased, the width of the high-resistance region 62 is equal to the length L2 of the second edge line 7211, and thus the area S2=L2*H2 of the high-resistance region 62 through which the current passes is increased. Since the voltage division of the high-resistance region 62 is fixed, the ratio R1 / R2=36 / 18=2 of the conventional design is fixed, that is, R2 is fixed, R2=ρ2*d2 / S2, and the increase of S2 will cause the proportional increase of d2, and thus the proportional decrease of the electric field E=(Vpu-Uc) / d2 of the high-resistance region 62. The decrease of the electric field causes the decrease of the impact of the hot carrier on the chemical bond of the oxide of the channel portion 6 (semiconductor), and thus the damage to the thin film transistor is avoided, the normal output is ensured, the PU point can be reset normally, and the display device can display normally.

[0085] In the example embodiment, the side of the first electrode 71 close to the second electrode 72 is the first side 712, the first side 712 is set as a plane, and the connecting line between the first side 712 and the first surface 711 is the first edge line 7111. The first side 712 is set as a whole plane, which is convenient for the process and can be directly formed by the photolithography process.

[0086] In the example embodiment, the side of the second electrode 72 close to the first electrode 71 is the second side 722, the second side 722 is set as a curve, the connecting line between the second side 722 and the second surface 721 is the second edge line 7211. The second side 722 is set as a curve, so that the second edge line 7211 is formed as a curve, and the process is convenient and the second electrode 72 can be directly formed by the photolithography process. Moreover, the first electrode 71 and the second electrode 72 are formed by the same photolithography process.

[0087] Of course, in some other example embodiments of the present disclosure, the first electrode 71 and the second electrode 72 are formed by different photolithography processes. Figure 14As shown, the second electrode 72 can be provided in layers, and specifically, the second electrode 72 can include a first layer 723 and a second layer 724, the first layer 723 is in contact with the channel portion, and the second layer 724 is provided on the first layer 723, the second side surface is provided on the first layer 723, and the second edge line is provided on the first layer 723. The specific structure of the first layer 723 is the same as that of the second electrode 72 described above, except that the thickness of the first layer 723 is less than that of the second electrode 72 described above. The second layer 724 is provided on the side of the first layer 723 away from the substrate, and the orthogonal projection of the second layer 724 on the substrate overlaps a part of the second edge line. For example, in the case where the second edge line is provided as a rectangular zigzag line, the orthogonal projection of the second layer 724 on the substrate can overlap a part of the second edge line away from the first electrode; or the orthogonal projection of the second layer 724 on the substrate does not overlap the second edge line, i.e., the second layer 724 does not cover the part of the first layer 723 provided as a curved surface. The material of the first layer 723 and the material of the second layer 724 can be the same.

[0088] Of course, in some example embodiments of the present disclosure, the material of the first layer 723 and the material of the second layer 724 can be different. For example, in the case where the first electrode 71 and the second electrode 72 are provided as a laminated structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or MoNb / Cu, the first layer 723 of the second electrode 72 close to the channel portion 6 can be provided as a curved surface, and the second layer 724 of the second electrode 72 away from the channel portion 6 can be provided as a flat surface. Figure 12 In the structure of the second electrode 72, one or two layers away from the channel portion 6 can be provided according to the structure in the prior art. For example, in the case where the second electrode 72 is provided as Ti / Al / Ti, i.e., the second electrode 72 includes a first titanium layer, an aluminum layer, and a second titanium layer provided in sequence, the first titanium layer is the first layer 723, the aluminum layer and the second titanium layer form the second layer 724, and the side surface of the first titanium layer close to the first electrode 71 can be provided as a curved surface, so that the second edge line 7211 forms a curved line; while the side surface of the aluminum layer and the second titanium layer close to the first electrode 71 can be provided as a flat surface, but the aluminum layer and the second titanium layer cannot cover the part of the first titanium layer provided as a curved surface.

[0089] Based on the same inventive concept, the example embodiments of the present disclosure provide an array substrate, which can include the thin film transistor described in any one of the above. The specific structure of the thin film transistor has been described in detail above, and therefore, will not be described here.

[0090] Compared with the prior art, the array substrate provided by the example embodiments of the present disclosure has the same beneficial effects as the thin film transistor provided by the above example embodiments, and therefore, will not be described here.

[0091] Based on the same inventive concept, the example embodiments of the present disclosure provide a display panel, which can include the array substrate described above. The display panel can be a liquid crystal display panel, an OLED display panel, or the like.

[0092] Compared with the prior art, the display panel provided by the example embodiments of the present disclosure has the same beneficial effects as the thin film transistor provided by the example embodiments described above, which will not be repeated here.

[0093] Based on the same inventive concept, the example embodiments of the present disclosure provide a display device, which can include the display panel described above. The display device can be a liquid crystal display, an OLED display, or the like.

[0094] The specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, such as a mobile device such as a mobile phone, a wearable device such as a watch, a VR device, or the like. A person skilled in the art can select a corresponding display device according to the specific use of the display device, which will not be repeated here.

[0095] It should be noted that the display device includes other necessary components and components in addition to the display panel. For example, a display device includes a housing, a circuit board, a power cord, and the like. A person skilled in the art can supplement according to the specific use requirements of the display device, which will not be repeated here.

[0096] Other embodiments of the present disclosure will be readily apparent to those skilled in the art after considering the specification and practice of the disclosed application. The present application is intended to cover any variations, uses, or adaptive changes of the present disclosure that follow the general principles of the present disclosure and include common knowledge or conventional technical means in the art that are not disclosed by the present disclosure. The specification and examples are only considered as exemplary, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A thin-film transistor, located on one side of a substrate, characterized in that, The thin-film transistor includes: The channel portion is disposed on one side of the substrate. A first electrode includes a first surface that contacts the channel portion, and the first surface includes a first edge line. The second electrode is disposed separately from the first electrode. The second electrode includes a second surface that contacts the channel portion. The second surface includes a second edge line located on the side of the second surface closer to the first electrode. The orthographic projection of the second edge line on the substrate is located within the orthographic projection of the channel portion on the substrate. Wherein, the first edge line is located on the side of the first surface closer to the second electrode, and the length of the second edge line is greater than the length of the first edge line, so as to increase the area of ​​the high-resistivity region near the second electrode and reduce the electric field of the high-resistivity region. The first electrode includes a first portion located on the side of the channel portion away from the substrate; the second electrode includes a second portion located on the side of the channel portion away from the substrate; the area of ​​the orthographic projection of the first portion on the substrate is less than or equal to the area of ​​the orthographic projection of the second portion on the substrate.

2. The thin-film transistor according to claim 1, characterized in that, The distance between the start and end points of the first edge line is equal to the distance between the start and end points of the second edge line. The first edge line is a straight line, and the second edge line is a curve.

3. The thin-film transistor according to claim 2, characterized in that, The second edge line includes one or both of the following: an arc and a broken line.

4. The thin-film transistor according to claim 1, characterized in that, The side of the first electrode closest to the second electrode is the first side surface, which is set as a plane, and the line connecting the first side surface and the first surface is the first edge line.

5. The thin-film transistor according to claim 4, characterized in that, The side of the second electrode closest to the first electrode is the second side surface, which is set as a curved surface, and the line connecting the second side surface and the second surface is the second edge line.

6. The thin-film transistor according to claim 1, characterized in that, The first surface is the side of the first portion that is close to the channel portion; the second surface is the side of the second portion that is close to the channel portion.

7. The thin-film transistor according to claim 1, characterized in that, The second electrode includes: The first layer is in contact with the channel portion, and the second edge line is located in the first layer; The second layer is disposed on the side of the first layer away from the substrate. The orthographic projection of the second layer on the substrate overlaps with a portion of the second edge line, or the orthographic projection of the second layer on the substrate does not overlap with the second edge line.

8. The thin-film transistor according to claim 1, characterized in that, The thin-film transistor further includes: A gate is disposed on one side of the substrate. A gate insulating layer is disposed on the side of the gate opposite to the substrate, and the channel portion is disposed on the side of the gate insulating layer opposite to the substrate.

9. The thin-film transistor according to claim 1, characterized in that, The channel portion is made of oxide semiconductor.

10. The thin-film transistor according to claim 1, characterized in that, The first electrode is the source electrode, and the second electrode is the drain electrode.

11. An array substrate, characterized in that, include: The thin-film transistor according to any one of claims 1 to 10.

12. A display panel, characterized in that, include: The array substrate according to claim 11.

13. A display device, characterized in that, include: The display panel according to claim 12.

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