Method for manufacturing thin film transistor array substrate and display panel

Abstract

The application provides a manufacturing method of a thin film transistor array substrate and a display panel. The method comprises the following steps: forming a plurality of dispersed metal oxide crystal grains on a substrate; forming an amorphous metal oxide semiconductor layer in contact with the plurality of metal oxide crystal grains, at least one metal element in the metal oxide crystal grains being the same as a metal element in the metal oxide semiconductor layer; and performing annealing treatment on the amorphous metal oxide semiconductor layer to obtain a crystallized metal oxide semiconductor layer.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a method for manufacturing a thin-film transistor array substrate and a display panel. Background Technology

[0002] As display panels develop towards larger sizes, higher resolutions, higher frequencies, and self-emissive display modes, increasingly higher requirements are being placed on the mobility and stability of thin-film transistors (TFTs) that control the switches and drive the display. Currently, the amorphous silicon TFT devices commonly used in the display industry have low mobility and low on-state current, which cannot meet the needs of high-end display products. In contrast, metal oxide transistors (MOTs) have a mobility that is 10 to 100 times that of amorphous silicon transistors, which can meet the needs of high-end display products. Therefore, MOTs are receiving increasing attention from the industry.

[0003] However, commonly used metal oxide semiconductor layers typically require temperatures above 600°C to crystallize, which presents a problem of excessively high crystallization temperatures. Summary of the Invention

[0004] The purpose of this application is to provide a method for manufacturing a thin-film transistor array substrate and a display panel, so as to reduce the temperature required for crystallization of the crystallized metal oxide semiconductor layer of the thin-film transistor.

[0005] To achieve the above objectives, the technical solution is as follows:

[0006] A method for manufacturing a thin-film transistor array substrate, the method comprising:

[0007] Multiple dispersed metal oxide grains are formed on the substrate;

[0008] An amorphous metal oxide semiconductor layer is formed in contact with a plurality of said metal oxide grains, wherein at least one metal element in said metal oxide grains is the same as the metal element in said metal oxide semiconductor layer;

[0009] The amorphous metal oxide semiconductor layer is annealed to obtain a crystallized metal oxide semiconductor layer.

[0010] A display panel, the display panel comprising a thin-film transistor array substrate, the thin-film transistor array substrate being prepared by the above-described method for manufacturing a thin-film transistor array substrate.

[0011] Beneficial effects: This application provides a method for manufacturing a thin-film transistor array substrate and a display panel. By forming a plurality of dispersed metal oxide grains on the substrate, an amorphous metal oxide semiconductor layer is formed in contact with the plurality of metal oxide grains. At least one metal element in the metal oxide grains is the same as the metal element in the metal oxide semiconductor layer. The amorphous metal oxide semiconductor layer is annealed. The metal oxide grains play a role in inducing crystallization during the annealing process of the metal oxide semiconductor layer, reducing the crystallization temperature required for annealing the amorphous metal oxide semiconductor layer, improving the stability of the metal oxide thin-film transistor, and facilitating the mass production of metal oxide thin-film transistor display panels. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the process for manufacturing a thin-film transistor array substrate according to the first embodiment of this application;

[0013] Figures 2A-2G This is a schematic diagram of the manufacturing process of the thin-film transistor array substrate in the first embodiment of this application;

[0014] Figure 3 for Figure 2C X-ray diffraction patterns of crystalline and amorphous indium tin oxide in the metal oxide film when the metal oxide film layer is an indium tin oxide layer;

[0015] Figure 4 Scanning electron microscope image of multiple dispersed metal oxide grains;

[0016] Figure 5 for Figure 2E Amorphous indium gallium zinc oxide and non-crystalline metal oxide semiconductor layers Figure 2F X-ray diffraction pattern of crystalline indium gallium zinc oxide in a crystalline metal oxide semiconductor layer;

[0017] Figure 6 This is a schematic diagram of the process for manufacturing a thin-film transistor array substrate according to the second embodiment of this application;

[0018] Figure 7 This is a schematic diagram of the process for manufacturing a thin-film transistor array substrate according to the third embodiment of this application;

[0019] Figures 8A-8F This is a schematic diagram of the manufacturing process of the thin-film transistor array substrate in the third embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] Please see Figure 1 This is a schematic diagram illustrating the process of manufacturing a thin-film transistor array substrate according to the first embodiment of this application. The method for manufacturing a thin-film transistor array substrate includes the following steps:

[0022] S100: A gate is formed on the substrate.

[0023] A substrate 10 is provided, and a first conductive layer is formed on the substrate 10 by physical sputtering. The first conductive layer is patterned by a first patterning process to obtain a gate 111, as shown below. Figure 2A As shown. The thickness of the first conductive layer is 800 angstroms to 10000 angstroms, for example, 1000 angstroms, 1500 angstroms, 1600 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 4000 angstroms and 5000 angstroms. The material used to prepare the first conductive layer is selected from at least one of molybdenum, aluminum, titanium, copper and silver.

[0024] S101: A metal oxide film layer is formed on a substrate, the metal oxide film layer including crystalline metal oxide and amorphous metal oxide.

[0025] First, a gate insulating layer 12 covering the gate 111 and the substrate 10 is formed by chemical vapor deposition, such as... Figure 2B As shown. The thickness of the gate insulating layer 12 is 800 angstroms to 3000 angstroms, for example, 1000 angstroms, 1500 angstroms, 1600 angstroms, 2000 angstroms, 2500 angstroms, and 3000 angstroms. The material used to fabricate the gate insulating layer 12 is selected from at least one of silicon nitride or silicon oxide.

[0026] Subsequently, using the first metal oxide target as raw material, a metal oxide film 13 is formed on the gate insulating layer 12 by magnetron sputtering physical vapor deposition in an inert gas, such as... Figure 2C As shown. The metal oxide film 13 comprises crystalline metal oxides and amorphous metal oxides. The thickness of the metal oxide film 13 is greater than or equal to 200 nm and less than or equal to 1500 nm, for example, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 1000 nm, 1200 nm, 1300 nm, and 1500 nm. The metal in the metal oxide film 13 includes one or two of In, Ga, Zn, and Sn. The inert gas includes argon.

[0027] Specifically, the first metal oxide target is an indium tin oxide (ITO) target, and the thickness of the metal oxide film 13 is 1500 angstroms.

[0028] like Figure 3 As shown, when the metal oxide film 13 is an indium tin oxide layer, the indium tin oxide layer includes crystalline indium tin oxide and amorphous indium tin oxide. The crystallization peak of crystalline indium tin oxide is at 30.69°, while no obvious crystallization peak is observed in amorphous indium tin oxide.

[0029] It should be noted that indium tin oxide is a mixture of indium oxide (In2O3) and tin oxide (SnO2), with indium oxide (In2O3) accounting for approximately 90% by weight. Crystalline indium tin oxide is predominantly composed of indium oxide, with some tin oxide dissolved in the indium oxide lattice. Crystalline indium tin oxide induces the growth of indium oxide along crystal nuclei in amorphous semiconductor layers containing indium oxide, thereby transforming the amorphous semiconductor layer into a crystalline semiconductor layer.

[0030] It is understandable that the metal oxide film 13 can also be made of indium oxide, zinc oxide, or indium zinc oxide. Compared to the metal oxide film 13, which can also be made of indium oxide, zinc oxide, or indium zinc oxide, indium tin oxide is a commonly used material in display panel manufacturing processes, and its technology is very mature.

[0031] S102: Remove amorphous metal oxides to obtain multiple dispersed metal oxide grains.

[0032] Multiple amorphous metal oxides are removed by wet etching, resulting in multiple dispersed metal oxide grains 131 located on the surface of the gate insulating layer 12 away from the gate 111, such as... Figure 2D As shown. The size of the metal oxide grains 131 is greater than or equal to 5 nanometers and less than or equal to 100 nanometers. For example, the size of the metal oxide grains is 10 nanometers, 20 nanometers, 30 nanometers, 40 nanometers, 50 nanometers, 60 nanometers, 70 nanometers, or 80 nanometers, to ensure the crystallization-inducing properties of the metal oxide grains 131 while preventing the metal oxide grains 131 from agglomerating into flakes. The solvent for wet etching is oxalic acid or nitric acid.

[0033] like Figure 4 As shown, when the metal oxide film 13 is indium tin oxide, multiple crystalline indium tin oxide grains (white parts) are randomly dispersed.

[0034] It should be noted that, because the etching rate of crystalline metal oxides is much lower than that of amorphous metal oxides during wet etching, multiple dispersed metal oxide grains composed of crystalline metal oxides will remain after the amorphous metal oxides are etched. For example, the etching rate of crystalline indium tin oxide is only about 1 / 100 of that of amorphous indium tin oxide; therefore, crystalline indium tin oxide will remain after the amorphous indium tin oxide is etched.

[0035] In addition, compared with inducing the subsequent crystallization of amorphous metal oxide semiconductor layers by crystalline oxides in metal oxide films, there is a problem that crystalline oxides in metal oxide films are difficult to contact with amorphous metal oxide semiconductor layers, making it difficult to induce the crystallization of amorphous metal oxide semiconductor layers. In this application, the amorphous metal oxides in the metal oxide film are removed, while metal oxide grains composed of crystalline oxides are retained. The metal oxide grains are used to induce the crystallization of the subsequently formed amorphous metal oxide semiconductor layers. The metal oxide grains can contact the amorphous metal oxide semiconductor layers more fully and are more likely to induce the crystallization of amorphous metal oxide semiconductor layers at lower temperatures.

[0036] Furthermore, when the metal oxide film 13 is made of indium tin oxide, the indium tin oxide layer is conductive. Directly inducing the subsequent amorphous metal oxide semiconductor layer to crystallize using the conductive metal oxide film 13 would cause the conductive metal oxide film 13 to conduct through the channel of the metal oxide semiconductor layer, thereby causing the channel function of the metal oxide semiconductor layer to fail. Additionally, when the metal oxide film 13 is made of indium oxide, zinc oxide, or indium zinc oxide, inducing the amorphous metal oxide semiconductor layer to crystallize using the crystalline oxide in the metal oxide film 13 would result in the metal oxide film 13 having a semiconductor front channel, which is inconsistent with the design of the subsequently formed metal oxide semiconductor film having a semiconductor front channel.

[0037] S103: Forming an amorphous metal oxide semiconductor layer in contact with multiple metal oxide grains, wherein at least one metal element in the metal oxide grains is the same as the metal element in the metal oxide semiconductor layer.

[0038] Using a second metal oxide target as raw material, an amorphous metal oxide semiconductor layer 14 is formed on the gate insulating layer 12 by magnetron sputtering physical vapor deposition in a mixed atmosphere of inert gas and oxygen. Figure 2EAs shown. The metal oxide semiconductor layer 14 has a thickness greater than or equal to 10 nanometers and less than or equal to 2000 nanometers, for example, 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, 300 nanometers, 500 nanometers, 800 nanometers, 1000 nanometers, 1200 nanometers, 1500 nanometers, 1600 nanometers, and 1800 nanometers. The metal element in the metal oxide semiconductor layer 14 includes at least three of In, Ga, Zn, and Sn. The inert gas includes argon.

[0039] At least one metal element in the metal oxide grains is the same as the metal element in the metal oxide semiconductor layer, so that the metal oxide grains can induce the crystallization of the amorphous metal oxide semiconductor layer during annealing. For example, the metal element in the metal oxide semiconductor layer 14 includes In, Ga, and Zn, and the metal element in the metal oxide grains 131 includes at least one of In, Ga, and Zn. Alternatively, the metal element in the metal oxide semiconductor layer includes In, Ga, and Sn, and the metal element in the metal oxide grains includes at least one of In, Ga, and Sn.

[0040] Specifically, when the metal oxide film layer 13 is an indium tin oxide layer, the second metal oxide target is an indium gallium zinc oxide layer, and the metal oxide semiconductor layer 14 is an indium gallium zinc oxide layer.

[0041] like Figure 5 As shown, Figure 5 Lines 1 and 2 are X-ray diffraction patterns of amorphous indium gallium zinc oxide obtained under different deposition powers. The peaks in the dashed boxes are the crystallization characteristic peaks of the glass substrate. No other related crystallization characteristic peaks were found. Therefore, amorphous indium gallium zinc oxide does not have crystallization characteristic peaks.

[0042] S104: Annealing the amorphous metal oxide semiconductor layer to obtain a crystallized metal oxide semiconductor layer.

[0043] Specifically, the amorphous metal oxide semiconductor layer 14 is heated for 0.5 to 1.5 hours at an annealing temperature greater than or equal to 300 degrees Celsius and less than or equal to 450 degrees Celsius. Then, a second patterning process is used to pattern the annealed metal oxide semiconductor layer 14 to obtain a crystallized metal oxide semiconductor layer 141. Figure 2F As shown. The annealing temperature can be 320 degrees, 350 degrees, 380 degrees, 400 degrees, 420 degrees and 450 degrees, and the annealing time can be 30 minutes, 40 minutes, 50 minutes, 60 minutes or 80 minutes.

[0044] like Figure 5 As shown, Figure 5Lines 3 and 4 are X-ray diffraction patterns of crystalline indium gallium zinc oxide (IGaZ) obtained by annealing amorphous IGaZ layers at different deposition powers. The characteristic crystallization peak of crystalline IGaZ is approximately at 30°. (Combined with...) Figure 5 As can be seen from lines 3 and 4, depositing amorphous indium gallium zinc oxide layers under different deposition conditions does not affect the crystallization of crystalline indium gallium zinc oxide.

[0045] It should be noted that, since at least one metal element in the metal oxide grain is the same as the metal element in the metal oxide semiconductor layer, the lattice parameters of the crystal in the metal oxide grain are similar to those of the crystal in the crystalline metal oxide semiconductor layer. The metal oxide grain acts as a crystal nucleus, inducing the amorphous metal oxide semiconductor layer to crystallize at temperatures below 450 degrees Celsius. Compared to the crystallization temperature of traditional metal oxide semiconductor layers, which is greater than or equal to 600 degrees Celsius, this significantly reduces the crystallization temperature of the amorphous metal oxide semiconductor layer, which is beneficial for the mass production of crystalline metal oxide thin film transistors and improves the device stability of metal oxide transistors.

[0046] S105: Source and drain electrodes are formed on the substrate, and the source and drain electrodes are in contact with the crystallized metal oxide semiconductor layer to obtain a thin film transistor array substrate.

[0047] Specifically, a second conductive layer covering a crystallized metal oxide semiconductor layer 141 and a gate insulating layer 12 is formed by physical sputtering deposition. A third patterning process is then used to pattern the second conductive layer to obtain a thin-film transistor array substrate. The thin-film transistor array substrate includes source and drain electrodes, with source 151 and drain 152, as shown below. Figure 2G As shown. The thickness of the second conductive layer is 1000 angstroms to 10000 angstroms. The material used to prepare the second conductive layer is selected from at least one of molybdenum, aluminum, titanium, copper, and silver.

[0048] The manufacturing method of the thin-film transistor array substrate in this embodiment involves forming multiple dispersed metal oxide grains on the substrate to form an amorphous metal oxide semiconductor layer in contact with the multiple metal oxide grains. At least one metal element in the metal oxide grains is the same as the metal element in the metal oxide semiconductor layer. The amorphous metal oxide semiconductor layer is annealed. During the annealing process of the metal oxide semiconductor layer, the metal oxide grains play a role in inducing crystallization, reducing the crystallization temperature required for annealing the amorphous metal oxide semiconductor layer, improving the stability of the metal oxide thin-film transistor, and facilitating the mass production of the metal oxide thin-film transistor array substrate.

[0049] Please see Figure 6 This is a schematic diagram of the process for manufacturing a thin-film transistor array substrate in the second embodiment of this application. Figure 6The flowchart shown is consistent with Figure 1 The flowcharts shown are basically similar, with the difference being that... Figure 6 S106 replacement Figure 1 S101, and Figure 6 S107 replacement Figure 1 S102.

[0050] S106 is basically similar to S101, except that the thickness of the metal oxide film 13 is greater than or equal to 10 nanometers and less than or equal to 200 nanometers. That is, the thickness of the metal oxide film 13 in S106 is thinner, for example, 10 nanometers, 15 nanometers, 20 nanometers, 50 nanometers or 100 nanometers.

[0051] S107 involves annealing the metal oxide film 13 to obtain multiple dispersed metal oxide grains 131. The annealing conditions are a temperature greater than or equal to 100 degrees Celsius and less than or equal to 400 degrees Celsius, and a time greater than or equal to 1 minute and less than or equal to 2 hours. The annealing temperature of the metal oxide film 13 can be 120 degrees Celsius, 150 degrees Celsius, 180 degrees Celsius, 200 degrees Celsius, 220 degrees Celsius, 250 degrees Celsius, 300 degrees Celsius, 320 degrees Celsius, 350 degrees Celsius, or 380 degrees Celsius, and the annealing time can be 1 minute, 3 minutes, 15 minutes, 30 minutes, 50 minutes, 60 minutes, 80 minutes, 90 minutes, or 120 minutes.

[0052] Compared to the first embodiment, which involves fabricating a thicker metal oxide film and then etching it to obtain multiple metal oxide grains, this embodiment involves fabricating a thinner metal oxide film and then annealing it. During the annealing process, the thinner metal oxide film crystallizes and shrinks in volume, thereby obtaining multiple dispersed metal oxide grains.

[0053] Please see Figure 7 This is a schematic diagram of the process for manufacturing a thin-film transistor array substrate according to the third embodiment of this application. The method for manufacturing the thin-film transistor array substrate includes:

[0054] S200: Multiple dispersed metal oxide grains are formed on the substrate.

[0055] Specifically, the methods in steps S101 and S102 of the first embodiment are used sequentially, or the methods in steps S106 and S107 of the second embodiment are used sequentially, to form a plurality of dispersed metal oxide grains 131 on the surface of the substrate 10, such as... Figure 8A As shown.

[0056] S201: An amorphous metal oxide semiconductor layer is formed in contact with multiple metal oxide grains, wherein at least one metal element in the metal oxide grains is the same as the metal element in the metal oxide semiconductor layer.

[0057] Specifically, using the method of step S103 in the first embodiment described above, an amorphous metal oxide semiconductor layer 14 is formed covering the substrate 10 and a plurality of dispersed metal oxide grains 131, such as... Figure 8B As shown.

[0058] S202: Annealing the amorphous metal oxide semiconductor layer to obtain a crystallized metal oxide semiconductor layer.

[0059] Specifically, the method of step S104 in the first embodiment described above is used to form a crystallized metal oxide semiconductor layer 141, such as... Figure 8C As shown; a gate insulating layer 12 covering the crystallized metal oxide semiconductor layer 141 and the substrate 10 is formed by chemical vapor deposition, such as... Figure 8D As shown.

[0060] S203: A gate electrode is formed on the substrate.

[0061] Specifically, a gate 111 is formed on the side of the gate insulating layer 12 away from the crystalline metal oxide semiconductor layer 141; an interlayer insulating layer 16 covering the gate 111 and the gate insulating layer 12 is formed by chemical vapor deposition, and the interlayer insulating layer 16 and the gate insulating layer 12 are processed by photolithography and etching processes to obtain a first contact hole 16a and a second contact hole 16b penetrating the interlayer insulating layer 16 and the gate insulating layer 12. The first contact hole 16a and the second contact hole 16b are located on opposite sides of the gate 111 and are disposed corresponding to the crystalline metal oxide semiconductor layer 141. Figure 8E As shown.

[0062] The thickness of the interlayer insulating layer 16 is 3000 angstroms to 6000 angstroms. The material used to prepare the interlayer insulating layer 16 is selected from at least one of silicon nitride and silicon oxide.

[0063] S204: Source and drain electrodes are formed on the substrate, and the source and drain electrodes are in contact with the crystallized metal oxide semiconductor layer to obtain a thin film transistor array substrate.

[0064] Specifically, using the method of step S105 in the first embodiment described above, a source electrode 151 and a drain electrode 152 are formed. The source electrode 151 is in contact with the crystallized metal oxide semiconductor layer 141 through a first contact hole 16a, and the drain electrode 152 is in contact with the crystallized metal oxide semiconductor layer 141 through a second contact hole 16b. Figure 8F As shown.

[0065] This application also provides a thin-film transistor array substrate, which is prepared by any of the above-described methods for manufacturing thin-film transistor array substrates.

[0066] This application also provides a display panel, which includes the aforementioned thin-film transistor array substrate.

[0067] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for manufacturing a thin film transistor array substrate, characterized by, The method comprises: forming a metal oxide film layer on the substrate, the metal oxide film layer comprising crystalline metal oxide and amorphous metal oxide; removing a plurality of the amorphous metal oxide to obtain a plurality of dispersed metal oxide grains; forming an amorphous metal oxide semiconductor layer in contact with a plurality of the metal oxide grains, at least one metal element in the metal oxide grains being the same as a metal element in the metal oxide semiconductor layer; annealing the amorphous metal oxide semiconductor layer to obtain a crystallized metal oxide semiconductor layer.

2. The method of manufacturing a thin film transistor array substrate according to claim 1, wherein The annealing process has a time greater than or equal to 1 min and less than or equal to 2 h.

3. The method of claim 1, wherein the photoresist is exposed to light through a mask having a pattern of a plurality of lines and spaces. The metal oxide film layer has a thickness greater than or equal to 10 nm and less than or equal to 200 nm.

4. The method of claim 1, wherein the photoresist is exposed to light through a mask having a pattern of a plurality of lines and spaces. The annealing process has a temperature greater than or equal to 100 °C and less than or equal to 400 °C.

5. The method of claim 1, wherein the photoresist is exposed to light through a mask having a pattern of a plurality of lines and spaces. The metal oxide film layer can comprise indium tin oxide, indium oxide, zinc oxide, or indium zinc oxide.

6. The method of claim 1, wherein the photoresist is exposed to light through a mask having a pattern of a plurality of lines and spaces. The metal oxide film layer has a thickness greater than or equal to 200 nm and less than or equal to 1500 nm.

7. The method of claim 1, wherein the photoresist is exposed to light through a mask having a pattern of a plurality of lines and spaces. The removing a plurality of the amorphous metal oxide comprises: etching to remove a plurality of the amorphous metal oxide.

8. The method for manufacturing a thin film transistor array substrate according to claim 1, 2 or 5, wherein The metal oxide grains have a size greater than or equal to 5 nm and less than or equal to 100 nm.

9. The method of manufacturing a thin film transistor array substrate according to any one of claims 1 to 7, wherein The metal elements in the metal oxide semiconductor layer comprise at least three of In, Ga, Zn, and Sn, and the metal elements in the metal oxide grains comprise one or two of In, Ga, Zn, and Sn.

10. The method of claim 9, wherein the photoresist is exposed to light through the mask. The metal oxide grains are prepared from indium tin oxide, and the metal oxide semiconductor layer is prepared from indium gallium zinc oxide.

11. The method of manufacturing a thin film transistor array substrate according to any one of claims 1 to 7, wherein The annealing the amorphous metal oxide semiconductor layer comprises: heating the amorphous metal oxide semiconductor layer at a temperature greater than or equal to 300 °C and less than or equal to 450 °C for 0.5 h to 1.5 h.

12. The method of manufacturing a thin film transistor array substrate according to claim 1, wherein Before forming a plurality of dispersed metal oxide grains on the substrate, the method further comprises: forming a gate on the substrate; and forming a gate insulating layer on the gate and the substrate; The forming a plurality of dispersed metal oxide grains on the substrate comprises: forming a plurality of dispersed metal oxide grains on a surface of the gate insulating layer away from the gate.

13. The method of claim 1, wherein the photoresist is exposed to light through a mask having a pattern of a plurality of lines and spaces. The forming a plurality of dispersed metal oxide grains on the substrate comprises: forming a plurality of dispersed metal oxide grains on a surface of the substrate; After forming the crystallized metal oxide semiconductor layer, the method further comprises: forming a gate insulating layer on the crystallized metal oxide semiconductor layer; and forming a gate on the gate insulating layer.

14. A display panel, characterized by The display panel comprises a thin film transistor array substrate prepared by the method for manufacturing a thin film transistor array substrate according to any one of claims 1-13.

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