In-memory computing (CIM) module

Abstract

An in-memory computing (CIM) module includes: a transistor array computer, each unit cell of which includes at least one transistor and at least one resistive random access memory (ReRAM); a buffer; and a weight gradient computer including at least one unit transistor. The weight gradient computer includes: a row digital-to-analog converter (DAC) configured to apply a voltage corresponding to an initial input voltage value (dI / dG = V) used in multiplication and accumulation (MAC) calculation to a first electrode of a unit transistor; a column DAC configured to apply, to a second electrode of the unit transistor, a voltage corresponding to a change amount (dE / dI) of an error of the MAC calculation with respect to a current value formed as a result of performing the MAC calculation; and an analog-to-digital converter (ADC) configured to output a digital signal corresponding to a current flowing into the third electrode of the unit transistor.

Description

[0001] Cross - reference to related applications

[0002] This patent document claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0129084, filed with the Korean Intellectual Property Office on September 24, 2024, the disclosure of which is incorporated herein by reference in its entirety as part of the disclosure of this application. Technical field

[0003] The technology and implementation disclosed in this patent document generally relate to semiconductor devices, and more particularly, to a weight gradient computer included in an in - memory computing (CIM) module. Background art

[0004] Computers designed to use semiconductor devices include a processor for performing information processing and a memory for providing data to the processor for such information processing. Program commands (instructions) and data required for the operation of the computer are loaded into the memory, and the data is processed according to the commands (or instructions) of the processor.

[0005] The amount of data exchanged between the processor and the memory is limited, such that the data processing speed may be restricted. When the amount of large - volume data such as images, audio, or video increases, an unexpected situation may occur where the speed of retrieving (or loading) necessary information from the memory cannot keep up with the performance of the processor.

[0006] To overcome the above problems, recently, in - memory computing technologies have emerged, for example, in - memory analog computing (ACiM) that enables simultaneous operation and storage due to the characteristics of non - volatile memory, or in - memory processing (PiM) that integrates a processor and a memory to simultaneously perform data processing and memory access. Summary of the invention

[0007] Various embodiments of the present disclosure relate to technologies capable of improving the power consumption efficiency of an in - memory computing (CIM) module designed to use semiconductor devices.

[0008] Various embodiments of the present disclosure relate to technologies for a transistor array used in a weight gradient computer, which improve the efficiency of the area required for device design and / or the number of transistors used in the transistor array, and reduce the cost required for such a design.

[0009] According to one embodiment of this disclosure, an in-memory computing (CIM) module may include: a transistor array computer, each unit cell of which includes at least one transistor and at least one resistive random access memory (ReRAM); a buffer; and a weighted gradient computer, which includes at least one unit transistor. The weighted gradient computer may include: a row digital-to-analog converter (DAC) configured to apply a voltage corresponding to an initial input voltage value (dI / dG = V) used in multiplication and accumulation (MAC) calculations to a first electrode of the unit transistor; a column digital-to-analog converter (DAC) configured to apply a voltage corresponding to an amount of change (dE / dI) in the error of the MAC calculation relative to the current value formed as a result of performing the MAC calculation to a second electrode of the unit transistor; and an analog-to-digital converter (ADC) configured to output a digital signal corresponding to the current flowing into a third electrode of the unit transistor.

[0010] According to another embodiment of this disclosure, an in-memory computing (CIM) module may include: a first transistor array in which a plurality of unit transistors are arranged; and a second transistor array configured to perform multiplication and accumulation (MAC) calculations. The first transistor array may include: a first row digital-to-analog converter (DAC) configured to apply a voltage corresponding to a first initial input voltage value used in the MAC calculation to the drain electrode of a unit transistor arranged in the first row of the first transistor array; a first column DAC configured to apply a voltage corresponding to a change in a first error of the MAC calculation relative to a first current value formed as a result of performing the MAC calculation to the gate electrode of a unit transistor arranged in the first column of the first transistor array; and a first analog-to-digital converter (ADC) configured to output a digital signal corresponding to the current flowing into the source electrode of a unit transistor arranged in the first column.

[0011] According to another embodiment of this disclosure, an in-memory computing (CIM) module may include: a transistor array computer, each unit cell including at least one transistor and at least one resistive random access memory (ReRAM); a buffer; and a weighted gradient computer, wherein the unit transistors are arranged in multiple rows and multiple columns. The weighted gradient computer may include: multiple bit lines configured to transmit signals corresponding to initial input voltage values ​​used in multiplication and accumulation (MAC) calculations to first electrodes of the unit transistors arranged in each row; multiple word lines configured to transmit signals corresponding to changes in the error of the MAC calculation relative to current values ​​resulting from performing the MAC calculations to second electrodes of the unit transistors arranged in each column; and multiple source lines configured to transmit signals corresponding to currents flowing into third electrodes of the unit transistors arranged in each column.

[0012] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0013] The above and other features and advantages of this disclosure will become apparent when considered in conjunction with the accompanying drawings and the following detailed description.

[0014] Figure 1 This is a block diagram illustrating an example of an in-memory computing (CIM) module according to some embodiments of the present disclosure.

[0015] Figure 2 This is a block diagram illustrating an example structure of a transistor array computer according to some embodiments of the present disclosure.

[0016] Figure 3 This is a block diagram illustrating an example structure of a weighted gradient computer according to some embodiments of the present disclosure.

[0017] Figure 4 This is a block diagram illustrating example operation of an apparatus for calculating weight gradients according to some embodiments of the present disclosure.

[0018] Figure 5 This is a diagram illustrating a unit cell of a transistor array computer according to some embodiments of the present disclosure.

[0019] Figure 6 and Figure 7 This is a diagram illustrating an example of a unit transistor in a weighted gradient computer according to some embodiments of the present disclosure.

[0020] Figure 8A This is a diagram illustrating an example of an inference artificial neural network (ANN) model according to some embodiments of the present disclosure.

[0021] Figure 8B This is a diagram illustrating examples of training artificial neural network (ANN) models according to some embodiments of the present disclosure. Detailed Implementation

[0022] This patent document provides implementations and examples of a weighted gradient computer included in an in-memory computing (CIM) module, which can be used in a configuration to substantially solve one or more technical or engineering problems and mitigate some limitations or drawbacks encountered in other weighted gradient computers. Some implementations of this disclosure relate to techniques capable of improving the power efficiency of in-memory computing (CIM) modules designed to use semiconductor devices. Some implementations of this disclosure relate to techniques for transistor arrays used in weighted gradient computers that improve the efficiency of the area required for device design and / or the number of transistors used in the transistor array, and reduce the cost required for such designs. Recognizing the above problems, this disclosure can provide an in-memory computing (CIM) that improves the area and power efficiency of the transistor array used in a weighted gradient computer included in a CIM module.

[0023] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Although the present disclosure may have various modifications and alternatives, specific embodiments are shown in the drawings by way of example only. However, the present disclosure should not be construed as being limited to the embodiments described herein.

[0024] Various embodiments will be described below with reference to the accompanying drawings. However, it should be understood that this disclosure is not limited to any particular embodiment, but includes various modifications, equivalents, and / or alternatives to the embodiments. Embodiments of this disclosure can provide a variety of effects that can be directly or indirectly recognized through this disclosure.

[0025] Figure 1 This is a block diagram illustrating an example of an in-memory computing (CIM) module according to some embodiments of the present disclosure.

[0026] Reference Figure 1 The CIM module 1000 can be implemented as part of a computing (arithmetic) device that performs data processing. The CIM module 1000 integrates the processor and memory into a single unit, allowing data stored in memory to be directly computed and processed by the processor in parallel. Therefore, the CIM module 1000 can improve power efficiency and data processing speed. For example, because the CIM module 1000 integrates memory and processor into a single module, it can reduce the space, power, and / or time consumption required for data communication between memory and processor.

[0027] Specifically, the CIM module 1000 can be used for machine learning or deep learning algorithms. Machine learning or deep learning algorithms may require large amounts of reference data and may require multiplication and accumulation (MAC) calculations on the reference data. For example, machine learning and / or deep learning algorithms may require multiplication and accumulation (MAC) calculations corresponding to operations that multiply gradient data or vectors by large amounts of reference data and sum the results.

[0028] According to one implementation, given the large amount of reference data that serves as the target of MAC calculations, machine learning or deep learning algorithms can utilize the CIM module 1000 to simultaneously access memory, perform data operations on the processor, and store data in memory, thereby improving the efficiency of calculations such as multiplication or addition. For example, in the CIM module 1000, since the memory and processor are integrated, the space, power, and / or time consumption required to transfer large amounts of reference data from memory to the processor can be reduced.

[0029] According to one implementation, CIM module 1000 may include transistor array computer 1100, global buffer 1200, weight gradient computer 1300, and / or global buffer controller 1400. In one example, CIM module 1000 may integrate one or more data processing devices (e.g., transistor array computer 1100 or weight gradient computer 1300) and data storage devices (e.g., global buffer 1200) into a single module. In one example, the data processing devices (such as transistor array computer 1100 or weight gradient computer 1300 of CIM module 1000) may perform operations (or calculations) such as addition or multiplication in rapid parallel execution.

[0030] According to one implementation, the transistor array computer 1100 can receive input data (ID) from the global buffer 1200. In one example, the transistor array computer 1100 can output input gradient data (IGD) based on the input data (ID).

[0031] According to one implementation, the input data (ID) transferred from the global buffer 1200 to the transistor array computer 1100 may include reference data for which MAC calculations are performed. For example, the input data (ID) may include image, audio, video data, and / or target data that needs to be inferred.

[0032] According to one implementation, the input gradient data (IGD) transmitted from the transistor array computer 1100 to the global buffer 1200 may correspond to data generated by the transistor array computer 1100 after processing the input data (ID). In one example, the input gradient data (IGD) may include input data and / or output data of a MAC calculation performed on image, audio, video data, and / or target data to be inferred. In one example, the input gradient data (IGD) may include data corresponding to the initial input voltage value and threshold voltage value used in the MAC calculation and / or the current value formed as a result of performing the MAC calculation.

[0033] In one implementation, the initial input voltage value used in the MAC calculation may correspond to the image, audio, image data, and / or target data to be inferred. In one example, the threshold voltage value used in the MAC calculation may correspond to the minimum voltage that must be applied to the gate electrode of the transistor in order to generate current in the transistor performing the MAC calculation. In one example, the current value generated as a result of performing the MAC calculation may correspond to the data corresponding to the result value of performing the MAC calculation on the image, audio, image data, and / or target data to be inferred.

[0034] According to one implementation, the transistor array computer 1100 can receive error data for MAC calculation from the global buffer 1200. For example, the global buffer 1200 can transmit data to the transistor array computer 1100 corresponding to the difference between a target value and the resulting value of the MAC calculation performed on the image, audio, video, and / or target data to be inferred. In one example, input gradient data (IGD) transmitted from the transistor array computer 1100 to the global buffer 1200 may include error data for the MAC calculation of the transistor array computer 1100.

[0035] According to one implementation, the weight gradient data (WGD) transferred from the global buffer 1200 to the transistor array computer 1100 can correspond to the weight gradient data (WGD) transferred from the weight gradient computer 1300 to the global buffer 1200.

[0036] According to one implementation, the global buffer 1200 can transmit input data (ID) to the transistor array computer 1100. In one example, the global buffer 1200 can receive input gradient data (IGD) from the transistor array computer 1100. In one example, the global buffer 1200 can transmit weight gradient data (WGD) to the transistor array computer 1100. In one example, the CIM module 1000 can perform inference artificial neural network (ANN) computations based on the input data (ID) and / or input gradient data (IGD) that can be transmitted and received (i.e., communicated) between the global buffer 1200 and the transistor array computer 1100. See below for further details. Figure 8A Provide a detailed description of the computation of inference artificial neural networks (ANNs).

[0037] According to one implementation, the global buffer 1200 can transmit input gradient data (IGD) to the weight gradient computer 1300. In one example, the global buffer 1200 can receive weight gradient data (WGD) from the weight gradient computer 1300. The global buffer 1200 can transmit the weight gradient data (WGD) received from the weight gradient computer 1300 to the transistor array 1100. In one example, the CIM module 1000 can perform training an artificial neural network (ANN) computation based on the input gradient data (IGD) communicated between the global buffer 1200 and the weight gradient computer 1300 and / or the weight gradient data (WGD) transmitted to the transistor array 1100. The training of the artificial neural network (ANN) computation can correspond to the operation of updating the gradient data used in the MAC computation based on the weight gradient data (WGD). See below for further details. Figure 8B Provide a detailed description of the computation for training an artificial neural network (ANN).

[0038] According to one implementation, the global buffer 1200 can transmit and receive buffer control data (BCD) from the global buffer controller 1400. In one example, the CIM module 1000 can control the storage and transmission of data required for MAC calculation, input gradient calculation, or weight gradient calculation based on the buffer control data (BCD) communicated between the global buffer 1200 and the global buffer controller 1400. For example, the buffer control data (BCD) may include data indicating the time and / or location at which at least one of the input data (ID), input gradient data (IGD), and weight gradient data (WGD) is transmitted or stored.

[0039] According to one implementation, the weight gradient computer 1300 can receive input gradient data (IGD) from the global buffer 1200. In one example, the weight gradient computer 1300 can output weight gradient data (WGD) based on the input gradient data (IGD).

[0040] According to one implementation, the input gradient data (IGD) transmitted from the global buffer 1200 to the weighted gradient computer 1300 may correspond to the input gradient data (IGD) transmitted from the transistor array computer 1100 to the global buffer 1200. In one example, the input gradient data (IGD) transmitted from the global buffer 1200 to the weighted gradient computer 1300 may include error data for the MAC calculation of the transistor array computer 1100.

[0041] According to one embodiment, the weighted gradient data (WGD) transmitted from the global buffer 1200 to the weighted gradient computer 1300 may include data obtained by performing a MAC calculation on the data included in the input gradient data (IGD). For example, the weighted gradient data (WGD) may include data corresponding to the result of performing a MAC calculation on the initial input voltage value and the error data included in the input gradient data (IGD). See below for further details. Figure 3 A detailed description of the weighted gradient computer 1300 is given.

[0042] According to one implementation, the global buffer controller 1400 can transmit and receive buffer control data (BCD) to and from the global buffer 1200. In one example, the buffer control data (BCD) may include an activation signal, an accumulation signal, or a pooling signal. In one example, the CIM module 1000 can control the storage and transmission of data (e.g., at least one of input data ID, input gradient data IGD, and weight gradient data WGD) required for MAC calculation, input gradient calculation, or weight gradient calculation based on the buffer control data (BCD).

[0043] According to one implementation, based on the activation signal of buffer control data (BCD), the calculation results of data processing devices (such as transistor array computer 1100 and / or weight gradient computer 1300) can be stored in global buffer 1200 or transmitted to the necessary location.

[0044] According to one implementation, the calculation results of the data processing device (such as transistor array computer 1100 and / or weight gradient computer 1300) can be accumulated or summed based on the accumulation signal of buffer control data (BCD).

[0045] According to one implementation, based on the pooling signal of buffer control data (BCD), some processes can be omitted or some data can be extracted during the calculation process of a data processing device such as a transistor array computer 1100 and / or a weight gradient computer 1300 used in the CIM module 1000.

[0046] Figure 2 This is a block diagram illustrating an example structure of a transistor array computer according to some embodiments of the present disclosure.

[0047] Reference Figure 1 and Figure 2 The transistor array computer 1100 can receive input data (ID) and output input gradient data (IGD). In one example, the transistor array computer 1100 may include at least one of the following: an input buffer 1150, an accumulator circuit 1160, an output buffer 1170, and first to fourth processing elements (PEs) (1110, 1120, 1130, 1140). Although this disclosure assumes that the transistor array computer 1100 includes first to fourth processing elements (1110, 1120, 1130, 1140), the scope or spirit of this disclosure is not limited thereto, and it should be noted that the number of processing elements in the transistor array computer 1100 is not limited thereto. The configuration of the transistor array computer 1100 according to this disclosure is merely an example, and some components may be added or omitted in the configuration of the transistor array computer 1100. In one embodiment, the transistor array computer 1100 may further include processing elements. In another embodiment, at least some components of the input buffer 1150 or the output buffer 1170 may be included in an external module, such as a global buffer 1200 (see [link to documentation]). Figure 1 ).

[0048] According to one implementation, the first to fourth processing elements (PEs) (1110, 1120, 1130, 1140) can receive first to fourth input data (ID1, ID2, ID3, ID4) respectively from the input buffer 1150, and can output first to fourth input gradient data (IGD1, IGD2, IGD3, IGD4) respectively in response to the received input data. In one example, the first to fourth input data (ID1, ID2, ID3, ID4) may correspond to the data included in the input data (ID).

[0049] According to one embodiment, the input buffer 1150 can classify the input data (ID) according to the positions of the first to fourth processing elements (1110, 1120, 1130, 1140), and can transmit the classification results to the first to fourth processing elements (1110, 1120, 1130, 1140). For example, the first processing element (PE) 1100 (in Figure 2 The input buffer (represented by "first PE") can receive the first input data (ID1) from the input buffer 1150.

[0050] According to one embodiment, the first to fourth processing elements (PEs) (1110, 1120, 1130, 1140) can generate and output the first to fourth input gradient data (IGD1, IGD2, IGD3, IGD4), respectively. For example, the first processing element (PE) 1110 can transmit the first input gradient data (IGD1) to the accumulator circuit 1160.

[0051] According to one implementation, the accumulator circuit 1160 can receive first to fourth input gradient data (IGD1, IGD2, IGD3, IGD4) from the first to fourth processing elements (PEs) (1110, 1120, 1130, 1140), respectively. In one example, the accumulator circuit 1160 can generate input gradient data (IGD) by summing the received first to fourth input gradient data (IGD1, IGD2, IGD3, IGD4).

[0052] According to one implementation, the output buffer 1170 may store input gradient data (IGD) received from the accumulator circuit 1160. In one example, the output buffer 1170 may transfer the stored input gradient data (IGD) to the global buffer 1200 (see [link to global buffer]). Figure 1 ).

[0053] According to one embodiment, a processing element (PE) may include one or more input gradient transistor arrays. In one example, a first processing element (PE) 1110 may include at least one of the following: a processing element (PE) input buffer 1111, a first to fourth input gradient transistor array (1112, 1113, 1114, 1115), an adder tree 1116, and a processing element (PE) output buffer 1117. Although this disclosure will assume that the first processing element (PE) 1110 includes the first to fourth input gradient transistor arrays (1112, 1113, 1114, 1115), other implementations are possible, and it should be noted that the number of input gradient transistor arrays in the first processing element is not limited thereto. The configuration of the processing element (PE) according to this disclosure is merely illustrative, and certain configurations may be added to or omitted from the processing element (PE). In one embodiment, the processing element (PE) may further include an input gradient transistor array. In another embodiment, at least some configurations of the processing element (PE) input buffer 1111 or the processing element (PE) output buffer 1117 may be included in an external module, such as a global buffer 1200 (see [link]). Figure 1 ).

[0054] According to one embodiment, the processing element (PE) input buffer 1111 of the first processing element (PE) 1110 can transmit the classified first input data ID1 from the input buffer 1150 in the form of classified first input data (ID1_1, ID1_2, ID1_3, ID1_4) to the first to fourth input gradient transistor arrays (1112, 1113, 1114, 1115). For example, the first input gradient transistor (IGT) array 1112 of the first processing element (PE) 1110 can receive the first first input data (ID1_1) from the processing element (PE) input buffer 1111.

[0055] According to one embodiment, the first to fourth input gradient transistor arrays (1112, 1113, 1114, 1115) of the first processing element (PE) 1110 can receive classified first input data (ID1_1, ID1_2, ID1_3, or ID1_4) from the processing element (PE) input buffer 1111, and can output classified first input gradient data (IGD1_1, IGD1_2, IGD1_3, IGD1_4) in response to the received input data. For example, the first input gradient transistor array 1112 of the first processing element (PE) 1110 can receive first first input data (ID1_1) from the processing element (PE) input buffer 1111, and can transmit the first first input gradient data (IGD1_1) to the adder tree 1116.

[0056] According to one implementation, the adder tree 1116 of the first processing element (PE) 1110 can receive classified first input gradient data (IGD1_1, IGD1_2, IGD1_3, IGD1_4) from the first to fourth input gradient transistor arrays (1112, 1113, 1114, 1115), respectively. In one example, the adder tree 1116 can generate the first input gradient data (IGD1) by summing (or adding) the classified first input gradient data (IGD1_1, IGD1_2, IGD1_3, IGD1_4).

[0057] According to one implementation, the processing element (PE) output buffer 1117 of the first processing element 1110 may store the first input gradient data (IGD1) received from the adder tree 1116. In one example, the processing element (PE) output buffer 1117 may transmit the first input gradient data (IGD1) to the accumulator circuit 1160.

[0058] Reference Figure 1 and Figure 2 According to one implementation, the transistor array computer 1100 may correspond to an input gradient computer. The input gradient may correspond to the gradient or vector multiplied by a large amount of reference data in a machine learning or deep learning algorithm. In one example, the input gradient transistor array of the transistor array computer 1100 may include one transistor and a resistive random access memory (ReRAM) per unit cell. In one example, the transistor array computer 1100 may perform a MAC calculation on the input data (ID) and may output input gradient data (IGD) corresponding to the MAC calculation.

[0059] According to one implementation, MAC calculations for preset input gradients and reference data can be performed in a unit cell of the transistor array computer 1100. In one example, the input gradients and reference data are input for each unit cell of the transistor array computer 1100, and the operation of multiplying the input gradients by the reference data can correspond to an inference artificial neural network (ANN) computation operation. See below for further details. Figure 5 A detailed description of the operation of input gradients and reference data for each unit cell input of the transistor array computer 1100 is given.

[0060] According to one implementation, the input gradient data (IGD) may include data input to and / or output from a MAC computation performed by a transistor array computer 1100. For example, see also... Figure 1The transistor array computer 1100 can perform MAC calculations for each unit cell. Here, during the MAC calculation for each unit cell, a current value is obtained by multiplying the initial input voltage value used in the MAC calculation, corresponding to the image data received from the global buffer 1200, by modifiable weight data (e.g., data corresponding to the conductance value of the ReRAM), and the resulting current values ​​are summed. Therefore, the input gradient data (IGD) output from the transistor array computer 1100 can include data corresponding to the initial input voltage value and threshold voltage value used in the MAC calculation process of the transistor array computer 1100 and / or the current value formed as a result of performing the MAC calculation.

[0061] According to one implementation, the input gradient data (IGD) output from the transistor array computer 1100 may include error data for the MAC calculation. The error data for the MAC calculation may be data corresponding to the difference between the result value of the MAC calculation and the target value. The error data for the MAC calculation may be calculated by an external module and transmitted to the transistor array computer 1100. In one example, the external module may be an external memory.

[0062] According to one implementation, the input gradient data (IGD) may include data corresponding to an initial input voltage value (dI / dG = V) for MAC calculations used in the transistor array computer 1100. The initial input voltage value for the MAC calculations may correspond to the change in the conductance of the ReRAM relative to the current value resulting from the execution of the MAC calculations. In one example, the input gradient data (IGD) may include data corresponding to the change in the current value (dE / dI) relative to the error in the MAC calculations as a result of the execution of the MAC calculations.

[0063] According to one implementation, CIM module 1000 may include one or more transistor array computers 1100, and the one or more transistor array computers 1100 may be grouped into a tile. In one example, CIM module 1000 may include one or more tiles. For example, CIM module 1000 may be arranged with one or more tiles for transmitting data to and receiving data from global buffer 1200.

[0064] Figure 3 This is a block diagram illustrating an example structure of a weighted gradient computer according to some embodiments of the present disclosure.

[0065] Reference Figure 3The weight gradient computer 1300 can receive input gradient data (IGD) and output weight gradient data (WGD). In one example, the weight gradient computer 1300 may include at least one of the following: a weight gradient input buffer 1350, a weight gradient accumulation circuit 1360, and a first to fourth weight gradient transistor array (represented by "WGT array") (1310, 1320, 1330, 1340) and a weight gradient output buffer 1370.

[0066] Although for ease of description, it is assumed that the weight gradient computer 1300 includes first to fourth weight gradient transistor arrays (1310, 1320, 1330, 1340), other implementations are possible, and it should be noted that the number of weight gradient transistor arrays in the weight gradient computer 1300 is not limited thereto. The configuration of the weight gradient computer 1300 according to this disclosure is merely illustrative, and certain configurations may be added to or omitted from the weight gradient computer 1300. In one embodiment, the weight gradient computer 1300 may further include a weight gradient transistor array. In another embodiment, at least some configurations of the weight gradient input buffer 1350 or the weight gradient output buffer 1370 may be included in an external module, such as a global buffer 1200 (see [link to documentation]). Figure 1 ).

[0067] According to one implementation, the input gradient data (IGD) received by the weighted gradient input buffer 1350 may include first to fourth initial input voltage value data (IVD1, IVD2, IVD3, IVD4) and / or first to fourth error data (EOD1, EOD2, EOD3, EOD4). In one example, see also [reference needed]. Figure 1 The first to fourth initial input voltage value data (IVD1, IVD2, IVD3, IVD4) may include data corresponding to the initial input voltage value (dI / dG = V) used in the MAC calculation of the transistor array computer 1100. In one example, the first to fourth error data (EOD1, EOD2, EOD3, EOD4) may include data corresponding to the amount of change (dE / dI) of the error in the MAC calculation relative to the current value formed as a result of the MAC calculation performed by the transistor array computer 1100.

[0068] According to one embodiment, the weighted gradient input buffer 1350 can classify the first to fourth initial input voltage value data (IVD1, IVD2, IVD3, IVD4) according to the positions of the first to fourth weighted gradient transistor arrays (1310, 1320, 1330, 1340), and can transmit the classification result data to the first to fourth weighted gradient transistor arrays (1310, 1320, 1330, 1340) respectively. Furthermore, the weighted gradient input buffer 1350 can classify the first to fourth error data (EOD1, EOD2, EOD3, EOD4) according to the positions of the first to fourth weighted gradient transistor arrays (1310, 1320, 1330, 1340), and can transmit the classification result data to the first to fourth weighted gradient transistor arrays (1310, 1320, 1330, 1340) respectively. For example, the first weighted gradient transistor (WGT) array (i.e., the first WGT array) 1310 can receive first initial input voltage value data (IVD1) and / or first error data (EOD1) from the weighted gradient input buffer 1350.

[0069] According to one embodiment, the first to fourth weighted gradient transistor arrays (1310, 1320, 1330, 1340) of the weighted gradient computer 1300 can receive first to fourth initial input voltage value data (IVD1, IVD2, IVD3, IVD4) from the weighted gradient input buffer 1350, respectively. Furthermore, the first to fourth weighted gradient transistor arrays (1310, 1320, 1330, 1340) can receive first to fourth error data (EOD1, EOD2, EOD3, EOD4) from the weighted gradient input buffer 1350.

[0070] According to one embodiment, the first to fourth weighted gradient transistor arrays (1310, 1320, 1330, 1340) can output the first to fourth weighted gradient data (WGD1, WGD2, WGD3, WGD4), respectively. For example, the first weighted gradient transistor array 1310 can receive the first initial input voltage value data (IVD1) and the first error data (EOD1) from the weighted gradient input buffer 1350, and can transmit the first weighted gradient data (WGD1) to the accumulation circuit 1360 of the weighted gradient computer 1300.

[0071] According to one implementation, the accumulation circuit 1360 of the weight gradient computer 1300 can receive first to fourth weight gradient data (WGD1, WGD2, WGD3, WGD4) from the first to fourth weight gradient transistor arrays (1310, 1320, 1330, 1340). In one example, the accumulation circuit 1360 of the weight gradient computer can generate weight gradient data (WGD) by summing the received first to fourth weight gradient data (WGD1, WGD2, WGD3, WGD4).

[0072] According to one implementation, the weight gradient output buffer 1370 can store weight gradient data (WGD) received from the accumulation circuit 1360 of the weight gradient computer 1300. In one example, the weight gradient output buffer 1370 can transfer the stored weight gradient data (WGD) to the global buffer 1200 (see [link to global buffer]). Figure 1 ).

[0073] According to one implementation, the first to fourth weight gradient transistor arrays (1310, 1320, 1330, 1340) of the weight gradient computer 1300 may include a transistor as a unit cell. In one example, the weight gradient computer 1300 may perform multiplication between the first to fourth error data (EOD1, EOD2, EOD3, EOD4) and the first to fourth initial input voltage value data (IVD1, IVD2, IVD3, IVD4), perform summation on the multiplication result data, and thus output weight gradient data (WGD).

[0074] According to one implementation, since the weighted gradient transistor array includes a single transistor as a unit cell, the efficiency of the transistor array in terms of cost, power consumption, and / or area can be improved.

[0075] According to one embodiment, a weighted gradient transistor array may include a transistor as a unit cell, and when a first voltage is applied to the gate electrode of the transistor included in the unit cell and a second voltage is applied to the drain electrode of the transistor, a current corresponding to the value obtained by multiplying the first voltage and the second voltage can flow into the source electrode of the transistor. Therefore, a multiplication calculation between the first voltage and the second voltage can be performed. Furthermore, for a transistor array in which the unit transistors are arranged in multiple rows and columns, the currents flowing into the source electrodes of the unit transistors are summed, so that the multiplication results can be summed (i.e., accumulated).

[0076] According to one implementation, the weighted gradient data (WGD) may include data obtained by performing MAC calculations on the input gradient data (IGD) of the weighted gradient computer 1300. For example, the weighted gradient computer 1300 may perform multiplication between the first to fourth initial input voltage value data (IVD1, IVD2, IVD3, IVD4) and the first to fourth error data (EOD1, EOD2, EOD3, EOD4), and may perform accumulation on the multiplication result data. Therefore, the weighted gradient data (WGD) output from the weighted gradient computer 1300 may include data corresponding to the sum of values ​​obtained by multiplying the first to fourth initial input voltage value data (IVD1, IVD2, IVD3, IVD4) by the first to fourth error data (EOD1, EOD2, EOD3, EOD4).

[0077] According to one implementation, the current (Ids) value in the transistor's triode mode increases correspondingly to the value of ((Vgs-Vth)×(Vds)). Therefore, for the transistors included in a unit cell of the first to fourth weighted gradient transistor arrays (1310, 1320, 1330, 1340), if the first to fourth error data (EOD1, EOD2, EOD3, EOD4) all correspond to "(Vgs-Vth)" and the first to fourth initial input voltage value data (IVD1, IVD2, IVD3, IVD4) all correspond to "Vds", then the value obtained by multiplying the first to fourth initial input voltage value data (IVD1, IVD2, IVD3, IVD4) by the first to fourth error data (EOD1, EOD2, EOD3, EOD4) can correspond to the current value formed in the transistors included in the unit cell. Furthermore, the sum of the current values ​​formed by the transistors included in each unit cell can correspond to the accumulated sum of the multiplication results.

[0078] For example, for a unit transistor included in a unit cell of the first weighted gradient transistor array 1310, if a voltage value corresponding to the first error data (EOD1) is applied to the gate electrode of the unit transistor, and a voltage value corresponding to the first initial input voltage value data (IVD1) is applied to the drain electrode of the unit transistor, a current corresponding to the value obtained by multiplying the voltage value corresponding to the first initial input voltage value data (IVD1) by the voltage value corresponding to the first error data (EOD1) can be generated at the source electrode of the unit transistor. The current value formed at the source electrode of the unit transistor can correspond to the first weighted gradient data (WGD1).

[0079] According to one implementation, the initial input voltage value used in the MAC calculation corresponds to "dI / dG = V", while the change in the error of the MAC calculation relative to the current value formed as a result of performing the MAC calculation can correspond to "dE / dI". Furthermore, the product of the initial input voltage value used in the MAC calculation and the change in the error of the MAC calculation relative to the current value formed as a result of performing the MAC calculation can correspond to "dE / dG". In one example, "dE / dG" can correspond to the gradient used in the MAC calculation relative to the error of the MAC calculation. In one example, since the gradient used in the MAC calculation corresponds to "dG", the gradient used in the MAC calculation can be updated by multiplying "dE / dG" by the gradient used in the MAC calculation. That is, by correcting the gradient used in the MAC calculation, the difference between the resulting value of the MAC calculation and the target value can be reduced. See below for further details. Figure 6 and Figure 7 Provide a detailed description of the unit transistor in the weighted gradient computer 1300.

[0080] Figure 4 This is a block diagram illustrating example operation of an apparatus for calculating weight gradients according to some embodiments of the present disclosure.

[0081] Reference Figure 1 and Figure 4 The CIM module 1000 can perform artificial neural network (ANN) training operations using not only the transistor array computer 1100 and global buffer 1200 included in the module, but also external memory (e.g., off-chip DRAM 1500). In one example, the artificial neural network (ANN) can correspond to a multilayer perceptron with multiple hidden layers set between an input layer and an output layer. It will be assumed that the artificial neural network (ANN) corresponds to the one described above. Figure 1 The machine learning or deep learning algorithms described herein can be used to describe this ANN. For example, in the description of an artificial neural network (ANN), multiple hidden layers can correspond to those described in the reference above. Figure 1 The gradient data or vector described. In one example, off-chip DRAM 1500 may correspond to a memory module located outside CIM module 1000. In this disclosure, for ease of description, external memory is described as corresponding to off-chip DRAM 1500, but the scope of this disclosure is not limited thereto, and external memory is not limited to off-chip DRAM.

[0082] According to one implementation, the artificial neural network (ANN) training operation performed by the CIM module 1000 may include an inference process 4000, an input gradient calculation process 4100, a weight gradient calculation process 4200, and / or a weight update process 4300. The artificial neural network (ANN) training operation according to this disclosure is merely an example, and certain operations may be added to or omitted from the ANN training operation. For example, the CIM module 1000 may additionally perform a second inference operation based on the gradient updated in the weight update process 4300.

[0083] According to one implementation, the inference process 4000 can be performed based on data transfer / reception (i.e., data communication) between the transistor array computer 1100, the global buffer 1200, and / or the off-chip DRAM 1500. In one example, the off-chip DRAM 1500 can transfer input data (ID) to the global buffer 1200. The global buffer 1200 can transfer the input data (ID) received from the off-chip DRAM 1500 to the transistor array computer 1100. The input data (ID) may include image, audio, video data, and / or target data to be inferred. See also... Figure 2 and Figure 4 , Figure 4 The input data (ID) can correspond to Figure 2 Input data (ID).

[0084] According to one embodiment, the transistor array computer 1100 can perform MAC calculations on input data (ID) received from the global buffer 1200 and can generate and output activation data (ALD) for each layer. In one example, the activation data (ALD) for each layer may correspond to data related to the MAC calculation of the input data (ID) by the transistor array computer 1100. For example, the activation data (ALD) for each layer may include data corresponding to an initial input voltage value (dI / dG = V) used in the MAC calculation of the transistor array computer 1100 and / or data corresponding to a current value (I) formed as a result of performing the MAC calculation of the transistor array computer 1100. In one example, reference is also made to... Figure 2 The activation data (ALD) for each layer can be included in Figure 2 In the input gradient data (IGD).

[0085] According to one implementation, the transistor array computer 1100 can transfer the activation data (ALD) of each layer to a global buffer 1200. The global buffer 1200 can transfer the activation data (ALD) of each layer received from the transistor array computer 1100 to an off-chip DRAM 1500. In one example, the off-chip DRAM 1500 can store the received activation data (ALD) of each layer.

[0086] According to one implementation, compared to the input gradient calculation process 4100, the weight gradient calculation process 4200, and / or the weight update process 4300 (described later), the inference process 4000 may correspond to the operation of generating activation data (ALD) for each layer in a forward-upward manner based on the input data (ID).

[0087] According to one implementation, the input gradient calculation process 4100 can be performed based on data transfer / reception (i.e., data communication) between the transistor array computer 1100, the global buffer 1200, and / or the off-chip DRAM 1500. In one example, the off-chip DRAM 1500 can transfer error data (ED) to the global buffer 1200. The global buffer 1200 can transfer the error data (ED) received from the off-chip DRAM 1500 to the transistor array computer 1100. The error data (ED) can include data corresponding to errors identified during the MAC calculation process of the transistor array computer 1100. In one example, the error data (ED) can correspond to data based on the difference between preset target data and the result data of performing the MAC calculation.

[0088] According to one embodiment, the transistor array computer 1100 can generate per-layer error data (ELD) in response to error data (ED) received from the global buffer 1200, and can output the generated ELD. In one example, the per-layer error data (ELD) may correspond to data related to the MAC calculation of the error data (ED) by the transistor array computer 1100. For example, the per-layer error data (ELD) may include data corresponding to the change (dE / dI) of the error in the MAC calculation with respect to the current value formed as a result of performing the MAC calculation by the transistor array computer 1100. In one example, reference is also made to... Figure 2 The error data (ELD) for each layer can be included in Figure 2 In the input gradient data (IGD).

[0089] According to one implementation, the transistor array computer 1100 can transfer the error data (ELD) of each layer to a global buffer 1200. The global buffer 1200 can transfer the error data (ELD) received from the transistor array computer 1100 to an off-chip DRAM 1500. In one example, the off-chip DRAM 1500 can store the received error data (ELD).

[0090] According to one implementation, the input gradient calculation process 4100 may correspond to an operation used to correct data related to the input data after the output data is generated, such that the input gradient calculation process 4100 may correspond to an inverse data processing operation.

[0091] According to one implementation, the input gradient calculation process 4100 may include operations for generating error data for the output data. In one example, the input gradient calculation process 4100 corresponds to operations for identifying input gradients that should be corrected based on the error data, and thus may correspond to operations necessary for training an artificial neural network (ANN).

[0092] According to one implementation, the weight gradient calculation process 4200 can be performed based on data transfer / reception (i.e., data communication) between the weight gradient computer 1300, the global buffer 1200, and / or the off-chip DRAM 1500. In one example, the off-chip DRAM 1500 can transfer the activation data (ALD) and / or the error data (ELD) of each layer to the global buffer 1200. The global buffer 1200 can transfer the activation data (ALD) and / or the error data (ELD) of each layer received from the off-chip DRAM 1500 to the weight gradient computer 1300. In one example, the activation data (ALD) of each layer may include data corresponding to the initial input voltage value (dI / dG = V) used in the MAC calculation of the transistor array computer 1100. In one example, the error data (ELD) of each layer may include data corresponding to the amount of change (dE / dI) of the error in the MAC calculation relative to the current value formed as a result of performing the MAC calculation of the transistor array computer 1100.

[0093] According to one implementation, the weighted gradient computer 1300 can generate weighted gradient data (WGD) in response to per-layer activation data (ALD) or per-layer error data (ELD) received from the global buffer 1200, and can output the generated weighted gradient data (WGD). In one example, the weighted gradient data (WGD) may correspond to data that corresponds to the value obtained by multiplying the per-layer activation data (ALD) by the per-layer error data (ELD). For example, the weighted gradient data (WGD) may include the value “(dI / dG)×(dE / dI)=(dE / dG)” obtained by multiplying the initial input voltage value (dI / dG=V) used in the MAC calculation of the transistor array computer 1100 by the change in the current value (dE / dI) formed relative to the result of performing the MAC calculation of the transistor array computer 1100.

[0094] According to one embodiment, the value “(dI / dG)×(dE / dI)=(dE / dG)” obtained by multiplying (1) the initial input voltage value (dI / dG=V) used in the MAC calculation of the transistor array computer 1100 calculated by the weight gradient computer 1300 by (2) the change in the current value (dE / dI) resulting from the MAC calculation performed by the transistor array computer 1100 can correspond to the value to be calculated by the weight gradient computer 1300 for training an artificial neural network (ANN) model. For example, since the value “(dE / dG)” can correspond to the value obtained by dividing the change in the MAC calculation error by the change in the weights or gradients, the value “(dE / dG)” is applied to the weights or gradients to reduce the MAC calculation error. In one example, reference is also made to… Figure 3 , Figure 4 The weighted gradient data (WGD) can correspond to Figure 3 Weighted gradient data (WGD).

[0095] According to one implementation, the weight gradient computer 1300 can transfer weight gradient data (WGD) to a global buffer 1200. The global buffer 1200 can transfer the weight gradient data (WGD) received from the weight gradient computer 1300 to an off-chip DRAM 1500. In one example, the off-chip DRAM 1500 can store the received weight gradient data (WGD).

[0096] According to one implementation, the weight gradient calculation process 4200 may correspond to an operation of correcting data related to the input data after generating output data, such that the weight gradient calculation process 4200 may correspond to an operation of processing data in the opposite direction (i.e., reverse data processing).

[0097] According to one implementation, the weight gradient calculation process 4200 may include an operation to calculate a value (dE / dG) obtained by dividing the amount of error change calculated by the MAC of the transistor array computer 1100 by the amount of change in modifiable weight data (e.g., the amount of data change corresponding to the conductance value of the ReRAM). In one example, the weight gradient calculation process 4200 may correspond to an operation to identify a correction value for the input gradient used to reduce the error, such that the weight gradient calculation process 4200 may correspond to the operations necessary for training an artificial neural network (ANN).

[0098] According to one implementation, the weight update process 4300 can be performed based on data transfer / reception (i.e., data communication) between the transistor array computer 1100, the global buffer 1200, and / or the off-chip DRAM 1500. In one example, the off-chip DRAM 1500 can transfer weight gradient data (WGD) to the global buffer 1200. The global buffer 1200 can transfer the weight gradient data (WGD) received from the off-chip DRAM 1500 to the transistor array computer 1100. The weight gradient data (WGD) can include the value “(dI / dG)×(dE / dI)=(dE / dG)” obtained by multiplying the initial input voltage value (dI / dG=V) used in the MAC calculation of the transistor array computer 1100 by the amount of change (dE / dI) of the current value formed as a result of performing the MAC calculation of the transistor array computer 1100.

[0099] According to one implementation, the transistor array computer 1100 can modify the input gradient value based on weight gradient data (WGD) received from the global buffer 1200. For example, the transistor array computer 1100 can modify the input gradient value by applying the weight gradient data (WGD) to modifiable weight data (e.g., data corresponding to the conductance value of the ReRAM). In one example, based on the modified input gradient value, the transistor array computer 1100 can compute a result value with a relatively smaller error than that in the inference process 4000.

[0100] According to one implementation, the weight update process 4300 can correspond to the operation of correcting data related to the input data after generating output data, and therefore can correspond to the operation of reverse data processing.

[0101] According to one implementation, the weight update process 4300 may include an operation to correct the weights or gradients to be applied to the input data based on the weight data. In one example, the weight update process 4300 corresponds to an operation to correct and update the input gradient that needs to be corrected based on the error, and therefore may correspond to the operations necessary for training an artificial neural network (ANN).

[0102] Figure 5 This is a diagram illustrating a unit cell of a transistor array computer according to some embodiments of the present disclosure.

[0103] Reference Figure 5 The unit cell array 5000 of the transistor array computer may include first to sixteenth unit cells (CL1 to CL16), first to fourth row lines (RL1 to RL4) connected to the drain electrodes of transistors arranged in each row of the unit cell array 5000, first to fourth gate column lines (GCL1 to GCL4) connected to the gate electrodes of transistors arranged in each column of the unit cell array 5000, and first to fourth source column lines (SCL1 to SCL4) connected to the source electrodes of transistors arranged in each column of the unit cell array 5000.

[0104] According to one embodiment, a unit cell may include at least one ReRAM and at least one transistor. For example, a first unit cell (CL1) may include at least one first ReRAM (RR1) and at least one first transistor (TR1). A second unit cell (CL2) may include at least one second ReRAM (RR2) and at least one second transistor (TR2); a third unit cell (CL3) may include at least one third ReRAM (RR3) and at least one third transistor (TR3); a fourth unit cell (CL4) may include at least one fourth ReRAM (RR4) and at least one fourth transistor (TR4); and a fifth unit cell (CL5) may include at least one fifth ReRAM (RR5) and at least one fifth transistor (TR5). In the same manner as described above, the sixth to sixteenth unit cells (CL6 to CL16) may each include at least one sixth to sixteenth ReRAM (RR6 to RR16) and at least one sixth to sixteenth transistor (TR6 to TR16).

[0105] According to one implementation, the conductance value of the ReRAM included in the unit cell can correspond to modifiable weight data. In one example, reference is also made to… Figure 2The conductance value of the ReRAM included in the unit cell can correspond to the gradient data or vector used in the MAC calculation performed by the transistor array computer 1100. In one example, the operation of multiplying the error change (dE / dG) of the MAC calculation by the gradient used in the MAC calculation can correspond to the operation of correcting the weights or gradients.

[0106] The configuration of the unit cell array 5000 of the transistor array computer 1100 according to this disclosure is merely an example, and some components may be added to or omitted from the unit cell array 5000 of the transistor array computer 1100. For example, besides Figure 5 In addition to the components shown, the unit cell array 5000 of the transistor array computer 1100 may further include unit cells, row lines, gate column lines, and / or source column lines. Although for ease of description... Figure 5 The diagram shows a unit cell array formed by a (4×4) matrix structure, but Figure 5 This is only an example of a partial configuration of the unit cell array, and the number of unit cells included in the unit cell array 5000 of the transistor array computer is not limited to this.

[0107] According to one implementation method, reference is also made to Figure 2 The transistor array computer's unit cell array 5000 can correspond to Figure 2 The input gradient transistor array in the [structure / process]. Figure 5 For ease of description, it is assumed that the unit cell array 5000 of the transistor array computer corresponds to... Figure 2 The first input gradient transistor array 1112.

[0108] According to one implementation method, reference is also made to Figure 2 The first input data (ID1_1) may include data corresponding to the first to fourth row voltage values ​​applied to the first to fourth row lines (RL1 to RL4), respectively. For example, the first input data (ID1_1) may include data corresponding to the first row voltage value applied to the first row line (RL1).

[0109] According to one implementation method, reference is also made to Figure 2 The first input data (ID1_1) may include data corresponding to the first to fourth gate column voltage values ​​applied to the first to fourth gate column lines (GCL1 to GCL4), respectively. For example, the first input data (ID1_1) may include data corresponding to the first gate column voltage value applied to the first gate column line (GCL1).

[0110] According to one implementation method, reference is also made to Figure 2The first input gradient data (IGD1_1) may include data corresponding to the current value formed as a result of applying a row voltage and a gate column voltage to each of the first to sixteenth unit cells (CL1 to CL16). For example, the first input gradient data (IGD1_1) may include data corresponding to the current value formed as a result of applying a first row voltage and a first gate column voltage to the first unit cell (CL1).

[0111] According to one embodiment, a first row voltage can be applied to a first unit cell (CL1) via a first row line (RL1), and a first gate column voltage can be applied via a first gate column line (GCL1). At this time, a current corresponding to the value obtained by multiplying the first row voltage by the first gate column voltage can be formed at the source electrode of the first unit cell (CL1). Furthermore, the current corresponding to the value obtained by multiplying the first row voltage by the first gate column voltage can be transmitted to the first source column line (SCL1). Figure 2 The adder tree 1116. Similarly, the current corresponding to the value obtained by multiplying the second row voltage by the second gate column voltage can be transferred through the second source column line (SCL2) to... Figure 2 Adder tree 1116. In this way, the same concept as described above can also be applied to the second to sixteenth unit cells (CL2 to CL16).

[0112] According to one embodiment, the current value formed at the source electrode of each of the first to sixteenth unit cells (CL1 to CL16) can correspond to the current value formed as a result of MAC calculation in the unit cell array 5000 that performs the transistor array computer. In one example, the first input gradient data (IGD1_1) may include data related to the MAC calculation performed by the first input gradient transistor array 1112 using the first to sixteenth unit cells (CL1 to CL16).

[0113] According to one implementation, the data corresponding to the row voltage values ​​included in the first input data (ID1_1) and the data corresponding to the gate column voltage values ​​can correspond to MAC calculation input data. In one example, the data corresponding to the row voltage values ​​included in the first input data (ID1_1) can correspond to the initial input voltage values ​​used in the MAC calculation. In one example, the data corresponding to the gate column voltage values ​​included in the first input data (ID1_1) can correspond to the threshold voltage values ​​used in the MAC calculation.

[0114] According to one implementation, the data corresponding to the current values ​​included in the first input gradient data (IGD1_1) can correspond to the MAC calculation output data. In one example, the data corresponding to the current values ​​included in the first input gradient data (IGD1_1) can correspond to the current values ​​formed as a result of performing the MAC calculation.

[0115] According to one embodiment, the first input gradient data (IGD1_1) may include data corresponding to the difference between a target value and a current value resulting from applying a first row voltage and a first gate column voltage to the first unit cell (CL1). The data corresponding to the difference between the target value and the current value resulting from applying the first row voltage and the first gate column voltage to the first unit cell (CL1) may correspond to error data calculated for the MAC.

[0116] According to one embodiment, the first input gradient data (IGD1_1) may include data corresponding to the amount of change in the error relative to the current value formed as a result of applying the first row voltage and the first gate column voltage to the first unit cell (CL1). The data corresponding to the amount of change in the error relative to the current value formed as a result of applying the first row voltage and the first gate column voltage to the first unit cell (CL1) may correspond to the amount of change in the error of the MAC calculation relative to the current value formed as a result of performing the MAC calculation. That is, the first input gradient data (IGD1_1) may include data corresponding to the amount of change in the error of the MAC calculation relative to the current value formed as a result of performing the MAC calculation.

[0117] According to one embodiment, the first input gradient data (IGD1_1) may further include data corresponding to the row voltage values ​​included in the first input data (ID1_1) and / or data corresponding to the gate column voltage values ​​included in the first input data (ID1_1). In one example, the row voltage values ​​may correspond to the initial input voltage values ​​used in the MAC calculation, while the gate column voltage values ​​may correspond to the threshold voltage values ​​used in the MAC calculation. That is, the first input gradient data (IGD1_1) may include data corresponding to the initial input voltage values ​​used in the MAC calculation.

[0118] Figure 6 and Figure 7 This is a diagram illustrating an example of a unit transistor in a weighted gradient computer according to some embodiments of the present disclosure.

[0119] Reference Figure 6The weighted gradient transistor array 6000 may include first to sixteenth unit transistors (UT1 to UT16), first to fourth bit lines (BL1 to BL4) connected to the drain electrodes of the unit transistors arranged in each row of the weighted gradient transistor array 6000, first to fourth word lines (WL1 to WL4) connected to the gate electrodes of the unit transistors arranged in each column of the weighted gradient transistor array 6000, first to fourth source lines (SL1 to SL4) connected to the source electrodes of the unit transistors arranged in each column of the weighted gradient transistor array 6000, first to fourth row digital-to-analog converters (RDACs) (RDAC1 to RDAC4) for applying row voltages to the first to fourth bit lines (BL1 to BL4), first to fourth column digital-to-analog converters (CDACs) (CDAC1 to CDAC4) for applying column voltages to the first to fourth word lines (WL1 to WL4), and / or first to fourth analog-to-digital converters (ADCs) (ADC1 to ADC4) for outputting digital signals corresponding to the currents flowing through the first to fourth source lines (SL1 to SL4).

[0120] The configuration of the weighted gradient transistor array 6000 according to this disclosure is merely an example, and some configurations can be added to or omitted from the weighted gradient transistor array 6000. For example, besides Figure 6 In addition to the configuration shown, the weighted gradient transistor array 6000 may further include unit transistors, bit lines, word lines, source lines, row DACs, column DACs, and / or ADCs. Although for ease of description... Figure 6 A transistor array formed in a (4×4) matrix structure is shown, but Figure 6 This is merely an example of some configurations of the weighted gradient transistor array, and the number of transistors in the weighted gradient transistor array 6000 is not limited to this.

[0121] According to one implementation, and also referring to Figure 3 The weighted gradient transistor array 6000 can correspond to Figure 3 A weighted gradient transistor array. Figure 6 For ease of description, it is assumed that the weighted gradient transistor array 6000 corresponds to Figure 3 The first weighted gradient transistor array 1310.

[0122] According to one implementation method, reference is also made to Figure 3The weighted gradient input buffer 1350 can classify the first initial input voltage value data (IVD1) received from the input gradient data (IGD). In one example, the weighted gradient input buffer 1350 can classify the first initial input voltage value data (IVD1) into first initial input voltage value data (IVD1_1), second initial input voltage value data (IVD1_2), third initial input voltage value data (IVD1_3), and fourth initial input voltage value data (IVD1_4) according to the column, row, and / or coordinates of the weighted gradient transistor array 6000. For example, the weighted gradient input buffer 1350 can transmit the first initial input voltage value data (IVD1_1) from the first initial input voltage value data (IVD1) to the first row DAC (RDAC1) corresponding to the first row of the weighted gradient transistor array 6000.

[0123] According to one implementation, first initial input voltage value data (IVD1_1), second initial input voltage value data (IVD1_2), third initial input voltage value data (IVD1_3), or fourth initial input voltage value data (IVD1_4) can be classified based on data control signals. For example, the weighted gradient input buffer 1350 can control the identification information and input time points of the first initial input voltage value data (IVD1_1), second initial input voltage value data (IVD1_2), third initial input voltage value data (IVD1_3), or fourth initial input voltage value data (IVD1_4) based on data control signals. In one example, reference is also made to... Figure 1 The data control signal can be included in the buffer control data (BCD) and can be transmitted to the weight gradient input buffer 1350 of the weight gradient computer 1300 through the global buffer 1200.

[0124] According to one implementation method, reference is also made to Figure 3 The weighted gradient input buffer 1350 can classify the first error data (EOD1) based on the input gradient data (IGD). In one example, the weighted gradient input buffer 1350 can classify the first error data (EOD1) into first first error data (EOD1_1), second first error data (EOD1_2), third first error data (EOD1_3), and fourth first error data (EOD1_4) according to the columns, rows, and / or coordinates of the weighted gradient transistor array 6000. For example, the weighted gradient input buffer 1350 can transmit the first first error data (EOD1_1) from the first error data (EOD1) to the first column DAC (CDAC1) corresponding to the first column of the weighted gradient transistor array 6000.

[0125] According to one implementation, first first error data (EOD1_1), second first error data (EOD1_2), third first error data (EOD1_3), or fourth first error data (EOD1_4) can be classified based on a data control signal. For example, the weighted gradient input buffer 1350 can control the identification information and input time point of the first first error data (EOD1_1), second first error data (EOD1_2), third first error data (EOD1_3), or fourth first error data (EOD1_4) based on the data control signal. In one example, reference is also made to... Figure 1 The data control signal can be included in the buffer control data (BCD) and can be transmitted to the weight gradient input buffer 1350 of the weight gradient computer 1300 through the global buffer 1200.

[0126] According to one implementation, the weighted gradient transistor array 6000 can be based on the first initial input voltage value data (IVD1_1, IVD1_2, IVD1_3, IVD1_4) being input to the first to fourth row DACs (RDAC1 to RDAC4) and the first error data (EOD1_1, EOD1_2, EOD1_3, EOD1_4) being input to the first to fourth column DACs (CDAC1 to CDAC4), and the first weighted gradient data (WGD1_1, WGD1_2, WGD1_3, WGD1_4) being output through the first to fourth ADCs (ADC1 to ADC4). For example, when the voltage corresponding to the first initial input voltage value data (IVD1_1) is applied to the drain electrode of the first unit transistor (UT1) through the first row DAC (RDAC1), and the voltage corresponding to the first error data (EOD1_1) is applied to the gate electrode of the first unit transistor (UT1) through the first column DAC (CDAC1), the current corresponding to the first weighted gradient data (WGD1_1) can flow to the source electrode of the first unit transistor (UT1).

[0127] According to one embodiment, the first to sixteenth unit transistors (UT1 to UT16) included in the weighted gradient transistor array 6000 may correspond to NMOS transistors, which output current through their source electrodes when a row voltage is applied to the drain electrode and a column voltage is applied to the gate electrode.

[0128] According to one implementation, the drain electrodes of the first to fourth unit transistors (UT1 to UT4) arranged in the first row of the weighted gradient transistor array 6000 can be connected to the first bit line (BL1). In one example, also refer to... Figure 5The first row DAC (RDAC1) can apply a first row voltage to the first bit line (BL1), allowing the first row voltage to be transmitted to the drain electrodes of the first to fourth unit transistors (UT1 to UT4) arranged in the first row. At this time, the first row voltage applied to the first bit line (BL1) corresponds to the voltage applied to... Figure 5 The first row voltage of the first line (RL1). In one example, the first row voltage may correspond to the voltage corresponding to the first initial input voltage value data (IVD1_1).

[0129] According to one implementation, the drain electrodes of the fifth to eighth unit transistors (UT5 to UT8) arranged in the second row of the weighted gradient transistor array 6000 can be connected to the second bit line (BL2). In one example, also refer to... Figure 5 The second row DAC (RDAC2) can transmit the second row voltage to the second bit line (BL2), allowing the second row voltage to be transmitted to the drain electrodes of the fifth to eighth unit transistors (UT5 to UT8) arranged in the second row. At this time, the second row voltage applied to the second bit line (BL2) corresponds to the voltage applied to... Figure 5 The second row of voltages (RL2). In one example, the second row of voltages may correspond to the voltages corresponding to the second first initial input voltage value data (IVD1_2).

[0130] According to one embodiment, the ninth to twelfth unit transistors are arranged in the third row of the weighted gradient transistor array 6000. Or the thirteenth to sixteenth transistors arranged in the fourth row of the weighted gradient transistor array 6000. It can be compared with the first to fourth unit transistors arranged in the first row of the weighted gradient transistor array 6000. Or the fifth to eighth unit transistors arranged in the second row of the weighted gradient transistor array 6000. The same method is used to transmit the row voltage to its drain electrode.

[0131] According to one implementation method, reference is also made to Figure 5 The third row voltage applied to the third bit line (BL3) can correspond to Figure 5 The third row voltage applied to the third row line (RL3). In one example, the third row voltage applied to the third bit line (BL3) may correspond to the voltage corresponding to the third first initial input voltage value data (IVD1_3).

[0132] According to one implementation method, reference is also made to Figure 5 The fourth row voltage applied to the fourth bit line (BL4) can correspond to Figure 5The fourth row voltage applied to the fourth bit line (RL4). In one example, the fourth row voltage applied to the fourth bit line (BL4) may correspond to the voltage corresponding to the fourth first initial input voltage value data (IVD1_4).

[0133] According to one implementation, the gate electrodes of the first, fifth, ninth, and thirteenth unit transistors (UT1, UT5, UT9, UT13) arranged in the first column of the weighted gradient transistor array 6000 can be connected to the first word line (WL1). In one example, also refer to... Figure 5 The first column DAC (CDAC1) can apply a first column voltage to the first word line (WL1) to transmit the first column voltage to the gate electrodes of the first, fifth, ninth, and thirteenth unit transistors (UT1, UT5, UT9, UT13) arranged in the first column. At this time, the first column voltage applied to the first word line (WL1) can correspond to... Figure 5 The first gate column voltage is applied to the first gate column line (GCL1). In one example, the first column voltage may correspond to the voltage corresponding to the first error data (EOD1_1).

[0134] According to one embodiment, the source electrodes of the first, fifth, ninth, and thirteenth unit transistors (UT1, UT5, UT9, UT13) arranged in the first column of the weighted gradient transistor array 6000 can be connected to a first source line (SL1). In one example, a first ADC (ADC1) can output a digital signal corresponding to the current flowing through the first source line (SL1) into the source electrode of at least one of the first, fifth, ninth, and thirteenth unit transistors (UT1, UT5, UT9, UT13) arranged in the first column. In one example, the first ADC (ADC1) can receive the current flowing into the source electrode of at least one of the first, fifth, ninth, and thirteenth unit transistors (UT1, UT5, UT9, UT13) arranged in the first column. Here, the received current can correspond to the current corresponding to the first weighted gradient data (WGD1_1).

[0135] According to one implementation, the gate electrodes of the second, sixth, tenth, and fourteenth unit transistors (UT2, UT6, UT10, UT14) arranged in the second column of the weighted gradient transistor array 6000 can be connected to the second word line (WL2). In one example, also refer to... Figure 5 The second column DAC (CDAC2) can apply a second column voltage to the second word line (WL2) to transmit the second column voltage to the gate electrodes of the second, sixth, tenth, and fourteenth unit transistors (UT2, UT6, UT10, UT14) arranged in the second column. At this time, the second column voltage applied to the second word line (WL2) can correspond to... Figure 5The second gate column voltage is applied to the second gate column line (GCL1). In one example, the second column voltage may correspond to the voltage corresponding to the second first error data (EOD1_2).

[0136] According to one embodiment, the source electrodes of the second, sixth, tenth, and fourteenth unit transistors (UT2, UT6, UT10, UT14) arranged in the second column of the weighted gradient transistor array 6000 can be connected to a second source line (SL2). In one example, the second ADC (ADC2) can output a digital signal corresponding to the current flowing through the second source line (SL2) into the source electrode of at least one of the second, sixth, tenth, and fourteenth unit transistors (UT2, UT6, UT10, UT14) arranged in the second column. In one example, the second ADC (ADC2) can receive the current flowing into the source electrode of at least one of the second, sixth, tenth, and fourteenth unit transistors (UT2, UT6, UT10, UT14) arranged in the second column. In this case, the received current can correspond to the current corresponding to the second first weighted gradient data (WGD1_2).

[0137] According to one embodiment, the third, seventh, eleventh, and fifteenth unit transistors (UT3, UT7, UT11, UT15) arranged in the third column of the weighted gradient transistor array 6000, or the fourth, eighth, twelfth, and sixteenth unit transistors (UT4, UT8, UT12, UT16) arranged in the fourth column of the weighted gradient transistor array 6000, can be configured such that each unit transistor can receive a column voltage through its gate electrode, in the same manner as the first, fifth, ninth, and thirteenth unit transistors (UT1, UT5, UT9, UT13) or the second, sixth, tenth, and fourteenth unit transistors (UT2, UT6, UT10, UT14) arranged in the first column. Also refer to... Figure 5 The voltage applied to the third column of the third word line (WL3) can correspond to Figure 5 The third gate column voltage is applied to the third gate column line (GCL3). Furthermore, the fourth column voltage applied to the fourth word line (WL4) can correspond to... Figure 5 The fourth gate column voltage is applied to the fourth gate column line (GCL4). In one example, the third column voltage may correspond to the voltage corresponding to the third first error data (EOD1_3), and the fourth column voltage may correspond to the voltage corresponding to the fourth first error data (EOD1_4).

[0138] According to one embodiment, the third ADC (ADC3) or the fourth ADC (ADC4) can output a digital signal corresponding to the current flowing into the source electrode of at least one of the third, seventh, eleventh, and fifteenth unit transistors (UT3, UT7, UT11, UT15) arranged in the third column of the weighted gradient transistor array 6000, or a digital signal corresponding to the current flowing into the source electrode of at least one of the fourth, eighth, twelfth, and sixteenth unit transistors (UT4, UT8, UT12, UT16) arranged in the fourth column, in the same manner as the first ADC (ADC1) or the second ADC (ADC2) described above. In one example, the current received by the third ADC (ADC3) flowing into the source electrode of at least one of the third, seventh, eleventh, and fifteenth unit transistors (UT3, UT7, UT11, UT15) arranged in the third column can correspond to the current corresponding to the third first weighted gradient data (WGD1_3). In one example, the current received by the fourth ADC (ADC4) and flowing into the source electrode of at least one of the fourth, eighth, twelfth, and sixteenth unit transistors (UT4, UT8, UT12, UT16) arranged in the fourth column can correspond to the current corresponding to the fourth first weighted gradient data (WGD1_4).

[0139] According to one implementation method, refer to Figure 2 and Figure 3 The weighted gradient input buffer 1350 can transmit the first initial input voltage value data (IVD1) to the weighted gradient transistor array 6000. At this time, based on the row, column, and / or coordinates of the unit transistor, the first initial input voltage value data (IVD1) can be classified into first initial input voltage value data (IVD1_1), second initial input voltage value data (IVD1_2), third initial input voltage value data (IVD1_3), and fourth initial input voltage value data (IVD1_4), and the weighted gradient input buffer 1350 can transmit the classified result data. In one example, the classified first initial voltage value data (IVD1_1, IVD1_2, IVD1_3, IVD1_4) transmitted to the weighted gradient transistor array 6000 may include data corresponding to the voltage values ​​(dI / dG = V) used in the MAC calculation of the transistor array computer 1100.

[0140] According to one implementation method, refer to together Figure 2 and Figure 3The weighted gradient input buffer 1350 can transmit the first error data (EOD1) to the weighted gradient transistor array 6000. At this time, based on the row, column, and / or coordinates of the unit transistor, the first error data (EOD1) can be classified into first first error data (EOD1_1), second first error data (EOD1_2), third first error data (EOD1_3), and fourth first error data (EOD1_4), allowing the weighted gradient input buffer 1350 to transmit the classification result data. In one example, the classified first error data (EOD1_1, EOD1_2, EOD1_3, EOD1_4) transmitted to the weighted gradient transistor array 6000 may include data corresponding to the change in current value (dE / dI) resulting from the MAC calculation error as a result of the MAC calculation performed by the transistor array computer 1100.

[0141] According to one embodiment, the first row DAC (RDAC1) can apply a voltage value corresponding to the initial input voltage value (dI / dG = V) used in the MAC calculation of the transistor array computer 1100 based on the first initial input voltage value data (IVD1_1) received by the weighted gradient transistor array 6000 to the first word line. Furthermore, the first column DAC (CDAC1) can transmit a value corresponding to the change in current value (dE / dI) resulting from the execution of the MAC calculation as a result of the transistor array computer 1100, based on the first error data (EOD1_1) received by the weighted gradient transistor array 6000, to the first word line.

[0142] According to one implementation, the first initial input voltage value data (IVD1_1) and the first error data (EOD1_1) may correspond to the row, column, and / or coordinates of the unit cell in the transistor array computer 1100 where MAC calculation has been performed. In one example, reference is also made to... Figure 2 The first initial input voltage value data (IVD1_1) may correspond to the initial input voltage value used in the MAC calculation performed in the first row of the first input gradient transistor array 1112 of the transistor array computer 1100. In one example, also refer to... Figure 2 The first error data (EOD1_1) can correspond to the amount of change in the error of the MAC calculation relative to the current value formed as a result of performing the MAC calculation in the first column of the first input gradient transistor array 1112 of the transistor array computer 1100. In the same manner as described above, the initial input voltage value data and the error data can also be applied to the remaining rows and columns other than the first row and the remaining columns other than the first column.

[0143] According to one embodiment, the current flowing into the source electrode of the first unit transistor (UT1) can be calculated as shown in Equation 1 below. In Equation 1, "Ids" can represent the current flowing into the source electrode in the transistor's bipolar mode, "Vgs" can represent the gate input voltage, "Vds" can represent the drain input voltage, "Vth" can represent the threshold voltage, and "A" can represent a constant.

[0144] [Formula 1]

[0145] Ids=A((Vgs-Vth)×Vds-((Vds^2) / 2))

[0146] According to one implementation method, refer to together Figure 2 According to Equation 1, when the voltage value of "(dI / dG = V)" calculated by the MAC of the transistor array computer 1100 is applied to the drain electrode of the first unit transistor (UT1), and the voltage value of "(dE / dI)" calculated by the MAC of the transistor array computer 1100 is applied to the gate electrode of the first unit transistor (UT1), (dE / dI) can correspond to "(Vgs - Vth)", and "(dI / dG = V)" can correspond to "Vds". In this case, "Ids" can have a value corresponding to "(dI / dG) * (dE / dI)", and the first unit transistor (UT1) can output a current value corresponding to "(dI / dG) × (dE / dI) = (dE / dG)" through the source electrode of the first unit transistor (UT1).

[0147] According to one implementation method, reference is also made to Figure 5 The first initial input voltage value data (IVD1_1) may include data corresponding to the initial input voltage values ​​used in the MAC calculations performed in the first to fourth units (CL1 to CL4) arranged in the first row of the unit cell array 5000 of the transistor array computer.

[0148] According to one implementation method, reference is also made to Figure 5 The first error data (EOD1_1) may include data corresponding to the change in current value formed by the error of the MAC calculation relative to the result of the MAC calculation of the first, fifth, ninth and thirteenth units (CL1, CL5, CL9, CL13) arranged in the first column of the unit cell array 5000, which is an execution transistor array computer.

[0149] According to one implementation method, reference is also made to Figure 5Data corresponding to the initial input voltage value used in the MAC calculation performed in the first unit cell (CL1) can be applied to the drain electrode of the first unit transistor (UT1) of the weighted gradient transistor array 6000. Furthermore, data corresponding to the change in the error of the MAC calculation relative to the change in the current value formed as a result of the MAC calculation performed in the first unit cell (CL1) can be applied to the gate electrode of the first unit transistor (UT1) of the weighted gradient transistor array 6000.

[0150] According to one implementation method, reference is also made to Figure 5 The first row DAC (RDAC1) can apply a voltage corresponding to the initial input voltage value used in the MAC calculation of the unit cell array 5000 of the transistor array computer to the first bit line (BL1). Furthermore, the first column DAC (CDAC1) can apply a voltage corresponding to the amount of change in the error of the MAC calculation relative to the current value formed as a result of performing the MAC calculation of the unit cell array 5000 of the transistor array computer to the first word line (WL1). In this case, the current flowing into the source electrode of the first unit transistor (UT1) can correspond to a value obtained by multiplying the "initial input voltage value used in the MAC calculation" by the "amount of change in the current value formed as a result of performing the MAC calculation." In this case, the first ADC (ADC) can generate and output data including the value corresponding to the current flowing into the source electrode of the first unit transistor (UT1) as first weighted gradient data (WGD1_1).

[0151] According to one implementation method, reference is also made to Figure 5 The first row DAC (RDAC1) applies a voltage corresponding to the initial input voltage value used in the MAC calculation of the first to fourth unit units (CL1 to CL4) to the first word line (BL1), and the first column DAC (CDAC1) applies a voltage corresponding to the change in current value resulting from the MAC calculation of the first, fifth, ninth, and thirteenth unit units (CL1, CL5, CL9, CL13) to the first word line (WL1). Furthermore, the second column DAC (CDAC2) applies a voltage corresponding to the change in current value resulting from the MAC calculation of the second, sixth, tenth, and fourteenth unit units (CL2, CL6, CL10, CL14) to the second word line (WL2).

[0152] According to one embodiment, when the initial input voltage value used in the MAC calculation of the first to fourth unit cells (CL1 to CL4) is a first voltage, the change in the MAC calculation error relative to the current value formed as a result of the MAC calculation of the first, fifth, ninth, and thirteenth unit cells (CL1, CL5, CL9, CL13) is a second voltage, and the change in the MAC calculation error relative to the current value formed as a result of the MAC calculation of the second, sixth, tenth, and fourteenth unit cells (CL2, CL6, CL10, CL14) is a third voltage. Therefore, when the voltage corresponding to the first voltage is applied to the first word line (BL1), the voltage corresponding to the second voltage is applied to the first word line (WL1), and the voltage corresponding to the third voltage is applied to the second word line (WL2), the current flowing into the source electrode of the first unit transistor (UT1) can correspond to the value obtained by multiplying the first voltage by the second voltage, and the current flowing into the source electrode of the second unit transistor (UT2) can correspond to the value obtained by multiplying the first voltage by the third voltage. The first ADC (ADC1) can generate data corresponding to the value of the current flowing into the source electrode of the first unit transistor (UT1) as first weighted gradient data (WGD1_1), and can output the first weighted gradient data (WGD1_1). Furthermore, the second ADC (ADC2) can generate data corresponding to the value of the current flowing into the source electrode of the second unit transistor (UT2) as second weighted gradient data (WGD1_2), and can output the second weighted gradient data (WGD1_2).

[0153] According to one embodiment, the operation of applying voltages corresponding to each of the second bit line (BL2), the first word line (WL1), and the second word line (WL2) can also be performed in the same manner as described above. In one example, the weighted gradient transistor array 6000 can activate multiple word lines or multiple source lines while activating one bit line at a time.

[0154] Reference Figure 7The weighted gradient transistor array 7000 may include: first to sixteenth unit transistors (UT1 to UT16); first to fourth bit lines (BL1 to BL4) connected to the drain electrodes of the unit transistors arranged in each row of the weighted gradient transistor array 7000; first to fourth word lines (WL1 to WL4) connected to the gate electrodes of the unit transistors arranged in each column of the weighted gradient transistor array 7000; first to fourth source lines (SL1 to SL4) connected to the source electrodes of the unit transistors arranged in each column of the weighted gradient transistor array 7000; a row DAC (RDAC) for applying row voltage; and selectively transmitting the first to fourth bit voltages. A bit-line demultiplexer (DEMUX) (i.e., RDMX) connected to at least one of the lines (BL1 to BL4) of the row DAC (RDAC); a column DAC (CDAC) for applying column voltage; a word-line DEMUX (CDMX) that selectively connects at least one of the first to fourth word lines (WL1 to WL4) of the column DAC (CDAC); an analog-to-digital converter (ADC) that outputs a digital signal corresponding to the current flowing into the first to fourth source lines (SL1 to SL4); and / or a source-line multiplexer (MUX) (i.e., MX) that selectively connects at least one of the first to fourth source lines (SL1 to SL4) of the ADC.

[0155] According to one implementation method, reference is also made to Figure 6 , Figure 7 The weighted gradient transistor array 7000 shown may further include... Figure 6 The weighted gradient transistor array 6000 shown is composed of common components. In one example, besides... Figure 6 In addition to the configuration of the weighted gradient transistor array 6000, Figure 7 The weighted gradient transistor array 7000 shown may further include bit lines DEMUX (RDMX), word lines DEMUX (CDMX), and / or source lines MUX (MX).

[0156] According to one embodiment, the signals applied to the first to fourth bit lines (BL1 to BL4), the first to fourth word lines (WL1 to WL4), and / or the first to fourth source lines (SL1 to SL4) can be controlled by the bit lines DEMUX (RDMX), word lines DEMUX (CDMX), or source lines MUX (MX) of the weighted gradient transistor array 7000. Figure 7 Among the constituent components shown, with Figure 6 The same components have been referenced. Figure 6 A description has been provided, and for the sake of brevity, it will not be repeated here.

[0157] According to one implementation method, reference is also made to Figure 3 , Figure 7 The weighted gradient transistor array 7000 shown can correspond to Figure 3 The weighted gradient transistor array is shown in the diagram. Figure 7 For ease of description, let's assume... Figure 7 The weighted gradient transistor array 7000 corresponds to Figure 3 The first weighted gradient transistor array 1310.

[0158] According to one implementation method, reference is also made to Figure 3 The weighted gradient input buffer 1350 can transmit the first initial input voltage value data (IVD1) to the weighted gradient transistor array 7000. In one example, the row DAC (RDAC) can receive the first initial input voltage value data (IVD1). In one example, the row DAC (RDAC) can apply a voltage corresponding to the first initial input voltage value data (IVD1) to at least one of the first to fourth bit lines (BL1 to BL4). In one example, the bit line DEMUX (RDMX) can connect the row DAC (RDAC) to at least one of the first to fourth bit lines (BL1 to BL4) based on the bit line selection signal (BLS).

[0159] According to one implementation method, reference is also made to Figure 3 The weighted gradient input buffer 1350 can transmit the first error data (EOD1) to the weighted gradient transistor array 7000. In one example, the column DAC (CDAC) can receive the first error data (EOD1). In one example, the column DAC (CDAC) can apply a voltage corresponding to the first error data (EOD1) to at least one of the first to fourth word lines (WL1 to WL4). In one example, the word line DEMUX (CDMX) can connect the column DAC (CDAC) to at least one of the first to fourth word lines (WL1 to WL4) based on the word line selection signal (WLS).

[0160] According to one embodiment, the weighted gradient transistor array 7000 can output first weighted gradient data (WGD1) via an analog-to-digital converter (ADC) based on first initial input voltage value data (IVD1) applied to the row DAC (RDAC) and first error data (EOD1) applied to the column DAC (CDAC). For example, the first bit line (BL1) and the row DAC (RDAC) are connected to each other via the bit line DEMUX (RDMX) so that the voltage corresponding to the first initial input voltage value data (IVD1) can be applied to the first bit line (BL1). Furthermore, the first word line (WL1) and the column DAC (CDAC) are connected to each other via the word line DEMUX (CDMX) so that the voltage corresponding to the first error data (EOD1) can be applied to the first word line (WL1). In this case, the voltage corresponding to the first initial input voltage value data (IVD1) can be applied to the drain electrode of the first unit transistor (UT1) through the first bit line (BL1), and the voltage corresponding to the first error data (EOD1) can be applied to the gate electrode of the first unit transistor (UT1) through the first word line (WL1). At this time, when the first source line (SL1) and the analog-to-digital converter (ADC) are connected to each other through the source line MUX (MX), the first weighted gradient data (WGD1) output from the ADC can include data corresponding to the current flowing into the source electrode of the first unit transistor (UT1).

[0161] The configuration of the weighted gradient transistor array 7000 according to this disclosure is merely an example, and certain configurations can be added to or omitted from the configuration of the weighted gradient transistor array 7000. For example, besides Figure 7 In addition to the components shown, the weighted gradient transistor array 7000 may further include unit transistors, bit lines, word lines, source lines, row DACs, column DACs, and / or ADCs. Although for ease of description... Figure 7 A transistor array formed in a (4×4) matrix structure is shown, but Figure 7 This is merely an example of some configurations for a weighted gradient transistor array, and it should be noted that the number of transistors, row DACs, column DACs, and / or ADCs in the weighted gradient transistor array 7000 are not limited to this.

[0162] According to one embodiment, at least at one point in time, current can simultaneously flow into the source electrodes of the first to fourth unit transistors (UT1 to UT4) disposed in the first row of the weighted gradient transistor array 7000. In one example, when the first bit line (BL1) is connected to the row DAC (RDAC) via the bit line DEMUX (RDMX), the row DAC (RDAC) can apply a voltage corresponding to the first initial input voltage value data (IVD1) to the first bit line (BL1). Furthermore, at least at one point in time, when at least one of the first to fourth word lines (WL1 to WL4) is connected to the column DAC (CDAC), the word line DEMUX (CDMX) and the column DAC (CDAC) can apply a voltage corresponding to the first error data (EOD1) to at least one connected word line. Therefore, when at least one of the first to fourth source lines (SL1 to SL4) is connected to the analog-to-digital converter (ADC) via the source line MUX (MX), the ADC can generate and output the current flowing into the source electrode of the unit transistor through the connected source line and the corresponding data as the first weighted gradient data (WGD1).

[0163] According to one implementation method, reference is also made to Figure 2 When the first word line (BL1) is connected to the row DAC (RDAC) via the bit line DEMUX (RDMX), the row DAC (RDAC) can transmit a voltage corresponding to a first voltage (dI / dG) used as the initial input voltage value for MAC calculation in the transistor array computer 1100 to the first word line (BL1). Additionally, when at least one of the first to fourth word lines (WL1 to WL4) is simultaneously connected to the column DAC (CDAC) via the word line DEMUX (CDMX) at least at one point in time, the column DAC (CDAC) can simultaneously transmit a voltage corresponding to a second voltage (dE / dI) to at least one connected word line at least at one point in time. This second voltage (dE / dI) corresponds to the change in the MAC calculation error relative to the current value formed as a result of the MAC calculation performed by the transistor array computer 1100. At this time, the current flows into each unit transistor connected to the first word line. The current at the source electrode can correspond to the value "(dI / dG)×(dE / dI)=(dE / dG)" obtained by multiplying the first voltage "(dI / dG)" by the second voltage. In this case, when the first to fourth source lines When at least one of them is connected to the ADC via the source line MUX(MX), the ADC can generate and output data corresponding to the sum of the currents flowing into the source electrode of the unit transistor through the connected source line “(4×(dE / dG))” as the first weighted gradient data (WGD1).

[0164] According to one embodiment, similar to the method described above, the weighted gradient transistor array 7000 can sequentially generate and output unit transistors that flow into the second row of the weighted gradient transistor array 7000. The sum of the currents at the source electrodes flows into the unit transistors located in the third row of the weighted gradient transistor array 7000. The sum of the currents at the source electrodes, or the current flowing into the unit transistors located in the fourth row of the weighted gradient transistor array 7000. The data corresponding to the sum of the currents at the source electrodes.

[0165] Figure 8A This is a diagram illustrating an example of an inference artificial neural network (ANN) model according to some embodiments of the present disclosure.

[0166] Reference Figure 8A The inference artificial neural network (ANN) computation process 8000 may include a process of calculating weights from input data and deriving a result value based on the computation result. For example, if the input data is image data about faces, the inference artificial neural network (ANN) computation process 8000 may include a process for recognizing faces from the input data and deriving a result called a "face" based on the recognition result. In one example, the MAC calculation may be performed in the process of multiplying the input data by weights or gradients. According to one implementation, the input gradient may correspond to the gradient multiplied with the input data to obtain the result of the MAC calculation.

[0167] According to one implementation, when preset weights or gradients are applied to input data, the output value changes according to the weights or gradients, so that the weights or gradients may need to be modified according to the output value. In one example, the process of multiplying or modifying the weights or gradients in the forward propagation direction from the input data to the result value in order to obtain the desired result can correspond to the inference artificial neural network (ANN) computation process 8000.

[0168] According to one implementation method, reference is also made to Figure 4 The inference process 4000 can correspond to the inference artificial neural network (ANN) computation process 8000. In one example, the inference artificial neural network (ANN) computation process 8000 can include a process of performing data communication (i.e., data transfer / reception) between a transistor array computer 1100, a global buffer 1200, or external memory (e.g., off-chip DRAM 1500). For example, image data about a face can correspond to input data (ID).

[0169] Figure 8B This is a diagram illustrating examples of training artificial neural network (ANN) models according to some embodiments of the present disclosure.

[0170] Reference Figure 8B The training process 8100 for an artificial neural network (ANN) may include an inference process 8110, an error checking process 8120, and / or an update process 8130. In one example, reference is also made to... Figure 8A The reasoning process can correspond to Figure 8A The reasoning artificial neural network (ANN) computation process 8000.

[0171] According to one implementation, the inference process 8110 may include a process of calculating weights from input data and deriving a result value. For example, when the input data is image data about a face, the inference process 8100 may include a process for identifying a face from the input data and obtaining a result referred to as a "face". For example, even if the input data is image data about a face, the inference process 8110 may also derive a result referred to as a "dog face" as a result of applying weights or gradients to the input data.

[0172] According to one implementation, the error checking process 8120 may include a process for determining the difference between a target value and a result value derived from weights calculated based on input data. For example, the error checking process 8120 may check the difference between the result value "dog face" obtained from the calculation of weights or gradients based on input data and the target result "human face". For example, in the error checking process 8120, error data may be generated based on the MAC calculation input data and / or MAC calculation output data of each transistor used for the result data "dog face" and "human face".

[0173] According to one implementation method, reference is also made to Figure 4 The input gradient calculation process 4100 or the weight gradient calculation process 4200 can correspond to the error checking process 8120. In one example, the artificial neural network training calculation process 8100 may include a process of performing data communication (data transfer / reception) between a transistor array computer 1100, a global buffer 1200, a weight gradient computer 1300, or external memory (e.g., off-chip DRAM 1500). For example, data regarding the errors of "dog faces" and "human faces" can correspond to error data (ED). Furthermore, the correction values ​​used for error correction gradients or weights can correspond to weight gradient data (WGD).

[0174] According to one implementation, the update process 8130 may include confirming an error value based on the output value to modify the gradient or weights, and correcting the gradient or weights in reverse order from the output to the input direction based on the confirmed error value. In one example, the gradient or error used in the inference process 8100 may be corrected based on a correction value used to correct the gradient or weights based on the error identified in the error checking process 8120. In one example, the process of correcting the gradient or weights through backpropagation (i.e., from the result data to the input data direction) based on the error value obtained after the completion of the inference process 8100 may correspond to the update process 8130.

[0175] According to one implementation method, reference is also made to Figure 4 The weight update process 4300 can correspond to the update process 8130. In one example, the update process 8130 may include a process of performing data communication (data transfer / reception) between the transistor array computer 1100, the global buffer 1200, and / or external memory (e.g., off-chip DRAM 1500). For example, the correction value used for error correction gradients or weights can correspond to weight gradient data (WGD). In one example, the gradient or weights can be corrected via backpropagation based on the weight gradient data (WGD).

[0176] According to one implementation, the artificial neural network (ANN) training computation process 8100 can perform ANN computation based on a large amount of input data. In one example, the ANN training computation process 8100 may include performing a gradient or weight MAC calculation on the large amount of input data, and then performing a reverse MAC calculation on the resulting error. In one example, Figure 1 The CIM module 1000 can improve the efficiency of the transistor array in terms of area and power consumption when performing MAC calculations on large amounts of input data, and thus improve the efficiency of training artificial neural networks (ANN) calculations.

[0177] It is evident from the above description that the in-memory computing (CIM) module according to embodiments of the present disclosure can improve the efficiency of area and power consumption of the transistor array used in the weighted gradient computer included in the CIM module.

[0178] The embodiments disclosed herein can provide a variety of effects that can be directly or indirectly recognized through the aforementioned patent documents.

[0179] Those skilled in the art will recognize that this disclosure can be implemented in other specific ways than those described herein. Furthermore, claims not expressly set forth in the appended claims may be presented as embodiments in combination, or incorporated as new claims through subsequent amendments after the filing of the application.

[0180] Although several illustrative embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments can be designed based on the description and / or illustration in this patent document.

Claims

1. A CIM module, wherein CIM is in-memory computing, the CIM module comprising: A transistor array computer, wherein each unit includes at least one transistor and at least one resistive random access memory (ReRAM); buffer; as well as A weighted gradient computer, comprising at least one unit transistor, The weight gradient computer includes: A line DAC, which applies a voltage corresponding to the initial input voltage value dI / dG = V used in MAC calculation to the first electrode of the unit transistor; DAC is a digital-to-analog converter, and MAC refers to multiplication and accumulation. A series DAC, which applies a voltage corresponding to the change in current value dE / dI resulting from the execution of the MAC calculation error to the second electrode of the unit transistor; and An ADC is an analog-to-digital converter that outputs a digital signal corresponding to the current flowing into the third electrode of the unit transistor.

2. The CIM module according to claim 1, wherein, The transistor array computer: In response to the MAC calculation, MAC calculation input data and MAC calculation output data are generated.

3. The CIM module according to claim 2, wherein, The MAC calculation input data includes: At least one of the data corresponding to the initial input voltage value used in the MAC calculation and the data corresponding to the threshold voltage value.

4. The CIM module according to claim 2, wherein, The buffer: Receive the MAC calculation output data and the MAC calculation input data from the transistor array computer; as well as The received MAC calculation output data and the received MAC calculation input data are transmitted to the row DAC or the column DAC.

5. The CIM module according to claim 2, wherein, The MAC calculation output data includes: At least one of the error data of the MAC calculation and the data corresponding to the current value formed as a result of performing the MAC calculation.

6. The CIM module according to claim 1, wherein: The first electrode corresponds to the drain electrode of the unit transistor; The second electrode corresponds to the gate electrode of the unit transistor; as well as The third electrode corresponds to the source electrode of the unit transistor.

7. The CIM module according to claim 1, wherein, The buffer: Receive data corresponding to the current flowing from the ADC to the third electrode.

8. The CIM module according to claim 7, wherein, The buffer: The data corresponding to the current flowing into the third electrode is transmitted to the transistor array computer.

9. A CIM module, wherein CIM is in-memory computing, the CIM module comprising: The first transistor array, in which multiple unit transistors are arranged; as well as The second transistor array performs MAC calculations, where MAC stands for multiplication and accumulation. The first transistor array includes: The first row of DACs applies a voltage corresponding to the first initial input voltage value used in the MAC calculation to the drain electrode of the unit transistor arranged in the first row of the first transistor array. The DAC is a digital-to-analog converter. A first column of DACs applies a voltage corresponding to the change in a first current value resulting from the execution of the MAC calculation relative to a first error in the MAC calculation to the gate electrode of the unit transistor arranged in the first column of the first transistor array; and The first ADC outputs a digital signal corresponding to the current flowing into the source electrode of the unit transistors arranged in the first column; the ADC is an analog-to-digital converter.

10. The CIM module according to claim 9, wherein, The first transistor array further includes: The second row of DACs applies a voltage corresponding to the second initial input voltage value used in the MAC calculation to the drain electrode of the unit transistor arranged in the second row of the first transistor array computer.

11. The CIM module according to claim 9, wherein, The first transistor array includes: The second column of DACs delivers a voltage to the gate electrode of the unit transistors arranged in the second column of the first transistor array, corresponding to the amount of change in the second error of the MAC calculation relative to the second current value formed as a result of performing the MAC calculation; and The second ADC outputs a digital signal corresponding to the current flowing into the source electrode of the unit transistors arranged in the second column.

12. The CIM module according to claim 11, wherein: A voltage corresponding to the change in a first current value resulting from the execution of the MAC calculation relative to the first error of the MAC calculation, and a voltage corresponding to the change in a second current value resulting from the execution of the MAC calculation relative to the second error of the MAC calculation, are applied simultaneously at least at one point in time.

13. The CIM module according to claim 11, wherein, The first ADC and the second ADC: Simultaneously, it outputs a digital signal corresponding to the current at at least one point in time.

14. The CIM module according to claim 9, further comprising: A buffer that receives from the second transistor array data corresponding to a first initial input voltage value used in the MAC calculation, and data corresponding to the amount of change of a first error in the MAC calculation relative to a first current value formed as a result of performing the MAC calculation.

15. A CIM module, wherein CIM is in-memory computing, the CIM module comprising: A transistor array computer, wherein each unit includes at least one transistor and at least one resistive random access memory (ReRAM); buffer; as well as A weighted gradient computer, in which unit transistors are arranged in multiple rows and columns. The weight gradient computer includes: Multiple bit lines transmit signals corresponding to the initial input voltage values ​​used in MAC calculations to the first electrode of the unit transistors arranged in each row. MAC stands for multiplication and accumulation. Multiple word lines, each transmitting a signal to the second electrode of a unit transistor arranged in each column, corresponding to the amount of change in the error of the MAC calculation relative to the current value formed as a result of performing the MAC calculation; and Multiple source lines transmit signals corresponding to the current flowing into the third electrode of the unit transistor arranged in each column.

16. The CIM module according to claim 15, further comprising: A digital-to-analog converter (DAC) generates a signal corresponding to the initial input voltage value. as well as Bit line DEMUX, which selectively connects at least one of the plurality of bit lines to the row DAC, DEMUX being a demultiplexer.

17. The CIM module according to claim 15, further comprising: A DAC generates a signal corresponding to the amount of change in the current value resulting from the execution of the MAC calculation, the error of the MAC calculation being a digital-to-analog converter. as well as A word line DEMUX, which selectively connects at least one of the plurality of word lines to the column DAC, wherein the DEMUX is a demultiplexer.

18. The CIM module according to claim 15, further comprising: ADC, ADC stands for Analog-to-Digital Converter; as well as A source line MUX selectively connects at least one of the plurality of source lines to the ADC; the MUX is a multiplexer.

19. The CIM module according to claim 15, wherein: Each of the first electrodes corresponds to each drain electrode of the unit transistor; Each of the second electrodes corresponds to each gate electrode of the unit transistor; as well as Each of the third electrodes corresponds to each source electrode of the unit transistor.

20. The CIM module according to claim 19, wherein, The buffer: Store data corresponding to the current flowing into the source electrode of the unit transistor.

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