Two-dimensional ring gate transistor doping method based on ultrafast laser direct writing and CMOS device

Abstract

The invention discloses a two-dimensional ring gate transistor doping method based on ultrafast laser direct writing and a CMOS device, and belongs to the technical field of microelectronic device manufacturing and advanced semiconductors. The method comprises the following steps: providing a substrate on which a two-dimensional semiconductor material ring gate transistor array is prepared; constructing a gas-phase or liquid-phase doping environment on the surface of the gate-all-around transistor; carrying out scanning doping on the selected channel region by adopting an ultrafast laser processing system; and carrying out a post-processing step. According to the method, the nonlinear optical effect and the cold machining characteristic of ultrafast laser are utilized, nanoscale precise doping of the two-dimensional ring gate transistor is achieved, and lattice damage of a traditional doping technology to atomic-scale thickness two-dimensional materials is effectively avoided. By regulating and controlling laser parameters and doping environment, monolithic integration of the N-type transistor and the P-type transistor can be realized in a single two-dimensional material system, and the threshold voltage can be precisely regulated and controlled. The method has the advantages of nanoscale spatial resolution, no-damage processing, controllable doping concentration, low process temperature and the like, and is suitable for advanced semiconductor manufacturing and high-performance CMOS (complementary metal oxide semiconductor) integrated circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronic device fabrication and advanced semiconductor technology, and particularly relates to a two-dimensional ring-gate transistor doping method based on ultrafast laser direct writing and a device structure prepared by the method. Specifically, the present application focuses on the selective doping technology of two-dimensional semiconductor materials in the ring-gate transistor architecture, including the implementation of the doping process, the optimization design of the device structure, and the application in advanced integrated circuit fabrication. BACKGROUND

[0002] With the continuous evolution of semiconductor technology, traditional silicon-based transistors have gradually approached the physical and quantum limits in terms of size scaling. The continuous reduction of device channel length leads to more serious short channel effects, enhanced electrostatic coupling between drain and source, and decreased control ability of the gate on the channel potential. At the same time, the quantum tunneling effect significantly increases the gate leakage current, and the traditional oxide layer is difficult to balance the reduction of thickness and insulation properties. The problems such as mobility degradation, parasitic capacitance increase, and power density increase jointly restrict the performance improvement of silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs). The continuation of Moore's law therefore faces unprecedented challenges, and it is urgent to explore new channel materials and new device structures. In addition, since the transition from FinFET to GAAFET structure has become an inevitable trend for advanced logic nodes, higher requirements are put forward for the electrical uniformity, interface controllability, and three-dimensional gate covering ability of the channel material. The mobility degradation and interface roughness scattering problems of traditional silicon materials under extremely thin body channels gradually become prominent, which further limits its application space in sub-3 nm nodes.

[0003] In this context, two-dimensional semiconductor materials (2D semiconductors) are considered as a key material system for continuing the silicon-based micro-scaling route due to their atomic thickness, high specific surface area, low interface defect density, and strong electrostatic gating capability. Among them, bismuth selenide oxide (Bi2O2Se) is a layered n-type two-dimensional semiconductor that has high electron mobility (>200 cm² / V·s), high thermal stability, and excellent chemical inertness, and has unique advantages in high-performance logic devices, memories, and photodetectors. Similarly, transition metal sulfides (such as MoS2, WS2) and black phosphorus (BP) and other materials have also been widely studied for the next generation of low-power field effect transistors. Compared with traditional silicon channels, the ultra-thin characteristics of two-dimensional materials can effectively suppress short channel effects, achieve ideal subthreshold swing and higher on-off ratio, and provide a theoretical and practical basis for transistor gating capability at advanced nodes. In recent years, various controllable preparation technologies of two-dimensional materials (such as MBE epitaxy, MOCVD, metal halide-assisted growth, etc.) have rapidly developed, making large-size, high-uniformity two-dimensional films possible, further promoting the feasibility of two-dimensional semiconductors in industrial applications. However, the "ultra-thin advantage" of two-dimensional materials also brings process challenges such as narrow processing window and strong interface sensitivity, making the practical application of two-dimensional materials in front-end-of-line (FEOL) still need to break through a large number of basic bottlenecks.

[0004] In recent years, two-dimensional materials have made breakthrough progress in transistor applications. For example, through epitaxial growth technology, in-situ hetero-integration of two-dimensional semiconductors and high-k dielectric layers provides high-quality interfaces for high-performance two-dimensional field effect transistors (2D-FET). In particular, the two-dimensional fin field effect transistor (2D FinFET) architecture reported in 2023 first demonstrated the feasibility and superiority of two-dimensional semiconductors in three-dimensional gate-all-around (GAA) structures. This achievement verifies the potential application prospects of two-dimensional materials in sub-5 nm process nodes and post-moore era logic devices, and provides an experimental basis for new device structures such as ring-gate transistors. At the same time, international major wafer factories and research institutions (IMEc, TSMC, IBM, MIT, etc.) have already laid out two-dimensional material CMOS platform research, but generally point out that the doping, contact, electrode interface engineering, and threshold voltage regulation of two-dimensional materials are still process bottlenecks, among which "immature doping technology" has been considered as the number one obstacle to the landing of 2D-CMOS.

[0005] However, to realize the scaling and practicality of two-dimensional ring gate transistors, its doping regulation technology still faces multiple bottlenecks. First, the traditional ion implantation doping technology relies on high-energy ion bombardment to achieve impurity introduction, but for atomic thickness two-dimensional materials, high-energy ions will directly damage the lattice structure, causing problems such as vacancy defects, atomic delamination, and chemical bond rupture. Studies have shown that the carrier mobility of two-dimensional materials treated by traditional ion implantation is usually reduced to less than 50% of the initial value, and the on-off ratio and sub-threshold characteristics of the device are significantly deteriorated. In addition, high-energy implantation also leads to increased interface state density and rising surface roughness, seriously affecting the interface stability and device consistency. Second, in terms of doping precision and controllability, existing technologies are difficult to achieve localized, high-resolution doping regulation for individual transistors at the nanoscale. Chemical vapor doping, thermal diffusion doping, and solution doping have advantages in process complexity and low cost, but their spatial resolution is limited, the doping distribution uniformity is poor, and they often involve high heat budget processes, which can easily cause thermal damage and performance degradation of two-dimensional materials. In addition, it is difficult to control the doping depth, concentration, and boundary, resulting in significant device performance dispersion, which is difficult to meet the strict requirements of advanced process nodes for device consistency and repeatability. Third, in terms of CMOS integration process compatibility, existing two-dimensional material doping strategies are still difficult to achieve the co-integration of N-type and P-type devices within the same wafer or the same two-dimensional material system. Traditional methods usually rely on material transfer, selective coverage, or multi-step epitaxy processes, increasing manufacturing complexity, alignment errors, and cost burdens, and are not conducive to large-area wafer-level integrated manufacturing. The lack of N / P controllable doping under a unified material system has become a key obstacle to the development of two-dimensional CMOS logic devices. In addition, the interface quality control between two-dimensional materials and high-k dielectric layers is also an important factor affecting threshold voltage regulation and device stability. Interface defects and trap states can cause charge trapping effects, leading to threshold drift, noise rise, and reliability decline. Although the traditional high-temperature annealing repair process can reduce the interface defect density to some extent, for two-dimensional materials, excessively high temperature can easily cause material delamination, oxidation, or component decomposition, making it difficult to achieve ideal interface passivation effect. It is worth emphasizing that the doping form of two-dimensional materials not only affects the carrier concentration, but also significantly affects the Schottky contact, work function regulation, and interface electric dipole distribution, further affecting the threshold voltage matching in the ring gate structure and the balance of bipolar CMOS devices. The existing technology generally lacks a comprehensive understanding of the relationship between "two-dimensional material local doping-interface electrical coupling-device structure response", resulting in a huge gap between theoretical design and process implementation.

[0006] In existing improvement schemes, some studies propose to use protective layer ion implantation technology, low-energy ion beam or plasma doping technology to reduce damage, but still cannot completely avoid the accumulation of lattice defects and the increase of carrier scattering. Some studies also use chemical vapor deposition (CVD) or solution chemical doping to introduce impurity atoms through high-temperature reaction, but the process window is narrow, the repeatability is poor, and the spatial control precision is insufficient. Although traditional laser doping processes (such as continuous wave or long pulse laser) can achieve non-contact doping, the thermal effect is significant, which can easily cause changes in the surface morphology or degradation of the structure of the two-dimensional material, and is limited by optical diffraction, making it difficult to break through the spatial resolution of hundreds of nanometers. Further, most existing laser doping technologies rely on thermal diffusion mechanism, which is severely limited by material thermal diffusion coefficient and absorption depth, making it difficult to meet the requirements of sub-50 nm feature size devices for the abruptness of the doping region boundary; at the same time, it is difficult to be directly integrated with photolithography process, which also limits its application potential as a "programmable doping module" in advanced nodes.

[0007] In summary, existing two-dimensional material doping technologies have significant limitations in damage control, spatial precision, concentration adjustability, and process compatibility, making it difficult to meet the performance and consistency requirements of advanced processes for nanoscale transistors. Therefore, there is an urgent need for a new technical path that can achieve non-contact, damage-free, nanoscale spatial resolution doping at room temperature or low temperature. This technology should have programmable and digital control capabilities, and be seamlessly integrated with existing CMOS processes, thereby realizing the monolithic integration of two-dimensional material N-type and P-type devices, and providing technical support for the manufacture of next-generation high-performance, low-power logic circuits. More importantly, this new technical path should be able to realize "reversible doping, erasable doping, sidewall doping in three-dimensional structures" and other functions for future reconfigurable devices, programmable logic units, and artificial intelligence accelerator architectures.

[0008] The present application is exactly aimed at the above problems, and proposes a two-dimensional ring gate transistor local doping method based on ultrafast laser direct writing technology. This method uses the nonlinear optical absorption characteristics of femtosecond ultra-short pulse laser to realize accurate energy deposition on the local area of the two-dimensional material surface, and realizes controllable doping under the premise of maintaining the integrity of the lattice, thereby providing an effective solution for the application of two-dimensional semiconductors in advanced processes and new CMOS architectures. SUMMARY

[0009] The primary purpose of the present application is to solve the technical bottlenecks existing in the practical application of the existing two-dimensional material doping technology, such as the great structural damage to the material body caused by the doping process, the limited spatial resolution, and the difficulty in achieving high-precision control of doping concentration and distribution, so as to propose a non-contact, nanoscale spatial resolution, programmable control method for local doping of two-dimensional ring gate transistors. Through the method of the present application, the carrier type and concentration of the local region of the two-dimensional semiconductor material can be controlled and adjusted without damaging the integrity of the crystal lattice of the two-dimensional semiconductor material, and high-precision electrical property control can be achieved.

[0010] Another important purpose of the present application is to provide a two-dimensional material doping method based on ultrafast laser direct writing technology. This method realizes precise energy injection into the surface and interface of the local region of the material by using the nonlinear light-matter interaction of ultra-short pulse laser, and further triggers selective chemical reaction or local structure modulation. This technology not only realizes spatial accurate definition of the doping region on the nanoscale, but also effectively controls the threshold voltage, mobility and carrier type while maintaining the intrinsic high mobility and stability of the material, meeting the strict requirements of high-performance electronic and optoelectronic devices for doping precision.

[0011] Still another purpose of the present application is to provide a high-performance two-dimensional ring gate transistor device prepared by the above method. This device can realize monolithic integrated manufacturing of N-type and P-type transistors in a single two-dimensional semiconductor material system, greatly simplifying the traditional epitaxy, multiple doping and complex doping mask process technology. The obtained device not only has excellent electrical switching characteristics and low power consumption characteristics, but also has high working stability and batch preparation consistency, providing technical support for the next generation of integrated circuits and system on a chip.

[0012] To achieve the above-mentioned purposes of the present application, the present application provides a two-dimensional ring gate transistor local doping method based on ultrafast laser direct writing, comprising the following detailed steps:

[0013] Step 1: Device structure preparation

[0014] A substrate prepared with a two-dimensional semiconductor material ring gate transistor array is provided, and the specific structure comprises:

[0015] Substrate: a standard SiO2 / Si substrate or other suitable insulating substrate is used, the thickness of the SiO2 layer is 90-300 nm, and the resistivity of the silicon substrate is 1-10 Ω·cm;

[0016] Two-dimensional semiconductor channel: a Bi2O2Se thin film with a thickness of 0.5-5 nm is used, and the mobility thereof should be higher than 200 cm² / V·s, and the surface roughness of the thin film is less than 0.3 nm;

[0017] Gate dielectric: including Bi2SeO5 natural oxide or atomic layer deposition of high-k dielectric (such as HfO2, Al2O3), equivalent oxide thickness (EOT) is 0.8-2.0 nm;

[0018] Gate electrode: using a work function adjustable metal gate (such as TiN, TaN) or a polysilicon gate, the thickness is 50-100 nm;

[0019] Source / drain electrode: using a metal system (such as Ni / Au, Ti / Au) that forms ohmic contact with two-dimensional materials, the contact resistance is less than 1×10⁻ 7 Ω·cm².

[0020] Step two: Doping environment construction

[0021] A controllable doping environment is constructed on the surface of the ring gate transistor, and the specific embodiment includes:

[0022] Gas phase environment construction: the device is placed in a special vacuum chamber, the chamber background vacuum degree is better than 1×10⁻ 6 Torr, high-purity doping gas is introduced, and the doping gas includes:

[0023] P-type doping gas: Cl2, Br2 or NO2, the concentration is accurately controlled in the range of 10-1000 ppm, and the carrier gas is high-purity N2 or Ar;

[0024] N-type doping gas: H2S, SF6 or NH3, the concentration is accurately controlled in the range of 10-1000 ppm; the gas flow is controlled in the range of 10-100 sccm, and the chamber pressure is maintained in the range of 10-760 Torr;

[0025] Liquid phase environment construction: spin coating a doping precursor solution on the surface of the device, controlling the film thickness in the range of 5-100 nm by spin coating speed (1000-5000 rpm), and the precursor includes:

[0026] P-type precursor: HAuCl4 (concentration 1-100 mM), MoCl5 or WCl6 solution, solvent is deionized water or ethanol;

[0027] N-type precursor: (NH4)2S (concentration 1-50%), CS2 or polyethyleneimine (PEI, concentration 0.1-10 mg / mL) solution.

[0028] Step three: ultrafast laser direct writing doping

[0029] A high-precision ultrafast laser processing system is used to scan and dope the selected ring gate transistor channel region, and the specific parameters and control requirements are as follows:

[0030] Laser system: femtosecond or picosecond laser, with beam quality M²<1.3, power stability ±1%;

[0031] Optical system: high numerical aperture objective lens (NA=0.5-1.4), matched with precise three-dimensional displacement platform, positioning accuracy ±10nm;

[0032] Laser parameters: wavelength: 400-1064nm, preferably 515nm or 1030nm; pulse width: 10-500fs, preferably 100-300fs; repetition rate: 1-1000kHz, selected according to scanning area and efficiency requirements; single pulse energy: 0.1-100nJ, which needs to be accurately calibrated and stably controlled; scanning speed: 0.1-100mm / s, matched with repetition rate to ensure sufficient pulse overlap rate; focused spot diameter: 200-800nm, controlled by objective lens NA and wavelength;

[0033] Scanning control: vector scanning path is adopted, programmed control is carried out according to preset doping pattern, and accurate doping of complex pattern can be realized;

[0034] Process monitoring: CCD camera is integrated for real-time observation of the processing process, and a spectrometer can be equipped to monitor the interaction between the laser and the material.

[0035] Step four: post-processing and performance recovery.

[0036] After laser direct doping is completed, the sample is subjected to necessary subsequent processing to stabilize and activate the doped region. First, the residual dopant is removed: for liquid-phase precursors, high-purity deionized water (resistivity > 18 MΩ·cm) can be used to flush for a few seconds and nitrogen gas is blown dry; for gas-phase doping, the chamber can also be purged with an inert gas under vacuum to remove unreacted gas molecules. Next, rapid thermal annealing (RTA) is performed: the sample is heated to 100-300 °C for 10-60 minutes (optionally, for example, 200 °C for 15 minutes) in an inert atmosphere such as N2or Ar, and the heating and cooling rates are controlled at 5-50 °C / s. Annealing helps to repair a small amount of dangling bonds or defects generated during laser processing, enables the introduced impurity atoms to form stable bonds in the two-dimensional lattice, and drives off adsorbed neutral fragments, thereby improving the activation rate of doping. For some materials, annealing can also slightly diffuse the doping profile and homogenize the impurity distribution. Then, a passivation layer (for example, a 2-10 nm thin layer of Al2O3or SiO2) can be deposited on the device surface as needed to cap the doped region, isolate the environment from oxidation or water vapor, and thus improve the long-term stability of the device. After the above steps are completed, the prepared doped device enters the electrical performance testing stage: a semiconductor parameter analyzer is used to comprehensively characterize the transfer characteristics (Id-Vg), output characteristics (Id-Vd), and subthreshold characteristics of the device. In particular, by comparing the characteristics of the device before and after doping, the doping effect and parameter changes can be verified. For the Bi2O2Se ring-gate transistor in this paper, P-type doping moves the threshold voltage in the positive direction, which is reflected in that the same drain-source current requires a higher positive gate voltage to be reached on the transfer curve; at the same time, the decrease in free electron concentration leads to a slight decrease in saturation on-current. N-type doping moves the threshold voltage in the negative direction, and the device is more easily turned on, but too strong n-type doping can increase the leakage current and slightly reduce the mobility. Through testing and extraction, the doping process of the present application can adjust the threshold voltage in the range of at least ±0.5 V, and keep the carrier mobility greater than 90% of the initial value, with little change in key performance such as subthreshold swing, proving that the method can accurately control the threshold without significantly damaging the intrinsic properties of the material.

[0037] Step five: complementary device integration

[0038] After the required N-type and P-type transistors are prepared in a single material system using the above method, CMOS circuit functional units can be further constructed. Figure 3The CMOS inverter (phase inverter) single chip integrated structure diagram in the application is shown, which contains a P-type transistor and an N-type transistor. The "ring gate" structure enables the two tubes to be closely arranged at the top layer, realizing vertical integration of the gate surrounding the channel; the sources / drains of the two tubes are connected with the power supply voltage V_DD and the ground GND through metal interconnection, and the output ends (the drain of the N tube and the drain of the P tube) of the two transistors are connected to form a common output node, and the gates are connected in parallel as the inverter input. Since the application can directly form channel regions of different polarities on the same two-dimensional semiconductor film, the channel materials and structures of the two transistors are completely the same, only one channel is converted to P-type (corresponding to P-channel transistor) and the other remains N-type through local doping, thereby realizing complementary symmetry. The positions of multiple inverter units can be defined on the whole chip at the same time through photolithography technology, then P-type or N-type regions are written at the corresponding positions by using laser direct writing doping, and metal interconnection lines are deposited, thereby completing the integration of the CMOS inverter circuit. It is worth noting that the laser scanning path is completely defined by software, so the positions and shapes of N-type / P-type regions can be freely laid out according to the needs of circuit design; the transition region of the doping boundary is narrower than 200 nm, ensuring good electrical isolation between adjacent devices. Since laser direct writing does not use a mask and can be programmed point by point, whether a small number of prototype devices or large-scale array manufacturing can be easily realized by adjusting the scanning program, meeting the requirements of flexible manufacturing and high yield of industrial production.

[0039] Through the above technical solution, the application can realize a doping spatial resolution better than 200 nm, which is much higher than that of the traditional photolithography doping process; the doping concentration can be continuously adjustable through laser energy and environmental parameters; the intrinsic high mobility and low defect characteristics of the two-dimensional semiconductor are maintained; N-type / P-type coexistence and monolithic integration are realized in a single material system; the process is non-contact and non-mechanical damage, suitable for large-scale programmable production.

[0040] Advantages of the application

[0041] 1. The cold processing characteristics of ultrafast laser fundamentally avoid the lattice damage of traditional doping technology to the atomic thickness two-dimensional material, and perfectly maintains the inherent high mobility characteristics of the material.

[0042] 2. Through the nonlinear optical effect, the diffraction limit is broken, and local doping of nanoscale is realized, meeting the stringent requirements of precise doping for advanced architectures such as ring gate transistors.

[0043] 3. It has digital direct writing capability, and can realize flexible design and preparation of complex doping patterns through software programming, providing a new possibility for customized circuit development.

[0044] 4. The wide range of transistor threshold voltage is precisely controlled, and the electrical characteristics of N-type and P-type devices can be perfectly matched on a single chip.

[0045] 5. The low-temperature process characteristics are fully compatible with existing semiconductor manufacturing processes, especially suitable for advanced packaging technologies such as three-dimensional integration, and have a clear industrialization path.

[0046] 6. While maintaining a high on-off ratio, the device interface quality, noise characteristics and long-term reliability are significantly improved, providing a reliable guarantee for high-performance chip manufacturing.

[0047] 7. Compared with traditional processes, energy consumption and chemical reagent consumption are greatly reduced, which meets the development direction of green manufacturing in the semiconductor industry.

[0048] In summary, the present application not only provides a new doping process, but also a "enabling" platform that can fully exploit the excellent intrinsic performance of two-dimensional materials. It successfully solves a core manufacturing bottleneck in the industrialization application of two-dimensional semiconductors, and provides key technical support for the development of the next generation of advanced integrated circuits based on two-dimensional materials. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the present application, the system structure and method flow of the present application are described below in conjunction with the drawings:

[0050] Figure 1 It is a two-dimensional ring gate transistor cross-sectional structure diagram of the present application.

[0051] Figure 2 It is a two-dimensional ring gate transistor doping method process flow diagram based on ultrafast laser direct writing of the present application.

[0052] Figure 3 It is a CMOS inverter monolithic integrated structure diagram of the present application. DETAILED DESCRIPTION

[0053] In order to further illustrate the technical solutions of the present application, the present application is described in detail below in conjunction with the drawings and examples. Those skilled in the art should understand that these examples are only used to explain the present application, and not to limit the scope of protection of the present application. Without departing from the spirit of the present application, various forms of improvements and changes can be made.

[0054] The application provides a two-dimensional ring gate transistor doping method based on ultrafast laser direct writing and a CMOS device. The method uses ultra-short pulse width laser (femtosecond or picosecond) to induce nonlinear absorption on the surface of two-dimensional semiconductor, realizes local energy deposition and controlled chemical reaction, and then realizes spatial programmable writing of P-type or N-type doping. By adjusting the laser energy density, focusing depth, scanning speed and gas / liquid phase environment, the application can accurately construct threshold complementary N-type and P-type transistor structures on a single chip, providing a basis for monolithic complementary circuit (CMOS) manufacturing of two-dimensional semiconductors.

[0055] Figure 1 The application is a two-dimensional ring gate transistor cross-sectional structure schematic diagram, which shows the basic hierarchical structure of the device of the application, including a substrate (Si / SiO2), an insulating layer (SiO2 layer), a two-dimensional semiconductor channel layer (such as a Bi2O2Se film), a ring gate dielectric layer (HfO2 dielectric) covering the channel, a ring gate electrode (TiN metal gate) surrounding the dielectric layer, and source / drain electrodes (Ti / Au ohmic contact) at both ends of the channel and a local laser doping area in the channel. Among them, the two-dimensional channel material Bi2O2Se has a thickness of about 0.5-5 nm, has a high mobility of >200 cm² / V·s and a surface of atomic level flatness. The ring gate structure realizes full coverage of the gate to the ultra-thin channel through the high dielectric constant HfO2 dielectric (equivalent oxide layer thickness EOT≈1.5 nm), effectively strengthens the electrostatic control ability; the TiN metal ring gate has a thickness of about 80 nm, forms a Gate-All-Around structure around the channel to suppress the short channel effect. The source and drain electrodes adopt 10 / 50 nm thick Ti / Au metal to realize ohmic contact with low contact resistance. Figure 1 The locally doped area indicated by the middle shadow represents the acceptor or donor impurity area introduced at a specific position of the channel by the laser doping method of the application, which is used to adjust the conductivity type and threshold voltage of the material at that position.

[0056] Figure 2 The application is a two-dimensional ring gate transistor doping method based on ultrafast laser direct writing and a CMOS device. The method uses ultra-short pulse width laser (femtosecond or picosecond) to induce nonlinear absorption on the surface of two-dimensional semiconductor, realizes local energy deposition and controlled chemical reaction, and then realizes spatial programmable writing of P-type or N-type doping. By adjusting the laser energy density, focusing depth, scanning speed and gas / liquid phase environment, the application can accurately construct threshold complementary N-type and P-type transistor structures on a single chip, providing a basis for monolithic complementary circuit (CMOS) manufacturing of two-dimensional semiconductors.

[0057] Figure 3 The schematic diagram of the CMOS inverter monolithic integrated structure of the present application.

[0058] Example One: P-type selective doping in gas phase environment

[0059] In this embodiment, local P-type doping is realized in Bi2O2Se two-dimensional ring gate transistors to control the threshold voltage of target devices. First, a Bi2O2Se ring gate transistor array (channel thickness of about 2 nm, mobility > 200 cm² / V·s) prepared according to step one above is provided. The sample is placed in a high vacuum laser processing chamber, and the background vacuum is brought to 1×10⁻ 6 Torr. Then, the doping atmosphere is introduced in a gas phase according to step two: high-purity NO2 gas (99.9%) is introduced into the chamber as the acceptor doping source, and the concentration is controlled at about 100 ppm (achieved by diluting pure NO2 gas), and the carrier gas N2 flow is 30 sccm, and the chamber pressure is maintained at about 40 Torr. Next, the laser parameters are set according to step three and scanning doping is performed: a femtosecond laser with a wavelength of 1030 nm and a pulse width of about 300 fs is used in this embodiment; the laser repetition frequency is selected to be 200 kHz, and an objective lens (NA = 0.8) is used to focus the laser on the Bi2O2Se channel surface 100 nm above (positive defocus). The channel region is scanned according to the predetermined doping pattern, and the scanning speed is 2 mm / s (to ensure that adjacent laser pulses overlap), and the line scanning interval is about 200 nm, so that the doping region covers the entire channel. The high-field effect of the femtosecond laser causes highly nonlinear optical effects on the surface of Bi2O2Se: a large number of carriers are excited by multiphoton absorption, and then a photochemical reaction of adsorbed NO2 molecules is triggered. The N–O bond of the NO2 gas molecules is broken under the action of the laser, and active nitrogen oxide radicals are released, which are embedded into the Bi2O2Se lattice (mainly occupying Se vacancies or combining with Bi–O bonds) to form acceptor energy levels. In this way, the originally n-type Bi2O2Se channel in the scanned region is converted into a P-type region doped with acceptors. After laser scanning is completed, the sample is annealed at 200 ℃ for 15 minutes in an N2 atmosphere to stabilize the doping effect (repair defects and enhance impurity activation). By changing the power and number of laser scans, the threshold voltage can also be gradually adjusted in this embodiment. As can be seen, the method of the present application realizes precise step-by-step control of the threshold voltage in a single device by controlling the laser dose, and has the potential to realize multi-threshold transistors and multi-stage logic circuits.

[0060] Example Two: N-type local doping assisted by liquid phase

[0061] In this embodiment, liquid precursor is used to realize local N-type doping of Bi2O2Se ring-gate transistor to reduce the channel threshold voltage. First, the prefabricated ring-gate transistor array is placed in a clean environment, and a layer of precursor solution containing sulfur elements is spin-coated on the surface of the device: (NH4)2S (aqueous solution) is selected as the N-type doping precursor (providing sulfur source), the concentration is 5 wt%, the spin-coating speed is 3000 rpm, and the time is 30 s, obtaining a uniform about 30 nm thick ammonium sulfide film covering the channel. Subsequently, the channel region is scanned and written under nitrogen protection using a 1030 nm femtosecond laser (pulse width 300 fs, repetition frequency 500 kHz). The laser is focused on the thin film / material interface through the objective lens, the scanning speed is 2 mm / s, and the line spacing is 150 nm. The multi-photon absorption effect of femtosecond laser generates a transient high temperature and high pressure environment locally, inducing the reaction between sulfur elements in the (NH4)2S thin film and the surface of Bi2O2Se: on the one hand, sulfur atoms may exchange with Se atoms on the surface of Bi2O2Se to form S-doping by filling Se vacancies; on the other hand, sulfur may form S-Bi bonds with Bi to form an n-type interface layer at the interface. After a single scan, the sample is washed with deionized water for 10 s to remove residual salt, then dried with N2, and annealed at 120 ℃ for 10 minutes to remove adsorbed solvent molecules and stabilize the sulfur doping bond. It should be noted that as the laser energy density increases, the degree of sulfur doping increases positively. Compared with traditional ion implantation, the method of this embodiment does not require photoresist mask and high-temperature diffusion process, avoiding serious bombardment damage to the two-dimensional lattice; using the digital direct writing of laser, the doping pattern precision can reach nanoscale and be flexible and adjustable, proving the significant advantages of this invention in low-damage and fine-controllable N-type doping.

[0062] Example Three: Same-chip N / P complementary doping and CMOS integrated preparation

[0063] This example demonstrates the simultaneous fabrication of N-type and P-type transistors on the same Bi2O2Se chip and their integration into a CMOS inverter circuit, verifying the application potential of the present application in two-dimensional CMOS integration. Specifically, the whole sample is first subjected to a mild N-type pre-doping, which preliminarily lowers the threshold voltage of all devices, and then a specific device region is selected for P-type doping to form complementary pairs. The procedure is as follows: First, following the method of Example 2, a thin film of (NH4)2S precursor is uniformly spin-coated on the channel of all transistors, and a global N-type doping scan is performed using a lower laser energy. The dose of the dopant is controlled at a low level, which lowers the threshold voltage of each transistor by about 0.2 V (e.g., from an initial ~0.5 V to ~0.2 V). The purpose of this treatment is to impart a certain n-type conductivity to the channel, thereby ensuring a sufficiently high on-current as an N-channel device, while providing a tunable reference for P-type devices. Next, the precursor thin film is removed from part of the transistor, and a local NO2 gas-phase doping is performed for the devices that need to achieve P-type (see Example 1). For example, in the designed CMOS inverter circuit, the unit region that serves as a P-channel transistor is exposed, and the channel is locally P-type by laser direct writing NO2 doping. The specific process parameters are: NO2 gas concentration 150 ppm, laser scanning speed 2 mm / s, and focus point offset 100 nm. Using a pre-programmed scanning program, only the selected P-type transistor channel positions in the layout are scanned and doped, while the remaining areas (including the transistors planned to be used as N-type) are not affected. By optimizing the laser focal spot and doping boundary control, the transition width of the doped region is kept within 200 nm, ensuring a clear P / N zone junction. After completing the complementary doping, the whole sample is annealed at 200 °C for 10 minutes under N2 atmosphere to eliminate the interface stress between different doped regions and stabilize the impurity distribution. In the final device array, N-type transistors and P-type transistors are uniformly distributed on the same wafer. Using standard photolithography and metal deposition processes, each pair of complementary transistors is connected according to the design of the CMOS inverter circuit. The final CMOS inverter circuit is shown in FIG. 6. The performance of the CMOS inverter circuit is evaluated by measuring the input-output transfer curve. The results are shown in FIG. 7. The CMOS inverter circuit exhibits a clear switching behavior, with a low threshold voltage of ~0.2 V and a high on-current of ~1.5 μA / μm. The performance of the CMOS inverter circuit is comparable to that of the conventional CMOS inverter circuit fabricated on a Si wafer, demonstrating the application potential of the present application in two-dimensional CMOS integration. Figure 3The connection is shown as an inverter structure: the P tube drain and the N tube drain are connected as an output, the P tube source is connected with V_DD, the N tube source is connected with GND, and the gate is used as an input. Test finds that the inverter can realize correct logic inversion at low working voltage (for example, V_DD=1 V): when the input is low (0 V), the P tube is turned on and the N tube is turned off, and the output is pulled to high level; when the input is high (~1 V), the N tube is turned on and the P tube is turned off, and the output is pulled to low level. The inversion voltage of the circuit is about 0.5 V, which is close to half of V_DD, proving that the threshold values of the two tubes are well matched, and the device parameters are excellent in symmetry. At the same time, the output swing of the inverter is close to flat, and the high / low level noise margin is sufficient, and it can still be stable at a frequency of 10 MHz or above, without obvious hysteresis or metastable state. This shows that the two-dimensional CMOS device prepared by the method has excellent characteristics of low power consumption, high gain and high speed. More importantly, the whole preparation process of the CMOS inverter is completed on the same material system and the same substrate, without the complex epitaxial growth and multi-step ion implantation in the traditional CMOS process. This monolithic complementary integration is first in the field of two-dimensional electronics, which lays a foundation for subsequent realization of more complex logic circuits (such as ring oscillators, compute-in-memory units, etc.). The present application provides a new two-dimensional CMOS integration route, which significantly simplifies the process flow and reduces the manufacturing difficulty, and has important significance in advanced semiconductor manufacturing.

[0064] In summary, the present application proposes a two-dimensional ring gate transistor local doping method based on ultrafast laser direct writing technology to solve the bottleneck problems of current two-dimensional material devices in terms of doping accuracy, electrical property regulation and integration difficulty, and constructs an integrated implementation path of CMOS complementary structure. The method constructs a controllable doping environment in the two-dimensional channel region and realizes spatial selective doping of P-type or N-type regions by using femtosecond laser-induced nonlinear optical physical reaction. The whole process has the characteristics of nanoscale resolution, low heat damage and non-contact processing, which not only significantly reduces the risk of damage to the two-dimensional material lattice, but also has excellent programmable ability of doping pattern and industrial compatibility. Therefore, the method provides key process support for constructing high-performance, low-power-consumption and compact two-dimensional transistor devices, and is especially suitable for advanced manufacturing platforms with sub-10 nanometer nodes.

[0065] The core advantage of the present application is its material versatility and process adjustability. Although the patent embodiment is mainly exemplified with Bi2O2Se, the method is not limited to this and is fully applicable to other mainstream two-dimensional semiconductor systems, such as transition metal chalcogenides (MoS2, WS2, WSe2), III-VI materials (GaSe, InSe), and graphene-like structure materials. By adjusting the laser wavelength and pulse width parameters to match the optical absorption bandgap characteristics of different materials, extensive compatibility with different two-dimensional material systems can be achieved; at the same time, by flexibly selecting and controlling the concentration of doping gases (such as Cl2, NO2, H2S) or liquid precursors (such as HAuCl4, (NH4)2S), the stability and repeatability of the doping concentration are ensured, thereby meeting the customized regulation and control requirements of different device types for threshold voltage, conductivity polarity, and mobility.

[0066] The application range of this doping technology has exceeded the traditional logic circuit field. With the high spatial precision, low thermal budget, and programmable characteristics of this process, it has great potential to extend to various new two-dimensional electronic and optoelectronic devices, such as high-sensitivity two-dimensional photodetectors, sub-threshold swing optimized memristors, local band control quantum tunneling devices, and heterostructure constructed neuromorphic computing units. Especially in complex circuits that require high integration density and precise functional area division, such as two-dimensional CMOS integrated arrays, system on a chip (SoC), and flexible logic chips, this method can achieve monolithic integration of different functional transistors on the same two-dimensional material sheet, effectively simplifying the device preparation process and improving overall performance consistency and chip space utilization efficiency.

[0067] In the future, with the trend of combining three-dimensional stacked packaging, high-density interconnection, and large-scale reconfigurable architecture, this invention technology also has broad application prospects. Since its process temperature is below 300°C, it is compatible with flexible substrates and existing silicon CMOS platforms; its laser direct writing without mask, flexible pattern, and high degree of automation also make it have great potential for large-scale processing. Further combined with intelligent doping systems such as laser confocal scanning, electrical mapping monitoring, and automatic path optimization, rapid and accurate writing of the entire wafer-level two-dimensional circuit structure can be achieved. In summary, this method not only provides a revolutionary means for electrical regulation of two-dimensional materials, but also lays a key foundation for the diversification and functional evolution of semiconductor technology in the post-Moore era.

Claims

1. A two-dimensional ring gate transistor doping method based on ultrafast laser direct writing, characterized in that, The method comprises the following steps: providing a substrate for preparing an array of ring-gate transistors of two-dimensional semiconductor material; constructing a doping environment on the surface of the ring-gate transistors; scanning and doping a selected channel region of the ring-gate transistors by using an ultrafast laser processing system; and performing post-processing.

2. The method of claim 1, wherein the method is based on ultrafast laser direct writing. The two-dimensional semiconductor material is Bi2O2Se, with a thickness of 0.5-5 nm, a mobility higher than 200 cm² / V·s, and a surface roughness less than 0.3 nm.

3. The method of claim 1, wherein, The doping environment comprises a gas-phase doping environment or a liquid-phase doping environment, the gas-phase doping environment comprises a doping gas with a concentration of 10-1000 ppm, and the liquid-phase doping environment comprises a doping precursor solution with a thickness of 5-100 nm; wherein the doping gas comprises a P-type doping gas Cl2, Br2 or NO2, or an N-type doping gas H2S, SF6 or NH3.

4. The method of claim 1, wherein, The parameters of the ultrafast laser include a wavelength of 400-1064 nm, a pulse width of 10-500 fs, a repetition frequency of 1-1000 kHz, a single-pulse energy of 0.1-100 nJ, a scanning speed of 0.1-100 mm / s, and a focused spot diameter of 200-800 nm.

5. The method of claim 4, wherein, The ultrafast laser is a femtosecond laser, with a pulse width of 100-300 fs, a wavelength of 515 nm or 1030 nm, a beam quality M²<1.3, and a power stability of ±1%.

6. The doping method according to claim 1, characterized in that, The ultrafast laser scanning and doping is a selective doping of a local region of the two-dimensional semiconductor channel, and the spatial position and range of the doped region are defined by the laser focusing position and scanning path, so as to realize the local electrical property regulation without destroying the lattice structure of the two-dimensional semiconductor material.

7. The doping method according to claim 1, characterized in that, By adjusting the energy parameters and scanning parameters of the ultrafast laser, the channel region of the two-dimensional ring-gate transistor is subjected to different degrees of doping treatment, so as to obtain transistors with different threshold voltage characteristics.

8. A two-dimensional gate-all-around transistor CMOS device, characterized by, The CMOS device is prepared by the method of any one of claims 1-7, and at least one N-type ring-gate transistor and at least one P-type ring-gate transistor are formed in the same two-dimensional semiconductor material layer on the same substrate.

9. The CMOS device of claim 8, wherein, The device structures of the N-type ring-gate transistor and the P-type ring-gate transistor are the same, and the difference in the conductivity type is formed by the difference in the doping type of the two-dimensional semiconductor channel region.

10. An integrated circuit chip, characterized by The integrated circuit chip comprises the two-dimensional ring-gate transistor CMOS device of claim 8 or 9, and is suitable for advanced semiconductor manufacturing.

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