In-memory computing circuit based on floating gate transistor, computing array and reading method

Abstract

The invention discloses an in-memory computing circuit based on a floating gate transistor, a computing array and a reading method. The in-memory calculation circuit comprises a selection tube array, a floating gate transistor array and a proportional capacitor array; wherein the selection tube array comprises a plurality of independent selection tubes; the floating gate transistor array comprises a plurality of independent floating gate transistors; the proportional capacitor array comprises a plurality of independent proportional capacitors; the drain electrode of each independent floating gate transistor is connected with the source electrode of one independent selection tube; the source electrode of each independent floating gate transistor comprises two branches, one branch is connected with a shared output bus through a switch, and the other branch is connected with an independent proportional capacitor. According to the invention, the calculation characteristic of the in-memory calculation circuit based on the floating gate memory is utilized, and the data stored in the floating gate transistor in the in-memory calculation circuit can be inversely deduced directly through the calculation result, so that a complex peripheral circuit sensitive amplifier is omitted, the circuit complexity is reduced, and the circuit area is also reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of in-memory computing, in particular to an in-memory computing circuit based on floating gate transistor, a computing array and a readout method. BACKGROUND

[0002] In computer architecture, memory is used to store data. Memory can be divided into registers, cache, main memory according to the distance from the processor. Among them, the main memory is far away from the processor, has slow transmission speed and large area, and often needs to store a large amount of data and needs to be kept for a long time. Therefore, a non-volatile floating gate transistor is often selected.

[0003] The structure of the floating gate transistor is based on the NMOS (N-Metal-Oxide-Semiconductor) transistor, and a floating gate layer is added under the insulating layer of the control gate. When the floating gate layer has electrons, the threshold voltage is high, and when the read voltage is applied to the gate, the current passing through is small, which represents that the stored data is "0". When the floating gate layer has no electrons, the threshold voltage is low, and when the read voltage is applied to the gate, the current passing through is large, which represents that the stored data is "1".

[0004] Because the current signal passing through the floating gate transistor is relatively weak, it is not easy to distinguish whether the stored data is "0" or "1". Therefore, a complex peripheral circuit sensitive amplifier is needed to convert the small current signal into a larger voltage signal. This results in a large circuit area of the floating gate transistor, which reduces the chip integration. SUMMARY

[0005] Therefore, the present application provides an in-memory computing circuit based on floating gate transistor, a computing array and a readout method.

[0006] The first aspect of the present application provides an in-memory computing circuit based on floating gate transistor, comprising a selection tube array, a floating gate transistor array and a proportional capacitor array; wherein the selection tube array comprises a plurality of independent selection tubes; the floating gate transistor array comprises a plurality of independent floating gate transistors; the proportional capacitor array comprises a plurality of independent proportional capacitors. The drain of each independent floating gate transistor is connected to the source of an independent selection tube; the source of each independent floating gate transistor comprises two branches, one branch is connected to a shared output bus through a switch, and the other branch is connected to an independent proportional capacitor.

[0007] Further, the capacitance size of each proportional capacitor in the proportional capacitor array is increased in binary bit weight; the weight of the proportional capacitor corresponding to the floating gate transistor storing data is represented by the capacitance size ratio of the proportional capacitor.

[0008] Further, the drain of each selection tube in the selection tube array is connected to a different data voltage input, and the gate is connected to a common selection tube conduction signal input; when the selection tube conduction signal is high, each selection tube in the selection tube array is turned on, and the data voltage input is transmitted to the corresponding floating gate transistor in the floating gate transistor array; The gate of each floating gate transistor in the floating gate transistor array is connected to a common floating gate transistor enable signal input. When the floating gate transistor enable signal reaches the turn-on voltage, the drain of each floating gate transistor in the floating gate transistor array receives the data voltage input transmitted by the source of the corresponding selection tube in the selection tube array, multiplies the data signal with the stored data of the floating gate transistor itself, and outputs the multiplication result through the source. When the floating gate transistor enable signal reaches the write voltage, each floating gate transistor in the floating gate transistor array performs a write operation on its stored data when the drain simultaneously receives the data voltage input, so that the stored data is 0; the write voltage is higher than the turn-on voltage. When the floating gate transistor enable signal reaches the erase voltage, each floating gate transistor in the floating gate transistor array performs an erase operation on its stored data, so that the stored data is 1; the erase voltage is higher than the write voltage.

[0009] Further, each floating gate transistor in the floating gate transistor array outputs the multiplication result through the source, including the case where the floating gate transistor stores data as 0 or 1. When the floating gate transistor stores data as 1, the floating gate transistor charges the proportional capacitor connected to the source until the voltage of the proportional capacitor reaches the data voltage input to the floating gate transistor. When the floating gate transistor stores data as 0, the floating gate transistor is turned off and does not charge the proportional capacitor.

[0010] Further, when the floating gate transistor charges the proportional capacitor, the floating gate transistor connects the branch switch of the shared output bus to be turned off; after the floating gate transistor finishes charging the proportional capacitor, the floating gate transistor connects the branch switch of the shared output bus to be turned on, so that the voltage on each proportional capacitor in the proportional capacitor array is shared and then output as an analog voltage value through the shared output bus.

[0011] Another aspect of the present application discloses a floating gate transistor-based in-memory computing array composed of a plurality of floating gate transistor-based in-memory computing circuits described above, the in-memory computing circuits are arranged in an array, the in-memory computing circuits in the same row receive the same selection tube conduction signal input and floating gate transistor enable signal input, and the data voltage inputs received by different selection tubes in each in-memory computing circuit are independent of each other.

[0012] Further, the operation mode of the in-memory computing array further includes an erase mode, in which the storage data of the in-memory computing circuit floating gate transistor of the target row is erased by applying a floating gate transistor enable signal reaching an erase voltage to the target row. The operation mode of the in-memory computing array further includes a write mode, in which after applying a select gate on signal and a floating gate transistor enable signal reaching a write voltage to the target row, the data to be written is bit-decomposed and arranged, and different data voltage inputs are applied to the floating gate transistor corresponding to each digit, so that the storage data corresponding to the data to be written is stored in the floating gate transistor of the in-memory computing circuit of the target row.

[0013] Further, the operation mode of the in-memory computing array further includes a calculation mode, in which the in-memory computing array is determined to participate in the calculation of the behavior computing row, and after applying a select gate on signal and a floating gate transistor enable signal reaching a turn-on voltage to all the computing rows, the data to be calculated is row-decomposed, and the same data voltage input is applied to the in-memory computing circuit corresponding to each row, so that the analog voltage value output by the shared output bus presents the calculation result of the multiplication and accumulation of the data to be calculated. The operation mode of the in-memory computing array further includes a readout mode, in which after applying a select gate on signal and a floating gate transistor enable signal reaching a turn-on voltage to the target row, a preset readout voltage is applied to the in-memory computing circuit to be read as a data voltage input, and the analog voltage value output by the shared output bus is compared with the preset reference table to determine the storage data in the in-memory computing circuit to be read.

[0014] In another aspect, the application discloses an in-memory computing array readout method applied to the above-mentioned floating gate transistor-based in-memory computing array, which comprises the following steps: A preset reference table is prepared; The in-memory computing circuit to be read is selected as a target in-memory computing circuit; The row where the target in-memory computing circuit is located is selected as a target row, and a select gate on signal and a floating gate transistor enable signal reaching a turn-on voltage are applied to the target row; A preset readout voltage is applied to the target in-memory computing circuit in the target row as a data voltage input, and no data voltage input is applied to the other in-memory computing circuits in the target row; The analog voltage value output by the shared output bus is compared with the preset reference table to determine the storage data in the target in-memory computing circuit.

[0015] Further, the preset reference table is prepared by the following steps: The values of all possible storage data of the target in-memory computing circuit are determined; After erasing the target memory computing circuit, write a certain value of stored data into the target memory computing circuit and record the analog voltage value output by the shared output bus. The analog voltage values ​​output by the shared output bus under different stored data values ​​are summarized in a table and used as a preset reference table.

[0016] The embodiments of the present invention have the following beneficial effects: The in-memory computing circuit, computing array, and readout method based on floating-gate transistors of the present invention utilize the computing characteristics of the in-memory computing circuit based on floating-gate memory. It can directly deduce the data stored in the floating-gate transistors of the in-memory computing circuit from the calculation results, thereby eliminating the need for complex external sensitive amplifier circuits, reducing circuit complexity, and also reducing circuit area. The in-memory computing circuit and computing array based on floating-gate transistors provided by the present invention have high reusability, can reduce circuit size, and can be widely used in the field of in-memory computing circuits.

[0017] Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the circuit structure when the data stored in the floating gate transistor is "0"; Figure 2 This is a schematic diagram of the circuit structure when the floating gate transistor stores data as "1"; Figure 3 This is a schematic diagram of the in-memory computing circuit structure based on a floating gate transistor according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the in-memory computing array structure based on a floating gate transistor according to an embodiment of the present invention; Figure 5 This is a flowchart illustrating the steps of an in-memory computing array readout method according to the present invention. Figure 6 This is a schematic diagram of reading data stored in a certain in-memory computing circuit in an in-memory computing array according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] A floating-gate transistor is based on an NMOS (N-Metal-Oxide-Semiconductor) transistor, with a floating gate layer added to the insulating layer under the control gate to store electrons. This property allows for data storage. When there are electrons in the floating gate layer, its threshold voltage is high, and when a conduction voltage is applied to its gate, the current flowing through it is relatively small, representing the stored data as "0". When there are no electrons in the floating gate layer, its threshold voltage is low, and when a conduction voltage is applied to its gate, the current flowing through it is relatively large, representing the stored data as "1".

[0022] The circuit when the floating gate transistor stores data as "0" is as follows: Figure 1 As shown, there are two transistors on the floating gate transistor. A voltage VBIAS is applied to the gate of transistor M3, a voltage VY is applied to the gate of transistor M2, and a voltage VGATE is applied to the gate of the floating gate transistor. A capacitor CBIT is connected in parallel with the drain of the floating gate transistor. Since the floating gate transistor stores "0" at this time, it is turned off. Current only flows in the branch with capacitor CBIT. When the upper plate of capacitor CBIT charges to the overdrive voltage (VGATE - Vth) of transistor M3, charging stops. At this time, there is no current in the circuit, and the output voltage Vsap is VDD.

[0023] The circuit when the floating gate transistor stores data as "1" is as follows: Figure 2 As shown, when the floating gate transistor stores data "1", the floating gate transistor is at a low threshold, and there is always current Icell flowing through the circuit. Therefore, its output voltage Vsae is (VDD-IcellR), which is less than the output voltage when the floating gate transistor stores data "0".

[0024] It is evident that the output voltage of a floating gate transistor when the stored data is "1" is less than the output voltage when the stored data is "0". Therefore, the stored data of a floating gate transistor can be determined by the magnitude of the output voltage.

[0025] Based on the above, this invention presents an in-memory computing circuit based on a floating gate transistor, which eliminates the need for additional external circuitry when reading data for storage purposes, thereby reducing the circuit area.

[0026] The following description uses an in-memory computing circuit containing three floating-gate transistors as an example. It should be noted that in this embodiment of the invention, the select transistor array, floating-gate transistor array, and proportional capacitor array of the in-memory computing circuit can contain two, four, five, or more select transistors, floating-gate transistors, and proportional capacitors, all capable of achieving the same readout and computational effects. Therefore, this embodiment of the invention does not limit the specific number of select transistors, floating-gate transistors, and proportional capacitors included in the in-memory computing circuit.

[0027] like Figure 3 As shown in the figure, an in-memory computing circuit based on floating gate transistors according to an embodiment of the present invention includes a select transistor array, a floating gate transistor array, and a proportional capacitor array; wherein the select transistor array includes independent select transistors 1, 2, and 3; the floating gate transistor array includes independent floating gate transistors 1, 2, and 3; and the proportional capacitor array includes independent proportional capacitors 1, 2, and 3.

[0028] The drains of floating gate transistors 1, 2, and 3 are each connected to the sources of select transistors 1, 2, and 3. The sources of floating gate transistors 1, 2, and 3 each include two branches, one of which is connected to the shared output bus via a switch, and the other branch is connected to proportional capacitors 1, 2, and 3.

[0029] Preferably, the capacitance of each proportional capacitor in the proportional capacitor array increases in binary bit weight; the proportional capacitance ratio represents the weight of the data stored by the corresponding floating gate transistor.

[0030] As a specific example Figure 3 When used for storage, the in-memory computing circuit can store one 3-bit data. The capacitors connected to the source terminals of the three floating-gate transistors are in a 4:2:1 ratio, representing the weight ratio of the data stored by the three floating-gate transistors as 4:2:1.

[0031] Preferably, the drain of each select transistor in the select transistor array is connected to a different data voltage Vd input, while the gate is connected to a common select transistor turn-on signal Vsg input; when the select transistor turn-on signal Vsg is high, each select transistor in the select transistor array is turned on, transmitting the data voltage Vd input to the corresponding floating gate transistor in the floating gate transistor array.

[0032] The gate of each floating gate transistor in the floating gate transistor array is connected to a common floating gate transistor enable signal Vcg input.

[0033] When the enable signal Vcg of the floating gate transistor reaches the turn-on voltage, the drain of each floating gate transistor in the floating gate transistor array receives the data voltage Vd input transmitted from the source of the corresponding select transistor in the select transistor array, multiplies the data signal with the stored data of the floating gate transistor itself, and outputs the multiplication result through the source.

[0034] When the enable signal Vcg of the floating gate transistor reaches the write voltage, each floating gate transistor in the floating gate transistor array performs a write operation on its own stored data when it simultaneously receives the data voltage Vd input at its drain, making the stored data 0; the write voltage is higher than the conduction voltage.

[0035] When the enable signal Vcg of the floating gate transistor reaches the erase voltage, each floating gate transistor in the floating gate transistor array erases its own stored data, making the stored data 1; this erase voltage is higher than the write voltage.

[0036] Preferably, each floating gate transistor in the floating gate transistor array outputs the multiplication result through its source, including cases where the floating gate transistor stores data as 0 or 1.

[0037] When the data stored in the floating gate transistor is 1, the floating gate transistor charges the proportional capacitor connected to the source until the voltage of the proportional capacitor reaches the data voltage Vd input to the floating gate transistor.

[0038] When the data stored in the floating gate transistor is 0, the floating gate transistor is turned off and does not charge the proportional capacitor.

[0039] When the floating gate transistor charges the proportional capacitor, the branch switch connecting the floating gate transistor to the shared output bus is turned off; after the floating gate transistor finishes charging the proportional capacitor, the branch switch connecting the floating gate transistor to the shared output bus is turned on, so that the voltage on each proportional capacitor in the proportional capacitor array is shared and then an analog voltage value is output through the shared output bus.

[0040] As a specific example Figure 3 When the in-memory computing circuit is used for calculation, it can perform a single multiplication. First, there's the control terminal of the in-memory computing circuit. When this circuit is selected for calculation, a conduction voltage (Vcg) is applied to the gate of the floating-gate transistor, and a high-level voltage (Vsg) is applied to the gate of the select transistor. Second, there's the input of the in-memory computing circuit; three floating-gate transistors are connected to the same input. This input value can be a single-bit digital input or an analog input converted from a digital-to-analog converter. Finally, there's the output of the in-memory computing circuit, which is an analog voltage value. This analog voltage value can then be connected to an analog-to-digital converter to obtain a digital output.

[0041] When used for storage, the in-memory computing circuit can retrieve stored data by leveraging its computational capabilities. The stored data can be inferred from the result of multiplying a specific input by the stored data, eliminating the need for a separate sensitive amplifier and reducing circuit area. Specifically, given a specific readout voltage Vdread, and referring to the calculation principle above, eight multiplication results can be calculated for eight different 3-bit data cases. These eight results serve as a reference table. Next, following the calculation process above, the in-memory computing circuit is set to calculation mode, and the specific readout voltage Vd_read is input for calculation. An output, representing the calculated analog voltage value, is obtained. Comparing this result with the reference table reveals the data stored in the in-memory computing circuit.

[0042] Similarly, an in-memory computing array designed based on this in-memory computing circuit can also use the aforementioned readout method without a sensitive amplifier to read the data of a certain in-memory computing circuit in the in-memory computing array. Therefore, the second embodiment of the present invention discloses an in-memory computing array based on a floating gate transistor, which is composed of multiple in-memory computing circuits based on the aforementioned floating gate transistor. The in-memory computing circuits are arranged in an array, and the in-memory computing circuits in the same row receive the same selection transistor on signal Vsg input and the floating gate transistor enable signal Vcg input. The data voltage Vd input received by different selection transistors in each in-memory computing circuit is independent.

[0043] The following description uses an in-memory computing array with 3×3 in-memory computing circuits as an example. It should be noted that the in-memory computing array in this embodiment can contain two, four, five, or more in-memory computing circuits, all capable of achieving the same read and calculation effects. Therefore, this embodiment does not limit the number of in-memory computing circuits included in the in-memory computing array.

[0044] like Figure 4 As shown, the in-memory computing array consists of nine in-memory computing circuits, arranged in rows of three. The gates of the floating-gate transistors and the gates of the select transistors of the three in-memory computing circuits in the same row are connected together, with a total of three rows. The outputs of the nine in-memory computing circuits are connected together.

[0045] Preferably, the operating mode of the in-memory computing array includes an erase mode. In the erase mode, the data stored in the floating gate transistors of the in-memory computing circuit of the target row is erased by applying an enable signal Vcg of the floating gate transistor that reaches the erase voltage to the target row.

[0046] The in-memory computing array also includes a write mode. In the write mode, after applying the select transistor turn-on signal Vsg and the floating gate transistor enable signal Vcg that reaches the write voltage to the target row, the data to be written is decomposed and arranged bit by bit, and a different data voltage Vd is applied to the floating gate transistor corresponding to each bit, so that the floating gate transistor of the in-memory computing circuit of the target row stores the data to be written.

[0047] Furthermore, the working mode of the in-memory computing array also includes a computing mode. In computing mode, the rows that need to participate in the computing in the in-memory computing array are determined to be computing rows. After applying the selection transistor turn-on signal Vsg and the floating gate transistor enable signal Vcg that reaches the turn-on voltage to all computing rows, the data to be calculated is decomposed by row. The same data voltage Vd is applied to the in-memory computing circuit corresponding to each row, so that the analog voltage value output by the shared output bus presents the calculation result of multiplying and accumulating the data to be calculated.

[0048] The in-memory computing array also includes a readout mode. In readout mode, after applying the select transistor turn-on signal Vsg and the floating gate transistor enable signal Vcg that reaches the turn-on voltage to the target row, a preset readout voltage Vd_read is applied to the in-memory computing circuit that needs to be read out as the data voltage Vd input. The analog voltage value output by the shared output bus is compared with a preset reference table to determine the stored data in the in-memory computing circuit that needs to be read out.

[0049] In a specific embodiment, when used for storage, the in-memory computing array can store nine 3-bit data segments. Programming the in-memory computing array involves programming a row simultaneously, requiring programming voltages to be applied to the gates of the floating-gate transistors and select transistors in that row. Furthermore, the drain inputs of each floating-gate transistor in each in-memory computing circuit are separate, allowing individual programming of each floating-gate transistor in each in-memory computing circuit within the same row. Erasing the in-memory computing array involves erasing a row simultaneously, requiring erasing voltages to be applied to the gates of the floating-gate transistors and select transistors in that row.

[0050] When used for computation, this in-memory computing array can perform a single multiplication and accumulation of 9 inputs and 9 stored data. First, regarding the control of the in-memory computing array, when a particular in-memory computing circuit is selected for computation, the gate on-state voltage (Vcg) of the three rows of floating-gate transistors in the array is simultaneously applied, along with a high-level gate (Vsg) for the select transistor. Second, regarding the inputs of the in-memory computing array, each in-memory computing circuit has its own input, and the array has a total of 9 in-memory computing circuits, allowing for 9 inputs. The input values ​​can be single-bit digital inputs or analog inputs converted from digital-to-analog converters. In each in-memory computing circuit, after the input is multiplied by a single floating-gate transistor, the switch under the floating-gate transistor turns on, and the voltage on the capacitors of the 9 in-memory computing circuits shares charge. Based on the principle of charge sharing, the final voltage value on the capacitor is the result of multiplying the 9 inputs by 9 3-bit data and then accumulating the sum. Finally, there is the output of the in-memory computing array, which is an analog voltage value representing the multiplication and accumulation calculation result of the in-memory computing array. This analog voltage value can then be connected to an analog-to-digital converter to obtain a digital output.

[0051] like Figure 4 As shown, the third embodiment of the present invention discloses an in-memory computing array readout method, applied to the above-mentioned in-memory computing array based on floating gate transistors, including the following steps: S1. Create a preset reference table; S2. Select the memory-in-memory computing circuit to be read as the target memory-in-memory computing circuit; S3. Select the row where the target memory calculation circuit is located as the target row, and apply the selection transistor turn-on signal Vsg and the floating gate transistor enable signal Vcg that reaches the turn-on voltage to the target row; S4. Apply a preset read voltage Vd_read as the data voltage Vd input to the target memory calculation circuit in the target row, and do not apply the data voltage Vd input to other memory calculation circuits in the target row; S5. Compare the analog voltage value output by the shared output bus with the preset reference table to determine the stored data in the target memory calculation circuit.

[0052] The effect of reading data stored in a specific in-memory computing circuit within an in-memory computing array according to an embodiment of the present invention is as follows: Figure 5As shown. First, a conduction voltage, Vcg, is applied to the gate of the floating-gate transistor in the row containing the memory calculation circuit to be read. A high level, Vsg, is applied to the gate of the select transistor in the same row. The gates of the floating-gate transistors and select transistors in the other two rows are both applied at 0V, meaning the other two rows are not selected. Then, a specific readout voltage, Vd_read, is applied to the input of the memory calculation circuit to be read, while the inputs of the other memory calculation circuits are applied at 0V. Calculations are then performed, and the memory calculation array will produce an output voltage, Vout.

[0053] Preferably, the preset reference table is created through the following steps: S1-1. Determine the values ​​of all possible stored data in the target memory computing circuit; S1-2. After erasing the target memory computing circuit, write a certain value of stored data into the target memory computing circuit and record the analog voltage value output by the shared output bus. S1-3. Summarize the analog voltage values ​​output by the shared output bus under different stored data values ​​into a table as a preset reference table.

[0054] As a specific implementation, based on the calculation principle, eight calculation results obtained by the in-memory computing array can be pre-calculated under the condition that the in-memory computing circuit to be read stores eight different 3-bit data. These eight calculation results are used as a reference table. In this calculation mode, the output voltage Vout actually calculated by the in-memory computing array is compared with the reference table, that is, the 3-bit data stored in the in-memory computing circuit to be read by the in-memory computing array can be deduced.

[0055] The in-memory computing circuit, computing array, and readout method based on floating-gate transistors provided in this invention utilize the computational characteristics of the in-memory computing circuit based on floating-gate memory. It directly infers the data stored in the floating-gate transistors within the in-memory computing circuit from the computational results, eliminating the need for complex external sensitive amplifier circuits. When reading the stored data of a specific in-memory computing circuit within the in-memory computing array, the computational characteristics of the in-memory computing array can be utilized. The stored data can be inferred from the result of multiplying and accumulating a specific input with the stored data, without requiring a separate sensitive amplifier external circuit, thus reducing the circuit area.

[0056] Those skilled in the art will understand that modules in the device of the embodiments of the present invention can be adaptively modified and placed in one or more devices different from those embodiments. Modules, units, or components in the embodiments of the present invention can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the corresponding claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the corresponding claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0057] Furthermore, the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. The embodiments of devices, equipment, etc., described above are merely illustrative, and the modules, units, etc., described as separate components may or may not be physically separate, that is, they may be located in one place or distributed in multiple places. Specifically, some or all of the modules and units can be selected according to actual needs to achieve the purpose of the above-described embodiments. Those skilled in the art can understand and implement this without creative effort.

[0058] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0059] Furthermore, the terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this invention can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this invention, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly specified in the embodiments.

[0060] In embodiments of the present invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of the present invention may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0061] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. Other embodiments of the present invention will readily conceive of by considering the specification and practicing the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

Claims

1. A memory computing circuit based on a floating-gate transistor, characterized in that, It includes a select transistor array, a floating gate transistor array, and a proportional capacitor array; wherein the select transistor array includes multiple independent select transistors; the floating gate transistor array includes multiple independent floating gate transistors; and the proportional capacitor array includes multiple independent proportional capacitors. The drain of each independent floating gate transistor is connected to the source of an independent select transistor; the source of each independent floating gate transistor includes two branches, one of which is connected to the shared output bus via a switch, and the other branch is connected to an independent proportional capacitor.

2. The in-memory computing circuit based on a floating-gate transistor according to claim 1, characterized in that, The capacitance of each proportional capacitor in the proportional capacitor array increases in binary bit weight; the proportional capacitance ratio represents the weight of the data stored by the corresponding floating gate transistor.

3. The in-memory computing circuit based on a floating-gate transistor according to claim 1, characterized in that, In the select transistor array, the drain of each select transistor is connected to a different data voltage input, while the gate is connected to a common select transistor turn-on signal input. When the select transistor turn-on signal is high, each select transistor in the select transistor array is turned on, transmitting the data voltage input to the corresponding floating gate transistor in the floating gate transistor array. The gate of each floating gate transistor in the floating gate transistor array is connected to a common floating gate transistor enable signal input; When the enable signal of the floating gate transistor reaches the turn-on voltage, the drain of each floating gate transistor in the floating gate transistor array receives the data voltage input transmitted from the source of the corresponding select transistor in the select transistor array, multiplies the data signal with the stored data of the floating gate transistor itself, and outputs the multiplication result through the source. When the enable signal of the floating gate transistor reaches the write voltage, each floating gate transistor in the floating gate transistor array performs a write operation on its own stored data when the data voltage input is received at the drain simultaneously, so that the stored data is 0; the write voltage is higher than the turn-on voltage. When the enable signal of the floating gate transistor reaches the erase voltage, each floating gate transistor in the floating gate transistor array erases its own stored data, making the stored data 1; the erase voltage is higher than the write voltage.

4. The in-memory computing circuit based on a floating-gate transistor according to claim 3, characterized in that, Each floating gate transistor in the floating gate transistor array outputs the multiplication result through its source, including the case where the floating gate transistor stores data as 0 or 1. When the data stored in the floating gate transistor is 1, the floating gate transistor charges the proportional capacitor connected to the source until the voltage of the proportional capacitor reaches the data voltage input to the floating gate transistor. When the data stored in the floating gate transistor is 0, the floating gate transistor is turned off and does not charge the proportional capacitor.

5. The in-memory computing circuit based on a floating-gate transistor according to claim 4, characterized in that, When the floating gate transistor charges the proportional capacitor, the branch switch connecting the floating gate transistor to the shared output bus is turned off. After the floating gate transistor finishes charging the proportional capacitor, the branch switch connecting the floating gate transistor to the shared output bus is turned on, so that the voltage on each proportional capacitor in the proportional capacitor array is shared and then an analog voltage value is output through the shared output bus.

6. A memory computing array based on floating-gate transistors, comprising a plurality of memory computing circuits based on floating-gate transistors as described in any one of claims 1-5, characterized in that, The in-memory computing circuits are arranged in an array. The in-memory computing circuits in the same row receive the same selection transistor turn-on signal input and floating gate transistor enable signal input. The data voltage input received by different selection transistors in each in-memory computing circuit is independent.

7. The in-memory computing array based on floating-gate transistors according to claim 6, characterized in that, The in-memory computing array has an erase mode. In the erase mode, the data stored in the floating gate transistors of the in-memory computing circuit of the target row is erased by applying an enable signal to the floating gate transistors that reaches the erase voltage to the target row. The in-memory computing array also includes a write mode. In the write mode, after applying a selection transistor turn-on signal and a floating gate transistor enable signal that reaches the write voltage to the target row, the data to be written is decomposed and arranged bit by bit, and a different data voltage input is applied to the floating gate transistor corresponding to each bit, so that the floating gate transistor of the in-memory computing circuit of the target row stores the storage data corresponding to the data to be written.

8. The in-memory computing array based on floating-gate transistors according to claim 6, characterized in that, The working mode of the in-memory computing array also includes a computing mode. In the computing mode, the rows that need to participate in the computing in the in-memory computing array are determined to be computing rows. After applying the selection transistor turn-on signal and the floating gate transistor enable signal that reaches the turn-on voltage to all computing rows, the data to be calculated is decomposed by row. The same data voltage input is applied to the in-memory computing circuit corresponding to each row, so that the analog voltage value output by the shared output bus presents the calculation result of multiplying the data to be calculated and then accumulating it. The in-memory computing array also includes a readout mode. In the readout mode, after applying a selection transistor turn-on signal and a floating gate transistor enable signal that reaches the turn-on voltage to the target row, a preset readout voltage is applied to the in-memory computing circuit that needs to be read out as the data voltage input. The analog voltage value output by the shared output bus is compared with a preset reference table to determine the stored data in the in-memory computing circuit that needs to be read out.

9. A method for reading out an in-memory computing array, applied to an in-memory computing array based on a floating-gate transistor as described in any one of claims 6-8, characterized in that, Includes the following steps: Create a preset reference table; Select the memory-in-memory computing circuit to be read as the target memory-in-memory computing circuit; The row containing the target memory computing circuit is selected as the target row, and the selection transistor turn-on signal and the floating gate transistor enable signal that reaches the turn-on voltage are applied to the target row. A preset read voltage is applied as the data voltage input to the target memory calculation circuit in the target row, while no data voltage input is applied to the other memory calculation circuits in the target row. The analog voltage value output by the shared output bus is compared with a preset reference table to determine the stored data in the target memory computing circuit.

10. A method for reading out an in-memory computing array according to claim 9, characterized in that, The preset reference table is created through the following steps: Determine the values ​​of all possible stored data in the target memory computing circuit; After erasing the target memory computing circuit, write a certain value of stored data into the target memory computing circuit and record the analog voltage value output by the shared output bus. The analog voltage values ​​output by the shared output bus under different stored data values ​​are summarized in a table and used as a preset reference table.

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