A high balance active balun circuit

Abstract

The application provides a high-balance active balun circuit, which comprises an RF signal input port, a signal input matching stage, a single-end to differential circuit and an output load stage, wherein the signal input matching stage comprises a first transistor, a second transistor, an input resistor and an input inductor, and the single-end to differential circuit comprises a third transistor, a fourth transistor, a fifth transistor and a capacitor. The application does not need to waste chip area to make a complex matching circuit. When the circuit is connected in the front stage, the circuit will not cause the problem that power cannot be transmitted due to high-frequency reflection. The phase adjusting inductor is introduced into the circuit, and the frequency phase characteristics of the inductor are used to compensate the phase imbalance of the differential output. The bandwidth extension technology is used in the load, so that the phase shifter maintains the flatness of the gain in a wide frequency. Meanwhile, the two-stage cascade transistor is used to realize the single-end input to differential output gain stage architecture, which is more suitable for low-voltage application.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency integrated circuits, and specifically refers to a high-balance active balun circuit. Background Technology

[0002] Driven by factors such as cost, integration, and power consumption, CMOS technology has made rapid progress. CMOS transistor cutoff frequencies can meet the requirements of integrated circuit designs in frequency bands above several GHz. With the development of 5G phased array technology, active phase shifters have received widespread attention due to their flexible design, high phase shifting accuracy, and ease of calibration. In recent years, with technological advancements, the bandwidth requirements for phase shifters have become increasingly stringent. Currently, only multi-stage filter technology is available to achieve large bandwidth quadrature, but multi-stage filters suffer from significant insertion loss. Therefore, high-performance active balun circuits have become a research challenge. Currently, most active baluns adopt the architecture proposed in the paper "An Ultra-Compact, Linearly-Controlled Variable Phase Shifter Designed With a Novel RC poly-Phase Filter," such as... Figure 1 As shown, the active balun circuit implemented in this way requires an additional input matching circuit, has poor in-band flatness, an amplitude imbalance of approximately 1 dB, and a phase imbalance of about 4°. It is evident that existing active balun circuits waste area in the input matching circuit and struggle to meet the requirements of high-precision phase shifters for low phase and amplitude imbalance. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an active balun circuit with wideband matching, high amplitude and good phase balance, so as to make up for the difficulties and shortcomings of the existing technology in the design of GHz wideband active balun circuits under CMOS process.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] A high-balance active balun circuit includes an RF signal input port, a signal input matching stage, a single-ended to differential circuit, an output load stage, and a differential signal positive output port and a differential signal negative output port. The single-ended to differential circuit has a positive output branch and a negative output branch. The output load stage includes a differential signal positive branch and a differential signal negative branch. An inductor is respectively provided on the differential signal positive branch and the differential signal negative branch of the output load stage. One end of the differential signal positive branch and the differential signal negative branch of the output load stage are connected to the power supply, and the other end is electrically connected to the corresponding positive output branch and negative output branch of the single-ended to differential circuit on one hand, and to the corresponding differential signal positive output port and differential signal negative output port on the other hand.

[0006] The signal input matching stage includes a first transistor, a second transistor, an input resistor, and an input inductor; the single-ended to differential circuit includes a third transistor, a fourth transistor, a fifth transistor, and a capacitor.

[0007] The radio frequency signal input port is electrically connected to the gate of the second transistor, one end of the input resistor, and one end of the input inductor. The other end of the input inductor is connected to the gate of the first transistor. The source of the first transistor is grounded. The drain of the first transistor is connected to the other end of the input resistor and the drain of the second transistor. The source of the second transistor is connected to the power supply.

[0008] The drain of the first transistor is connected to the gate of the third transistor, the source of the third transistor is grounded, the drain of the third transistor is connected to one end of the capacitor and the source of the fourth transistor, the gate of the fourth transistor is connected to the power supply, the other end of the capacitor is connected to the gate of the fifth transistor, and the source of the fifth transistor is grounded.

[0009] Furthermore, DC blocking capacitors are provided at the radio frequency signal input port, the differential signal forward output port, and the differential signal reverse output port.

[0010] Furthermore, a resistor is connected in series in both the forward branch and the reverse branch of the differential signal in the output load stage.

[0011] Furthermore, it also includes a phase imbalance compensation network, which includes a differential signal forward branch and a differential signal reverse branch. An inductor is respectively provided on the differential signal forward branch and the differential signal reverse branch of the phase imbalance compensation network. The inductor located on the differential signal forward branch is connected between the drain of the fifth transistor and the differential signal forward branch of the output load stage, and the inductor located on the differential signal reverse branch is connected between the drain of the fourth transistor and the differential signal reverse branch of the output load stage.

[0012] Furthermore, the second transistor is a PMOS transistor, while the first, third, fourth, and fifth transistors are all NMOS transistors.

[0013] Compared with the prior art, the advantages of the present invention are as follows:

[0014] 1) This invention achieves input matching within the circuit, thus eliminating the need to design a separate bias electrical matching network for the circuit. This reduces both design complexity and chip area.

[0015] 2) The present invention incorporates a phase adjustment inductor in the circuit, which can compensate for the phase imbalance of the differential output through the frequency-phase characteristics of the inductor.

[0016] 3) This invention fully considers output matching, circuit gain and bandwidth issues.

[0017] 4) This invention uses two layers of cascaded transistors to achieve the function of single-ended input to differential output, which has high gain and is more suitable for low-voltage applications. Attached Figure Description

[0018] Figure 1 This is a circuit schematic diagram of an active balun in the prior art;

[0019] Figure 2 This is the schematic diagram of the active balun circuit of the present invention;

[0020] Figure 3 This is a simulation diagram of the input matching of the active balun circuit in this invention;

[0021] Figure 4 The results are simulations of the phase difference of the differential output signal of the active balun circuit in this invention.

[0022] Figure 5 This is the simulation result of the amplitude imbalance of the active balun circuit in this invention;

[0023] Figure 6 These are the simulation results of the gain-frequency characteristics of the active balun circuit in this invention. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0025] like Figure 2 As shown, a high-balance active balun circuit comprises four parts: a signal input matching stage, a single-ended to differential circuit, a phase imbalance compensation network, and an output load stage. Transistors M1 and M2, resistor R1, inductor L5, and capacitor C1 constitute the signal input matching stage; transistors M3, M4, and M5, and capacitor C2 constitute the single-ended to differential circuit; transistors M3 and M4 constitute the cascode gain stage; inductors L1 and L2 constitute the phase imbalance compensation network; inductors L3 and L4, and resistors R2 and R3 constitute the output load stage, which also provides output matching and bandwidth extension functions; capacitors C3 and C4 are DC blocking capacitors.

[0026] The specific connection relationships of these devices are as follows:

[0027] At the input matching stage, the RF input signal V inConnect one end of capacitor C1, and the other end of capacitor C1 to the gate of PMOS transistor M2, one end of resistor R1, and one end of inductor L5. The other end of inductor L5 is connected to the gate of NMOS transistor M1. The source of transistor M1 is connected to ground. The drain of M1 is connected to the other end of resistor R1, and also to the drain of PMOS transistor M2. The source of transistor M2 is connected to the power supply VDD.

[0028] In the single-ended to differential circuit, the drain of transistor M1 is connected to the gate of NMOS transistor M3, and the source of M3 is grounded. The drain of M3 is connected to one end of capacitor C2, and also to the source of NMOS transistor M4. The gate of transistor M4 is connected to VDD. The source of M4 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to the gate of NMOS transistor M5. The source of transistor M5 is grounded.

[0029] The drain of transistor M5 is connected to one end of inductor L1, and the drain of transistor M4 is connected to one end of inductor L2.

[0030] In the phase imbalance compensation network, the other end of inductor L1 is connected to one end of capacitor C3 and one end of resistor R2; the other end of inductor L2 is connected to one end of capacitor C4 and one end of resistor R3. In the output load stage, the other end of resistor R2 is connected to one end of inductor L3, and the other end of inductor L3 is connected to VDD; the other end of resistor R3 is connected to one end of inductor L4, and the other end of inductor L4 is connected to VDD. The other end of capacitor C3 is connected to the output VDD. OUTP The other end of capacitor C4 is connected to the output V. OUTN .

[0031] The NMOS and PMOS transistors in this circuit are both RF transistors supported by CMOS technology, with gate lengths selected to the smallest size supported by the process. The inductor uses a common on-chip planar spiral structure, the resistors are polysilicon resistors, and the capacitors are MOM capacitors. Table 1 lists the parameter values ​​of the components used in the above circuit:

[0032] Table 1. Device parameters of active balun circuit examples

[0033]

[0034] Depend on Figure 2 The input impedance of this active balun circuit can be obtained:

[0035]

[0036]

[0037] In the formula, ω represents the angular frequency, and C gs1 L represents the gate capacitance of the input transistor M1. g1This represents the value of inductor L5, C gs2 This represents the gate capacitance of the input transistor M2. m1 G represents the transconductance of transistor M1. m2 R represents the transconductance of transistor M2, and R1 represents the resistance value of resistor R1.

[0038] Input impedance matching is achieved when the input signal angular frequencies ω1 and ω2 satisfy the following conditions:

[0039] ω1=0 (3)

[0040]

[0041] The output employs a parallel inductor resonant technique. The current flowing through the load resistor is prolonged due to the effect of inductors L3 / L4, which accelerates the charging rate of the load capacitor. Inductors L3 / L4 further delay the time it takes for current to flow into other networks, thereby improving system bandwidth. The final derivation conclusion is given here directly:

[0042]

[0043] In the formula, L represents the value of L3 / L4, R represents the value of resistor R2, and C represents the output load capacitance. k is a reference coefficient, the value of which affects the maximum flatness delay of the system, and is generally around 0.5.

[0044] The gain of the active balun is:

[0045] A V (jω)=g m3 (g m1 +g m2 )(r 01 / / r 02 )(R+jωL4) / (R+jωL4+jωL2) (6)

[0046] In the formula, the transconductance of the input transistor M3 is g. m3 The small-signal impedances of transistors M1 and M2 are r 01 With r 02 r 01 / / r 02 Indicates r 01 With r 02 The parallel resistors. L4 represents the value of inductance L4, and L2 represents the value of inductance L2.

[0047] Figure 3 This is a simulation diagram of the input reflection coefficient of the circuit. As can be seen from the diagram, the input reflection coefficient of the circuit is less than -12.3dB from 4GHz to 8GHz.

[0048] Figure 4It is the differential output phase difference of the circuit, and the phase imbalance of the output is less than 1.2°.

[0049] Figure 5 The simulation results show the amplitude inconsistency at the differential output. Figure 5 As can be seen, the amplitude inconsistency at the differential output is less than 0.39dB.

[0050] Figure 6 This is the gain simulation curve of the differential output terminal, with a gain flatness of less than 0.3dB.

[0051] In summary, this invention incorporates an input matching gain stage into an active balun, consisting of an inductor, input transistor, isolation capacitor, and capacitor bank, eliminating the need for complex matching circuits that waste chip space. When connected to the front-end, this circuit avoids power transfer issues caused by high-frequency reflections. Furthermore, a phase-adjusting inductor is introduced to compensate for the phase imbalance of the differential output through its frequency-phase characteristics. The load employs bandwidth extension technology, ensuring the phase shifter maintains flat gain across a wide frequency range. Moreover, this circuit utilizes a two-layer cascaded transistor architecture to achieve a single-ended input to differential output gain stage, making it more suitable for low-voltage applications.

[0052] This invention features high-performance input matching, minimal amplitude and phase imbalance in the low-frequency band, and high gain flatness.

Claims

1. A high balance active balun circuit, comprising a radio frequency signal input port, a signal input matching stage, a single-ended to differential circuit, an output load stage, and a differential signal forward output port and a differential signal reverse output port, the single-ended to differential circuit having a forward output branch and a reverse output branch, the output load stage comprising a differential signal forward branch and a differential signal reverse branch, an inductor being arranged on each of the differential signal forward branch and the differential signal reverse branch of the output load stage, one end of the differential signal forward branch and the differential signal reverse branch of the output load stage being connected to a power supply, and the other end of the differential signal forward branch and the differential signal reverse branch of the output load stage being electrically connected to the forward output branch and the reverse output branch of the single-ended to differential circuit on the one hand, and to the differential signal forward output port and the differential signal reverse output port on the other hand; characterized in that the signal input matching stage comprising a first transistor, a second transistor, an input resistor, and an input inductor, and the single-ended to differential circuit comprising a third transistor, a fourth transistor, a fifth transistor, and a capacitor; the radio frequency signal input port being electrically connected to a gate of the second transistor, one end of the input resistor, and one end of the input inductor, the other end of the input inductor being connected to a gate of the first transistor, a source of the first transistor being grounded, a drain of the first transistor being connected to the other end of the input resistor and a drain of the second transistor, and a source of the second transistor being connected to a power supply; a drain of the first transistor being connected to a gate of the third transistor, a source of the third transistor being grounded, a drain of the third transistor being connected to one end of the capacitor and a source of the fourth transistor, a gate of the fourth transistor being connected to the power supply, and the other end of the capacitor being connected to a gate of the fifth transistor, a source of the fifth transistor being grounded; a direct current blocking capacitor being arranged at each of the radio frequency signal input port, the differential signal forward output port, and the differential signal reverse output port; a resistor being connected in series with each of the differential signal forward branch and the differential signal reverse branch of the output load stage.

2. The high balance active balun circuit of claim 1, wherein, a phase imbalance compensation network is further included, the phase imbalance compensation network comprising a differential signal forward branch and a differential signal reverse branch, an inductor being arranged on each of the differential signal forward branch and the differential signal reverse branch of the phase imbalance compensation network, the inductor arranged on the differential signal forward branch being connected between a drain of the fifth transistor and the differential signal forward branch of the output load stage, and the inductor arranged on the differential signal reverse branch being connected between a drain of the fourth transistor and the differential signal reverse branch of the output load stage.

3. The high balance active balun circuit of claim 1, wherein, the second transistor is a PMOS transistor, and the first transistor, the third transistor, the fourth transistor, and the fifth transistor are NMOS transistors.

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