Multi-layer gate analog CMOS process edge stress optimization integration method and low voltage coefficient polycrystalline capacitor

Abstract

The invention discloses a multi-layer gate analog CMOS process edge stress optimization integration method and a low voltage coefficient polycrystalline capacitor. The method steps include: 1) forming an N-type well in a low voltage coefficient integrated dual polycrystalline capacitor area, and forming a self-aligned P-type well in an area outside the N-type well; 2) depositing a polycrystalline film layer of a lower electrode of the low voltage coefficient integrated dual polycrystalline capacitor; 3) depositing a first layer of dielectric of the dual polycrystalline capacitor, and realizing the production of an edge protection layer of the lower electrode of the dual polycrystalline capacitor; 4) depositing a capacitor dielectric layer, and completing the production of a capacitor dielectric layer structure; the low voltage coefficient polycrystalline capacitor includes a P-type substrate, a P-type epitaxial layer, an N-type well, a self-aligned P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline film layer, a silicon dioxide dielectric layer, a capacitor dielectric layer, a low dielectric coefficient filling film layer, a metal interconnect film layer, and a protective dielectric passivation layer outside a top metal bonding area; the patent improves the edge effect of the dual polycrystalline capacitor and reduces the mechanical stress of the integrated dual polycrystalline capacitor.

Description

Technical Field

[0001] The invention relates to the field of semiconductor integrated circuits, in particular to a multi-layer gate analog CMOS process edge stress optimization integration method and a low voltage coefficient polycrystalline capacitor. Background Art

[0002] In the field of semiconductor device manufacturing, analog CMOS integrated circuits are gradually developing towards high speed and high precision. Integrating double polysilicon capacitors directly into the circuit is a trend towards lightweight and miniaturized equipment.

[0003] Especially for high-precision detection and complex working environment analog CMOS integrated circuits used for weather forecasting, ocean exploration, polar expeditions, etc., it is required to develop towards the ultimate circuit performance direction of high and low voltage compatible power supply voltage, high speed, high precision, low drift, low offset, etc. These requirements put forward higher requirements for the organic combination of circuit design and process manufacturing artistry and science. Low voltage coefficient integrated dual polycrystalline capacitors are widely used in precise matching capacitors of charge redistribution analog-to-digital converters ADC and digital-to-analog converters DAC with their superior process compatibility, which have strict requirements on voltage modulation effects and work at different voltages.

[0004] On the other hand, in analog CMOS integrated circuits containing low voltage coefficient dual polycrystalline capacitors, the stress mismatch and electric field concentration caused by the edge effects of integrated polycrystalline capacitors significantly affect the grain regrowth in the polycrystalline thin layer, the redistribution of impurities in the grains, the grain depletion, and the grain boundary size and shape. These effects have an important impact on the electrical performance stability and long-term reliability of low voltage coefficient integrated dual polycrystalline capacitors.

[0005] Therefore, the use of effective process technology to optimize the high mechanical stress caused by the edge effect of the integrated low voltage coefficient dual polycrystalline capacitor and the local electric field concentration is an important task to improve the high precision, high linear stability and long-term reliability of analog integrated circuits and meet the gradual development of analog integrated circuits towards high speed, high precision and miniaturization. Summary of the invention

[0006] The object of the present invention is to provide a multi-layer gate analog CMOS process edge stress optimization integration method, comprising the following steps:

[0007] 1) forming an N-type well of a low voltage coefficient integrated dual polycrystalline capacitor region on a P-type substrate, and forming a self-aligned P-type well in a region outside the N-type well;

[0008] 2) forming a field oxide layer of m angstroms on the surface of the N-type well and the self-aligned P-well;

[0009] 3) depositing a polycrystalline film layer of a lower electrode of a low voltage coefficient integrated dual polycrystalline capacitor with a thickness of P1 angstrom on the field oxide layer above the N-type well in the integrated low voltage coefficient dual polycrystalline capacitor region, and completing N-type photolithography implantation doping; wherein the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated dual polycrystalline capacitor serves as the lower electrode plate of the low voltage coefficient integrated dual polycrystalline capacitor;

[0010] 4) growing an n angstrom thermal oxide layer using thermal oxidation process conditions;

[0011] 5) depositing the first dielectric layer of the dual polycrystalline capacitor with a thickness of d1 angstroms, and using an exposure and etching process to realize the production of the edge protection layer of the lower electrode of the dual polycrystalline capacitor;

[0012] 6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and completing the capacitor dielectric layer structure by using an exposure and etching process;

[0013] 7) Complete the conventional process before the gate poly deposition of analog CMOS integrated circuits;

[0014] 8) depositing a P2 angstrom thick MOS transistor gate polycrystalline film layer and completing MOS transistor gate polycrystalline doping;

[0015] 9) Complete the subsequent conventional processes of normal analog CMOS integrated circuits.

[0016] Further, the method of depositing the P1 angstrom polycrystalline film layer, the first dielectric layer of the double polycrystalline capacitor, and the gate polycrystalline film layer of the MOS transistor includes a low-pressure chemical vapor deposition method.

[0017] Furthermore, the dielectric constant of the first layer of the dual polycrystalline capacitor is recorded as ε1, and the dielectric constant of the capacitor dielectric layer is recorded as ε2. ε1 and ε2 are constants.

[0018] Furthermore, in step 1), before forming the N-type well, a layer of P-type epitaxy is grown on the P-type substrate, and then an N-type well is formed on the P-type epitaxy, and a self-aligned P-type well is formed in the area outside the N-type well.

[0019] Furthermore, the subsequent conventional processes of normal analog CMOS integrated circuits include source and drain implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, and metal interconnection.

[0020] Furthermore, the conventional process before the gate poly deposition of the simulated CMOS integrated circuit includes sacrificial oxidation, channel adjustment implantation, exposure etching, and gate oxide oxidation.

[0021] Furthermore, the thermal oxidation process conditions include: the main process temperature of the thermal oxidation process is ≤850°C, and the main process time is ≤30min.

[0022] Furthermore, in step 3), a polycrystalline film layer and an edge protection film layer are deposited to form an upper plate of a low voltage coefficient integrated dual polycrystalline capacitor.

[0023] Furthermore, the polycrystalline film layer and edge protection film layer of the upper plate of the low voltage coefficient integrated dual polycrystalline capacitor adopt the same polycrystalline side protection structure as the MOS transistor gate in the normal analog CMOS integrated circuit process.

[0024] The low voltage coefficient polycrystalline capacitor manufactured by the multi-layer gate analog CMOS process edge stress optimization integration method includes a P-type substrate or a P-type epitaxial layer, an N-type well, a self-aligned P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline film layer, a silicon dioxide dielectric layer, a capacitor dielectric layer, a low dielectric coefficient filling film layer, a metal interconnect film layer, and a protective dielectric passivation layer outside the top metal bonding area;

[0025] The P-type substrate or the P-type epitaxial layer is located at the bottom;

[0026] The well region is located on the surface of the P-type substrate or the P-type epitaxial layer; the well region includes an N-type well and a self-aligned P-type well;

[0027] The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well;

[0028] The polycrystalline film layer of the low voltage coefficient polycrystalline capacitor is located on the upper surface of the field oxide layer above the N-type well;

[0029] The top surface and side walls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers and capacitor dielectric layers.

[0030] The low dielectric constant filling film layer fills the area between the metal interconnect film layers;

[0031] The metal interconnect film layer includes a silicon-metal interconnect film layer, a polysilicon-metal interconnect film layer, a field oxygen-metal interconnect film layer, and a multi-layer metal interconnect region;

[0032] The protective dielectric passivation layer outside the top metal bonding area covers the top metal layer area in the multi-layer metal interconnection area.

[0033] Furthermore, it also includes a silicon oxynitride dielectric layer;

[0034] The top surface and side walls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers, silicon oxynitride dielectric layers, and capacitor dielectric layers.

[0035] The technical effect of the present invention is unquestionable. The present invention significantly improves the edge effect of dual polycrystalline capacitors through a modularized, precisely matched, low voltage coefficient polycrystalline capacitor edge effect high stress optimization manufacturing method integrated with a multi-layer gate high and low voltage compatible analog CMOS process, reduces the mechanical stress of the integrated dual polycrystalline capacitor, alleviates the electric field concentration in the edge area of ​​the dual polycrystalline capacitor, and improves the electrical performance stability and process consistency of the voltage modulation of the dual polycrystalline capacitor in the high and low voltage compatible analog CMOS integrated circuit.

[0036] The present invention adopts a modularized, precisely matched, low-voltage-coefficient polycrystalline capacitor edge effect high-stress optimized manufacturing method integrated with a multi-layer gate high- and low-voltage compatible analog CMOS process, which improves the uniformity of grain regrowth in the polycrystalline thin layer and impurity redistribution in the grains, and effectively improves the low-voltage-coefficient integrated dual polycrystalline capacitor in high- and low-voltage compatible analog CMOS integrated circuits for complex, high-precision detection work in weather forecasting, ocean exploration, polar scientific research, and other working environments.

[0037] The present invention adopts a modularized, precisely matched, low-voltage-coefficient polycrystalline capacitor edge effect high-stress optimized manufacturing method integrated with a multi-layer gate high-low-voltage compatible analog CMOS process, which improves the grain depletion and grain boundary size and shape in the polycrystalline thin layer of the polycrystalline capacitor plate under the action of electrical stress, and effectively improves the long-term reliability of low-voltage-coefficient integrated dual polycrystalline capacitor products in analog integrated circuits.

[0038] Through the modularized precise matching low voltage coefficient polycrystalline capacitor edge effect high stress optimization manufacturing method integrated with the multi-layer gate high and low voltage compatible analog CMOS process of the present invention, the mismatch degree of the integrated dual polycrystalline capacitor can be reduced from ±0.1% to the precisely matched ±0.01% mismatch level, which can be applicable to high-precision A / D and D / A converters with a resolution of more than 14 bits, thereby improving the process compatibility and device integration density and enhancing the market competitiveness of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a cross-sectional view of the growth of the shield oxide layer after completing conventional analog CMOS integrated circuit processes such as epitaxial growth, well implantation, annealing, and field oxidation;

[0040] Figure 2 It is a cross-sectional view of the lower plate of the double polycrystalline capacitor after the polycrystalline film layer is deposited and doped;

[0041] Figure 3 It is a cross-sectional view of the edge protection film layer of the polycrystalline film layer of the lower plate of the polycrystalline capacitor after completing the thick and thin dual gate oxide oxidation process;

[0042] Figure 4 It is a cross-sectional view of the polycrystalline capacitor capacitor dielectric layer deposition and exposure etching structure;

[0043] Figure 5 The local magnified cross-sectional view and SEM analysis view of the structure after the subsequent wet etching and oxidation processes are completed without the edge optimization technology solution;

[0044] Figure 6 It is a partial enlarged cross-sectional diagram and SEM analysis diagram of the structure after the subsequent wet etching and oxidation processes are completed using the edge optimization technology solution;

[0045] Figure 7 It is a schematic diagram of the 3D structure after the polycrystalline film layer of the upper plate of the polycrystalline capacitor is deposited and doped, and exposed and etched;

[0046] Figure 8 It is a schematic diagram of the structure of a low voltage coefficient dual polycrystalline capacitor after completing a two-layer metal interconnection process;

[0047] Fig. 9 It is a schematic diagram of the structure of a low voltage coefficient integrated dual polycrystalline capacitor in the high and low voltage compatible analog CMOS integrated circuit process of Example 1;

[0048] In the figure: LOCOS field oxide layer area 11, P-type MOS lightly doped source and drain injection area 12, N-type well injection area 13, low-voltage MOS thin gate oxide layer area 14, gate polycrystalline layer area 15, sidewall protection area 16, P-type MOS source and drain injection area 17, polycrystalline layer I18, oxygen-nitrogen dielectric layer 19, self-aligned P-type well area 20, N-type MOS source and drain injection area 21, high-voltage MOS thick gate oxide layer area 22, gate polycrystalline top layer nitrogen-oxygen dielectric protection layer area 23, 100 crystal orientation P-type substrate / epitaxial layer 24, silicon / polycrystalline silicon-metal 1 interlayer contact hole tungsten plug structure area 101, silicon / polycrystalline silicon / field oxygen-metal 1 interlayer ILD dielectric planarization layer 102, multi-layer metal interlayer IMD dielectric planarization layer 103, first metal film layer area 104, multi-layer metal interlayer through hole tungsten plug structure area 105, top metal layer area 106. DETAILED DESCRIPTION

[0049] The present invention is further described below in conjunction with the embodiments, but it should not be understood that the above subject matter of the present invention is limited to the following embodiments. Without departing from the above technical ideas of the present invention, various substitutions and changes are made according to the common technical knowledge and customary means in the art, which should all be included in the protection scope of the present invention.

[0050] Embodiment 1:

[0051] See also Figures 1 to 9 , a multi-layer gate analog CMOS process edge stress optimization integration method, comprising the following steps:

[0052] 1) forming an N-type well of a low voltage coefficient integrated dual polycrystalline capacitor region on a P-type substrate or a P-type epitaxial layer, and forming a self-aligned P-type well in a region outside the N-type well;

[0053] 2) forming a field oxide layer of m angstroms on the surface of the N-type well and the self-aligned P-well;

[0054] 3) depositing a polycrystalline film layer of a lower electrode of a low voltage coefficient integrated dual polycrystalline capacitor with a thickness of P1 angstrom on the field oxide layer above the N-type well in the low voltage coefficient integrated dual polycrystalline capacitor region, and completing N-type photolithography implantation doping; wherein the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated dual polycrystalline capacitor serves as the lower electrode plate of the low voltage coefficient integrated dual polycrystalline capacitor;

[0055] 4) growing an n angstrom thermal oxide layer using thermal oxidation process conditions;

[0056] 5) depositing the first dielectric layer of the dual polycrystalline capacitor with a thickness of d1 angstroms, and using an exposure and etching process to realize the production of the edge protection layer of the lower electrode of the dual polycrystalline capacitor;

[0057] 6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and completing the capacitor dielectric layer structure by using an exposure and etching process;

[0058] 7) Complete the conventional process before the gate poly deposition of analog CMOS integrated circuits;

[0059] 8) depositing a P2 angstrom thick MOS transistor gate polycrystalline film layer and completing MOS transistor gate polycrystalline doping;

[0060] 9) Complete the subsequent conventional processes of normal analog CMOS integrated circuits.

[0061] The method of depositing the P1 angstrom polycrystalline film layer, the first dielectric layer of the double polycrystalline capacitor, and the gate polycrystalline film layer of the MOS transistor includes a low-pressure chemical vapor deposition method.

[0062] The dielectric constant of the first layer of the double polycrystalline capacitor is denoted as ε1, and the dielectric constant of the capacitor dielectric layer is denoted as ε2.

[0063] ε1 and ε2 are constants.

[0064] The subsequent conventional processes of normal analog CMOS integrated circuits include source and drain implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, and metal interconnection.

[0065] The conventional processes before gate poly deposition of analog CMOS integrated circuits include sacrificial oxidation, channel injection, exposure etching, and gate oxide oxidation.

[0066] The thermal oxidation process conditions include: the main process temperature of the thermal oxidation process is ≤850°C, and the main process time is ≤30min.

[0067] In step 3), a polycrystalline film layer and an edge protection film layer of the upper plate of the low voltage coefficient integrated dual polycrystalline capacitor are also deposited.

[0068] The upper plate polycrystalline film layer and edge protection film layer of the low voltage coefficient integrated dual polycrystalline capacitor adopt the same polycrystalline side protection structure as the MOS transistor gate in the normal analog CMOS integrated circuit process.

[0069] The low voltage coefficient polycrystalline capacitor manufactured by the multi-layer gate analog CMOS process edge stress optimization integration method includes a P-type substrate or a P-type epitaxial layer, an N-type well implantation region 13, a self-aligned P-type well region 20, a field oxide layer 11, a sacrificial oxide layer, a gate oxide layer 14, a gate polycrystalline layer region 15, a silicon dioxide dielectric layer, a capacitor dielectric layer, a low dielectric coefficient filling film layer, a metal interconnect film layer, a top metal bonding region outer protective dielectric passivation layer, and a silicon oxynitride dielectric layer 19;

[0070] The P-type substrate or the P-type epitaxial layer is located at the bottom;

[0071] The well region is located on the surface of the P-type substrate or the P-type epitaxial layer; the well region includes an N-type well and a self-aligned P-type well;

[0072] The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well;

[0073] The polycrystalline film layer of the low voltage coefficient polycrystalline capacitor is located on the upper surface of the field oxide layer above the N-type well;

[0074] The top surface and side walls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers and capacitor dielectric layers.

[0075] The low dielectric constant filling film layer fills the area between the metal interconnect film layers;

[0076] The metal interconnect film layer includes a silicon-metal interconnect film layer, a polysilicon-metal interconnect film layer, a field oxygen-metal interconnect film layer, and a multi-layer metal interconnect region;

[0077] The protective dielectric passivation layer outside the top metal bonding area covers the top metal layer area in the multi-layer metal interconnection area.

[0078] The top surface and side walls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers, silicon oxynitride dielectric layers, and capacitor dielectric layers.

[0079] Embodiment 2:

[0080] The multi-layer gate analog CMOS process edge stress optimization integration method comprises the following steps:

[0081] 1) forming an N-type well of a low voltage coefficient integrated dual polycrystalline capacitor region on a P-type substrate, and forming a self-aligned P-type well in a region outside the N-type well;

[0082] 2) forming a field oxide layer of m angstroms on the surface of the N-type well and the self-aligned P-well;

[0083] 3) depositing a polycrystalline film layer of a lower electrode of a low voltage coefficient integrated dual polycrystalline capacitor with a thickness of P1 angstrom on the field oxide layer above the N-type well in the low voltage coefficient integrated dual polycrystalline capacitor region, and completing N-type photolithography implantation doping; wherein the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated dual polycrystalline capacitor serves as the lower electrode plate of the low voltage coefficient integrated dual polycrystalline capacitor;

[0084] 4) growing an n angstrom thermal oxide layer using thermal oxidation process conditions;

[0085] 5) depositing the first dielectric layer of the dual polycrystalline capacitor with a thickness of d1 angstroms, and using an exposure and etching process to realize the production of the edge protection layer of the lower electrode of the dual polycrystalline capacitor;

[0086] 6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and completing the capacitor dielectric layer structure by using an exposure and etching process;

[0087] 7) Complete the conventional process before the gate poly deposition of analog CMOS integrated circuits;

[0088] 8) depositing a P2 angstrom thick MOS transistor gate polycrystalline film layer and completing MOS transistor gate polycrystalline doping;

[0089] 9) Complete the subsequent conventional processes of normal analog CMOS integrated circuits.

[0090] Embodiment 3:

[0091] The multi-layer gate analog CMOS process edge stress optimization integration method comprises the following steps:

[0092] 1) forming an N-type well of a low voltage coefficient integrated dual polycrystalline capacitor region in a P-type epitaxial layer, and forming a self-aligned P-type well in a region outside the N-type well;

[0093] 2) forming a field oxide layer of m angstroms on the surface of the N-type well and the self-aligned P-well;

[0094] 3) depositing a polycrystalline film layer of a lower electrode of a low voltage coefficient integrated dual polycrystalline capacitor with a thickness of P1 angstrom on the field oxide layer above the N-type well in the low voltage coefficient integrated dual polycrystalline capacitor region, and completing N-type photolithography implantation doping; wherein the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated dual polycrystalline capacitor serves as the lower electrode plate of the low voltage coefficient integrated dual polycrystalline capacitor;

[0095] 4) growing an n angstrom thermal oxide layer using thermal oxidation process conditions;

[0096] 5) depositing the first dielectric layer of the dual polycrystalline capacitor with a thickness of d1 angstroms, and using an exposure and etching process to realize the production of the edge protection layer of the lower electrode of the dual polycrystalline capacitor;

[0097] 6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and completing the capacitor dielectric layer structure by using an exposure and etching process;

[0098] 7) Complete the conventional process before the gate poly deposition of analog CMOS integrated circuits;

[0099] 8) depositing a P2 angstrom thick MOS transistor gate polycrystalline film layer and completing MOS transistor gate polycrystalline doping;

[0100] 9) Complete the subsequent conventional processes of normal analog CMOS integrated circuits.

[0101] Embodiment 4:

[0102] The multi-layer gate analog CMOS process edge stress optimization integration method comprises the following steps:

[0103] 1) forming an N-type well of a low voltage coefficient integrated dual polycrystalline capacitor region on a P-type substrate or a P-type epitaxial layer, and forming a self-aligned P-type well in a region outside the N-type well;

[0104] 2) forming a field oxide layer of m angstroms on the surface of the N-type well and the self-aligned P-well;

[0105] 3) depositing a polycrystalline film layer of a lower electrode of a low voltage coefficient integrated dual polycrystalline capacitor with a thickness of P1 angstrom on the field oxide layer above the N-type well in the low voltage coefficient integrated dual polycrystalline capacitor region, and completing N-type photolithography implantation doping; wherein the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated dual polycrystalline capacitor serves as the lower electrode plate of the low voltage coefficient integrated dual polycrystalline capacitor;

[0106] 4) growing an n angstrom thermal oxide layer using thermal oxidation process conditions;

[0107] 5) depositing the first dielectric layer of the dual polycrystalline capacitor with a thickness of d1 angstroms, and using an exposure and etching process to realize the production of the edge protection layer of the lower electrode of the dual polycrystalline capacitor;

[0108] 6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and completing the capacitor dielectric layer structure by using an exposure and etching process;

[0109] 7) Complete the conventional process before the gate poly deposition of analog CMOS integrated circuits;

[0110] 8) depositing a P2 angstrom thick MOS transistor gate polycrystalline film layer and completing MOS transistor gate polycrystalline doping;

[0111] 9) Complete the subsequent conventional processes of normal analog CMOS integrated circuits.

[0112] Embodiment 5:

[0113] The multi-layer gate analog CMOS process edge stress optimization integration method, the main content of which is shown in Example 2, 3 or 4, wherein the method of depositing the P1 angstrom polycrystalline film layer, the first layer of the dual polycrystalline capacitor dielectric, and the MOS transistor gate polycrystalline film layer includes a low-pressure chemical vapor deposition method.

[0114] Embodiment 6:

[0115] The multi-layer gate analog CMOS process edge stress optimization integration method, the main content of which is shown in Example 2, 3 or 4, wherein the dielectric constant of the first layer of the dual polycrystalline capacitor is recorded as ε1, and the dielectric constant of the capacitor dielectric layer is recorded as ε2.

[0116] Embodiment 7:

[0117] The integrated method for optimizing edge stress of a multi-layer gate analog CMOS process, the main contents of which are shown in Embodiment 2, 3 or 4, wherein the subsequent conventional processes of a normal analog CMOS integrated circuit include source and drain implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, and metal interconnection.

[0118] Embodiment 8:

[0119] The multi-layer gate analog CMOS process edge stress optimization integration method, the main content of which is shown in Example 2, 3 or 4, wherein the conventional process before the analog CMOS integrated circuit gate polycrystalline deposition includes sacrificial oxidation, channel injection, exposure etching, and gate oxide oxidation.

[0120] Embodiment 9:

[0121] The multi-layer gate analog CMOS process edge stress optimization integration method, the main content of which is shown in Example 2, 3 or 4, wherein the thermal oxidation process conditions include: the main process temperature of the thermal oxidation process is ≤850°C, and the main process time is ≤30min.

[0122] Embodiment 10:

[0123] The multi-layer gate analog CMOS process edge stress optimization integration method, the main content of which is shown in Example 2, 3 or 4, wherein in step 3, a polycrystalline film layer and an edge protection film layer are also deposited to form the upper plate of a low voltage coefficient integrated dual polycrystalline capacitor.

[0124] Embodiment 11:

[0125] The multi-layer gate analog CMOS process edge stress optimization integration method, the main contents of which are shown in Examples 2, 3 or 4, wherein the upper plate polycrystalline film layer and edge protection film layer of the low voltage coefficient integrated dual polycrystalline capacitor adopt the same MOS transistor gate polycrystalline side protection structure as in the normal analog CMOS integrated circuit process.

[0126] Embodiment 12:

[0127] The low voltage coefficient polycrystalline capacitor manufactured by the multi-layer gate analog CMOS process edge stress optimization integration method described in Examples 1-11 comprises a P-type substrate, an N-type well injection region 13, a self-aligned P-type well region 20, a field oxide layer 11, a sacrificial oxide layer, a gate oxide layer 14, a gate polycrystalline layer region 15, a silicon dioxide dielectric layer, a capacitor dielectric layer, a low dielectric coefficient filling film layer, a metal interconnect film layer, and a protective dielectric passivation layer outside the top metal bonding region;

[0128] The P-type substrate is located at the bottom;

[0129] The well region is located on the surface of the P-type substrate; the well region includes an N-type well and a self-aligned P-type well;

[0130] The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well;

[0131] The polycrystalline film layer of the low voltage coefficient polycrystalline capacitor is located on the upper surface of the field oxide layer above the N-type well;

[0132] The top surface and side walls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers and capacitor dielectric layers.

[0133] The low dielectric constant filling film layer fills the area between the metal interconnect film layers;

[0134] The metal interconnect film layer includes a silicon-metal interconnect film layer, a polysilicon-metal interconnect film layer, a field oxygen-metal interconnect film layer, and a multi-layer metal interconnect region;

[0135] The protective dielectric passivation layer outside the top metal bonding area covers the top metal layer area in the multi-layer metal interconnection area.

[0136] Embodiment 13:

[0137] The low voltage coefficient polycrystalline capacitor manufactured by the multi-layer gate analog CMOS process edge stress optimization integrated method described in Examples 1-11 comprises a P-type epitaxial layer, an N-type well implantation region 13, a self-aligned P-type well region 20, a field oxide layer 11, a sacrificial oxide layer, a gate oxide layer 14, a gate polycrystalline layer region 15, a silicon dioxide dielectric layer, a capacitor dielectric layer, a low dielectric coefficient filling film layer, a metal interconnect film layer, and a protective dielectric passivation layer outside the top metal bonding region;

[0138] The P-type epitaxial layer is located at the bottom;

[0139] The well region is located on the surface of the P-type epitaxial layer; the well region includes an N-type well and a self-aligned P-type well;

[0140] The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well;

[0141] The polycrystalline film layer of the low voltage coefficient polycrystalline capacitor is located on the upper surface of the field oxide layer above the N-type well;

[0142] The top surface and side walls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers and capacitor dielectric layers.

[0143] The low dielectric constant filling film layer fills the area between the metal interconnect film layers;

[0144] The metal interconnect film layer includes a silicon-metal interconnect film layer, a polysilicon-metal interconnect film layer, a field oxygen-metal interconnect film layer, and a multi-layer metal interconnect region;

[0145] The protective dielectric passivation layer outside the top metal bonding area covers the top metal layer area in the multi-layer metal interconnection area.

[0146] Embodiment 14:

[0147] A low voltage coefficient polycrystalline capacitor manufactured by the multi-layer gate analog CMOS process edge stress optimization integration method, the main contents of which are shown in Example 12 or 13, wherein the capacitor further includes a silicon oxynitride dielectric layer 19;

[0148] The top surface and side walls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers, silicon oxynitride dielectric layers, and capacitor dielectric layers.

[0149] Embodiment 15:

[0150] The manufacturing method of the edge effect high stress optimization of the precisely matched low voltage coefficient dual polycrystalline capacitor integrated with the multi-layer gate high and low voltage compatible analog CMOS process mainly includes the following steps:

[0151] 1) forming an N-type well in the substrate and forming a self-aligned P-type well in the area outside the N-type well;

[0152] For high-performance and high-precision analog CMOS technology, a layer of P-type epitaxy is grown on a P-type substrate according to circuit performance requirements. An N-type well is formed on the P-type epitaxy, and a self-aligned P-type well is formed in the area outside the N-type well.

[0153] 2) forming a field oxide layer of m angstroms on the surface of the N-type well and the self-aligned P-well;

[0154] 3) Deposit a P1 angstrom polycrystalline film layer on the field oxide layer by low-pressure chemical vapor deposition, and complete N-type photolithography implantation doping according to the performance requirements of the capacitor. The polycrystalline film layer can be used as the lower plate of the low voltage coefficient integrated dual polycrystalline capacitor;

[0155] A polycrystalline film layer of the lower plate of the double polycrystalline capacitor is deposited on the field oxide layer above the N-type well, and the doping oxidation enhancement effect is utilized to reduce the influence of parasitic capacitance and substrate noise and improve the performance of the polycrystalline capacitor device.

[0156] 4) growing an n angstrom thermal oxide layer using thermal oxidation process conditions;

[0157] The main process temperature of thermal oxidation is ≤850℃, and the main process time is ≤30min, which is conducive to process compatibility and reduces the impact on the main process devices of analog CMOS integrated circuits.

[0158] A chlorine-containing oxidizing atmosphere is used in the thermal oxygen oxidation process to improve the quality of the oxide layer and reduce interface defects and interface state traps.

[0159] 5) Using low pressure chemical vapor deposition to deposit the first layer of dielectric (dielectric constant is ε1) of d1 angstrom dual polycrystalline capacitor and exposure etching process, the edge protection structure of the lower electrode of the dual polycrystalline capacitor is fabricated.

[0160] 6) Based on the parameters and performance of the low voltage coefficient integrated dual polycrystalline capacitor, the required capacitor dielectric layer is deposited, with a dielectric constant of ε2 and a film thickness of d2 angstroms. The capacitor dielectric layer structure is fabricated using an exposure and etching process;

[0161] The capacitor dielectric layer can select a high dielectric constant film layer to increase the unit capacitance of the double polycrystalline capacitor.

[0162] Under the premise of ensuring the performance requirements of the polycrystalline capacitor, the capacitor dielectric film layer can be the same film layer as the dielectric film layer of the polycrystalline capacitor edge protection structure described in 5) to simplify the process steps.

[0163] 7) forming a m1 angstrom thick gate oxide layer in the area of ​​the well surface not covered by the field oxide layer; removing the m1 angstrom thick gate oxide layer in the active area of ​​the low voltage device, and forming a m2 angstrom thin gate oxide layer after cleaning;

[0164] After the thick gate oxide layer is generated, the threshold adjustment and implantation of the CMOS device are completed as required. Then the thick gate oxide layer is removed in the active area of ​​the low voltage device, and the required thin gate oxide layer is generated after cleaning, which is conducive to improving the integrity of the gate oxide layer.

[0165] Especially for the integrated dual polycrystalline capacitor array circuit layout, the polycrystalline film layer of the polycrystalline capacitor bottom electrode with edge protection structure significantly improves Figure 5 The stress mismatch warping phenomenon of the polycrystalline film layer shown in the figure improves the matching degree and integration density of the integrated dual polycrystalline capacitor. The optimized structure is as follows Figure 6 shown.

[0166] 8) using low pressure chemical vapor deposition to deposit a P2 angstrom MOS transistor gate polycrystalline film layer, and completing MOS transistor gate polycrystalline doping according to MOS device performance requirements;

[0167] 9) Next, complete the normal analog CMOS integrated circuit source and drain implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, metal interconnection and other processes; Example 16:

[0168] The manufacturing method for optimizing the edge effect and high stress of a precisely matched low voltage coefficient dual polycrystalline capacitor integrated with a multi-layer gate high and low voltage compatible analog CMOS process is mainly shown in Example 13, wherein the integrated manufacturing of the high stress edge effect optimization of the low voltage coefficient integrated dual polycrystalline capacitor is carried out on the basis of completing the processes of epitaxial growth, N-type well injection push-junction, P-well injection push-junction, field oxide layer growth, etc., and the steps include:

[0169] 1) Using the MOS transistor gate polycrystalline film layer as the lower plate polycrystalline film layer of the polycrystalline capacitor, and adopting the polycrystalline plate edge optimization technical solution described in Implementation 1.

[0170] If the gate polycrystalline sidewall structure is used in the analog CMOS integrated circuit process, the gate polycrystalline sidewall structure can be optimized for protecting the edge area of ​​the polycrystalline film layer of the lower plate of the polycrystalline capacitor.

[0171] 2) Depositing a polycrystalline film layer for the upper plate of the double polycrystalline capacitor, and completing doping, exposure, and etching to form the upper plate structure of the polycrystalline capacitor.

[0172] The subsequent steps adopt the normal analog CMOS integrated circuit process scheme:

[0173] Embodiment 17:

[0174] The manufacturing method of the edge effect high stress optimization of the precisely matched low voltage coefficient dual polycrystalline capacitor integrated with the multi-layer gate high and low voltage compatible analog CMOS process is mainly shown in Example 13, wherein, for the high-performance and high-precision analog CMOS process, a layer of P-type epitaxy is grown on the P-type substrate according to the circuit performance requirements. An N-type well is formed on the P-type epitaxy, and a self-aligned P-type well is formed in the area outside the N-type well. :

[0175] The subsequent steps adopt the normal analog CMOS integrated circuit process scheme:

[0176] Embodiment 18:

[0177] The manufacturing method for optimizing the edge effect and high stress of a precisely matched low voltage coefficient dual polycrystalline capacitor integrated with a multi-layer gate high and low voltage compatible analog CMOS process is shown in Example 13. The silicided source / drain region and the silicided gate polycrystalline process are used to obtain lower contact resistance and reduce the gate polycrystalline depletion effect. Silicide is widely used in the process. The integrated manufacturing of the high stress edge effect optimization of the low voltage coefficient integrated dual polycrystalline capacitor is carried out on the basis of completing the processes of epitaxial growth, N-type well injection push junction, P-well injection push junction, field oxide layer growth, etc.

[0178] The previous process steps are the same as those in implementation 1. After the gate poly sidewall structure is etched back and the source / drain injection annealing is completed,

[0179] 1) Use metal sputtering process to carry out Ti / TiN sputtering, and then complete the source / drain region and polysilicon metallization through annealing process.

[0180] Sputtering a suitable thin metal layer not only enables silicide processing, but also allows the integration of Schottky diodes in the process;

[0181] The voltage modulation effect of polycrystalline capacitors can be reduced by using a suitable silicide blocking mask to obtain polycrystalline capacitors with lower voltage coefficients.

[0182] 2) Remove the sputtered metal thin layer outside the clean silicided area. Then use dielectric layer deposition, contact hole exposure etching and metal sputtering to achieve metal interconnection.

[0183] The subsequent steps adopt the normal analog CMOS integrated circuit process scheme:

[0184] Embodiment 19:

[0185] The multi-layer gate analog CMOS process edge stress optimization integration method comprises the following steps:

[0186] 1) forming an N-type well in a P-type substrate and forming a self-aligned P-type well in a region outside the N-type well;

[0187] 2) forming a field oxide layer of m angstroms on the surface of the N-type well and the self-aligned P-well;

[0188] 3) A P1 angstrom polycrystalline film layer is deposited on the field oxide layer above the N-type well in the low voltage coefficient integrated dual polycrystalline capacitor region by low pressure chemical vapor deposition, and N-type photolithography implantation doping is completed according to the capacitor performance requirements. The polycrystalline film layer can be used as the lower plate of the low voltage coefficient integrated dual polycrystalline capacitor;

[0189] 4) growing an n angstrom thermal oxide layer using thermal oxidation process conditions;

[0190] 5) Using low pressure chemical vapor deposition to deposit the first layer of dielectric (dielectric constant is ε1) of d1 angstrom dual polycrystalline capacitor and exposure etching process, the edge protection structure of the lower electrode of the dual polycrystalline capacitor is fabricated.

[0191] 6) Based on the performance of low voltage coefficient integrated dual polycrystalline capacitor, the required capacitor dielectric layer is deposited, the dielectric constant is ε2, and the film thickness is d2 angstroms. The capacitor dielectric layer structure is completed by using exposure and etching process;

[0192] 7) Complete the normal process steps such as sacrificial oxidation, channel injection, exposure etching, gate oxide oxidation, etc. before the gate polycrystalline deposition of the simulated CMOS integrated circuit;

[0193] 8) using low pressure chemical vapor deposition to deposit a P2 angstrom MOS transistor gate polycrystalline film layer, and completing MOS transistor gate polycrystalline doping according to MOS device performance requirements;

[0194] 9) Next, complete the normal analog CMOS integrated circuit source and drain implantation, annealing activation, dielectric layer deposition, reflow filling and flattening, contact hole etching, metal interconnection and other processes;

[0195] For high-performance and high-precision analog CMOS technology, a layer of P-type epitaxy is grown on a P-type substrate. Then an N-type well is formed on the P-type epitaxy, and a self-aligned P-type well is formed in the area outside the N-type well.

[0196] The method for forming the polycrystalline film oxide layer, the edge protection layer, and the dielectric layer of the capacitor of the low voltage coefficient integrated dual polycrystalline capacitor is as follows:

[0197] 1) In the thermal oxidation process of the polycrystalline film layer of the lower electrode of the double polycrystalline capacitor, the main process temperature is ≤850°C and the main process time is ≤30min;

[0198] 2) In the edge protection layer of the polycrystalline film layer of the lower electrode of the double polycrystalline capacitor, a dielectric film layer with a thickness of d1 angstroms and a dielectric constant of ε1 is deposited by low-pressure chemical vapor deposition;

[0199] 3) In the production of the dielectric layer of the low voltage coefficient dual polycrystalline capacitor, a dielectric film layer with a thickness of d2 angstroms and a dielectric constant of ε2 is deposited according to the performance requirements of the capacitor;

[0200] The edge protection film layer of the polycrystalline film layer of the upper plate of the low voltage coefficient integrated dual polycrystalline capacitor adopts the same structure as the polycrystalline side protection structure of the gate of the MOS transistor in the normal analog CMOS integrated circuit process.

[0201] A low voltage coefficient polycrystalline capacitor based on the high-low voltage compatible analog CMOS process low voltage coefficient dual polycrystalline capacitor edge effect optimization manufacturing method, mainly comprising a P-type substrate, a P-type epitaxial layer, an N-type well, a self-aligned P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer and a low dielectric coefficient filling film layer, a metal interconnect film layer, and a passivation layer;

[0202] The substrate is located at the bottom; the epitaxial layer is located above the substrate layer; and the well region is located on the surface of the epitaxial layer;

[0203] The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well;

[0204] The polycrystalline film layer of the double polycrystalline capacitor is located above the field oxide layer above the N-type well;

[0205] The top surface and sidewall of the polycrystalline film layer are covered with different silicon dioxide and silicon nitride composite dielectric layers and a high dielectric constant capacitor dielectric layer.

[0206] The low dielectric constant filling film layer is filled in the region between silicon-metal 1, polysilicon-metal 1, field oxygen-metal 1 and the multi-layer metal.

[0207] Embodiment 20:

[0208] See also Fig. 9 The low voltage coefficient polycrystalline capacitor manufactured based on the high and low voltage compatible analog CMOS process low voltage coefficient dual polycrystalline capacitor edge effect optimization manufacturing method described in Example 1-19 includes a LOCOS field oxide layer region 11, a P-type MOS lightly doped source and drain injection region 12, an N-type well injection region 13, a low voltage MOS thin gate oxide layer region 14, a gate polycrystalline layer region 15, a sidewall protection region 16, a P-type MOS source and drain injection region 17, a polycrystalline layer I18, an oxygen-nitrogen dielectric layer 19, and a self-aligned P-type well region 20. , N-type MOS source and drain injection region 21, high-voltage MOS thick gate oxide layer region 22, gate polycrystalline top layer nitride oxide dielectric protection layer region 23, 100 crystal orientation P-type substrate / epitaxial layer 24, silicon / polysilicon-metal 1 interlayer contact hole tungsten plug structure region 101, silicon / polysilicon / field oxygen-metal 1 interlayer ILD dielectric planarization layer 102, multi-layer metal interlayer IMD dielectric planarization layer 103, first metal film layer region 104, multi-layer metal interlayer through hole tungsten plug structure region 105, top metal layer region 106.

Claims

1. A multi-layer gate analog CMOS process edge stress optimization integration method, characterized in that: The following steps are involved: 1) forming an N-type well of a low voltage coefficient integrated dual polycrystalline capacitor region on a P-type substrate, and forming a self-aligned P-type well in a region outside the N-type well; 2) forming a field oxide layer of m angstroms on the surface of the N-type well and the self-aligned P-well; 3) depositing a polycrystalline film layer of a lower electrode of a low voltage coefficient integrated dual polycrystalline capacitor with a thickness of P1 angstrom on the field oxide layer above the N-type well in the integrated low voltage coefficient dual polycrystalline capacitor region, and completing N-type photolithography implantation doping; wherein the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated dual polycrystalline capacitor serves as the lower electrode plate of the low voltage coefficient integrated dual polycrystalline capacitor; 4) growing an n angstrom thermal oxide layer using thermal oxidation process conditions; 5) depositing a first layer of dielectric of the dual polycrystalline capacitor with a thickness of d1 angstroms, and using an exposure and etching process to realize the production of a protective layer at the edge of the lower electrode of the dual polycrystalline capacitor; the dielectric constant of the first layer of dielectric of the dual polycrystalline capacitor is denoted as ε1; 6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and completing the capacitor dielectric layer structure by using an exposure and etching process; the dielectric constant of the capacitor dielectric layer is denoted as ε2; 7) Complete the conventional process before the gate poly deposition of analog CMOS integrated circuits; 8) depositing a P2 angstrom thick MOS transistor gate polycrystalline film layer and completing MOS transistor gate polycrystalline doping; 9) Complete the subsequent conventional processes of normal analog CMOS integrated circuits; After step 6), a polycrystalline film layer and an edge protection film layer of an upper plate of a low voltage coefficient integrated dual polycrystalline capacitor are deposited; The upper plate polycrystalline film layer and edge protection film layer of the low voltage coefficient integrated dual polycrystalline capacitor adopt the same polycrystalline side protection structure as the MOS transistor gate in the normal analog CMOS integrated circuit process.

2. The multi-layer gate analog CMOS process edge stress optimization integration method according to claim 1, characterized in that: The method of depositing the P1 angstrom polycrystalline film layer, the first dielectric layer of the double polycrystalline capacitor, and the gate polycrystalline film layer of the MOS transistor includes a low-pressure chemical vapor deposition method.

3. The multi-layer gate analog CMOS process edge stress optimization integration method according to claim 1, characterized in that: In step 1), before forming the N-type well, a layer of P-type epitaxy is grown on the P-type substrate, and then an N-type well is formed on the P-type epitaxy, and a self-aligned P-type well is formed in the area outside the N-type well.

4. The multi-layer gate analog CMOS process edge stress optimization integration method according to claim 1, characterized in that: The subsequent conventional processes of normal analog CMOS integrated circuits include source and drain implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, and metal interconnection.

5. The multi-layer gate analog CMOS process edge stress optimization integration method according to claim 1, characterized in that: The conventional processes before gate poly deposition of analog CMOS integrated circuits include sacrificial oxidation, channel injection, exposure etching, and gate oxide oxidation.

6. The multi-layer gate analog CMOS process edge stress optimization integration method according to claim 1, characterized in that: The thermal oxidation process conditions include: the main process temperature of the thermal oxidation process is ≤850°C, and the main process time is ≤30min.

7. A low voltage coefficient polycrystalline capacitor manufactured based on the multi-layer gate analog CMOS process edge stress optimization integration method according to any one of claims 1 to 6, characterized in that: It includes a P-type substrate or a P-type epitaxial layer, an N-type well, a self-aligned P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline film layer, a silicon dioxide dielectric layer, a capacitor dielectric layer, a low dielectric constant filling film layer, a metal interconnect film layer, and a protective dielectric passivation layer outside the top metal bonding area; The polycrystalline film layer includes a low voltage coefficient polycrystalline capacitor polycrystalline film layer and a double polycrystalline capacitor bottom electrode polycrystalline film layer; The P-type substrate or the P-type epitaxial layer is located at the bottom; The well region is located on the surface of the P-type substrate or the P-type epitaxial layer; the well region includes an N-type well and a self-aligned P-type well; The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well; The polycrystalline film layer of the low voltage coefficient polycrystalline capacitor is located on the upper surface of the field oxide layer above the N-type well; The top surface and sidewalls of the polycrystalline film layer of the lower electrode of the double polycrystalline capacitor are covered with different silicon dioxide dielectric layers and capacitor dielectric layers; The low dielectric constant filling film layer fills the area between the metal interconnect film layers; The metal interconnect film layer includes a silicon-metal interconnect film layer, a polysilicon-metal interconnect film layer, a field oxygen-metal interconnect film layer, and a multi-layer metal interconnect region; The protective dielectric passivation layer outside the top metal bonding area covers the top metal layer area in the multi-layer metal interconnection area.

8. The low voltage coefficient polycrystalline capacitor according to claim 7, characterized in that: Also includes a silicon oxynitride dielectric layer; The top surface and side wall of the polycrystalline film layer of the lower electrode of the double polycrystalline capacitor are covered with different silicon dioxide dielectric layers, silicon oxynitride dielectric layers and capacitor dielectric layers.

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