Sgt device and process method

Abstract

The application discloses an SGT device and a process method thereof, which comprises the following steps: first, forming a composite layer on the surface of a semiconductor substrate; etching the semiconductor substrate to form a groove; second, depositing a first oxide layer, then depositing a first polysilicon layer; filling the groove; third, performing back etching on the first polysilicon layer to form a source electrode of the SGT device; fourth, etching the first oxide layer in the groove; fifth, forming a pad oxide layer, then depositing a second polysilicon layer and performing back etching; sixth, depositing a dielectric layer; then removing the composite layer on the surface of the semiconductor substrate; performing etching to form an upper space in the groove; seventh, forming a gate dielectric layer and a gate electrode; eighth, respectively performing ion implantation to form a well region and a source region; forming a contact hole; and after the top metal layer is made, completing subsequent processes. The SGT device disclosed by the application comprises a floating electrode forming a lateral field plate, which optimizes the electric field of a drift region and improves the breakdown voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and in particular to an SGT device. This invention also relates to a process method for manufacturing the SGT device. Background Technology

[0002] In the field of low-to-medium voltage devices with a withstand voltage of 60V and above, shielded gate trench (SGT) devices are widely used due to their low specific on-resistance and low gate-drain coupling capacitance. The gate structure of an SGT device includes a shielded polysilicon (SPS) and a polysilicon gate. The SPS, often referred to as source polysilicon, is formed within a trench. Depending on the arrangement of the SPS and the polysilicon gate within the trench, they are typically classified as either a top-bottom structure or a left-right structure. In a top-bottom structure, the SPS is located at the bottom of the trench, and the polysilicon gate is located at the top, with the polysilicon gate and SPS arranged either top-bottom or left-right. In the top-bottom structure, the source is located at the bottom of the trench, and the polysilicon trench gate is above the source. A dielectric layer separates the source, gate, and substrate, providing mutual isolation. In the SGT device with a left-right structure, the trench-type source is located in the middle of the trench, while the polysilicon gate is located on the upper left and right sides of the source polysilicon in the trench. The source, gate and substrate are isolated from each other by a dielectric layer.

[0003] The breakdown voltage of a device is closely related to the distribution of the electric field in the drift region. Optimizing the electric field in the drift region is a relatively effective method to make the device have a higher breakdown voltage. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an SGT device that can optimize the electric field in the drift region of the device and improve the breakdown voltage of the device.

[0005] Another technical problem that the present invention needs to solve is to provide a process method for the SGT device.

[0006] To address the aforementioned problems, the present invention provides a process method for forming an SGT device with an upper and lower structure, comprising the following process steps:

[0007] The first step involves providing a semiconductor substrate, and sequentially depositing a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer on the surface of the semiconductor substrate to form a composite layer; photolithography and etching are then used to open the composite layer, and the exposed semiconductor substrate is etched to form trenches;

[0008] The second step is to deposit a first oxide layer, and then deposit a first polysilicon layer to fill the trench.

[0009] The third step is to etch back the first polysilicon to form the source of the SGT device;

[0010] Fourthly, etching the first oxide layer in the trench, so that the top surface of the first oxide layer on the inner wall of the trench is lower than the top surface of the remained first polysilicon in the trench, forming a certain difference;

[0011] Fifthly, forming a liner oxide layer, which covers the inner wall of the trench and the top surface of the first polysilicon and its sidewall which is higher than the first oxide layer; then depositing the second polysilicon and etching back, so that the remained second polysilicon is in the space formed by the difference between the first polysilicon and the inner wall of the trench, and the second polysilicon after etching back is used as the floating electrode;

[0012] Sixthly, depositing a dielectric layer, which fills the trench; then removing the composite layer on the surface of the semiconductor substrate; and etching back so that the top surface of the dielectric layer in the trench is lower than the surface of the semiconductor substrate, forming the upper space in the trench;

[0013] Seventhly, forming a gate dielectric layer, then filling the third polysilicon in the upper space of the trench and etching back;

[0014] Eighthly, respectively implanting ions to form the well region and the source region, forming the contact hole, and making the top metal to complete the subsequent process.

[0015] Further, in the first step, the material of the semiconductor substrate includes any one or combination of germanium, silicon, germanium-silicon, gallium arsenide, gallium nitride, silicon carbide, and gallium oxide.

[0016] Further, in the second step, the first oxide layer covers the surface of the semiconductor substrate and the inner wall of the trench, filling a part of the space in the trench, and the remained space is filled with the first polysilicon, and the remaining space is filled completely; the filling amount of the first polysilicon in the trench should be enough to form the source of the SGT device.

[0017] Further, in the fourth step, the etching of the first oxide layer adopts the wet etching process, and the difference between the top surface of the first oxide layer and the top surface of the first polysilicon forms a certain accommodating space.

[0018] Further, in the fifth step, the liner oxide layer is formed by deposition or directly thermal oxidation of the polysilicon.

[0019] Further, in the sixth step, the medium layer is deposited by HDP method; the medium layer is a silicon oxide layer; the semiconductor substrate surface is subjected to CMP grinding process to remove the composite layer, and then the medium layer in the trench is etched by wet etching process, so that the upper top surface of the medium layer is lower than the upper top surface of the semiconductor substrate, and an upper accommodation space in the trench is formed.

[0020] Further, in the seventh step, the upper space of the trench is filled with third polysilicon, and then etched back to be lower than the semiconductor substrate surface, and the remaining third polysilicon is used as the gate of the SGT device.

[0021] The SGT device of the present application is an up-down structure SGT device; the semiconductor substrate has a trench, the internal space of the trench is divided into two parts, the lower part of the trench contains the source of the SGT device, and the two sides of the source further have floating electrodes; the upper part of the trench has the gate of the SGT device; the source, floating electrode, gate and trench are all isolated by an insulating medium layer;

[0022] The semiconductor substrate further has the well region and source region of the SGT device, the source region is in the well region; the channel region of the SGT device is formed in the well region when the SGT device works; a contact hole is formed by etching the medium layer deposited on the semiconductor substrate surface, and the medium layer further has a metal interconnection layer on the surface;

[0023] The semiconductor substrate is thinned on the back surface to be used as the drain of the SGT device.

[0024] To solve the above problems, the present application further provides a process method of SGT device, which forms a left-right structure SGT device, and comprises the following process steps:

[0025] First step, providing a semiconductor substrate, etching a trench on the semiconductor substrate; then forming a first medium layer on the surface of the semiconductor substrate, the first medium layer covers the inner wall and bottom of the trench, a first medium layer with a certain thickness is formed, then the remaining space in the trench is filled with first polysilicon and etched back to form the source of the SGT device;

[0026] Second step, etching back the first medium layer to remove a part of the first medium layer in the trench, so that the upper top surface of the first medium layer in the trench is located at the half depth of the trench, and two accommodation spaces are formed between the two sides of the first polysilicon and the inner wall of the trench.

[0027] Third step, forming a liner oxide layer;

[0028] Fourth step, depositing second polysilicon and etching back;

[0029] fifth step, removing the liner oxide layer of the trench sidewall;

[0030] sixth step, forming a gate dielectric layer;

[0031] seventh step, depositing a third polysilicon and etching back;

[0032] eighth step, respectively performing ion implantation to form a well region and a source region, forming a contact hole, and making a top layer metal to complete subsequent processes.

[0033] Further, in the first step, the material of the semiconductor substrate comprises any one or combination of germanium, silicon, germanium-silicon, gallium arsenide, gallium nitride, silicon carbide, and gallium oxide; the thickness of the first dielectric layer deposited inside the trench is not less than the lateral width of the floating electrode of the SGT device; and after etching back the first polysilicon, the top surface of the first polysilicon is flush with the surface of the semiconductor substrate.

[0034] Further, in the second step, after etching is completed, the first polysilicon in the trench is an entirety as the source electrode of the SGT device.

[0035] Further, in the third step, the liner oxide layer is a silicon oxide layer; and the liner oxide layer is attached to the inner wall of the trench and the two sides and top of the first polysilicon.

[0036] Further, in the fourth step, the second polysilicon is filled in the accommodation space formed between the two sides of the first polysilicon and the trench and is isolated by the liner oxide layer; after etching back, the second polysilicon in the accommodation space is etched away by half; and the remaining second polysilicon forms the shield electrode of the SGT device.

[0037] Further, in the fifth step, the liner oxide layer inside the trench is removed by a wet etching process, so that the liner oxide layer attached to the top of the second polysilicon is completely removed.

[0038] Further, in the sixth step, the gate dielectric layer is an oxide layer formed by a thermal oxidation method; and the gate dielectric layer covers the entire surface of the semiconductor substrate and the inner wall of the accommodation space in the trench.

[0039] Further, in the seventh step, the third polysilicon fills the remaining space inside the trench; after filling, the third polysilicon is located above the second polysilicon and on the two sides of the first polysilicon; the third polysilicon serves as the gate electrode of the SGT device, and forms a left-right structure SGT device.

[0040] The application provides an SGT device, which is an SGT device with left-right structure.

[0041] The semiconductor substrate has a groove, the inner space of the groove is divided into three parts, the middle part of the groove contains a source of the SGT device, and both sides of the source have a floating electrode and a gate of the SGT device; the gate is located directly above the floating electrode, and the two floating electrodes are independent and not connected, and are used as field plates to optimize the electric field of the drift region; the floating electrode, the gate and the source are isolated by an insulating medium layer; the whole groove has a left-right symmetrical structure formed by a center line.

[0042] The semiconductor substrate further has a well region and a source region of the SGT device, and the source region is located in the well region; the channel region of the SGT device is formed in the well region when the SGT device works; a contact hole is formed by etching after a medium layer is deposited on the surface of the semiconductor substrate; and the medium layer further has a metal interconnection layer.

[0043] The semiconductor substrate is thinned on the back surface to serve as a drain of the SGT device.

[0044] The SGT device has a floating electrode on both sides of the source poly-silicon, which is not connected to the outside, and forms a horizontal floating field plate; the floating field plate covers the drift region on both sides of the source poly-silicon when the SGT device works, optimizes the distribution of the electric field and voltage, and further improves the withstand voltage of the drift region and the breakdown voltage BV.

[0045] The process method is designed for the SGT device with the above structure, and the floating electrode is formed on both sides of the source based on the existing process, so that the process difficulty is low. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figures 1-8 Fig. 1 is a schematic diagram of the manufacturing process steps of the SGT device with up-down structure.

[0047] Figures 9-15 Fig. 2 is a flow chart of the manufacturing process steps of the SGT device with left-right structure.

[0048] Figure 16 Fig. 3 is a schematic diagram of the electric field intensity distribution curve of the SGT device with the traditional structure.

[0049] REFERENCE SIGNS

[0050] 1 is the substrate or epitaxial layer, 2 is the composite layer, 3 is the first oxide layer, 4 is the first polysilicon (source), 5 is the pad oxide layer, 6 is the second polysilicon (floating electrode), 7 is the (inter-polysilicon) dielectric layer, 8 is the third polysilicon (gate), 9 is the well, 10 is the source region, 11 is the dielectric layer, 12 is the metal, and 13 is the contact hole. Detailed Implementation

[0051] The following detailed description, in conjunction with the accompanying drawings, provides specific embodiments of the present invention and clearly and completely describes the technical solutions of the present invention. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] It should be understood that the present invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout. It should be understood that when an element or layer is referred to as “on,” “adjacent to,” “connected to,” or “coupled to” other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0053] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to specific illustrations.

[0054] Example 1: Top-and-bottom structure SGT device

[0055] The SGT device of the present application is an up-down structure SGT device, referring to Figure 8 The semiconductor substrate has a trench therein, the inner space of the trench is divided into two halves, the lower half of the trench contains the source of the SGT device, and both sides of the source have floating electrodes respectively; the upper half of the trench has the gate of the SGT device; the source, floating electrodes, gate and trench are all isolated by an insulating medium layer;

[0056] The semiconductor substrate further has the well region and source region of the SGT device formed therein, the source region is located in the well region; the channel region of the SGT device is formed in the well region when the SGT device is working; a contact hole is formed by etching after a medium layer is deposited on the surface of the semiconductor substrate, and the medium layer further has a metal interconnection layer thereon;

[0057] The semiconductor substrate is thinned from the back to serve as the drain of the SGT device.

[0058] The up-down structure SGT device has a process method as described above, which is combined with the drawings as follows Figures 1-8 and comprises the following steps:

[0059] Firstly, a semiconductor substrate such as a silicon substrate (or on an epitaxial layer) 1 is provided, a composite layer 2 of a silicon oxide layer-nitride silicon layer-silicon oxide layer is deposited on the surface of the semiconductor substrate 1 in sequence, the composite layer is opened by photolithography and etching, and the exposed semiconductor substrate is etched to form a trench. The trench is used for forming the gate, source and shielding electrode of the SGT device subsequently, and thus the size of the trench needs to be calculated and determined according to the above structure.

[0060] Secondly, a first oxide layer 2 is deposited, and then a first polycrystalline silicon 3 is deposited. The first oxide layer 2 covers the surface of the semiconductor substrate and the inner wall of the trench, fills part of the space in the trench, and the remaining space is filled with the first polycrystalline silicon to fill the remaining space completely; the filling amount of the first polycrystalline silicon in the trench needs to be sufficient to form the source of the SGT device.

[0061] Thirdly, the first polycrystalline silicon is etched back to form the source of the SGT device. After etching back, the remaining first polycrystalline silicon is located in the lower half of the trench, and the upper half of the trench is empty.

[0062] Fourthly, the first oxide layer 3 in the trench is etched by using a wet etching process, so that the upper top surface of the first oxide layer on the inner wall of the trench is lower than the upper top surface of the remaining first polycrystalline silicon in the trench after etching, a certain difference is formed, and a containing space is generated between the first polycrystalline silicon and the inner wall of the trench.

[0063] The fifth step is to form a pad oxide layer 5 by deposition or thermal oxidation. The pad oxide layer covers the inner wall of the trench, the top surface of the first polysilicon and the sidewall of the first oxide layer. Then, the second polysilicon is deposited and etched back, so that the remaining second polysilicon is located in the gap between the sidewall of the trench and the first polysilicon. The second polysilicon after etching back is used as a floating electrode.

[0064] The sixth step is to fill the trench with a dielectric layer such as silicon oxide by HDP process. Then, the surface of the semiconductor substrate is polished by CMP process to remove the composite layer on the surface of the substrate. Then, the dielectric layer in the trench is etched by wet etching process, so that the top surface of the dielectric layer is lower than the top surface of the semiconductor substrate, and an upper space in the trench is formed.

[0065] The seventh step is to form a gate dielectric layer, and then fill the third polysilicon in the upper space of the trench and etch back. The third polysilicon remaining in the trench forms the gate of the SGT device.

[0066] The eighth step is to perform the conventional back-end process, i.e. ion implantation to form the well region and the source region, respectively, to form the contact hole, and to manufacture the top metal to complete the front electrode. The back surface of the semiconductor substrate is thinned to form the drain of the SGT device.

[0067] Embodiment two: SGT device with left-right structure

[0068] The SGT device with left-right structure according to the present application is described with reference to Figure 15 The trench is etched in the silicon substrate, and the inner space of the trench is divided into left, middle and right parts. The middle part of the trench is the source of the SGT device, and the two sides of the source each have a floating electrode and a gate of the SGT device. The gate is located directly above the floating electrode, and the left and right floating electrodes are independent and not connected, which are used as field plates to optimize the electric field of the drift region. The floating electrode, the gate and the source are isolated by an insulating dielectric layer. The entire trench has a left-right symmetrical structure formed by a center line.

[0069] The well region and the source region of the SGT device are also formed in the semiconductor substrate, and the source region is located in the well region. The channel region of the SGT device is formed in the well region when the SGT device is working. The contact hole is formed by etching the dielectric layer deposited on the surface of the semiconductor substrate, and the metal interconnection layer is also formed on the dielectric layer.

[0070] The semiconductor substrate is thinned on the back surface to serve as the drain of the SGT device.

[0071] The process method for forming the SGT device with the above left-right structure comprises the following steps:

[0072] In the first step, a semiconductor substrate such as a silicon substrate is provided, and a trench is etched on the semiconductor substrate. Then, a first oxide layer is formed on the surface of the semiconductor substrate, covering the inner wall and bottom of the trench. The first oxide layer has a thickness not less than the lateral width of the floating electrode of the SGT device. Then, the remaining space inside the trench is filled with first polysilicon and re-etched. After re-etching, the top surface of the first polysilicon is flush with the surface of the semiconductor substrate. The first polysilicon forms the source electrode of the SGT device.

[0073] In the second step, the first dielectric layer is re-etched to remove a portion of the first dielectric layer inside the trench, so that the top surface of the first dielectric layer inside the trench is located at a position half the depth of the trench. After etching, the first polysilicon in the trench forms an integral part as the source electrode of the SGT device. The two sides of the first polysilicon and the inner wall of the trench form two accommodation spaces.

[0074] In the third step, a pad oxide layer such as a silicon oxide layer is formed. The pad oxide layer adheres to the inner wall of the trench, the two sides and top of the first polysilicon, and serves as an isolation medium between the source electrode, the gate electrode, and the trench.

[0075] In the fourth step, second polysilicon is deposited and re-etched. The second polysilicon is filled in the accommodation spaces formed between the two sides of the first polysilicon and the trench, and is isolated by the pad oxide layer. After re-etching, the second polysilicon in the accommodation spaces is etched away by half. The remaining second polysilicon forms the shield electrode of the SGT device, which is in a floating state and can be used to adjust the electric field distribution of the drift region and improve the breakdown voltage.

[0076] In the fifth step, the pad oxide layer inside the trench is removed by a wet etching process, so that the pad oxide layer adhering to the top of the second polysilicon is completely removed.

[0077] In the sixth step, a gate dielectric layer is formed by a thermal oxidation method. The gate dielectric layer covers the entire surface of the semiconductor substrate and the inner wall of the accommodation space in the trench.

[0078] In the seventh step, third polysilicon is deposited and re-etched. The third polysilicon fills the remaining space inside the trench. After filling, the third polysilicon is located above the second polysilicon and on both sides of the first polysilicon. The third polysilicon serves as the gate electrode of the SGT device, forming the SGT device with the left-right structure.

[0079] The eighth step is the same as that in the first embodiment, and subsequent processes are performed, including ion implantation for forming a well region and a source region respectively, forming a contact hole, and manufacturing a top metal layer, and after thinning the back of the substrate, forming a drain of the SGT device.

[0080] The SGT device provided by the present application includes an up-down structure and a left-right structure. The present application adds floating shield electrodes on both sides of the source structure in the trench, and the shield electrodes form lateral field plates on both sides of the source polysilicon, which adjust the electric field of the drift region. By simulating and comparing the structure of the present application with the conventional structure, as shown in FIG. 6, the shield electrodes of the present application further reduce the electric field of the drift region close to the substrate surface, and make the electric field of the drift region deeper into the substrate, so that the electric field intensity of the drift region close to the substrate surface is reduced, and the breakdown voltage of the device is improved. Figure 16

[0081] The above is only the preferred embodiment of the present application, and is not used to limit the present application. The present application can have various changes and variations for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.​

Claims

1. A process method for SGT device, forming SGT device of up-down structure, characterized in that: The process comprises the following steps: In the first step, a semiconductor substrate is provided, and a composite layer of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer is deposited on the surface of the semiconductor substrate in sequence. The composite layer is opened by photolithography and etching, and the exposed semiconductor substrate is etched to form a trench. In the second step, a first oxide layer is deposited, and then a first polysilicon layer is deposited to fill the trench. In the third step, the first polysilicon layer in the trench is etched back to form the source electrode of the SGT device. In the fourth step, the first oxide layer in the trench is etched, and the upper surface of the first oxide layer on the inner wall of the trench is lower than the upper surface of the remaining first polysilicon layer in the trench, forming a certain gap. In the fifth step, a pad oxide layer is formed, which covers the upper surface of the first polysilicon layer and the sidewall of the first oxide layer. Then, a second polysilicon layer is deposited and etched back, and the remaining second polysilicon layer is located in the gap space between the first polysilicon layer and the inner wall of the trench, and the etched second polysilicon layer serves as a floating electrode. In the sixth step, a dielectric layer is deposited. The dielectric layer fills the trench. Then, the composite layer on the surface of the semiconductor substrate is removed. Then, the dielectric layer in the trench is etched to be lower than the surface of the semiconductor substrate, forming an upper space in the trench and a gate dielectric layer. In the seventh step, a third polysilicon layer is deposited in the upper space of the trench and etched back. In the eighth step, the semiconductor substrate outside the trench is ion implanted to form a well region and a source region in the well region, a contact hole extending to the source region is formed, and a top metal layer connected to the contact hole is made to complete the subsequent process. In the first step, the material of the semiconductor substrate includes any one or a combination of germanium, silicon, germanium-silicon, gallium arsenide, gallium nitride, silicon carbide, and gallium oxide.

2. The process method of SGT device as claimed in claim 1 wherein: In the second step, the first oxide layer covers the surface of the semiconductor substrate and the inner wall of the trench, filling part of the space in the trench. The remaining space is filled with the first polysilicon layer, and the remaining space is filled with the first polysilicon layer. The filling amount of the first polysilicon layer in the trench is sufficient to form the source electrode of the SGT device.

3. The process method of SGT device as claimed in claim 1 wherein: In the fourth step, the first oxide layer is etched using a wet etching process, and the gap between the upper surface of the first oxide layer and the upper surface of the first polysilicon layer forms a certain accommodation space.

4. The process method of SGT device as claimed in claim 1 wherein: In the fifth step, the pad oxide layer is formed by deposition or direct thermal oxidation of the polysilicon.

5. The process method of SGT device as claimed in claim 1, wherein: In the sixth step, the dielectric layer is deposited by HDP method; and the dielectric layer is a silicon oxide layer.

6. The process method of SGT device as claimed in claim 1, wherein: The surface of the semiconductor substrate is subjected to a CMP polishing process to remove the composite layer, and then a wet etching process is used to etch the dielectric layer in the trench, so that the upper surface of the dielectric layer is lower than the upper surface of the semiconductor substrate, forming an upper accommodation space in the trench. In the seventh step, the third polysilicon layer is etched back to be lower than the surface of the semiconductor substrate after being filled in the upper space of the trench, and the remaining third polysilicon layer serves as the gate electrode of the SGT device.

7. The process method of SGT device as claimed in claim 1 wherein: ​ 8. An SGT device formed by a process employing the SGT device of claim 1, wherein: The SGT device is an up-down structure SGT device; a groove is formed in the semiconductor substrate, the inner space of the groove is divided into two halves, the lower half of the groove contains the source of the SGT device, and both sides of the source further have floating electrodes; the upper half of the groove has the gate of the SGT device; the source, floating electrodes, gate and groove are all isolated by an insulating medium layer; The semiconductor substrate further has the well region and source region of the SGT device, the source region is in the well region, the channel region of the SGT device is formed in the well region when the SGT device is working; a contact hole is formed by etching after a medium layer is deposited on the surface of the semiconductor substrate, and the medium layer further has a metal interconnection layer on the surface; The semiconductor substrate is thinned on the back side to serve as the drain of the SGT device.

9. A process for forming a SGT device in a left-right configuration, comprising: The process comprises the following steps: ​ In the first step, a semiconductor substrate is provided, a groove is etched in the semiconductor substrate, a first medium layer is formed on the surface of the semiconductor substrate, the first medium layer covers the inner wall and bottom of the groove, a first polysilicon is filled in the remaining space in the groove and is etched back so that the top surface of the first polysilicon is flush with the surface of the semiconductor substrate, and the source of the SGT device is formed; In the second step, the first medium layer is etched back to remove a part of the first medium layer in the groove, the top surface of the first medium layer in the groove is located at the half depth of the groove, and two accommodating spaces are formed between the two sides of the first polysilicon and the inner wall of the groove; In the third step, a liner oxide layer is formed on the inner wall of the groove and the two sides of the first polysilicon; In the fourth step, a second polysilicon is deposited in the two accommodating spaces and is etched back, and the remaining second polysilicon is the floating electrode; In the fifth step, the liner oxide layer on the sidewall of the groove above the second polysilicon is removed; In the sixth step, a gate medium layer is formed on the surface of the semiconductor substrate and the inner wall of the accommodating space in the groove; In the seventh step, a third polysilicon is deposited in the remaining space in the groove and is etched back; In the eighth step, the semiconductor substrate outside the groove is ion implanted to form a well region and a source region in the well region, a contact hole extending to the source region is formed, and the top layer metal connected to the contact hole is made to complete the subsequent process.

10. The process method of SGT device as claimed in claim 9, wherein: In the first step, the material of the semiconductor substrate comprises any one or combination of germanium, silicon, germanium-silicon, gallium arsenide, gallium nitride, silicon carbide and gallium oxide; the thickness of the first medium layer deposited in the groove is not less than the lateral width of the floating electrode of the SGT device; and the top surface of the first polysilicon is flush with the surface of the semiconductor substrate after the first polysilicon is etched back.

11. The process method of SGT device as claimed in claim 9, wherein: In the second step, the first polysilicon in the groove is an integral whole as the source of the SGT device after etching.

12. The process method of SGT device as claimed in claim 9, wherein: In the third step, the liner oxide layer is a silicon oxide layer; and the liner oxide layer is attached to the inner wall of the groove and the two sides and top of the first polysilicon.

13. The process method of SGT device as claimed in claim 9, wherein: In the fourth step, the second polysilicon fills the space formed between the first polysilicon and the trench, and is isolated by the liner oxide layer; after etching back, the second polysilicon in the space is etched away by half; the remaining second polysilicon forms the shielding electrode of the SGT device.

14. The process method of SGT device as claimed in claim 9, wherein: In the fifth step, the liner oxide layer in the trench is removed by wet etching process, so that the liner oxide layer attached to the second polysilicon is completely removed.

15. The process method of SGT device as claimed in claim 9, wherein: In the sixth step, the gate dielectric layer is an oxide layer formed by thermal oxidation; the gate dielectric layer covers the entire surface of the semiconductor substrate and the inner wall of the space in the trench.

16. The process method of SGT device as claimed in claim 9, wherein: In the seventh step, the third polysilicon fills the remaining space in the trench, and after filling, the third polysilicon is located above the second polysilicon and on both sides of the first polysilicon; the third polysilicon serves as the gate of the SGT device, forming a left-right structure SGT device.

17. An SGT device formed by a process employing the SGT device of claim 9, wherein: The SGT device is a left-right structure SGT device. The semiconductor substrate has a trench, and the internal space of the trench is divided into left, middle and right parts; the middle part of the trench contains the source of the SGT device, and both sides of the source further have floating electrodes and the gate of the SGT device; the gate is located directly above the floating electrode, and the left and right floating electrodes are independent and not connected, serving as field plates to optimize the electric field of the drift region; the floating electrodes, the gate and the source are isolated by an insulating dielectric layer; the entire trench forms a left-right symmetric structure with a center line; The semiconductor substrate further has the well region and the source region of the SGT device, and the source region is located in the well region; the channel region of the SGT device is formed in the well region when the device is working; after depositing a dielectric layer on the surface of the semiconductor substrate, a contact hole is etched; the dielectric layer further has a metal interconnection layer on the top. After the back of the semiconductor substrate is thinned, it serves as the drain of the SGT device.

Images