A layout self-testing method and storage device

Abstract

This invention provides a layout self-checking method, including acquiring all or part of the routing path information to be self-checked in the layout, and preset layout coloring layer rules; using the preset layout coloring layer rules, performing self-checks on the coloring layer information of the routing paths to be self-checked, including: traversing and checking whether the coloring layer of each connection block in the routing path to be self-checked is correct, and obtaining the self-check result. The self-checking method of this invention can quickly verify the layout coloring layer after automatic routing, enabling early detection of problems; and for various connection situations of metal layer paths, it can automatically and quickly verify the correctness of the coloring layer covering the metal layer, which is beneficial for improving chip design efficiency and further optimizing the process. This invention also provides a storage device with corresponding advantages.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor design and manufacturing technology, and particularly relates to a layout self-testing method and a storage device. Background Technology

[0002] In the integrated circuit industry, with the continuous advancement of chip manufacturing processes, the further miniaturization of transistor dimensions, and the shrinking of inter-metal pitch, a single photomask is often insufficient for the needs of the same metal layer, sometimes requiring two, three, or even more photomasks. In GDSII layouts, for example, different color layers are needed to distinguish different photomasks for the same metal layer, which increases the likelihood of color layer conflicts in the layout. Therefore, verifying the correctness of the color layers covered by metal layer paths becomes crucial in GDSII layouts.

[0003] Currently, the standard practice for checking the color layer overlay of the metal layer in the layout is to run DRC to check for color layer conflicts. However, this is already in the latter half of the chip design process. Even if a problem is found, it will be discovered late. Correcting these color layer conflicts after they are discovered will add a lot of extra work and affect the entire production process.

[0004] Therefore, it is necessary to study a method that can verify the correctness of the color layer covered by the metal layer path in the GDSII layout at any time in the early stage of the chip design process or throughout the entire design process. This method should be applicable to the inspection of the color layer covered by the metal layer in the layout, solving the problem that the current practice can only verify in the latter half of the process, which leads to the delay in problem detection and affects production efficiency. This would bring convenience to chip design and further promote the in-depth development and widespread application of semiconductor design and manufacturing technology. Summary of the Invention

[0005] This invention addresses all or part of the problems of the prior art. One aspect of this invention provides a layout self-testing method capable of checking whether the color layer covered by the metal layer winding path of an integrated circuit layout is correct. Another aspect of this invention provides a storage device storing instructions capable of executing the layout self-testing method of this invention.

[0006] This invention provides a layout self-checking method, comprising: acquiring all or part of the routing path information to be self-checked in the layout, and a preset layout color layer rule; wherein, the routing path is composed of several directly connected or connected by vias or contacts; the connecting block is a polygonal structure in the connecting layer; the routing path information includes color layer information; the preset layout color layer rule refers to configuration information, representing the optional color layer information of the connecting layer in the layout; using the preset layout color layer rule, performing a self-check on the color layer information of the routing path to be self-checked, including: traversing and checking whether the color layer of each connecting block in the routing path to be self-checked is correct, and obtaining a self-check result. In the example case, the preset layout color layer rule is obtained from the color layer settings in the layout design tool, i.e., the preset layout color layer rule. By first obtaining the preset color layer rules, the color layer information of the routing path can be self-checked at any time in the early stage of the chip design process or throughout the entire layout design process. This allows for checking whether there are any conflicts between the color layers covering the metal layers on the routing path, thus enabling timely detection of problems. This greatly facilitates chip design, overcomes the limitation of delayed problem detection in existing practices, and provides a feasible solution for effectively guiding subsequent layout modifications and process optimization.

[0007] The layout self-checking method describes a system where different color layers correspond to different photomasks. Taking a GDSII layout as an example, a single metal layer may have one or more photomasks covered by several color layers, with each color layer corresponding to a photomask. When different photomasks are distinguished by covering the same metal layer with different color layers, the layout self-checking method can promptly and accurately detect color layer conflicts within the layout.

[0008] The self-test checks the correctness of the color layer of the connector block, including: whether the color layer of the connector block itself is correct; whether the color layer of the connector block is the same as that of the directly connected pin; and whether the color layer of the connector block is the same as that of other directly connected connector blocks on the same layer. It checks for various possible color layer conflicts in the routing path, thus providing a more comprehensive reflection of the correctness of the color layer covering the metal layer in the layout design in the self-test results.

[0009] After obtaining the preset layout coloring layer rules, a dictionary data structure is set up for storage. This dictionary data structure stores the connection layers as keys and the coloring layers that each connection layer can select as values; each key corresponds to several values. Storing the layout coloring layer rules using a dictionary data structure facilitates searching and comparison, streamlines the self-checking process, and promotes efficient implementation of the self-checking process.

[0010] After setting up the dictionary data structure, iterate through the dictionary data structure. If the shader corresponding to all connection layers is empty, then end the layout self-check. By iterating through the dictionary data structure to make a preliminary judgment, if the shader corresponding to all connection layers is empty, there is no need to perform subsequent steps, thus improving this layout self-check mechanism and increasing overall efficiency.

[0011] In general, each connection block of all or part of the routing path to be self-tested is obtained and denoted as a set P{P1, P2, ..., Pi, ..., Pn}, where Pi is a connection block and i∈[1, n]. An error information data set E is set and initialized to empty, with i=1 initialized. The method for traversing and checking whether the color layer of each connection block in the routing path to be self-tested is correct includes: Step 1: According to the preset layout color layer rules, determine whether the connection block Pi corresponds to the correct color layer: if yes, continue to the subsequent steps; if no, add the error information to the error information data set E and directly execute step 4; Step 2: Determine whether the connection block Pi has a direct connection relationship with the pin: if yes, according to the preset layout color layer rules, determine whether the color layer of the connection block Pi is directly connected to the pin. The pins have the same coloring layer: If they are the same, continue to the next step; if they are different, add the error information to the error information data set E and directly execute step four; if not, directly continue to the next step; Step three: Determine whether the connection block Pi has a direct connection relationship with other connection blocks in the same layer: If it exists, then according to the preset layout coloring layer rules, determine whether the coloring layer of the connection block Pi is the same as the coloring layer of the directly connected connection block in the same layer: If they are the same, continue to the next step; if they are different, add the error information to the error information data set E and start step four; if not, directly start step four; Step four: Determine whether i is equal to n: If yes, complete the self-check of all or part of the winding paths to be self-checked and obtain the self-check result, i.e., the error information data set E; if not, let i = i + 1 and return to step one to continue traversing. Only add error information to set E, and do not add correct information. It can be added to set E with a label similar to Pi coloring layer error. Each time a judgment is made, an error is added in time. By traversing set P to perform self-checks on all or part of the winding paths to be checked, an error information data set containing different types of error data can be obtained to reflect the specific problem, which is beneficial for subsequent analysis and improvement and has higher self-checking efficiency.

[0012] After completing the self-test of the winding path to be self-tested, if the obtained error information data set E is empty, it indicates that the self-tested winding path has passed verification; if the obtained error information data set E is not empty, it indicates that the self-tested winding path has failed verification. The self-test result includes whether the error information data set E is empty. Whether the data set is empty can intuitively determine whether the self-tested winding path has passed verification.

[0013] In other cases, after completing the self-check for all the routing paths to be self-checked, if all the routing paths to be self-checked pass the verification, it means that the shader layer of the layout has passed the verification; otherwise, a self-check report will be output for layout modification reference. The self-check report can be automatically generated using the error information set and a preset report template.

[0014] Another aspect of the present invention provides a storage device storing a plurality of instructions adapted to be loaded and executed by a processor: a layout self-test method of one aspect of the present invention.

[0015] Compared with the prior art, the main beneficial effects of the present invention are: 1. The layout self-checking method of the present invention is simple and efficient. Based on pre-set layout color layer rules, it can quickly verify the color layer of the layout during the layout design process or at the end of automatic routing. This allows for timely detection of problems, avoiding the adverse effects of delayed detection on the entire production process and providing an effective solution for further process optimization. Furthermore, it can automatically and quickly verify the correctness of the color layer in the layout design for various connection situations of routing paths in the metal layer. The self-checking results are comprehensive and reliable, greatly facilitating the improvement of subsequent layout designs and bringing significant convenience to chip design work.

[0016] 2. A storage device according to the present invention stores instructions capable of executing the layout self-test method of the present invention. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the self-testing method process according to Embodiment 1 of the present invention.

[0018] Figure 2 This is a schematic diagram of the traversal process in Embodiment 1 of the present invention.

[0019] Figure 3 This is a schematic diagram of the layout of Embodiment 2 of the present invention. Detailed Implementation

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings. The operation of the embodiments is described in a specific order in the following embodiments. This order is provided for a better understanding of the details in the embodiments to fully comprehend the invention, but such description is not intended to limit the scope of the invention. Hereinafter, "metal layer" refers to a metal layer, serving as an example of a connecting layer, and "color layer" refers to a coloring layer.

[0021] Example 1 In Embodiment 1 of this invention, a GDSII layout is used as an example for ease of understanding, but the specific details of the layout design tool and layout file format are not limited. Figure 1 As shown, the layout self-check method includes: Step S1: Obtain the color layer settings related to the metal layer in the layout design tool (obtain the preset layout color layer rules), and store them as a dictionary data structure, where the metal layer is used as the key, and the corresponding optional color layer information of the metal layer is used as the value. Step S2: Traverse the dictionary data structure of Step S1. If the color layer corresponding to all metal layers is empty, the self-check process ends; otherwise, proceed to Step S3. Step S3: Read the layout data, collect the winding paths of all metal layers in the layout and store them in the data set respectively, and perform a self-check on the color layer information of each winding path metal path to obtain the self-check result and output it. In this embodiment, the routing path to be self-tested consists of several directly connected connecting blocks or connecting blocks connected by vias and contacts. The connecting blocks are polygonal structures in the metal layer. This embodiment only performs self-testing on the color layer of the connecting blocks in the metal layer, that is, it does not perform self-testing on vias and contacts. However, it does not exclude the possibility that vias and contacts may also need to be self-tested, and this is not limited here. The preset layout color layer rule in the example refers to the configuration information, which indicates the optional color layer information of the connecting layers in the layout.

[0022] In some implementations, when the self-check results show that the layer mask verification of the layout has failed, in addition to outputting the conclusion of failure, the error information obtained during the self-check process will also be compiled into a self-check report and output, which will be used as a reference for subsequent layout modifications. The specific approach is not limited here.

[0023] It should be noted that storing the acquired preset layout coloring layer rules in a dictionary data structure is an example of a self-checking process in this embodiment. In other implementations, other types of data structures are used for the self-checking process, or no specific data structure is set for storage. The specific implementation method is not limited here.

[0024] In this embodiment, combined with Figure 2 The specific steps for self-checking the metal path of the metal layer are illustrated below. Collect all metal paths in the layout, and denote all connected blocks of all metal paths to be self-checked as the data set P{P1,P2,P3,…,Pi,…,Pn}. Initialize the error information data set E, initializing i=1: Decision 1: Based on the preset layout coloring layer rules, determine whether the color layer corresponding to its metal layer is covered on the connecting block Pi. If so, proceed to Decision 2; otherwise, add the error message Ej obtained from Decision 1 to set E and proceed directly to Decision 4. Decision 1 involves checking whether the color layer covered on the metal path matches the settings.

[0025] Decision 2: Determine if the connection block Pi is connected to a pin of a unit structure (e.g., a transistor) in the layout. If no connection exists, proceed to Decision 3. If a connection exists, check if the color layer covering the connection block Pi matches the color layer covering the pin according to the preset layout color layer rules. If they do not match, add the error message Em obtained from Decision 2 to set E and proceed directly to Decision 4. Decision 2 checks whether the color layer on a path matches the color layer of the pin.

[0026] Decision 3: Determine if connecting block Pi is directly connected to other connecting blocks in the same metal layer. If so, according to the preset layout coloring rules, further determine if the color layer of connecting block Pi is consistent with the color layer of other directly connected blocks in the same metal layer. If they are inconsistent, add the error message Ek obtained from decision 3 to set E, and then proceed to decision 4. If there is no direct connection with other connecting blocks in the same metal layer, proceed directly to decision 4. Decision 3 checks if the routing path metal path has a shared path, and then checks if the coloring of the routing path metal path and the shared path is consistent.

[0027] Decision 4: Determine if the join block Pi is the last unverified join block (i.e., whether i equals n). If yes, proceed to Decision 5; otherwise, set i = i + 1 and return to Decision 1. Decision 4 is used to determine whether all join blocks in the data set P have been traversed.

[0028] Judgment 5: Determine if the error information set E is empty. If it is empty, the verification result is passed; otherwise, the verification result is failed, the self-check ends, and the error information set E is output. In this embodiment, the error information set E can contain different types of error information, such as the color layer error Ej of the connection block itself, the color layer error Em of the connection block and the directly connected pin, and the color layer error Ek of the connection block and other directly connected connection blocks in the same layer.

[0029] In the example scenario, all routing paths to be self-tested in the layout are obtained, and all connecting blocks of all routing paths to be self-tested are grouped into a set P. In some implementations, only a portion of the routing paths to be self-tested in the layout may be obtained, and the obtained portion of the routing paths to be self-tested are self-tested, and all connecting blocks of the obtained routing paths to be self-tested are grouped into a set. In other implementations, all connecting blocks of a single routing path to be self-tested are used as a data set, and the connecting blocks of each routing path to be self-tested are traversed separately, without limiting the specific implementation.

[0030] Example 2 The following embodiments are provided to enable those skilled in the art to gain a more comprehensive understanding of the present invention, but do not limit the invention in any way. These embodiments are based on... Figure 3 The following is a targeted example of the layout self-checking method using a simple GDSII file as an example.

[0031] First, read the GDSII file to obtain the layout, and retrieve the color layer settings from the layout design tool and store them as a dictionary data structure, namely {“M1_drawing”:“M1CA_drawing,M1CB_drawing”,”M2_drawing”:“M2CA_drawing,M2CB_drawing”}.

[0032] The code reads the wire paths from the metal layer patterns M1_drawing and M2_drawing in the GDSII file. All connecting blocks of all wire paths are stored in a set P{P1,P2,P3,P4,P5}. Each connecting block stores information including the layer, path width, and point coordinates. The error message set E is then initialized. The example wire path consists of connecting blocks, where the via pattern is... Figure 3 The meaning is shown in V1_drawing.

[0033] Iterate through set P, read the first connected block P1, located in the M1_drawing layer, and determine if this layer is in one of the color layer settings of M1_drawing, namely M1CA_drawing or M1CB_drawing. Figure 3 In the example, M1CA_drawing meets the requirements. Next, it checks if there is a pin of the M1_drawing layer that intersects with the connecting block P1. Since P1 intersects with pin I1, and P1 and pin I1 cover the same color layer (M1CA_drawing), this also meets the requirements. Since there are no other connecting blocks connected to P1, the connection block P1 passes the verification.

[0034] The second connection block P2 is read. It is located in the M2_drawing layer. No pins in the M2_drawing layer intersect with P2, so this check is skipped. Next, it is checked whether there are any other M2_drawing connection blocks that intersect with P2. Connection block P4 is found. Connection block P4 is also located in the M2_drawing layer, and it covers the color layer at the same coordinates, i.e., M2CA_drawing, which is consistent with the color layer of P2. Therefore, connection block P2 passes verification.

[0035] Read the third connection block P3, located on the M1_drawing layer. Check if there is an intersection between the M1_drawing pin and P3. Since P3 intersects with pin I12 and both cover the layer with color layer M1CA_drawing, it meets the requirements. Since there is no M1_drawing connection block connected to P3, skip this check, and connection block P3 passes verification.

[0036] Read the fourth connection block P4, which is located on the M2_drawing layer. Connection block P4 is covered by a layer with the color layer M2CA_drawing. The connection block P2 that intersects with it is also covered by the color layer M2CA_drawing. Then the connection block P4 passes the verification.

[0037] Read the fifth connection block P5, which is located on the M1_drawing layer. Connection block P5 is covered by a layer with the color layer M1CB_drawing. There is a pin I2 with the same layer and its color layer is M1CB_drawing, which is consistent with connection block P5. Then connection block P5 is verified.

[0038] Following the self-checking method described above, after traversing all connection blocks, it checks whether the final error information set is empty. If empty, it outputs the information that the color layer of the layout has passed verification; if not empty, it outputs the layer, coordinate points, and color layer information of the routing path. Error types generally include incorrect color layers covering the routing path, inconsistencies between the path and pin color layers, and color layer conflicts between the routing path and shared paths.

[0039] The commonly used English terms or letters used in this invention for clarity are merely illustrative purposes and not limiting interpretations or specific usages. Their possible Chinese translations or specific letters should not be used to limit the scope of protection of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A layout self-checking method, characterized in that: include: Obtain all or part of the routing path information to be self-checked in the layout, as well as the preset layout coloring layer rules; The winding path consists of several directly connected or connected blocks via through holes or contact holes; the connecting block is a polygonal structure in the connecting layer; the winding path information includes shading layer information; the preset layout shading layer rules refer to configuration information, representing the optional shading layer information of the connecting layer in the layout; Using the preset layout coloring layer rules, the coloring layer information of the routing paths to be self-checked is self-checked, including: obtaining each connection block of all or part of the routing paths to be self-checked, and traversing to check whether the coloring layer of each connection block in the routing paths to be self-checked is correct. The method includes: Based on the preset layout coloring layer rules, determine whether the connecting block corresponds to the correct coloring layer; Determine whether the color layer of the connecting block is the same as the color layer of the directly connected pin; Determine whether the coloring layer of the connecting block is the same as the coloring layer of the directly connected connecting blocks in the same layer; Determine whether the self-test of all or part of the winding path to be self-tested has been completed. If so, obtain the self-test result.

2. The layout self-inspection method according to claim 1, characterized in that: Different coloring layers correspond to different photomasks.

3. The layout self-inspection method according to claim 1, characterized in that: After obtaining the preset layout coloring layer rules, a dictionary data structure is set up for storage; the dictionary data structure refers to storing the connection layer as the key and storing the coloring layer that each connection layer can select as the value; and each key corresponds to several values.

4. The layout self-inspection method according to claim 3, characterized in that: After setting the dictionary data structure, iterate through the dictionary data structure. If the shader corresponding to all connection layers is empty, then end the current layout self-check.

5. A layout self-inspection method according to any one of claims 1-4, characterized in that: Obtain all or part of the winding paths to be self-checked and denote each connecting block as a set P{P1, P2, ..., Pi, ..., Pn}, where Pi is a connecting block and i∈[1, n]; set the error information data set E and initialize the error information data set E to empty, and initialize i=1; The method for traversing and checking whether the color layer of each connection block in the winding path to be self-tested is correct includes: Step 1: Based on the preset layout coloring layer rules, determine whether the connecting block Pi corresponds to the correct coloring layer: if yes, continue to the subsequent steps; if no, add the error information to the error information data set E, and directly execute Step 4; Step 2: Determine whether the connection block Pi has a direct connection with the pin: If so, then according to the preset layout coloring layer rules, determine whether the coloring layer of the connection block Pi is the same as the coloring layer of the pin: if they are the same, continue with the subsequent steps; if they are different, add the error information to the error information data set E, and directly execute step four. If not, proceed directly to the next steps; Step 3: Determine whether the connecting block Pi has a direct connection with other connecting blocks in the same layer: If it exists, then according to the preset layout coloring layer rules, determine whether the coloring layer of the connecting block Pi is the same as the coloring layer of the directly connected connecting block in the same layer: if they are the same, continue to the subsequent steps; if they are different, add the error information to the error information data set E and start step four. If it does not exist, proceed directly to step four; Step 4: Determine if i is equal to n: If yes, complete the self-check of all or part of the winding paths to be self-checked, and obtain the self-check result, i.e., the error information data set E; If not, let i = i + 1 and return to step one to continue the traversal.

6. The layout self-inspection method according to claim 5, characterized in that: After completing the self-test of the winding path to be self-tested, if the obtained error information data set E is empty, it means that the self-test of the winding path has passed the verification; if the obtained error information data set E is not empty, it means that the self-test of the winding path has failed the verification.

7. The layout self-inspection method according to claim 1, characterized in that: After completing the self-test for all the routing paths to be self-tested, if all the routing paths to be self-tested pass the verification, it means that the shading layer of the layout has passed the verification; otherwise, a self-test report will be output for layout modification reference.

8. A storage device storing a plurality of instructions adapted to be loaded and executed by a processor: the layout self-test method according to any one of claims 1-7.

Images