Phase change memory

Abstract

Embodiments of the present disclosure relate to phase change memory. A memory cell is fabricated by: (a) forming a stack comprising a first layer made of a phase change material and a second layer made of an electrically conductive material; (b) forming a mask on the stack covering only memory cell locations; and (c) etching portions of the stack not covered by the first mask. The forming of the mask covering only memory cell locations includes defining, for each row of memory cell locations, a first mask extending in a row direction, and then patterning the first mask in a column direction for each column of memory cell locations.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to French Patent Application No. 2105618, filed May 28, 2021, the entire contents of which are incorporated herein by reference to the maximum extent legally permissible. TECHNICAL FIELD

[0003] The present disclosure relates generally to electronic devices, and more specifically to phase change memory and methods of manufacturing the same. BACKGROUND

[0004] Phase change materials are materials that can be converted between a crystalline phase and an amorphous phase under the action of heat. This phenomenon can be used to define two memory states, such as 0 and 1, distinguished by the resistance measured through the phase change material, since the resistance of amorphous material is significantly higher than the resistance of crystalline material.

[0005] The memory cells are preferably arranged within a memory as an array comprising, for example, rows associated with word lines and, for example, columns associated with bit lines. SUMMARY

[0006] One embodiment provides a method for manufacturing a memory cell, comprising: a) forming a stack comprising a first layer of phase change material and a second layer of electrically conductive material; b) forming a first mask covering only memory cell locations on the stack; and c) etching a portion of the stack not covered by the first mask.

[0007] According to one embodiment, step a) comprises forming at least a third layer of electrically insulating material between the second layer and the first mask.

[0008] According to one embodiment, step c) does not etch both the first layer and another layer of another material at the same time.

[0009] According to one embodiment, the method comprises forming a resistive element in contact with the first layer.

[0010] According to one embodiment, step b) comprises: depositing a fourth layer of material of the first mask on the stack; forming a second mask extending in a first direction and covering the memory cell locations; etching a portion of the fourth layer not covered by the second mask; forming a third mask extending in a second direction and covering the memory cell locations; and etching a portion of the fourth layer not covered by the third mask.

[0011] According to one embodiment, the etching method used to etch the fourth layer etches the material of the fourth layer at a speed at least 20 times faster than the material of the layers located below the fourth layer.

[0012] According to one embodiment, the first mask is made of titanium nitride.

[0013] According to an embodiment, the first layer is made of an alloy of germanium, antimony and tellurium.

[0014] According to an embodiment, the method comprises manufacturing an array of memory cells, each cell being manufactured by a method according to the above method.

[0015] According to an embodiment, a first mask is formed over the position of each memory cell, and wherein step c) is performed simultaneously for all cells.

[0016] According to an embodiment, each first mask is common for a row of cells in the array, and wherein each second mask is common for a column of cells in the array.

[0017] According to an embodiment, the method comprises depositing at least one electrically insulating layer on the cells of the array.

[0018] According to an embodiment, the method comprises depositing an electrically conductive via through the insulating layer so as to reach the second layer.

[0019] According to an embodiment, the method comprises forming an electrically conductive strip extending over the second layer of cells in a row or column of the array. BRIEF DESCRIPTION OF DRAWINGS

[0020] The foregoing features and advantages, as well as others, will be given in the description of specific embodiments which follows, with reference to the accompanying drawings, given by way of illustration and not limitation, in which:

[0021] Figures 1 to 8 Steps of one embodiment of a method for manufacturing a phase change memory are shown, preferably consecutive steps;

[0022] Figure 9 An alternative step to the steps of Figure 8 is shown; and

[0023] Figure 10 An alternative step to the steps of Figure 8 and 9 is shown. DETAILED DESCRIPTION

[0024] In the various drawings, like features are denoted by like reference numerals. In particular, structural and / or functional features common to the various embodiments can have the same reference numerals and can be provided with the same structural, dimensional and material properties.

[0025] For the sake of clarity, only the operations and elements necessary for understanding the operation of the embodiments described herein are described and detailed.

[0026] Unless otherwise stated, when referring to two elements connected together, this means a direct connection without any intermediate elements other than a conductor, and when referring to two elements connected together, this means that the two elements can be connected or they can be coupled via one or more other elements.

[0027] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or to relative position qualifiers, such as the terms "upper", "lower", "higher", "lower", etc., or to orientation qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figures.

[0028] Unless otherwise stated, the expressions "about", "approximately", "substantially" and "of" mean within 10%, preferably within 5%.

[0029] Figures 1 to 8 The steps of one embodiment of a method for manufacturing a phase change memory are illustrated, preferably consecutively.

[0030] Figure 1 One step of an embodiment of a method for manufacturing a phase change memory cell is illustrated.

[0031] The manufacturing step comprises forming an electrically conductive via 10. The step comprises manufacturing a resistive element 12 placed on the electrically conductive via 10. The resistive element 12 is preferably L-shaped, with a horizontal part on the via 10 and a vertical part extending substantially perpendicular to the horizontal part. The via 10 and the resistive element 12 are surrounded by an electrically insulating layer 14. The upper surface of the vertical part of the resistive element 12 is flush with the upper surface of the layer 14. The layer 14 comprises a stack of a plurality of electrically insulating layers of different electrically insulating materials, for example.

[0032] The upper surface of the layer 14 and of the vertical part of the resistive element is covered by a stack comprising a layer 16 of phase change material, a layer 18 of electrically conductive material and a hard mask 20.

[0033] The layer 16 is a planar layer covering the upper surface of the vertical part of the resistive element 12 and preferably covers the layer 14 completely. Thus, the layer 16 is in contact with the layer 14. The layer 16 is preferably made of a germanium-antimony-tellurium (GST) alloy. The layer 18 is titanium nitride, for example.

[0034] The mask 20 is a layer extending through all the layers 18, preferably. The mask 20 is made of a metal or a metal alloy, such as titanium nitride, for example.

[0035] The mask 20 and the layer 18 are separated by one or more layers of the stack, such as an insulating layer, such as to form an etch mask. In Figure 1In the illustrated example, the mask 20 and the layer 18 are separated by a layer 22 of electrically insulating material, such as silicon nitride; a layer 24 of electrically insulating material, for example amorphous carbon; and a layer 26 of antireflective material for photolithography, for example an electrically insulating material including silicon oxide.

[0036] Figure 2 Another step in one embodiment of a method for manufacturing a phase change memory cell is illustrated.

[0037] During this step, a band 28 is formed on the mask 20. For example, the band 28 corresponds to a photolithographic mask.

[0038] The band 28 covers the location of a memory cell. For example, the band 28 extends in a first direction, for example in the direction of a row of the array of memory cells. For example, the band 28 covers the location of a plurality of cells, such as all cells in a line (i.e. row) of the array. In a direction orthogonal to the row direction, for example corresponding to the direction of a column of the array, the band 28 covers the location of only one memory cell.

[0039] Figure 3 Another step in one embodiment of a method for manufacturing a phase change memory cell is illustrated.

[0040] In this step, the portion of the mask 20 not covered by the band 28 is etched. The etching is preferably a selective etching of the material of the mask 20 with respect to the material of the layer below the mask 20, for example the material of the layer 26. Preferably, the etching method etches the layer material 20 at a speed 20 times faster than it etches the material of the layer 26. Preferably, only the mask 20 is etched in this step. Preferably, the layers 18, 22, 24 and 26 are not etched during this step. The layer 16 is not etched during this step.

[0041] The band 28 is then removed.

[0042] Figure 4 Another step in one embodiment of a method for manufacturing a phase change memory cell is illustrated.

[0043] In this step, a band 30 is formed on the mask 20. For example, the band 30 corresponds to a photolithographic mask.

[0044] The band 30 covers the location of a memory cell. The band 30 extends in a second direction substantially orthogonal to the first direction, for example in the direction of a column of the array of memory cells. The band 30 overlaps the location of a plurality of cells, for example, such as all cells in a column of the array. In a direction orthogonal to the column direction, for example corresponding to the direction of a row of the array, the band 30 covers the location of only one memory cell.

[0045] The band 30 covers the mask portion 20 located at the memory cell location. Preferably, the band 30 covers only the mask portion 20 located at the memory cell location. For example, the band 30 covers a portion of the layer 26.

[0046] Figure 5 The illustration shows another step in one embodiment of a method for manufacturing a phase-change memory cell.

[0047] In this step, the portions of mask 20 not covered by band 30 are etched. Etching is preferably selective etching of the material of mask 20 relative to the layer material below mask 20 (e.g., the material of layer 26). Preferably, only mask 20 is etched in this step. Preferably, layers 18, 22, 24, and 26 are not etched during this step. Layer 16 is not etched during this step.

[0048] Then remove the part with 30.

[0049] As Figure 5 The mask 20 obtained as a result of the steps in the process is preferably a cuboid.

[0050] Figures 2 to 5 The steps in this process make it possible to form a mask 20 that covers the memory cell locations. The mask 20 is therefore oriented towards the memory cell locations, preferably only towards the memory cell locations.

[0051] In a variant, this can be achieved by forming a mask that replaces masks 28 and 30 and only covers the memory cell locations, and then etching mask layer 20. Figures 2 to 5 The steps in the process. Then, the formation of mask 20 involves only a single etching of mask layer 20.

[0052] Figure 6 The illustration shows another step in one embodiment of a method for manufacturing a phase-change memory cell.

[0053] This step includes etching layers 26, 18, and 16 around mask 20, and etching layers separating layer 18 from mask 20, in this case layers 22, 24, and 26. This step may also include etching a portion of layer 14 around the memory cell.

[0054] The stacked layers (i.e., layers 16, 18, 22, 24, and 26) are planar layers extending in a planar manner around the memory cells (e.g., throughout the memory cell array location). Specifically, layer 16 of the phase change material extends continuously between the individual memory cells of the array. Therefore, in the stacking etching step (i.e., Figure 6 During the steps in the process, the material of individual layers is not etched simultaneously. In particular, the material of layer 16 is not etched simultaneously with the materials of other layers in the stack.

[0055] At least some of the layers above layer 18 were also removed. Figure 6 In the example shown, layers 24, 26, and 20 are removed from the memory cell locations.

[0056] Forming a memory cell can be achieved by: performing a first etching on the stack including the phase change material layer 16 to separate the array rows from each other; specifically, depositing one or more electrically insulating layers between the array rows; and performing a second etching on the stack including the phase change material layer 16 to separate the array columns from each other. The layer 16 is then etched together with the electrically insulating material formed at the layers 16 between the rows. Simultaneous etching of the phase change material and another material (especially the electrically insulating material) can alter the phase change material and reduce the efficiency of the memory cell.

[0057] Figure 7 The illustration shows another step in one embodiment of a method for manufacturing a phase-change memory.

[0058] This step includes compliant (i.e., conformal) deposition of the passivation layer 31. Layer 31 is made of an electrically insulating material, such as silicon nitride. The passivation layer 31 covers... Figure 6 The etching process exposes the walls of layers 14, 16, 18, and 22. Passivation layer 31 covers the upper surface of the memory cell, in this case, the upper surface of layer 22.

[0059] This step also includes forming layer 32, which is transparently shown by dashed lines. Layer 32 is made of an electrically insulating material such as silicon oxide.

[0060] Figures 8 to 10 Three different embodiments of the steps for manufacturing the upper contacts or electrodes of the cell are shown.

[0061] Figure 8 Another step is shown in one embodiment of a method for manufacturing a phase-change memory. Specifically, Figure 8 The formation of the conductive via 34 is shown. This step is preferably performed during... Figure 7 Execute after the steps in the instructions.

[0062] This step includes forming a cavity extending from the upper surface of layer 32 to layer 18 and filling the cavity with a conductive material such as a metal. The cavity is etched through layer 32, passivation layer 31, and layer 22 to reach the conductive layer 18. Through-holes 34 of cells in the same row or column of the cell array are connected, for example, by a conductive strip (not shown), which is placed, for example, on the upper surface of layer 32.

[0063] Figure 9 It shows Figure 8 An alternative step. In other words, this step is... Figure 7 It is executed after the step, not after.Figure 8 is performed after the step of Figure 9 Formation of conductive strips 36 connecting cells in the same row or column is shown.

[0064] During this step, cavities are etched in layer 32 and in layers 31 and 22 of the cells connected by strips 36. The cavities thus extend from the upper surface of layer 32 to layer 18. Thus, the cavities extend through layers 22 and 31 in the memory cells. Between the memory cells, the cavities extend into layer 31. The cavities are then filled with a conductive material such as metal.

[0065] Figure 10 An alternative to the steps in Figure 8 and 9 is shown. Namely, after the step of Figure 7 , this step is performed instead of the step of Figure 8 or 9. In particular, Figure 10 Formation of conductive strips 38 connecting cells in the same row or column of the memory array is shown.

[0066] In this step, layers 32, 31, layer 22 are etched in a planar manner until the upper surface of layer 18 is exposed. A planar layer of a conductive material such as metal is then formed on the structure obtained after etching. This layer thus covers the upper surface of layer 18 as well as the upper surfaces of layers 31 and 32 around the memory cells. The conductive layer is then etched, leaving strips extending along the first direction on layer 18 of the plurality of cells. For example, in the second direction, strips 38 extend across the entire layer 18 and partially across the upper surface of layer 31.

[0067] An embodiment for manufacturing a single memory cell is described. The method can be used to simultaneously manufacture a plurality of cells, such as an array of memory cells. The method then comprises forming a mask 20 covering each memory cell location and simultaneously etching the stack around the memory cell locations, i.e. etching the stack in the parts not covered by the mask 20.

[0068] One advantage of the described embodiments is that the layer of phase change material is not etched at the same time as another material.

[0069] Another advantage of the described embodiments is that the described method comprises an etching step and a layer deposition step with respect to known methods.

[0070] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these embodiments can be combined and that other variants will readily suggest themselves to the person skilled in the art.

[0071] Finally, actual implementation of the embodiments and variants described herein is within the capabilities of the person skilled in the art, based on the functional description provided above.

Claims

1. A method for manufacturing a memory cell, comprising: (a) Forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material; (b) A first mask is formed on the stack, the first mask covering only the location of the memory cells; as well as (c) Etching the stacked portion not covered by the first mask; Step b) includes: A fourth layer made of the same material as the first mask is deposited on the stack; A second mask is formed, which extends in the first direction and covers the location of the memory cell; Etch the portion of the fourth layer that is not covered by the second mask; A third mask is formed, extending in the second direction and covering the location of the memory cell; and Etch the portion of the fourth layer that is not covered by the third mask.

2. The method according to claim 1, wherein step a) comprises: At least a third layer made of an electrically insulating material is formed between the second layer and the first mask.

3. The method of claim 1, wherein the etching in step c) does not simultaneously etch the phase change material of the first layer and the material of another layer in the stack.

4. The method according to claim 1, further comprising: A resistive element is formed in contact with the first layer.

5. The method of claim 1, wherein etching a portion of the fourth layer comprises: The material of the fourth layer is etched at a rate at least twenty times faster than the material of the layer below the fourth layer.

6. The method of claim 1, wherein the first mask is made of titanium nitride.

7. The method of claim 1, wherein the first layer is made of an alloy of germanium, antimony and tellurium.

8. The method of claim 1, wherein the memory cell is one of the memory cells in an array of memory cells.

9. The method of claim 8, wherein the first mask is formed over the location of each memory cell in the array, and wherein step c) is performed simultaneously for all memory cells.

10. The method of claim 8, further comprising: At least one electrically insulating layer is deposited on the memory cell of the array.

11. The method of claim 8, further comprising: Conductive vias are deposited through the electrically insulating layer to reach the second layer.

12. The method according to claim 8, further comprising: Conductive strips extending above the second layer of memory cells formed in rows or columns of the array.

13. A method for manufacturing a memory array, the memory array comprising a plurality of memory cells arranged in columns and rows, the method comprising: (a) Forming a stack comprising multiple layers in the following order: a first layer made of a phase change material; A second layer made of conductive material; Electrical insulation layer; And a fourth layer made of photolithography material; (b) A first strip is formed on the fourth layer, the first strip covering the memory cell locations along each row; (c) Using the first layer, the fourth layer is photolithographically patterned to form a first mask covering the memory cell locations along each row; (d) A second strip is formed on the first mask, the second strip covering the memory cell locations along each column; (e) Using the second tape, the first mask is photolithographically patterned to form a second mask, the second mask individually covering each memory cell location along the column and the row; (f) Etching the portion of the stack not covered by the second mask to define individual memory cells.

14. The method of claim 13, wherein the electrical insulating layer comprises: A first insulating layer made of a first electrical insulating material; And a second insulating layer made of a second electrical insulating material.

15. The method of claim 14, wherein the first electrical insulating material is silicon nitride and the second electrical insulating material is amorphous carbon.

16. The method of claim 13, wherein the photolithography material is an anti-reflective material for photolithography.

17. The method of claim 16, wherein the antireflective material used for photolithography is titanium nitride.

18. The method of claim 13, wherein the first layer is made of an alloy of germanium, antimony, and tellurium, and the second layer is made of titanium nitride.

19. The method of claim 13, further comprising: At least one electrically insulating layer is deposited on the individual memory cell.

20. The method of claim 19, further comprising: Conductive vias are deposited through the electrical insulating layer to reach the second layer for each individual memory cell.

21. The method of claim 19, further comprising: A conductive strip is formed, the conductive strip extending to make partial contact with the second layer in the individual memory cell in the row or column of the array.

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