A method of forming a fin structure of a device

Abstract

The application discloses a method for forming a fin structure of a device, comprising: obtaining a substrate formed with a first fin, a shallow trench isolation and a well region; performing first low-temperature oxidation on the surface of the first fin to conformally form a first oxide layer on the surface of the first fin; performing in-situ removal on the first oxide layer to conformally form an intrinsic layer on the surface of the first fin; performing second low-temperature oxidation on the intrinsic layer to conformally form a second oxide layer on the surface of the intrinsic layer; forming a first gate oxide layer on the second oxide layer by using a low-temperature deposition process; and performing hardening and low-temperature annealing treatment on the first gate oxide layer and the second oxide layer to form a dense second gate oxide layer composed of the first gate oxide layer and the second oxide layer below the first gate oxide layer, and a size-repaired second fin composed of the intrinsic layer and the first fin inside the intrinsic layer. The application can repair the fin size and damaged lattice, and form a densified gate oxide layer, thereby improving the device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a method for forming a fin structure of a device. Background Technology

[0002] As the size of FinFET devices continues to shrink, the critical dimensions of the fins are also gradually decreasing. However, multiple steps in the fin fabrication process, such as shallow trench isolation annealing and gate oxide formation, consume fins, resulting in the loss of critical dimensions.

[0003] Furthermore, the crystal structure of the fin surface can be damaged during the fin fabrication process. Specifically, ion implantation in the trap region damages the fin's crystal structure and leaves residual impurity ions on the fin; processes with some oxidation, such as shallow trench isolation annealing, allow oxygen to diffuse to the fin surface. This surface lattice damage increases the density of interface traps at the fin-gate oxide interface, reducing device performance and increasing flicker noise.

[0004] In addition, traditional gate oxide generation methods, such as in-situ water vapor oxidation and high-temperature steps such as nitriding followed by annealing, may cause ion diffusion problems in N-wells and P-wells, thereby reducing device performance.

[0005] Given the existing critical dimension loss and lattice damage on the fin surface, as well as the high-temperature thermal budget problem, it is necessary to propose a new method for low-temperature thermal budget gate oxide formation that can repair the lattice surface of the fin and reduce the critical dimension loss of the fin. Summary of the Invention

[0006] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide a method for forming the fin structure of a device.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] A method for forming a fin structure of a device, comprising:

[0009] Obtain a substrate having a first fin, shallow trench isolation, and a well region formed thereon;

[0010] The surface of the first fin is subjected to a first low-temperature oxidation to form a first oxide layer on the surface of the first fin in a shape-preserving manner;

[0011] The first oxide layer is removed in situ, and then an intrinsic layer of the first fin material is formed on the exposed surface of the first fin in a conformal manner.

[0012] The intrinsic layer is subjected to a second low-temperature oxidation to form a second oxide layer on the surface of the intrinsic layer in a conformal manner;

[0013] A first gate oxide layer is formed on the second oxide layer using a low-temperature deposition process;

[0014] The first gate oxide layer and the second oxide layer are subjected to hardening and low-temperature annealing.

[0015] Furthermore, the first low-temperature oxidation and the second low-temperature oxidation method include a low-temperature oxidation method using oxygen plasma as an oxidant.

[0016] Furthermore, the in-situ removal method includes a chemical oxide removal method.

[0017] Furthermore, the process of forming an intrinsic layer of the first fin material on the exposed surface of the first fin specifically includes:

[0018] Atomic layer deposition process is used to first form a single crystal nucleus layer of the first fin material on the surface of the first fin in a shape-preserving manner.

[0019] Then, a single-crystal intrinsic layer of the first fin material is formed along the surface of the single-crystal nucleation layer in a conformal manner.

[0020] Furthermore, the low-temperature deposition process includes atomic layer deposition.

[0021] Furthermore, the hardening process specifically includes:

[0022] First, the first gate oxide layer and the second oxide layer are subjected to ozone permeation treatment.

[0023] Then, the first gate oxide layer and the second oxide layer are subjected to ultraviolet light irradiation treatment.

[0024] Furthermore, the temperature of the permeation treatment is below 100°C.

[0025] Furthermore, the low-temperature annealing process includes rapid thermal annealing.

[0026] Furthermore, the rapid thermal annealing time is less than 1 millisecond.

[0027] Furthermore, the low temperature is below 400°C.

[0028] As can be seen from the above technical solution, this invention transforms the damaged lattice surface of the first fin (original fin) into an oxide layer by performing a low-temperature oxidation treatment on the surface of the first fin. After in-situ removal, an intrinsic layer of the first fin material is formed on the remaining surface of the first fin in a conformal manner, thereby repairing the fin size and damaged lattice. By performing a low-temperature oxidation treatment on the intrinsic layer, the oxide layer formed on the surface of the intrinsic layer acts as a barrier layer, preventing oxygen consumption of the fin during subsequent gate oxide processes. Through hardening and low-temperature annealing, a dense gate oxide layer can be formed. This invention uses a low-temperature gate oxide formation process below 400℃, which greatly reduces the ion diffusion problems of N-wells and P-wells caused by previous high-temperature thermal budgets. It can repair the lattice damage on the fin surface while ensuring the size of the fin and the quality of the gate oxide film, thereby improving device performance. Attached Figure Description

[0029] Figure 1 This is a flowchart of a method for forming a fin structure of a device according to a preferred embodiment of the present invention;

[0030] Figures 2-8 According to a preferred embodiment of the present invention Figure 1 A schematic diagram of the process steps for fabricating the fin structure of a device using this method. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0032] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0033] Please see Figure 1 , Figure 1 This is a flowchart illustrating a method for forming a fin structure of a device according to a preferred embodiment of the present invention. Figure 1 As shown, a method for forming a fin structure in a device according to the present invention may include the following steps:

[0034] Step S1: Obtain a substrate with a first fin, shallow trench isolation and a well region formed thereon.

[0035] Please see Figure 2 A substrate 100 having a partial structure of a FinFET device can be obtained, for example, a silicon substrate 100 having a first fin 101, a shallow trench isolation 102 and a well region formed using conventional processes.

[0036] In conventional processes, the edge of the first fin 101 will develop a lattice damage region 1011 after the trap implantation process. The following method of the present invention can be used to improve this problem.

[0037] Step S2: Perform a first low-temperature oxidation on the surface of the first fin to form a first oxide layer on the surface of the first fin in a shape-preserving manner.

[0038] Please see Figure 3 In a preferred embodiment, when performing a first low-temperature oxidation on the surface of the first fin 101, a low-temperature oxidation method using oxygen plasma as an oxidant can be used to form a first oxide layer 103 on the surface of the first fin 101 in a conformal manner.

[0039] For example, an oxygen plasma atomic layer deposition process can be used, with oxygen plasma replacing the reaction precursor, so that the oxygen plasma comes into contact with the surface of the first fin 101 and acts as an oxidant to oxidize the silicon material on the surface of the first fin 101. Thus, by utilizing the characteristics of the atomic layer deposition process, a first silicon dioxide oxide layer 103 can be formed on the surface of the first fin 101 in a conformal manner.

[0040] In the above atomic layer deposition process, inert gases such as helium or argon can be used as carrier gases, but conventional precursors are not used. Instead, oxygen plasma is used as an oxidant to oxidize the silicon material on the surface of the first fin 101.

[0041] A first oxide layer 103 of silicon dioxide with a thickness of less than 2 nm can be formed on the surface of the first fin 101 by controlling the atomic layer deposition process conditions.

[0042] By forming a first oxide layer 103 of a certain thickness on the surface of the first fin 101, the silicon in the lattice damage region 1011 present on the surface of the first fin 101 can be converted into oxide, so that it can be removed in the future.

[0043] In a preferred embodiment, the low-temperature oxidation process during atomic layer deposition in this step can be below 400°C. For example, the low-temperature oxidation process in this step can be between 100°C and 400°C.

[0044] Step S3: Remove the first oxide layer in situ, and then form an intrinsic layer of the first fin material on the exposed surface of the first fin in a conformal manner.

[0045] Please see Figure 4 In a preferred embodiment, the in-situ removal method may include a chemical oxide removal method. For example, a reaction method containing HF or NH3 capable of removing oxides, such as the chemical gas etching system method of Certas or the COR (chemical OX remove) chemical oxide removal treatment system method, may be used to remove the first oxide layer 103 in situ, thereby maintaining the shape of the first fin 101 after the removal of the first oxide layer 103.

[0046] After removing the first oxide layer 103, the impurities on the surface of the first fin 101 are removed by oxidation, so that the remaining first fin 101 has a new surface with a complete crystal lattice, thereby achieving good repair.

[0047] Please see Figure 5 Next, a monocrystalline silicon layer needs to be formed on the surface of the first fin 101 after the first oxide layer 103 has been removed, in order to repair the reduced size of the first fin 101.

[0048] In a preferred embodiment, when the first fin 101 is dimensionally repaired, an atomic layer deposition process can be used to first form a single crystal silicon nucleation layer 104 on the surface of the first fin 101 in a conformal manner, which is consistent with the silicon material of the first fin 101; then, a single crystal silicon intrinsic layer (main layer) 105 is formed along the surface of the single crystal silicon nucleation layer 104 in a conformal manner.

[0049] For example, atomic layer deposition (ALD) can be used, with diisopropylaminosilane (trade name LTO 520) as a precursor, to form a conformally oriented hot silicon nucleation layer 104 of monocrystalline silicon on the silicon surface of the first fin 101. Then, DS (diisopropylaminosilane) is used as a precursor to cause DS to decompose along the surface of the monocrystalline silicon nucleation layer 104, thereby further forming a conformally oriented intrinsic monocrystalline silicon layer 105 on the surface of the already formed monocrystalline silicon nucleation layer 104.

[0050] The monocrystalline silicon thermal nucleation layer 104 and the monocrystalline silicon intrinsic layer 105 form a monocrystalline silicon pad layer 106 with a good step coverage morphology on the first fin 101. Furthermore, the newly grown monocrystalline silicon pad layer 106 on the first fin 101 has a defect-free complete lattice.

[0051] In a preferred embodiment, the process temperature of the atomic layer deposition process in this step can be below 400°C. For example, the process temperature in this step can be 300-400°C; more preferably, the process temperature in this step can be 380°C.

[0052] In a preferred embodiment, the thickness of the monocrystalline silicon thermal nucleation layer 104 formed in this step may be less than 2 nm.

[0053] Furthermore, the thickness of the monocrystalline silicon pad layer 106 formed in this step can be less than 4 nm.

[0054] In this step, a single-crystal silicon pad layer 106 of a certain thickness is formed on the surface of the first fin 101 after the first oxide layer 103 is removed, thereby achieving good repair of the fin size and damaged lattice.

[0055] Step S4: Perform a second low-temperature oxidation on the intrinsic layer to form a second oxide layer on the surface of the intrinsic layer in a conformal manner.

[0056] Please see Figure 6 In a preferred embodiment, when performing a second low-temperature oxidation on the surface of the monocrystalline silicon intrinsic layer 105, a low-temperature oxidation method using oxygen plasma as an oxidant can be used to form a second oxide layer 108 on the surface of the monocrystalline silicon intrinsic layer 105 in a conformal manner.

[0057] For example, an oxygen plasma atomic layer deposition process can be used, with oxygen plasma replacing the reaction precursor, so that the oxygen plasma comes into contact with the surface of the monocrystalline silicon intrinsic layer 105 and acts as an oxidant to oxidize the silicon material on the surface of the monocrystalline silicon intrinsic layer 105. Thus, by utilizing the characteristics of the atomic layer deposition process, a second silicon dioxide oxide layer 108 can be formed on the surface of the monocrystalline silicon intrinsic layer 105 in a conformal manner.

[0058] In this atomic layer deposition process, inert gases such as helium or argon can be used as carrier gases, but conventional precursors are not used. Instead, oxygen plasma is used as the oxidant to oxidize the silicon material on the surface of the intrinsic layer 105 of the single crystal silicon.

[0059] A second silicon dioxide layer 108 with a thickness of less than 2 nm can be formed on the surface of the intrinsic silicon layer 105 (single-crystal silicon pad layer 106) by controlling the atomic layer deposition process conditions.

[0060] In a preferred embodiment, the low-temperature oxidation process during atomic layer deposition in this step can be below 400°C. For example, the low-temperature oxidation process in this step can be between 100°C and 400°C.

[0061] By forming a second oxide layer 108 of a certain thickness on the surface of the intrinsic single-crystal silicon layer 105, the formed second oxide layer 108 can be used as a barrier layer to prevent oxygen from consuming the fins in the subsequent gate oxide deposition process.

[0062] Meanwhile, the radio frequency power during the atomic layer deposition process can be used to reduce hydrogen bonds in the monocrystalline silicon pad layer 106 and densify the monocrystalline silicon pad layer 106.

[0063] Step S5: A first gate oxide layer is formed on the second oxide layer using a low-temperature deposition process.

[0064] Please see Figure 7 In a preferred embodiment, the cryogenic deposition process may include an atomic layer deposition process.

[0065] For example, a high-quality first gate oxide layer 109 of silicon dioxide with a thickness of 1 to 4 nm can be epitaxially grown on the second oxide layer 108 of silicon dioxide using a conventional atomic layer deposition process.

[0066] At this time, since the fin is covered with a second oxide layer 108, a barrier layer is formed, which can prevent the oxygen in the atomic layer deposition gate oxide process from consuming the fin.

[0067] Step S6: Harden and anneal the first gate oxide layer and the second oxide layer at low temperature.

[0068] Please see Figure 8 In a preferred embodiment, when hardening the first gate oxide layer 109 and the second oxide layer 108, the first gate oxide layer 109 and the second oxide layer 108 can first be subjected to ozone permeation treatment; then, the first gate oxide layer 109 and the second oxide layer 108 can be subjected to ultraviolet light irradiation treatment.

[0069] For example, the device with the above structure can be placed in a sealed cavity and ozone can be introduced to place the first gate oxide layer 109 and the second oxide layer 108 in an ozone atmosphere, so as to use ozone to permeate the first gate oxide layer 109 and the second oxide layer 108 and replace the hydrogen in the first gate oxide layer 109 and the second oxide layer 108 with oxygen.

[0070] In a preferred embodiment, the temperature of the permeation treatment may be below 100°C.

[0071] Then, the first gate oxide layer 109 and the second oxide layer 108 are further subjected to ultraviolet light irradiation treatment. The irradiation energy of ultraviolet light can promote the breaking of excess hydrogen bonds in the first gate oxide layer 109 and the second oxide layer 108 and replace them with oxygen, thereby generating a denser second gate oxide layer 110 that can be highly close to the gate oxide quality formed by high temperature oxidation or ISSG process.

[0072] A dense second gate oxide layer 110 is formed by the first gate oxide layer 109 and the second oxide layer 108 located below it.

[0073] In a preferred embodiment, the low-temperature annealing process may include a rapid thermal annealing process.

[0074] Furthermore, the processing temperature for rapid thermal annealing can be below 400°C, and the processing time can be within 1 millisecond.

[0075] The above-mentioned low-temperature rapid thermal annealing treatment can further densify the second gate oxide layer 110 film.

[0076] Since the quality of the second gate oxide layer 110 formed by the present invention is very close to that of the gate oxide formed by high-temperature oxidation or ISSG process, high-temperature steps such as DPN (decoupled plasma nitriding) and PNA can be omitted.

[0077] Meanwhile, through the above method, a second fin 107 with repaired dimensions is also formed, which is composed of a monocrystalline silicon intrinsic layer 105, a monocrystalline silicon nucleation layer 104 and a first fin 101 therein.

[0078] In summary, this invention repairs the fin size and damaged lattice by performing a low-temperature oxidation treatment on the surface of the first fin 101 (original fin). This transforms the damaged lattice surface of the first fin 101 into an oxide layer. After in-situ removal, an intrinsic layer 105 of the first fin material is formed on the remaining surface of the first fin 101 in a conformal manner. The low-temperature oxidation treatment of the intrinsic layer 105 utilizes the resulting oxide layer as a barrier layer to prevent oxygen consumption of the fin during subsequent gate oxide processes. Hardening and low-temperature annealing processes form a dense gate oxide layer (second gate oxide layer 110). This invention employs a low-temperature gate oxide formation process below 400°C, significantly reducing the ion diffusion problems of N-wells and P-wells caused by previous high-temperature thermal budgets. It can repair lattice damage on the fin surface while ensuring the fin size and the quality of the gate oxide film, thereby improving device performance.

[0079] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A method of forming a fin structure of a device, characterized by, The method comprises the following steps: obtaining a substrate formed with a first fin, a shallow trench isolation and a well region; performing first low-temperature oxidation on the surface of the first fin to conformally form a first oxide layer on the surface of the first fin, wherein the processing temperature of the first low-temperature oxidation is below 400℃; performing in-situ removal on the first oxide layer, and then conformally forming an intrinsic layer of the first fin material on the exposed surface of the first fin, wherein the process temperature for forming the intrinsic layer is below 400℃; performing second low-temperature oxidation on the intrinsic layer to conformally form a second oxide layer on the surface of the intrinsic layer, wherein the processing temperature of the second low-temperature oxidation is below 400℃; forming a first gate oxide layer on the second oxide layer by using a low-temperature deposition process; performing hardening and low-temperature annealing treatment on the first gate oxide layer and the second oxide layer, wherein the temperature of the low-temperature annealing treatment is below 400℃.

2. The method according to claim 1, wherein The first low-temperature oxidation and the second low-temperature oxidation method comprise a low-temperature oxidation method using oxygen plasma as an oxidant.

3. The method according to claim 1, wherein The in-situ removal method comprises a chemical oxide removal method.

4. The method according to claim 1, wherein The method of conformally forming the intrinsic layer of the first fin material on the exposed surface of the first fin specifically comprises the following steps: first, conformally forming a single-crystal nucleation layer of the first fin material on the surface of the first fin by using an atomic layer deposition process; then, conformally forming a single-crystal intrinsic layer of the first fin material on the surface of the single-crystal nucleation layer.

5. The method according to claim 1, wherein The low-temperature deposition process comprises an atomic layer deposition process.

6. The method according to claim 1, wherein The hardening treatment specifically comprises the following steps: first, making the first gate oxide layer and the second oxide layer permeate in ozone; then, performing ultraviolet irradiation treatment on the first gate oxide layer and the second oxide layer.

7. The method according to claim 6, wherein The temperature of the permeation treatment is below 100℃.

8. The method according to claim 1, wherein The low-temperature annealing treatment comprises a rapid thermal annealing treatment.

9. The method according to claim 8, wherein The time of the rapid thermal annealing is within 1 millisecond.

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