TECHNOLOGIES FOR A HIGH GRADIENT OF DOP CONCENTRATION IN GATE ALL-AROUND TRANSISTORS

Abstract

Technologies for achieving a high gradient of dopant concentration in gate all-around transistors are disclosed. In an illustrative embodiment, a source / drain region of a gate all-around transistor can have a relatively high dopant concentration, for example, a concentration greater than 10²⁰ cm⁻³, and an adjacent channel region can have a relatively low dopant concentration, for example, a concentration less than 10¹⁸ cm⁻³. At an interface between the source / drain region and the channel region, the logarithmic slope of the dopant concentration can be high, for example, two orders of magnitude in less than one nanometer. To maintain such a high dopant concentration, the source / drain region with the high dopant concentration is deposited after completion of the high-temperature processing steps using a low-temperature deposition technique.

Description

BACKGROUND Transistors are ubiquitous devices found in virtually all electronic devices. With the ever-increasing density of transistors, new architectures, such as fin field-effect transistors (FETs) and gate-all-around (GAA) FETs, are used to reduce the footprint of a transistor. A GAA FET can contain multiple nanoribbons or nanowires stacked vertically. The channel region may have a different dopant concentration than the source and drain region, with a high dopant concentration in the source and drain region and a lower dopant concentration in the channel region. In some cases, fabrication steps can cause dopant migration, which can reduce the device's performance. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an isometric view of a gate all-around field-effect transistor. Fig. 2 is a cross-sectional side view of an embodiment of the transistor from Fig. 1. Fig. 3 is a cross-sectional side view of an embodiment of the transistor from Fig. 1. Fig. 4 is a cross-sectional side view of an embodiment of the transistor from Fig. 1. Fig. 5 is a simplified flowchart of at least one embodiment of a method for fabricating the transistor from Fig. 1. Fig. 6 is a cross-sectional side view at one step of the flowchart from Fig. 5. Fig. 7 is a cross-sectional side view at one step of the flowchart from Fig. 5. Fig. 8 is a cross-sectional side view at one step of the flowchart from Fig. 5. Fig. 9 is a cross-sectional side view at one step of the flowchart from Fig. 5. Fig. 10 is a cross-sectional side view at one step of the flowchart from Fig. 5.Figure 11 is a cross-sectional side view at a step of the flowchart from Figure 5. Figure 12 is a cross-sectional side view at a step of the flowchart from Figure 5. Figure 13 is a cross-sectional side view at a step of a flowchart of at least one embodiment of a method for manufacturing a gate all-around transistor. Figure 14 is a simplified flowchart of at least one embodiment of a method for manufacturing a gate all-around transistor. Figure 15 is a cross-sectional side view at a step of the flowchart from Figure 14. Figure 16 is a cross-sectional side view at a step of the flowchart from Figure 14. Figure 17 is a cross-sectional side view at a step of the flowchart from Figure 14. Figure 18 is a cross-sectional side view at a step of the flowchart from Figure 14. Fig. 19 is a cross-sectional side view at one step of the flowchart from Fig. 14.Figure 20 is a simplified flowchart of at least one embodiment of a method for fabricating a gate all-around transistor. Figure 21 is a cross-sectional side view at one step of the flowchart from Figure 20. Figure 22 is a cross-sectional side view at one step of the flowchart from Figure 20. Figure 23 is a simplified flowchart of at least one embodiment of a method for fabricating a gate all-around transistor. Figure 24 is a cross-sectional side view at one step of the flowchart from Figure 23. Figure 25 is a cross-sectional side view at one step of the flowchart from Figure 23. Figure 26 is a diagram showing the dopant concentration as a function of position for one embodiment of a gate all-around transistor. Figure 27 is a top view of a wafer and dies that may be included in a microelectronic assembly according to one of the embodiments disclosed herein.Figure 28 is a cross-sectional side view of an integrated circuit device that may be included in any of the microelectronic assemblies disclosed herein. Figures 29A-29D are perspective views of exemplary planar, FinFET, gate-all-around, and stacked gate-all-around transistors. Figure 30 is a cross-sectional side view of an integrated circuit device assembly that may contain a microelectronic assembly according to any of the embodiments disclosed herein. Figure 31 is a block diagram of an exemplary electrical device that may contain a microelectronic assembly according to any of the embodiments disclosed herein. DETAILED DESCRIPTION In an embodiment disclosed herein, as described in more detail below, a source / drain region of a gate-all-around (GAA) field-effect transistor (FET) has a relatively high dopant concentration, for example, more than 10²¹ cm⁻³, and a channel region of the GAA FET has a relatively low dopant concentration, for example, less than 10¹⁹ cm⁻³. The dopant concentration increases over a relatively short distance, for example, by two orders of magnitude in less than one nanometer. As used here, an order of magnitude refers to a factor of ten, so that an increase of two orders of magnitude in less than one nanometer corresponds to an increase by a factor of 100 in less than one nanometer, for example, an increase from less than 10¹⁹ cm⁻³ to more than 10²¹ cm⁻³ in less than one nanometer. A high doping concentration in the source / drain regions can reduce the resistivity of the semiconductor material. However, at high temperatures, such as those encountered during certain steps in the fabrication of a GAA-FET wafer, the dopants can diffuse into adjacent materials, for example, into the transistor's channel region. Diffusion of dopants into the channel region can reduce electron mobility through charge carrier scattering and also create leakage current paths with low resistivity under the gate of the GAA-FET. In an illustrative embodiment, and as described in more detail below, a high gradient concentration can be achieved by creating a trench for the source / drain regions and filling the trench with sacrificial material. After completion of the processing steps requiring high temperatures, the sacrificial material can be removed, and source / drain regions with high dopant concentrations can be deposited at low temperatures using the techniques described below. Deposition of the dopant concentrations at low temperatures, after completion of the high-temperature processing steps, allows for a high logarithmic slope of the dopant concentration, thereby achieving a high dopant concentration in the source and drain regions and a low dopant concentration in the channel region. The following description details specific aspects, but embodiments of the technologies described herein can be implemented without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid complicating the understanding of the present description. Expressions such as "one embodiment," "different embodiments," "some embodiments," and the like may include features, structures, or properties, but not every embodiment necessarily includes the specific features, structures, or properties. Some embodiments may have some, all, or none of the features described for other embodiments. "First," "second," "third," and the like describe a common object and indicate different instances of similar objects being referred to. Such adjectives do not imply that objects so described must exist in any given sequence, whether temporally or spatially, in any order of precedence, or in any other way. “Connected” can indicate that elements are in direct physical or electrical contact with one another, and “coupled” can indicate that elements cooperate or interact with one another, although they may or may not be in direct physical or electrical contact with one another. Furthermore, the terms “comprise,” “contain,” “exhibit,” and the like, as used with reference to embodiments of the present disclosure, are synonymous. As used here, the phrase "is on" in the context of a first layer or component located on top of a second layer or component indicates that the first layer or component is directly physically attached to the second part or component (no layers or components between the first and second layers or components) or physically attached to the second layer or component with one or more intervening layers or components. As used here, the term "adjacent" refers to layers or components that are in physical contact with each other. That is, there is no layer or component between the specified adjacent layers or components. For example, a layer X adjacent to a layer Y refers to a layer that is in physical contact with layer Y.As used here, the term "electrically coupled" refers to the presence of one or more electrically conductive paths between components that are specified as electrically coupled. Certain terminology may be used here for reference purposes only and should therefore not be considered restrictive. For example, terms such as "upper," "lower," "above," "below," "below," and "above" refer to directions in the referenced figures. Terms such as "front," "back," and "side" describe the orientation and / or location of layers, components, parts of components, etc., within a consistent but arbitrary frame of reference, which is clarified by referring to the text and the associated figures that describe the layers, components, parts of components, etc., discussed here. Such terminology may include the words explicitly mentioned above, derivatives thereof, and words of similar meaning. As used herein, the term "integrated circuit component" refers to an encapsulated or non-encapsulated integrated circuit product. An encapsulated integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate, with the integrated circuit dies and the package substrate being encapsulated in an encapsulation material, such as metal, plastic, glass, or ceramic. In an example, an encapsulated integrated circuit component contains one or more processor units mounted on a substrate, with one outer surface of the substrate comprising a solder ball grid array (BGA). In an example of a non-encapsulated integrated circuit component, a single monolithic integrated circuit die comprises solder contact mounds attached to contacts on the die.The solder pads allow the die to be attached directly to a printed circuit board. An integrated circuit component can include one or more computing system components as described or referenced herein, or any other computing system component such as a processor unit (e.g., a system-on-a-chip (SoC), a processor core, a graphics processing unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller. As used herein, the term “electronic component” can refer to an active electronic component (for example, a processing unit, a working memory, a storage device, a transistor) or a passive electronic component (for example, a resistor, an inductor, a capacitor). As used herein, the terms “working”, “executing”, or “running”, relating to software or firmware in respect of a system, device, platform, or resource, are used interchangeably and may refer to software or firmware stored on one or more computer-readable storage media which the system, device, platform, or resource can access, even if the software or firmware instructions are not actively executed by the system, device, platform, or resource. Reference is now made to the drawings, which are not necessarily drawn to scale and may use similar or identical reference numerals to denote the same or similar parts in different illustrations. The use of similar or identical reference numerals in different illustrations does not imply that all illustrations containing similar or identical reference numerals represent a single or identical embodiment. Identical reference numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example but not as a limitation, various embodiments discussed in this document. The following description presents numerous specific details for illustrative purposes, in order to provide a thorough understanding. However, it may be obvious that the novel embodiments can be implemented without these specific details. In other cases, well-known structures and devices are shown in block diagram form to facilitate their description. It is intended to cover all modifications, equivalents, and alternatives within the scope of the claims. As used in this application and in the claims, a list of elements joined by the term "and / or" can mean any combination of the listed elements. For example, the expression "A, B and / or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. As used in this application and in the claims, a list of elements joined by the term "at least one of" can mean any combination of the listed terms. For example, the expression "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. Furthermore, as used in this application and in the claims, a list of elements joined by the term "one or more of" can mean any combination of the listed terms.For example, the phrase “one or more of A, B and / or C” can mean A; B; C; A and B; A and C; B and C or A, B and C. As used in this application and the claims, the phrase “a single one of” or “a respective one of”, followed by a list of elements that have been named or specified as having a property, feature, etc., means that all elements in the list have the specified or named property, feature, etc. For example, the phrase “single ones of A, B or C contain a side wall” or “respective ones of A, B or C contain a side wall” means that A contains a side wall, B contains a side wall and C contains a side wall. The disclosed methods, devices, and systems are not to be understood as being limiting in any way. Instead, the present disclosure relates to all new and non-obvious features and aspects of the various disclosed embodiments, both individually and in various combinations and sub-combinations. The disclosed methods, devices, and systems are neither limited to any particular aspect or feature, nor do the disclosed embodiments require that any particular advantages or problems be solved. Operations theories, scientific principles, or other theoretical descriptions presented herein with reference to the devices or procedures of this disclosure are provided for convenience only and are not intended to limit the scope. The devices and procedures in the appended claims are not limited to those devices and procedures that function in the manner described by such operations theories. Even though the operations of some of the disclosed methods are described in a particular sequential order for the sake of convenience, it is understood that this type of description involves rearranging them unless a specific order is necessary according to the special statements set forth herein. For example, sequentially described operations may, in some cases, be rearranged or performed concurrently. Furthermore, for the sake of simplicity, the accompanying figures may not show the various ways in which the disclosed methods can be used in conjunction with other methods. Referring to Figures 1-4, Figure 1 shows a perspective view of a GAA-FET 100 in one embodiment, Figure 2 shows a cross-sectional view of the GAA-FET 100 derived from the view labeled 2 in Figure 1, Figure 3 shows a cross-sectional view of the GAA-FET 100 derived from the view labeled 3 in Figure 1, and Figure 4 shows a cross-sectional view of the GAA-FET 100 derived from the view labeled 4 in Figure 1. In some embodiments, the GAA-FET 100 can also be referred to as a ribbon FET transistor, a nanoribbon transistor, a nanowire transistor, a nanosheet transistor, etc. The GAA-FET 100 is supported by a substrate 102. The GAA-FET 100 has one or more semiconductor nanobands 104A, 104B, and 104C. The semiconductor nanobands 104A-C contain channel regions 202A, 202B, and 202C (see Figs. 2 and 3). Source-drain regions 204 are located on both sides of the channel regions 202A-C. Dielectric spacers 108 are located between the source / drain regions 204 and the region containing the channel regions 202A-C, the gate 114, and the gate dielectric layer 112. A gate dielectric layer 112 surrounds the channel regions 202A-C within the region bounded by the dielectric spacers 108 and the dielectric insulating layers 110. The gate 114 surrounds the gate dielectric layer 112 and the channel regions 202A-C. A conductive material 120 is located on the gate 114. The dielectric insulating layers 110 surround the channel regions 202A-C and other structures of the GAA-FET 100.A Contact 106 is located on top of each Source / Drain area 204. As described in more detail below, the source / drain regions 204 are formed separately from the remainder of the nanobands 104A-C and from the channel regions 202A-C. In an illustrative embodiment, the source / drain regions 204 have a relatively high dopant concentration, for example, more than 10²¹ per cubic centimeter (cm⁻³), and the channel regions 202A-C and / or the remainder of the nanobands 104A-C have a relatively low dopant concentration, for example, less than 10¹⁹ cm⁻³. The dopant concentration increases over a relatively short distance, for example, by two orders of magnitude in less than one nanometer, at an interface between the source / drain regions 204 and the channel regions 202A-C.The high dopant concentration in the source / drain regions 204 ensures a low resistivity, and the low dopant concentration in the channel regions 202A-C, due to reduced charge carrier scattering, results in high electron mobility and also reduces the formation of leakage current paths with low resistivity under the gate 114 of the GAA-FET 100. In some cases, the interface between the source / drain regions 204 and a channel region 202A-C can be considered a separate region with a dopant concentration gradient. In other cases, the region with a dopant concentration gradient can be considered part of the source / drain regions 204 and / or the channel regions 202A-C. Substrate 102 supports the rest of the GAA-FET 100. In the illustrative embodiment, substrate 102 is made of silicon. In other embodiments, substrate 102 can be made of, for example, silicon oxide, gallium nitride, perovskite, strontium titanium oxide, etc. The GAA-FET 100 can be an n-MOS transistor or a p-MOS transistor. The semiconductor nanobands 104A-C can be made of any suitable material or combination of materials, such as undoped or lightly doped semiconductor. In the illustrative embodiment, the channel regions 202A-C and the nanobands 104A-C are undoped or lightly doped silicon, such as silicon with a dopant concentration of less than, for example, 10¹⁵–10¹⁹ cm⁻³. The channel regions 202A-C can refer to regions of the nanobands 104A-C surrounded by the gate dielectric layer 112 and the gate 114, as well as to regions of the nanobands 104A-C extending further into regions of dielectric insulating layers 110 separated by the dielectric spacers 108 and the dielectric insulating layers 110.In an illustrative embodiment, the channel region 202A-C refers to the region of the nanobands 104A-C between the source / drain regions 204. The illustrative source / drain regions 204 are doped with, for example, phosphorus or arsenic. More generally, the source / drain regions 204 and the channel regions 202A-C, or other parts of the nanobands 104A-C, can be made from any suitable combination of doped or undoped semiconductors, such as silicon, silicon-germanium, germanium, germanium-tin alloys, germanium-silicon-tin alloys, a III-V semiconductor, a perovskite, a compound semiconductor, etc. The source / drain regions 204 can have any suitable concentration of any suitable dopant, for example, a dopant concentration of 10¹⁷-10²³ cm⁻³ of phosphorus, arsenic, boron, aluminum, indium, gallium, antimony, and / or the like. The contact 106 on the source / drain regions 204 can consist of any suitable material, for example, a metal silicide and / or a metal such as tungsten, molybdenum, niobium, ruthenium, and / or the like. The contact 106 can be associated with one or more redistribution or bonding layers. In the illustrative embodiment, the GAA-FET 100 is symmetrical, and there is no structural distinction between, for example, the source electrode and the drain electrode of the GAA-FET 100. Thus, the source / drain region 204 can be either the source region or the drain region. Accordingly, the term "source region" or "drain region" in this document can refer to a region that can function as the source of a transistor or to a region that can function as the drain of a transistor. The nanoband 104A-C and the channel regions 202A-C, B, 204D-E can have any suitable dimensions, such as a thickness or width of, for example, 0.5-20 nanometers and a length of, for example, 2-50 nanometers. The source / drain regions 204 can have any suitable dimensions, such as a width (into / out of the image plane) of 10-70 nanometers. The source / drain regions 204 can have any suitable length (across the image plane) of 5-50 nanometers. The source / drain regions 204 can have any suitable height, such as a height of 10-100 nanometers. The GAA-FET 100 can contain any suitable number of semiconductor nanobands 104A-C, such as 1-8. In the illustrative embodiment, the dielectric spacers 108 are a low-k material, such as silicon oxide or silicon nitride. The dielectric insulating layers 110 can consist of any suitable material, for example, silicon oxide or silicon nitride. The dielectric insulating layers 110 can have any suitable dimensions, for example, a length along the substrate 102 of, for example, 2–50 nanometers, a height of, for example, 5–50 nanometers, and a width of, for example, 2–30 nanometers. The gate dielectric layer 112 can be any suitable dielectric, such as a high-k dielectric. In the illustrative embodiment, the gate dielectric layer consists of hafnium oxide. The gate dielectric layer 112 can have any suitable thickness, approximately 0.5–25 nanometers. Depending on whether the transistor is intended to be a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor, the illustrative gate 114 may have at least one p-type or n-type work-working metal. In some implementations, gate 114 may have a stack of two or more metal layers, where one or more metal layers are work-working metal layers and at least one metal layer is a filler metal layer. For a p-MOS transistor, the metals that may be used for gate 114 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an n-MOS transistor (e.g., for work-working tuning).For an n-MOS transistor, the following metals, among others, can be used for the gate 114: hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a p-MOS transistor (e.g., for work function tuning). The conductive material 120 adjacent to the gate 114 can be any suitable conductor. In the illustrative embodiment, the conductive material 120 is tungsten. With reference to Fig. 5, a flowchart for a method 500 for manufacturing a transistor is shown in one embodiment. The method 500 can be carried out by a technician and / or by one or more automated machines. In some embodiments, one or more machines can be programmed to perform some or all of the steps of the method 500. Such a machine can, for example, include a working memory, a processor, a data storage device, etc. Instructions can be stored in the working memory and / or the data storage device which, when executed by the machine, cause the machine to perform some or all of the steps of the method 500.The Process 500 can utilize any suitable set of techniques employed in semiconductor processing, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam epitaxy, pulsed laser deposition, layer transfer, photolithography, ion implantation, dry etching, wet etching, plasma etching, reactive ion etching, ion-assisted chemical vapor etching, thermal treatments, etc. Figures 6-12 show various stages of the Process 500 from the same perspective as Figure 2. The process 500 begins in block 502, in which a stack 600 of semiconductor nanoribbons 104A-C is prepared. In the illustrative embodiment, the stack 600 contains alternating layers of silicon germanium 602 and silicon nanoribbons 104A-C, as shown in Fig. 6. In block 504, trenches 702 are created for the source / drain regions, as shown in Fig. 7. In an illustrative embodiment, the dielectric spacers 108 are arranged around the trenches 702, as shown in the figure. In block 506, the source / drain trenches 702 are filled with a sacrificial material 802, as shown in Fig. 8. The sacrificial material 802 can be any suitable material that can be selectively removed in a subsequent processing step, such as highly doped silicon, doped or undoped silicon-germanium alloys, doped or undoped germanium, amorphous silicon, polycrystalline silicon, etc. Possible dopants include, for example, phosphorus, arsenic, and boron. It should be noted that, in an illustrative embodiment, dopants in a lattice structure that would diffuse during high-temperature processing steps are not used for the sacrificial material 802.Rather, the sacrificial material 802 is a material that either does not have a high dopant concentration or uses dopants that do not diffuse into the adjacent channel areas 202A-C during high-temperature processing steps. In block 508, the channel regions 202A-C are exposed by selective etching of the silicon-germanium 602 layers or another superspaced material. In block 510, the gate dielectric layer 112, the gate 114, and the conductive material 120 are deposited, as shown in Fig. 9. It should be noted that, in an illustrative embodiment, the formation of the gate dielectric layer 112, the gate 114, and the conductive material 120 may require high temperatures, for example, temperatures above 450 °C. In some embodiments, the temperatures may exceed, for example, 450–600 °C. In block 512, the sacrificial material 802 is removed, leaving source / drain trenches 702, as shown in Fig. 10. The sacrificial material 802 is removed using a selective etching process that does not remove substantial portions of the nanosheets 104A-C, including the channel regions 202A-C. In block 514, a low-temperature deposition of highly doped source / drain regions 204 is carried out. In an illustrative embodiment, the source / drain regions 204 consist of silicon. The deposition can be carried out at relatively low temperatures, for example, at temperatures of 400–450 °C or below. It should be noted that growing doped silicon, germanium, or silicon-germanium using standard techniques at lower temperatures is difficult. In one example of a standard technique, epitaxial growth of silicon is desired only at specific locations, while growth on hard marks and spacers, for instance, is generally undesirable. To selectively epitaxially grow silicon at high temperatures, an etchant such as hydrogen chloride is introduced along with the deposition gases. The etchant removes the unwanted growth while allowing the desired epitaxial layer to grow. However, at lower temperatures, hydrogen chloride is less effective as an etchant, thus preventing the selective growth of silicon.Other possible techniques to reduce dopant diffusion include diffusion barriers, ion implantation, alternative dopant precursors, low-diffusion films in the growth state, and / or similar methods. In any case, the specific resistance is not as low as with highly doped epitaxial contacts. To selectively grow silicon at low temperatures, an alternative etching chemistry is used. In one illustrative embodiment, chlorine gas is used as the etchant. However, chlorine gas is not compatible with hydride chemicals such as hydrogen, phosphine, or silane. To keep the chlorine separate from the deposition gases, such as silicon and doping precursors, these are first routed to block 516, where they form a thin silicon layer. Subsequently, the deposition gases are shut off, and the etching gas is introduced into block 518. In the illustrative embodiment, the etching gas is chlorine. In other embodiments, a different gas can be used. The etching gas preferably removes the silicon or other dielectric deposits such as hardmarks and spacers.These two steps allow a small amount of silicon or other semiconductor material to grow in trenches 702 without causing it to grow elsewhere. The steps are repeated until the desired amount of silicon has grown in trenches 702. In block 520, a contact 106 is added to the source / drain areas 204, for example by etching away part of the source / drain areas 204 and depositing the contact 106. It should be noted that the embodiment described above in Figures 1-4 and the embodiment described above with reference to Figures 5-12 represent only some of the possible embodiments for creating such an embodiment, and that other embodiments are also conceivable. In general, any suitable sacrificial layer can be used and / or low-temperature deposition of highly doped silicon can be used in any suitable manufacturing stage for any suitable purpose, for example, to create an interface with a high logarithmic slope of the dopant concentration. Various embodiments are described in more detail below. In some cases, the various features of different embodiments can optionally be used together.For example, the steps described in various embodiments can be used to replace or supplement the steps described above in relation to Method 500. Referring to Fig. 13, in one embodiment, nubs 1302 can be deposited on the nanosheet 104A-C after the grooves 702 have been formed. Due to the way the nubs 1302 grow on the nanosheet 104A-C, they can extend to a point at one or both ends of the channel regions 202A-C. In some embodiments, the nubs 1302 can be undoped or lightly or heavily doped with any suitable dopant. The sacrificial material 802 can then be deposited, and the gate dielectric layer 112, the gate 114, etc., can then be formed as described above with reference to Fig. 5. The sacrificial material 802 can then be removed, and the sour / drain regions 204 can be deposited using a low-temperature deposition process. With reference to Fig. 14, a flowchart for a method 1400 for manufacturing a transistor is shown in one embodiment. Method 1400 (and / or methods 2000 and 2300 described below) can be carried out in a similar manner and using similar techniques as method 500 described above, which is not repeated for clarity. Method 1400 (and / or methods 2000 and 2300) may optionally include any suitable step from method 500 or other methods disclosed herein. Method 1400 begins in block 1402, where gate-all-around transistors are prepared, for example, using some or all of the steps of Method 500. In an illustrative embodiment, the gate-all-around transistors are fabricated using steps similar to those described in blocks 502-510 of Fig. 5. In an illustrative embodiment, the material 1502 of the first source / drain region is deposited in the trenches 702. The material 1502 of the first source / drain region may be similar to the sacrificial material 802 or to the source / drain region 204. In block 1404, one or more interconnection layers 1504 can be formed above the transistor, as shown in Fig. 15. The interconnection layers 1504 can form connections between the gate 114 and the materials 1502 of the source / drain region of different transistors. In block 1406, the wafer, including the substrate 102, is flipped over, as shown in Fig. 16. The substrate 102 can be diluted or completely removed, as shown in Fig. 17. In block 1408, part or all of the material 1502 of the first source / drain region can be etched away, creating trenches 1802, as shown in Fig. 18. In block 1410, a low-temperature deposition of second source / drain regions 1904 is carried out. In an illustrative embodiment, the second source / drain regions 1904 can be similar to the source / drain regions 204 described above. The deposition can be carried out at relatively low temperatures, for example, at temperatures of 400–450 °C or below. A contact 1902 can be deposited on the second source / drain regions 1904, as shown in Fig. 19. In block 1412, one or more power supply lines or power supply vias can be connected to contacts 1902 or to the second source / drain regions 1904. It should be noted that in some embodiments, the rear side of the die can be used for power supply with the transistors, and the front side can be used to provide connections or logic contacts for various logic signals. In some embodiments, the second source / drain regions 1904 can be more heavily doped than the first source / drain regions. In embodiments where the power supply (and thus larger currents) is provided by the second source / drain regions 1904, the more heavily doped second source / drain regions 1904 can reduce resistance losses and overall current consumption. With reference to Fig. 20, a flowchart for a process 2000 for fabricating a transistor is shown in one embodiment. The process 2000 begins in block 2002, in which gate-all-around transistors are prepared, for example, using some or all of the steps of process 500. In an illustrative embodiment, the gate-all-around transistors are fabricated using steps similar to those described in blocks 502-510 of Fig. 5. In an illustrative embodiment, the material 2102 of the first source / drain region is deposited in the trenches 702. The material 2102 of the first source / drain region may be similar to the sacrificial material 802 or to the source / drain regions 204.In some embodiments, the material 2102 of the first source / drain region can be designed as a material with low diffusion capacity, for example as a material with low doping concentrations or as a material doped with dopants known to have lower diffusion at elevated temperatures. In Block 2004, deep trenches 2104 can be formed in the material 2102 of the first source / drain region, as shown in Fig. 21. The deep trenches 2104 can be created using any suitable deep etching technique, such as plasma-based dry etching techniques, reactive ion etching, deep reactive ion etching, laser-assisted etching, focused ion beam etching, and / or the like. In Block 2006, a low-temperature deposition of secondary source / drain regions 2202 is carried out, creating the secondary source / drain regions 2202 in the deep trenches 2104 and adjacent to the material 2102 of the first source / drain region, as shown in Fig. 22. In an illustrative embodiment, the secondary source / drain regions 2202 can be similar to the source / drain regions 204 described above. The deposition can be carried out at relatively low temperatures, for example, at temperatures of 400–450 °C or below. With reference to Fig. 23, a flowchart for a method 2300 for fabricating a transistor is shown in one embodiment. The method 2300 begins in block 2302, in which gate-all-around transistors are prepared, for example, using some or all of the steps of method 500. In an illustrative embodiment, the gate-all-around transistors are fabricated using steps similar to those described in blocks 502-510 of Fig. 5. In block 2304, the sacrificial material 802 is removed. In block 2306, a low-temperature deposition of source / drain regions 2402 is performed, creating a thin layer of source / drain regions 2402, as shown in Fig. 24. As shown in Fig. 24, the source / drain regions 2402 have a U-shape in a cross-sectional side view. The source / drain regions 2402 can be similar to the source / drain regions 204 described above. The source / drain regions 2402 can be grown to any suitable thickness, for example, 1–5 nanometers. In block 2308, a contact 2502 is deposited on the source / drain regions 2402, as shown in Fig. 25. The contact 2502 can be similar to contact 106. It should be noted that contact 2502 has a larger contact area with the source / drain regions 2402 compared to the contact shown in Fig. 12, which may be advantageous in some embodiments. Referring to Fig. 26, diagram 2600 of one embodiment shows the dopant concentration 2602 as a function of position for various embodiments of the GAA-FETs 100 described herein. The dopant concentration 2602 can be measured, for example, at an interface between the source / drain region 204 and the channels 202A-C, with the interface centered approximately at the midpoint of the dopant concentration transition, or about 3 nanometers in the graph shown. The logarithmic slope of the dopant concentration can be high, for example, a change in the dopant concentration of two orders of magnitude in less than one nanometer. By comparison, high-temperature processing steps can reduce the logarithmic slope of the dopant concentration to a significantly lower value, for example, a change in the dopant concentration of two orders of magnitude in ten nanometers.In general, the techniques described here allow for a high logarithmic slope in dopant concentration, for example, 0.2–2 orders of magnitude per nanometer. The higher dopant concentration can have any suitable value, for example, a dopant concentration of 10¹⁷–10²⁴ cm⁻³, and the lower dopant concentration can have any suitable value, for example, 10¹³–10¹⁹ cm⁻³. In general, the difference in dopant concentration between the high and low dopant concentrations can take any suitable magnitude, for example, 1–6 orders of magnitude. Fig. 27 is a top view of a wafer 2700 and dies 2702, which may be included in any of the microelectronic assemblies disclosed herein (e.g., as any suitable substrate 102). The wafer 2700 may consist of semiconductor material and dies 2702 with integrated circuit structures formed on a surface of the wafer 2700. The individual dies 2702 may form a repeating unit of an integrated circuit product containing any suitable integrated circuit. After the fabrication of the semiconductor product is complete, the wafer 2700 may undergo a singulation process in which the dies 2702 are separated from one another to provide discrete “chips” of the integrated circuit product. The die 2702 may be any of the substrates 102 disclosed herein. The dies 2702 may contain one or more transistors (e.g., transistors 2840 from Fig. 27).28, described below), a supporting circuit arrangement for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components that may be fabricated on the wafer. In some embodiments, the wafer 2700 or the dies 2702 may include a memory device (e.g., a random-access memory device (RAM device), such as a static RAM device (SRAM device), a magnetic RAM device (MRAM device), a resistive RAM device (RRAM device), a conductive bridge RAM device (CBRAM device), etc.), logic gates (e.g., AND, OR, NAND, and NOR gates), or any other suitable circuit element. Several of these devices and components may be combined on a single die.For example, a memory array formed from multiple memory devices can be formed on the same die as a processor unit or other logic configured to store information in the memory devices or to execute instructions stored in the memory array. Several of the microelectronic assemblies disclosed herein can be fabricated using a die-to-wafer assembly technique in which some substrates 102 are attached to a wafer 2700 containing other substrates 102, and the wafer 2700 is subsequently singulated. Fig. 28 is a cross-sectional view of an integrated circuit structure 2800, which may be contained in any of the microelectronic assemblies disclosed herein (e.g., in any of the substrates 102). Several instances of the integrated circuit structure 2800 may be contained in the dies 2702 (Fig. 27). The integrated circuit structure 2800 may be formed on a die substrate 2802. The die substrate 2802 may be a semiconductor substrate consisting of semiconductor material, for example, n-type or p-type materials (or a combination of both). The die substrate 2802 may, for example, contain a crystalline substrate formed using silicon base material or a silicon-on-insulator (SOI) substructure.In some embodiments, the die substrate 2802 may comprise a silicon layer on an SOI layer with silicon substrate material beneath the SOI layer. In some embodiments, the die substrate 2802 may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 2802. Although only a few examples of materials from which the die substrate 2802 may be formed are described herein, any material suitable for use as a basis for an integrated circuit structure 2800 may be used. The die substrate 2802 can be part of a single die (e.g., the die 2702 from Fig.27 ) or a wafer (e.g., wafer 2700 from Fig. 27 ). The integrated circuit structure 2800 can include a device layer 2804 arranged on the die substrate 2802. The device layer 2804 can have features of transistors 2840 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 2802. The transistors 2840 can, for example, have source and drain (S / D) regions 2820, a gate 2822 for controlling current flow between the S / D regions 2820, and S / D contacts 2824 for conducting electrical signals to and from the S / D regions 2820. The transistors 2840 can have additional features, not shown for clarity, such as device isolation regions, gate contacts, and the like. The 2840 transistors are not the ones shown in Fig.The type and configuration shown in Figure 28 are limited and can exhibit a wide variety of other types and configurations, such as non-planar transistors or a combination of planar and non-planar transistors. Non-planar transistors can include FinFET transistors, such as dual-gate or tri-gate transistors, and wrap-around or all-around-gate transistors, such as nanoband, nanosheet, or nanowire transistors. Figures 29A-29D are perspective views of exemplary planar, FinFET, gate-all-around, and stacked gate-all-around transistors. The transistors shown in Figures 29A-29D are formed on a substrate 2916 with a substrate surface 2908 and a base material region 2918. Insulation regions 2914 separate the source and drain regions of the transistors from other transistors. Fig. 29A is a perspective view of an exemplary transistor 2900, which includes a gate 2902 that controls a current flow between a source region 2904 and a drain region 2906. The transistor 2900 is planar in that the source region 2904, the drain region 2906, and the substrate surface 2908 lie in the same plane. Fig. 29B is a perspective view of an exemplary transistor 2920, which includes a gate 2922 that controls current flow between a source region 2924 and a drain region 2926. The transistor 2920 is non-planar in that the source region 2924 and the drain region 2926 contain "fins" that extend upwards from the substrate surface 2908. The transistor 2920 can be described as a FinFET. Since the gate 2922 surrounds three sides of the fin that extends from the source region 2924 to the drain region 2926, the transistor 2920 can be considered a tri-gate transistor. Fig. 29B shows an S / D fin extending through the gate 2922, however, multiple S / D fins can extend through the gate of a FinFET transistor. Fig. 29C is a perspective view of a transistor 2940 containing a gate 2942 that controls current flow between a source region 2944 and a drain region 2946. The transistor 2940 is non-planar in that the source region 2944 and the drain region 2946 lie in a different plane than the substrate surface 2908. Since the gate 2942 surrounds all sides of the channel region of the transistor 2940, which extends from the source region 2944 to the drain region 2946, the transistor 2940 can be described as a gate-all-around transistor (GAA transistor). Fig. 29D is a perspective view of a transistor 2960 containing a gate 2962 that controls current flow between several raised source regions 2964 and several raised drain regions 2966. The transistor 2960 is a stacked GAA transistor because the gate controls the current flow between several raised S / D regions stacked on top of each other. The transistors 2940 and 2960 are considered gate-all-around transistors because the gates surround all sides of the transistor's channel regions, extending from the source regions to the drain regions. The transistors 2940 and 2960 can alternatively be referred to as nanowire, nanosheet or nanoband transistors, depending on the width (e.g. widths 2948 and 2968 of the transistors 2940 and 2960 respectively) of the channel regions that extend through the gate. Returning to Fig. 28: The transistors 2840 can contain a gate 2822 formed from at least two layers, a gate dielectric and a gate electrode. The gate dielectric can contain one or more layers. The one or more layers can contain silicon oxide, silicon dioxide, silicon carbide and / or a high-k dielectric material. The high-k dielectric material can contain elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc cniobate. In some embodiments, a tempering process can be performed on the gate dielectric to improve its quality when a high-k material is used. The gate electrode can be formed on the gate dielectric and, depending on whether the transistor is a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor, can have at least one p-type or n-type exit metal. In some implementations, the gate electrode can consist of a stack of two or more metal layers, where one or more metal layers are exit metal layers and at least one metal layer is a filler metal layer. Additional metal layers may be included for other purposes, for example, as a depletion layer. For PMOS transistors, the following metals, among others, can be used for the gate electrode: ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and all metals described below in relation to an NMOS transistor (e.g., for adjusting the work function). For NMOS transistors, the following metals, among others, can be used for the gate electrode: hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and all metals described above in relation to a PMOS transistor (e.g., for adjusting the work function). In some embodiments, such as the FinFET shown in Fig. 29B, the gate electrode can have an inverted U-shape, comprising a top section that is substantially parallel to the surface of the die substrate 2802 and two side sections that are substantially perpendicular to the top of the die substrate 2802. In other embodiments, such as the planar FET shown in Fig. 29A, at least one of the metal layers forming the gate electrode can be a planar layer that is substantially parallel to the top of the die substrate 2802 without side sections. In other embodiments, the gate electrode can consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode can consist of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers. In some embodiments, a pair of sidewall spacers can be formed on opposite sides of the gate stack (containing the gate dielectric and the gate electrode) to clamp the gate stack. The sidewall spacers can be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally involve deposition and etching process steps. In some embodiments, a plurality of sidewall spacer pairs can be used; for example, two pairs, three pairs, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack. The S / D regions 2820 can be formed within the die substrate 2802 adjacent to the gate 2822 of the transistors 2840. These S / D regions can be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the die substrate 2802 to form the S / D regions 2820. The ion implantation process can be followed by an annealing process, which activates the dopants and causes them to diffuse further into the die substrate 2802. In the latter process, the die substrate 2802 can first be etched to create depressions at the locations of the S / D regions 2820. An epitaxial deposition process can then be carried out to fill the depressions with a material used to fabricate the S / D areas 2820.In some embodiments, the S / D regions 2820 can be fabricated using a silicon alloy such as silicon-germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy can be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 2820 can be formed using one or more alternative semiconductor materials such as germanium or a material or alloy of Group III-V. In further embodiments, one or more layers of metal and / or metal alloys can be used to form the S / D regions 2820. Electrical signals, such as current and / or information-transmitting signals (e.g., input / output signals (I / O signals)), can be routed to and / or from devices (e.g., transistors 2840) of the device layer 2804 via one or more interconnection layers arranged on the device layer 2804 (shown in Fig. 28 as interconnection layers 2806-2810). For example, electrically conductive features of the device layer 2804 (e.g., the gate 2822 and the S / D contacts 2824) can be electrically coupled to interconnection structures 2828 of the interconnection layers 2806-2810. The one or more interconnect layers 2806-2810 can form a metallization stack 2819 (which can also be referred to as the “ILD stack” (Inter-Layer Dielectric Stack)) of the integrated circuit structure 2800. The interconnection structures 2828 can be arranged within the interconnection layers 2806-2810 to conduct electrical signals according to a variety of designs; in particular, the arrangement is not limited to the specific configuration of interconnection structures 2828 shown in Fig. 28. Although a specific number of interconnection layers 2806-2810 is shown in Fig. 28, embodiments of the present disclosure include integrated circuit structures with more or fewer interconnection layers than shown. In some embodiments, the interconnect structures 2828 can include conductors or traces 2828a and / or vias 2828b filled with an electrically conductive material, such as a metal. The traces 2828a can be arranged to conduct electrical signals in a plane that is substantially parallel to a surface of the die substrate 2802 on which the device layer 2804 is formed. For example, the traces 2828a can conduct electrical signals in a direction into and out of the side and / or in a direction across the side from the perspective of Fig. 28. The vias 2828b can be arranged to conduct electrical signals in a direction in a plane that is substantially perpendicular to the surface of the die substrate 2802 on which the device layer 2804 is formed.In some embodiments, the conductors 2828a of different interconnection layers 2806-2810 are electrically coupled by vias 2828b. The interconnect layers 2806-2810 can contain a dielectric material 2826 in which the interconnect structures 2828 are arranged, as shown in Fig. 28. In some embodiments, the dielectric material 2826 can have different compositions in different interconnect layers 2806-2810; in other embodiments, the composition of the dielectric material 2826 can be the same between different interconnect layers 2806-2810. The device layer 2804 can contain a dielectric material 2826 in which the transistors 2840 are arranged and on which a lower layer of the metallization stack is located.The dielectric material 2826, which is part of the device layer 2804, may have a different composition than the dielectric material 2826 contained in the compound layers 2806-2810; in other embodiments, the composition of the dielectric material 2826 in the device layer 2804 may be the same as that of a dielectric material 2826 contained in one of the compound layers 2806-2810. A first interconnect layer 2806 (which may be referred to as the Metal-1 or “M1” layer) can be formed directly on the device layer 2804. In some embodiments, the first interconnect layer 2806 may include conductors 2828a and / or vias 2828b, as shown. The conductors 2828a of the first interconnect layer 2806 may be coupled to contacts (e.g., the S / D contacts 2824) of the device layer 2804. The vias 2828b of the first interconnect layer 2806 may be coupled to the conductors 2828a of a second interconnect layer 2808. The second interconnect layer 2808 (which may be referred to as the Metal-2 or “M2” layer) can be formed directly on the first interconnect layer 2806. In some embodiments, the second interconnect layer 2808 may include vias 2828b to couple the conductors 2828a of the second interconnect layer 2808 to the conductors 2828a of a third interconnect layer 2810. Although the conductors 2828a and the vias 2828b are structurally separated by a line within individual interconnect layers for clarity, in some embodiments the conductors 2828a and the vias 2828b may be structurally and / or materially connected (e.g., filled simultaneously during a dual-damascene process). The third interconnect layer 2810 (which may be referred to as the Metal 3 or “M3” layer) (and further interconnect layers, as required) may be formed sequentially on the second interconnect layer 2808 according to similar techniques and configurations described in connection with the second interconnect layer 2808 or the first interconnect layer 2806. In some embodiments, the interconnect layers located “higher up” (i.e., farther away from the device layer 2804) in the metallization layer 2819 of the integrated circuit structure 2800 may be thicker than the interconnect layers located lower down in the metallization stack 2819, with the conductors 2828a and vias 2828b in the higher interconnect layers being thicker than those in the lower interconnect layers. The integrated circuit structure 2800 can include a solder mask material 2834 (e.g., polyimide or a similar material) and conductive contacts 2836 formed on the stack of interconnect layers 2806-2810. In Fig. 28, the conductive contacts 2836 are shown in the form of bond pads. The conductive contacts 2836 can be electrically coupled to interconnect structures 2828 of the top layer in the metallization stack 2819 and configured to conduct electrical signals between the transistors 2840 and components outside the integrated circuit structure 2800. For example, solder bonds can be formed on the conductive contacts 2836 to mechanically and / or electrically couple an integrated circuit component containing the integrated circuit structure 2800 to another component (e.g., a printed circuit board).The integrated circuit structure 2800 may include additional or alternative structures for conducting electrical signals from the interconnect layers 2806-2810; for example, the conductive contacts 2836 may include other analog features (e.g., pins) that can conduct electrical signals between the transistors 2840 and external components. In some embodiments where the integrated circuit structure 2800 is part of a double-sided die (e.g., like the substrate 102), the integrated circuit structure 2800 may include a second metallization stack (not shown) located on the opposite side of the die substrate 2802 from the device layer 2804. This second metallization stack may have multiple interconnection layers, as described above with respect to the interconnection layers 2806-2810. Silicon vias (TSVs) extending through the die substrate 2802 may provide electrically conductive paths from the transistors 2840 to the second metallization stack, and the second metallization stack may electrically couple the TSVs to additional conductive contacts (not shown) located on the opposite side of the integrated circuit structure 2800 from the conductive contacts 2836. In some embodiments, TSVs extending through the die substrate 2802 can be used to conduct power and ground signals from conductive contacts located on the opposite side of the integrated circuit structure 2800 from the conductive contacts 2836 to the transistors 2840 and all other components integrated into the integrated circuit structure 2800. The metallization stack 2819 can be used to conduct information-carrying signals from the conductive contacts 2836 to the transistors 2840 and all other components integrated into the integrated circuit structure 2800. In other words, the conduction of power and ground signals to the transistors 2840 (via a rear-side or bottom-side metallization stack and TSVs) can be separated from the conduction of information-carrying signals to the transistors.Power and ground signals are provided by a rear or bottom metallization stack and TSVs, and information-carrying signals are provided by a top metallization stack (e.g., metallization stack 2819). Multiple integrated circuit dies can be stacked with one or more TSVs in each stacked die, providing a connection between each die and each of the other dies in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on a base integrated circuit die, and TSVs in the HBM dies can provide a connection between each HBM die and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be finely spaced solder bumps (microbumps). Fig. 30 is a cross-sectional view of an integrated circuit device 3000, which may contain any of the microelectronic assemblies disclosed herein. In some embodiments, the integrated circuit device assembly 3000 may contain any GAA-FETs 100. The integrated circuit device assembly 3000 contains a number of components arranged on a printed circuit board 3002 (which may be a motherboard, a system board, a main board, etc.). The integrated circuit device assembly 3000 contains components arranged on a first surface 3040 and a second surface 3042 of the printed circuit board 3002, the second surface 3042 being opposite the first surface 3040. In general, components can be arranged either on the first surface 3040 or the second surface 3042 of the printed circuit board 3002, or on both.Each of the integrated circuit components described below with respect to the integrated circuit device assembly 3000 may include any suitable embodiment of the GAA-FETs 100 disclosed herein. In some embodiments, the circuit board 3002 can be a printed circuit board (PCB) comprising several metal layers (or interconnect layers) separated from one another by layers of a dielectric material and interconnected by electrically conductive vias. The individual metal layers contain conductive traces. The metal layers can be arranged in a desired pattern to conduct electrical signals between components that are electrically coupled to the circuit board 3002. In other embodiments, the circuit board 3002 can be a non-PCB substrate. The integrated circuit device assembly 3000 shown in Fig. 30 comprises a package-on-interposer structure 3036, which is coupled to the first surface 3040 of the printed circuit board 3002 by coupling components 3016. The coupling components 3016 can electrically and mechanically couple the package-on-interposer structure 3036 to the printed circuit board 3002 and can include solder balls (as shown in Fig. 30), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), plug and socket sections of a connector, an adhesive, a filler material, and / or any other suitable electrical and / or mechanical coupling structure. (Thus, a coupling component can contain a conductive contact.) The coupling components 3016 can be used as required, as shown or described here, for any substrate arrangement or substrate arrangement component described here (e.g.,Integrated circuit components) are used. The package-on-interposer structure 3036 can include an integrated circuit component 3020 coupled to an interposer 3004. The interposer 3004 can provide an intermediate substrate that forms a bridge between the printed circuit board 3002 and the integrated circuit component 3020. The integrated circuit component 3020 is coupled to the interposer 3004 by coupling components 3018. The coupling components 3018 can take any suitable shape, for example, the shapes described above with respect to the coupling components 3016. Although Fig. 30 shows only one integrated circuit component attached to the interposer, several integrated circuit components can be coupled to the interposer 3004. Additional interposers can be coupled to the interposer 3004. The integrated circuit component 3020 can be an encapsulated or non-encapsulated integrated circuit product comprising one or more integrated circuit dies (e.g., the die 2702 from Fig. 27, a die containing the integrated circuit structure 2800 from Fig. 28) and / or one or more other suitable components. An encapsulated integrated circuit component comprises one or more integrated circuit dies mounted on a housing substrate, wherein the integrated circuit dies and the housing substrate are encapsulated in an encapsulation material, such as metal, plastic, glass, or ceramic. In an example of a non-encapsulated integrated circuit component 3020, a single monolithic integrated circuit die comprises solder pad ridges attached to contacts on the die. The solder pad ridges enable the die to be mounted directly to the interposer 3004.The integrated circuit component 3020 can include one or more computing system components, such as one or more processor units (e.g., a system-on-a-chip (SoC)), a processor core, a graphics processing unit (GPU), an accelerator, a chipset processor, an I / O controller, a memory, or a network interface controller. In some embodiments, the integrated circuit component 3020 can include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices. In embodiments where the 3020 integrated circuit component contains multiple integrated circuit dies, the dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM). In addition to containing one or more processor units, the 3020 integrated circuit component can include additional components, such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components can reside on the same integrated circuit die as a processor unit or on one or more integrated circuit dies that are separate from the integrated circuit dies containing the processor units. These separate integrated circuit dies can be referred to as "chiplets."In embodiments where an integrated circuit component contains multiple integrated circuit dies, connections between the dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® Embedded Multi-Die Interconnect Bridges (EMIBs)), or combinations thereof. In general, the interposer 3004 can distribute connections over a wider or narrower distance or redirect one connection to another. For example, the interposer 3004 can couple coupling components 3018 at a first distance to coupling components 3016 at a greater distance than the first distance. In the embodiment shown in Fig. 30, the integrated circuit component 3020 and the printed circuit board 3002 are mounted on opposite sides of the interposer 3004. In other embodiments, the integrated circuit component 3020 and the printed circuit board 3002 can be mounted on the same side of the interposer 3004. In some embodiments, three or more components can be interconnected via the interposer 3004. In some embodiments, the interposer 3004 can be configured as a printed circuit board comprising several metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 3004 can be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 3004 can be formed from alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other materials of Groups III-V and IV.The interposer 3004 can include metal connections 3008 and vias, including but not limited to vias 3010-1 (extending from a first face 3050 of the interposer 3004 to a second face 3054 of the interposer 3004), blind vias 3010-2 (extending from the first face 3050 or the second face 3054 of the interposer 3004 to an internal metal layer) and buried vias 3010-3 (connecting internal metal layers). In some embodiments, the interposer 3004 can include a silicon interposer. Silicon vias (TSVs) extending through the silicon interposer allow connections on a first side of the silicon interposer to be made to a opposite second side of the silicon interposer. In some embodiments, an interposer 3004 containing a silicon interposer can further include one or more wiring layers to form connections on a first side of the interposer 3004 to a opposite second side of the interposer 3004. In some embodiments, both the interposer 3004 and the printed circuit board 3002 may contain an amorphous solid glass layer (which may be referred to as the glass core or glass substrate). In some embodiments, the glass layer may contain silicon (comprising silicon dioxide (SiO2)), fused silica, aluminum silicate (comprising aluminum oxide (Al2O3) and silicon dioxide), borosilicate (comprising silicon dioxide and boron trioxide (B2O3)), or aluminum borosilicate (comprising aluminum oxide, silicon dioxide, and boron trioxide). In some embodiments, the glass layer may contain one or more of the following additives: aluminum oxide, boron trioxide, magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), barium oxide (BaO), tin(IV) oxide (SnO2), nitrogen oxide (Na2O), potassium oxide (K2O), diphosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium and zinc.In some embodiments, the glass layer may contain silicon and oxygen, as well as one or more of the elements aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass layer contains at least 23% silicon by weight, at least 26% oxygen by weight, and at least 5% aluminum by weight. In some embodiments, the glass layer contains no organic adhesive or organic material. For example, the glass layer is not a substrate or a plate containing glass fibers and an epoxy binder, such as a printed circuit board (PCB), which contains multiple metal layers (or compound layers) separated from each other by layers of dielectric material (e.g., FR-4 or another glass-fiber-reinforced epoxy laminate) and interconnected by electrically conductive vias. In some embodiments, the glass layer has a thickness in the range of about 50 micrometers to about 1.4 millimeters. In some embodiments, the glass layer is a multilayer glass substrate (a coreless substrate) or a portion thereof. Individual glass layers within a multilayer glass substrate may have a thickness in the range of about 25 micrometers to about 50 micrometers. In some embodiments, a glass layer may have a length in the range of about 10 millimeters to about 250 millimeters on one side (i.e., have an area in the range of about 10 mm x 10 mm to about 250 mm x 250 mm). In some embodiments, the glass layer comprises a rectangular prism volume in which sections or parts (e.g., glass vias) are removed and filled with other metals (e.g., metal). In some embodiments, redistribution layers (RDLs) can be arranged on one or both sides of the glass layer to provide electrically conductive paths from the top and / or bottom of the interposer 3004 or the printed circuit board 3002 to the glass layer. The glass layer can include glass through-hole vias (TGVs) extending through the glass layer to provide electrically conductive paths through the glass core, the glass substrate, or the glass layer. The interposer 3004 can further include embedded devices 3014, including both passive and active devices. Such devices can include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the interposer 3004. The package-on-interposer structure 3036 can take the form of any package-on-interposer structure known in the prior art. The integrated circuit device assembly 3000 can include an integrated circuit component 3024, which is coupled to the first surface 3040 of the printed circuit board 3002 by coupling components 3022. The coupling components 3022 can take the form of one of the embodiments described above with respect to the coupling components 3016, and the integrated circuit component 3024 can take the form of one of the embodiments described above with respect to the integrated circuit component 3020. The integrated circuit device assembly 3000 shown in Fig. 30 further comprises a case-on-case structure 3034, which is coupled to the second surface 3042 of the printed circuit board 3002 via coupling components 3028. The case-on-case structure 3034 can include an integrated circuit component 3026 and an integrated circuit component 3032, which are coupled to each other by coupling components 3030 such that the integrated circuit component 3026 is arranged between the printed circuit board 3002 and the integrated circuit component 3032. The coupling components 3028 and 3030 can take the form of any embodiment of the coupling components 3016 described above, and the integrated circuit components 3026 and 3032 can take the form of any embodiment of the integrated circuit component 3020 described above.The case-on-case structure 3034 can be configured according to any of the case-on-case structures known in the prior art. Fig. 31 is a block diagram of an exemplary electrical device 3100, which may contain any of the microelectronic assemblies disclosed herein. For example, any suitable components of the electrical device 3100 may comprise one or more of the integrated circuit device assemblies 3000, integrated circuit components 3020, or integrated circuit structures 2800, or integrated circuit dies 2702 disclosed herein, and may be arranged in one of the microelectronic assemblies disclosed herein. Fig. 31 shows a number of components included in the electrical device 3100; however, any one or more of these components may be omitted or included multiple times, as is suitable for the application.In some embodiments, some or all of the components contained in the electrical device 3100 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are manufactured on a single system-on-a-chip (SoC) die. In addition, in various embodiments, the electrical device 3100 may lack one or more of the components shown in Fig. 31, but may include an interface circuit arrangement for coupling with the one or more components. For example, the electrical device 3100 need not include a display device 3106, but may include a circuit arrangement for a display device interface (e.g., a connector and a driver circuit arrangement) to which a display device 3106 can be coupled. In another set of examples, the electrical device 3100 may lack an audio input device 3124 or an audio output device 3108, but may include an audio input or output device interface circuit arrangement (e.g., a connector and a driver circuit arrangement).connectors and a support circuit arrangement) with which an audio input device 3124 or an audio output device 3108 can be coupled. The electrical device 3100 can contain one or more processor units 3102. As used herein, the term "processor unit," "processing unit," or "processor" can refer to any device or any part of a device that processes electronic data from registers and / or from a memory to transform such electronic data into other electronic data that can be stored in registers and / or a memory. The one or more processor units 3102 can be one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processors (NPUs), data processing units (DPUs), accelerators (e.g.,Graphics accelerators, compression accelerators, AI accelerators), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within the hardware), server processors, controllers, or other suitable types of processors. Therefore, the processor unit can be referred to as an XPU (or xPU). The electrical device 3100 can include a memory 3104, which itself can include one or more memory devices, such as volatile memory (e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), chalcogenide-based voltage-free phase-change memory), flash memory, solid-state memory, and / or a hard disk. In some embodiments, the memory 3104 can include memory located on the same integrated circuit die as the processor units 3102. This memory can be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last-Level Cache (LLC)) and can include embedded dynamic random-access memory (eDRAM) or magnetic spin transfer torque random-access memory (STT-MRAM). In some embodiments of the electrical device 3100, a first of the one or more processor units 3102 may be heterogeneous or asymmetric with respect to a second of the one or more processor units 3102 in the electrical device 3100. There may be a variety of differences between the one or more processor units 3102 in a system with respect to a range of performance metrics, including architectural, microarchitecture, thermal, power consumption characteristics, and the like. These differences may effectively manifest as an asymmetry and heterogeneity among the one or more processor units 3102 in the electrical device 3100. In some embodiments, the electrical device 3100 may include a communication component 3112. For example, the communication component 3112 may manage wireless communications for the transmission of data to and from the electrical device 3100. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium by using modulated electromagnetic radiation. The term "wireless" does not mean that the associated devices do not contain wires, although this may be the case in some embodiments. The 3112 communication component can implement any number of wireless standards or protocols, including, but not limited to, standards of the Institute for Electrical and Electronic Engineers (IEEE), including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), the Long-Term Evolution Project (LTE Project) along with all amendments, updates, and / or revisions (e.g., the Advanced LTE Project, the Ultra-Mobile Broadband Project (UMB Project) (also known as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access and is a certification mark for products that pass compliance and interoperability tests for the IEEE 802.16 standards.The 3112 communication component can operate according to a GSM (Global System for Mobile Communication), GPRS (General Packet Radio Service), UMTS (Universal Mobile Telecommunications System), HSPA (High Speed ​​Packet Access), E-HSPA (Evolved HSPA), or LTE network. The 3112 communication component can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The 3112 communication component can operate according to Code-Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the 3112 communication component can operate according to other wireless protocols.The electrical device 3100 may have an antenna 3122 to facilitate wireless communication and / or to receive other wireless communication (such as AM or FM radio transmissions). In some embodiments, the communication component 3112 can manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). In some embodiments, the electrical device 3100 includes multiple communication components. For example, a first communication component can be dedicated to shorter-range wireless communication, such as WiFi or Bluetooth, and a second communication component can be dedicated to longer-range wireless communication, such as the Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component can be dedicated to wireless communication, and a second communication component can be dedicated to wired communication. The electrical device 3100 may include a battery / power supply circuit arrangement 3114. The battery / power supply circuit arrangement 3114 may include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuit arrangement for coupling components of the electrical device 3100 to a power source separate from the electrical device 3100 (e.g., AC power from the mains). The electrical device 3100 can include a display device 3106 (or a corresponding interface circuit arrangement as described above). The display device 3106 can include one or more embedded or wired or wirelessly connected external visual displays, such as a head-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display. The electrical device 3100 can include an audio output device 3108 (or a corresponding interface circuit arrangement as described above). The audio output device 3108 can include any embedded, wired, or wirelessly connected external device that produces an acoustic signal, such as a loudspeaker, headphones, or earphones. The electrical device 3100 may include an audio input device 3124 (or a corresponding interface circuit arrangement as described above). The audio input device 3124 may include any embedded, wired, or wireless device that generates a signal representing sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a Musical Instrument Digital Interface (MIDI) output). The electrical device 3100 may include a global navigation satellite system (GNSS) device (or a corresponding interface circuit arrangement as described above), such as a global positioning system (GPS) device.The GNSS device 3118 can communicate with a satellite-based system and can determine a geographic location of the electrical device 3100 based on information received from one or more GNSS satellites, as is known in the prior art. The electrical device 3100 may include another output device 3110 (or a corresponding interface circuit arrangement, as described above). Examples of the other output device 3110 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for supplying information to other devices, or an additional storage device. The electrical device 3100 may include another input device 3120 (or a corresponding interface circuit arrangement as described above). Examples of the other input device 3120 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touch panel, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a quick-response (QR) code reader, an electrocardiogram sensor (ECG sensor), a photoplethysmogram (PPG) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader. The 3100 electrical device can be of any form factor, such as a handheld or mobile electrical device (for example, a mobile phone, a smartphone, a mobile internet device, a music playback device, a tablet computer, a laptop computer, a convertible 2-in-1 computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console), a desktop electrical device, a server, a rack-level computing solution (for example, blade, tray, or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a home game console, a smart television, a vehicle control unit, a digital camera, a digital video recorder,an electrical wearable device or an embedded computing system (for example, computing systems that are part of a vehicle, a smart home device, a consumer electronics product or equipment, or manufacturing equipment). In some embodiments, the electrical device 3100 can be any other electronic device that processes data. In some embodiments, the electrical device 3100 can include several discrete physical components. Considering the variety of devices that the electrical device 3100 can manifest as in different embodiments, the electrical device 3100 can be referred to as a computing device or computing system in some embodiments. EXAMPLES The following are illustrative examples of the technologies disclosed herein. An embodiment of the technologies may include any one or any number of the examples described below and any combination thereof. Example 1 includes a device with a gate all-around transistor comprising a first source or drain region; a second source or drain region; and a channel region, wherein the channel region adjoins the first source or drain region and the second source or drain region, wherein an interface of the first source or drain region and the channel region has a dopant concentration gradient, wherein the dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer. Example 2 contains the subject from Example 1, wherein the first source or drain region has a first dopant concentration level at a first position, wherein the channel region has a second dopant concentration level at a second position, wherein the first dopant concentration level is at least two orders of magnitude higher than the second dopant concentration level, and wherein the second position is less than two nanometers away from the first position. Example 3 contains the subject matter from one of Examples 1 and 2, wherein the gate all-around transistor is an NMOS transistor, wherein an interface of the first source or drain region and the channel region has a phosphorus dopant concentration gradient, wherein the phosphorus dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer. Example 4 contains the item from one of Examples 1-3, wherein the phosphorus dopant concentration in the first source or drain area is more than 5 times 1019 per cubic centimeter, and the phosphorus dopant concentration in the channel area is less than 5 times 1018 per cubic centimeter. Example 5 includes the subject matter of any one of Examples 1-4, wherein the gate all-round transistor further includes a third source or drain region and a fourth source or drain region, wherein the third source or drain region is adjacent to the first source or drain region, wherein the fourth source or drain region is adjacent to the second source or drain region, wherein the first source or drain region has a higher dopant concentration than the third source or drain region, wherein the second source or drain region has a higher dopant concentration than the fourth source or drain region, wherein a first rear-side power supply contact is adjacent to the first source or drain region, wherein a second rear-side power supply contact is adjacent to the second source or drain region, and wherein a first front-side logic contact is adjacent to the third source or drain region.where a second front-side logic contact adjoins the fourth source or drain area. Example 6 contains the object from one of Examples 1-5, wherein the channel area contains one or more knobs extending to a point at one or both ends of the channel area. Example 7 contains the object from one of Examples 1-6, wherein in a cross-sectional side view the first source or drain region has a U-shape, wherein the thickness of the first source or drain region is between 1 and 3 nanometers, and wherein in a cross-sectional side view the second source or drain region has a U-shape, wherein the thickness of the second source or drain region is between 1 and 3 nanometers. Example 8 contains the item from one of Examples 1-7 and furthermore a processor, wherein the processor contains the gate all-around transistor. Example 9 contains the object from one of Examples 1-8 and furthermore one or more storage devices that are communicatively coupled to the processor. Example 10 includes a device comprising a transistor containing a first region, wherein the first region has a first dopant concentration; a second region, wherein the second region has a second dopant concentration; and an interface region, wherein the interface region is located between the first region and the second region and adjacent to the first region and the second region, wherein the interface region has a dopant concentration gradient from the first region to the second region, wherein the dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer, wherein at least a part of the interface region has a dopant concentration of less than 10¹⁹ per cubic centimeter and at least a part of the interface region has a dopant concentration of more than 10¹⁹ per cubic centimeter. Example 11 contains the subject from Example 10, wherein the first region is a source / drain region, wherein the second region is a channel region, wherein the source / drain region has a first dopant concentration level at a first position, wherein the channel region has a second dopant concentration level at a second position, wherein the first dopant concentration level is at least two orders of magnitude higher than the second dopant concentration level, and wherein the second position is less than two nanometers away from the first position. Example 12 contains the subject from one of Examples 10 and 11, wherein the transistor is an NMOS gate all-around transistor, wherein the interface region has a phosphorus dopant concentration gradient, wherein the phosphorus dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer. Example 13 contains the item from one of Examples 10-12, wherein the phosphorus dopant concentration in the first area is more than 5 times 1019 per cubic centimeter, and the phosphorus dopant concentration in the second area is less than 5 times 1018 per cubic centimeter. Example 14 contains the object from one of Examples 10-13, wherein the first region is a first source or drain region, wherein the second region is a second source or drain region, wherein the transistor further contains a channel region, wherein the second source or drain region is adjacent to the channel region. Example 15 contains the object from one of Examples 10-14, wherein the second area contains one or more studs extending to a point at one or both ends of the second area. Example 16 contains the object from one of Examples 10-15, wherein in a cross-sectional side view the first region has a U-shape, with a thickness of the first region being between 1 and 3 nanometers. Example 17 contains the item from one of Examples 10-16 and furthermore a processor, wherein the processor contains the transistor. Example 18 contains the object from one of Examples 10-17 and also one or more storage devices that are communicatively coupled to the processor. Example 19 contains a method for manufacturing a transistor, wherein the method includes performing one or more high-temperature semiconductor processing steps at a temperature of about 500 °C; and, after performing the one or more high-temperature semiconductor processing steps, growing a silicon region at a temperature of less than 450 °C, wherein the silicon region has a dopant concentration of at least 1020 per cubic centimeter, wherein the growth of the silicon region includes alternating flows of deposition gases and flows of an etching gas. Example 20 contains the subject of Example 19, wherein the corrosive gas contains chlorine. Example 21 contains the subject matter of one of Examples 19 and 20, wherein the performance of one or more high-temperature semiconductor processing steps includes the deposition of a gate dielectric, a gate, or both the gate dielectric and the gate. Example 22 includes the subject matter of one of Examples 19-21 and further includes the deposition of a sacrificial material prior to carrying out one or more high-temperature semiconductor processing steps; and the removal of the sacrificial material after carrying out one or more high-temperature semiconductor processing steps and prior to allowing the silicon region to grow. Example 23 contains the subject matter of one of Examples 19-22, wherein an interface between the silicon region and an adjacent channel region has a dopant concentration gradient, wherein the dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer. Example 24 contains the subject from one of Examples 19-23, wherein the adjacent channel region has a first dopant concentration level at a first position, wherein the silicon region has a second dopant concentration level at a second position, wherein the first dopant concentration level is at least two orders of magnitude higher than the second dopant concentration level, and wherein the second position is less than two nanometers away from the first position. Example 25 includes the subject matter from one of Examples 19-24 and further the fabrication of a gate all-around transistor, wherein the fabrication of the gate all-around transistor includes performing one or more high-temperature semiconductor processing steps and growing the silicon region. Example 26 contains the subject matter from one of Examples 19-25, wherein the gate all-around transistor is an NMOS transistor, wherein an interface of the silicon region and an adjacent channel region has a phosphorus dopant concentration gradient, wherein the phosphorus dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer. Example 27 contains the subject from one of Examples 19-26, wherein the phosphorus dopant concentration in the silicon region is more than 5 times 1019 per cubic centimeter, and wherein the phosphorus dopant concentration in a channel region adjacent to the silicon region is less than 5 times 1018 per cubic centimeter. Example 28 contains the object from one of Examples 19-27, wherein in a cross-sectional side view the first silicon region has a U-shape, wherein the thickness of the first silicon region is between 1 and 3 nanometers.

Claims

Device comprising: a gate all-round transistor comprising: a first source or drain region; a second source or drain region; and a channel region, wherein the channel region adjoins the first source or drain region and the second source or drain region, wherein an interface between the first source or drain region and the channel region has a dopant concentration gradient, wherein the dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer. Device according to claim 1, wherein the first source or drain region has a first dopant concentration level at a first position, wherein the channel region has a second dopant concentration level at a second position, wherein the first dopant concentration level is at least two orders of magnitude higher than the second dopant concentration level, and wherein the second position is less than two nanometers away from the first position. Device according to one of claims 1-2, wherein the gate all-around transistor is an NMOS transistor, wherein an interface between the first source or drain region and the channel region has a phosphorus dopant concentration gradient, wherein the phosphorus dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer. Device according to one of claims 1-3, wherein a phosphorus dopant concentration in the first source or drain area is more than 5 x 1019 per cubic centimeter, wherein a phosphorus dopant concentration in the channel area is less than 5 x 1018 per cubic centimeter. Device according to any one of claims 1-4, wherein the gate all-around transistor further comprises a third source or drain region and a fourth source or drain region, wherein the third source or drain region is adjacent to the first source or drain region, wherein the fourth source or drain region is adjacent to the second source or drain region, wherein the first source or drain region has a higher dopant concentration than the third source or drain region, wherein the second source or drain region has a higher dopant concentration than the fourth source or drain region, wherein a first rear-side power supply contact is adjacent to the first source or drain region, wherein a second rear-side power supply contact is adjacent to the second source or drain region, and wherein a first front-side logic contact is adjacent to the third source or drain region.where a second front-side logic contact adjoins the fourth source or drain area. Device according to one of claims 1-5, wherein the channel area contains one or more knobs extending to a point at one or both ends of the channel area. Device according to one of claims 1-6, wherein in a cross-sectional side view the first source or drain region has a U-shape, wherein the thickness of the first source or drain region is between 1 and 3 nanometers, wherein in a cross-sectional side view the second source or drain region has a U-shape, wherein the thickness of the second source or drain region is between 1 and 3 nanometers. Device according to one of claims 1-7, further comprising a processor, wherein the processor comprises the gate all-around transistor. Device according to claim 8, further comprising one or more storage devices that are communicatively coupled to the processor. A device comprising: a transistor comprising: a first region, wherein the first region has a first dopant concentration; a second region, wherein the second region has a second dopant concentration; and an interface region, wherein the interface region is located between the first region and the second region and adjacent to the first region and the second region, wherein the interface region has a dopant concentration gradient from the first region to the second region, wherein the dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer, wherein at least a part of the interface region has a dopant concentration of less than 10¹⁹ per cubic centimeter and at least a part of the interface region has a dopant concentration of more than 10¹⁹ per cubic centimeter. Device according to claim 10, wherein the first region is a source / drain region, wherein the second region is a channel region, wherein the source / drain region has a first dopant concentration level at a first position, wherein the channel region has a second dopant concentration level at a second position, wherein the first dopant concentration level is at least two orders of magnitude higher than the second dopant concentration level, and wherein the second position is less than two nanometers away from the first position. Device according to one of claims 10-11, wherein the transistor is an NMOS gate all-around transistor, wherein the boundary region has a phosphorus dopant concentration gradient, wherein the phosphorus dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer. Device according to one of claims 10-12, wherein the phosphorus dopant concentration in the first area is more than 5 times 1019 per cubic centimeter, wherein the phosphorus dopant concentration in the second area is less than 5 times 1018 per cubic centimeter. Device according to one of claims 10-13, wherein the first region is a first source or drain region, wherein the second region is a second source or drain region, wherein the transistor further comprises a channel region, wherein the second source or drain region is adjacent to the channel region. Device according to one of claims 10-14, wherein in a cross-sectional side view the first region has a U-shape, wherein the thickness of the first region is between 1 and 3 nanometers. A method for manufacturing a transistor, comprising: performing one or more high-temperature semiconductor processing steps at a temperature of about 500 °C; and after performing the one or more high-temperature semiconductor processing steps, growing a silicon region at a temperature of less than 450 °C, wherein the silicon region has a dopant concentration of at least 1020 per cubic centimeter, wherein the growth of the silicon region includes alternating flows of deposition gases and flows of an etching gas. Method according to claim 16, wherein the etching gas contains chlorine. Method according to one of claims 16-17, wherein performing one or more high-temperature semiconductor processing steps includes the deposition of a gate dielectric, a gate, or both the gate dielectric and the gate. A method according to any one of claims 16-18, further comprising: depositing a sacrificial material prior to performing one or more high-temperature semiconductor processing steps; and removing the sacrificial material after performing one or more high-temperature semiconductor processing steps and prior to allowing the silicon region to grow. Method according to one of claims 16-19, wherein an interface between the silicon region and an adjacent channel region has a dopant concentration gradient, wherein the dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer. The method of claim 20, wherein the adjacent channel region has a first dopant concentration level at a first position, wherein the silicon region has a second dopant concentration level at a second position, wherein the first dopant concentration level is at least two orders of magnitude higher than the second dopant concentration level, and wherein the second position is less than two nanometers away from the first position. A method according to one of claims 16-21, further comprising the fabrication of a gate all-around transistor, wherein the fabrication of the gate all-around transistor comprises performing one or more high-temperature semiconductor processing steps and growing the silicon region. Method according to claim 22, wherein the gate all-around transistor is an NMOS transistor, wherein an interface between the silicon region and an adjacent channel region has a phosphorus dopant concentration gradient, wherein the phosphorus dopant concentration gradient has a logarithmic slope of the dopant concentration of at least one order of magnitude per nanometer. Method according to one of claims 16-23, wherein a phosphorus dopant concentration in the silicon region is more than 5 x 1019 per cubic centimeter, wherein a phosphorus dopant concentration in a channel region adjacent to the silicon region is less than 5 x 1018 per cubic centimeter. Method according to one of claims 16-24, wherein in a cross-sectional side view the first silicon region has a U-shape, wherein the thickness of the first silicon region is between 1 and 3 nanometers.

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