A neuronal circuit for temporal coding

Abstract

The present invention discloses a neuron circuit for time coding, comprising a resistor R1, a capacitor C1, a capacitor C2, and a memristor IMT. The resistor R1 and the capacitor C1 form a charging loop, denoted as a CL loop; the capacitor C1 and the memristor IMT form a DL loop; when a pulse input comes in, it first passes through the CL loop and enters the charging link; in the link where a current spike is generated, when the CL loop makes the potential of two points greater than the threshold voltage V of the memristor, the pulse is charged. th When the current flowing through capacitor C2 suddenly increases, a current spike occurs. Each pulse intensity corresponds to a current spike duration, and each current spike duration corresponds to an analog value. By encoding each current spike duration, a time encoding function is implemented. This circuit can implement time encoding based on the threshold transition characteristics and switching action of the memristor switch, fully utilizing the inherent characteristics of the memristor device and greatly simplifying the circuit design.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits and neural network technologies, and in particular to a neuron circuit oriented to time coding. Background Art

[0002] Brain science and artificial intelligence research are experiencing rapid development through mutual promotion. Spiking neural networks (SNNs) are at the core of brain-inspired intelligence research. By emphasizing highly brain-inspired structural foundations and functional optimization methods, they attempt to accelerate our understanding of the essence of biological intelligence through computational means, laying the theoretical foundation for a new generation of human-level artificial intelligence models. Common neural network encoding methods include frequency coding and temporal coding. Temporal coding represents information as the time of a neuron's first spike. Assuming a neuron generates only one spike, it remains in an inhibited state until the next stimulus arrives. The time at which the spike is generated is proportional to the value of the analog quantity, indicating that the time of the first spike after receiving a stimulus contains all the information about the stimulus.

[0003] like Figure 1 The figure shows a circuit structure for implementing time coding in the prior art. This circuit structure uses a transmission gate and a D flip-flop to control the circuit to generate only one current spike. However, the circuit design of this scheme is relatively complex and contains many components, which cannot effectively simulate the random excitation characteristics of biological neurons. Summary of the Invention

[0004] The purpose of the present invention is to provide a neuron circuit for time coding, which can realize the time coding function based on the threshold transition characteristics and switching action of the memristor switch, fully utilize the inherent characteristics of the memristor device, greatly simplify the circuit design, and better simulate the random excitation characteristics of biological neurons.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] A neuron circuit for time coding, comprising a pre-resistor R1, a pre-capacitor C1, a post-capacitor C2, and a threshold-shift memristor TS, wherein:

[0007] The pre-resistor R1 and the pre-capacitor C1 are connected in series to form a CL loop, which is used to charge the pre-capacitor C1 and increase the front-end potential of the threshold transition memristor TS;

[0008] The threshold-shift memristor TS is connected in series with the pre-capacitor C1 to form a DL loop, which discharges the pre-capacitor C1.

[0009] During the period when the threshold transition memristor TS is turned on, the post capacitor C2 is charged to increase the potential at the other end of the threshold transition memristor TS, thereby ensuring that TS is turned on only once;

[0010] In the charging phase, when the pulse is input from the input signal access point, that is, node 1, it first passes through the CL loop and enters the charging phase. At this time, the threshold transition memristor TS is in the off state and has a large resistance value, which is recorded as R HRS , that is to say, the memristor at this time is equivalent to an open switch, with only a very small current flowing through it, which can be ignored, and no current flows through the post capacitor C2; when the CL loop makes the potential of the node on the right side of the pre resistor R1, that is, node 2, greater than the threshold voltage V of the threshold transition memristor TS th When , the charging phase ends;

[0011] In the process of generating current spike, when the CL loop makes the potential of node 2 greater than the threshold voltage V of the threshold transition memristor TS, th When the memristor is turned on, the resistance becomes smaller, and its resistance is recorded as R LRS , due to the state transition of the memristor, from the high resistance state R HRS Transformed into low resistance state R LRS , which is equivalent to the switch being closed, and the memristor changes very quickly. The current flowing through the post-capacitor C2 suddenly increases, resulting in a current spike. After generating and emitting a current spike, the memristor will be closed again;

[0012] In the encoding phase, when a current spike occurs, that is, when the memristor is turned on, the current flowing through the memristor and the post-capacitor C2 increases, charging the post-capacitor C2, causing the potential of the node where the threshold-shift memristor TS and the post-capacitor C2 are connected, that is, node 3, to rise, which will make the voltage across the memristor less than the holding voltage V of the threshold-shift memristor TS. hold , so that the memristor is closed again; when the CL loop continues to charge, even if the potential of node 2 reaches the threshold voltage V th Since the potential of node 3 also increases, the potential difference between the two ends of the memristor cannot reach its threshold voltage V again. th Therefore, the memristor cannot be turned on again and cannot generate a current spike again. In other words, the entire circuit will only generate one current spike. For inputs with different pulse intensities, only one current spike will be generated. The difference is that the time when the current spike arrives is different. Each pulse intensity corresponds to a current spike time, and each current spike time corresponds to an analog quantity. The input voltage signal is encoded in sequence according to the time sequence of the current spikes.

[0013] It can be seen from the technical solution provided by the present invention that the above circuit can realize the time coding function based on the threshold transition characteristics and switching action of the memristor switch, fully utilizes the inherent characteristics of the memristor device, greatly simplifies the circuit design, and can better simulate the random excitation characteristics of biological neurons. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 It is a circuit structure for realizing time coding in the prior art;

[0016] Figure 2 A schematic diagram of a neuron circuit structure for time coding provided by an embodiment of the present invention;

[0017] Figure 3 This is a current spike simulation diagram generated by LTspice software simulation according to an embodiment of the present invention;

[0018] Figure 4 This is a simulation diagram of current spikes generated by different pulse inputs using LTspice software simulation in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and do not constitute a limitation of the present invention. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] like Figure 2 This is a schematic diagram of a neuron circuit structure for time coding provided by an embodiment of the present invention. The circuit includes a pre-resistor R1, a pre-capacitor C1, a post-capacitor C2, and a threshold-shift memristor TS, wherein:

[0021] The pre-resistor R1 and the pre-capacitor C1 are connected in series to form a CL loop, which is used to charge the pre-capacitor C1 and increase the front-end potential of the threshold transition memristor TS;

[0022] The threshold-shift memristor TS is connected in series with the pre-capacitor C1 to form a DL loop, which discharges the pre-capacitor C1.

[0023] During the period when the threshold transition memristor TS is turned on, the post capacitor C2 is charged to increase the potential at the other end of the threshold transition memristor TS, thereby ensuring that TS is turned on only once;

[0024] In the specific implementation, in the charging link, when the pulse is input from the input signal access point, that is, node 1, it first passes through the CL loop and enters the charging link. At this time, the threshold transition memristor TS is in the off state and has a large resistance value, which is recorded as R HRS , that is to say, the memristor at this time is equivalent to an open switch, with only a very small current flowing through it, which can be ignored, and no current flows through the post capacitor C2; when the CL loop makes the potential of the node on the right side of the pre resistor R1, that is, node 2, greater than the threshold voltage V of the threshold transition memristor TS th When , the charging phase ends; if Figure 3 The figure shows a current spike simulation diagram generated by LTspice software simulation according to an embodiment of the present invention. The Integrate part in the figure is the charging link.

[0025] In the process of generating current spike, when the CL loop makes the potential of node 2 greater than the threshold voltage V of the threshold transition memristor TS, th When the memristor is turned on, the resistance becomes smaller, and its resistance is recorded as R LRS , due to the state transition of the memristor, from the high resistance state R HRS Transformed into low resistance state R LRS , which is equivalent to the switch being closed, and the memristor changes very quickly. The current flowing through the post-capacitor C2 suddenly increases, resulting in a current spike. After generating and emitting a current spike, the memristor will be closed again; Figure 3 The Fire section shown is the link that generates the current spike. The charging link and the link that generates the current spike fully utilize the threshold transition characteristics of the memristor.

[0026] In the encoding phase, when a current spike occurs, that is, when the memristor is turned on, the current flowing through the memristor and the post-capacitor C2 increases, charging the post-capacitor C2, causing the potential of the node where the threshold-shift memristor TS and the post-capacitor C2 are connected, that is, node 3, to rise, which will make the voltage across the memristor less than the holding voltage V of the threshold-shift memristor TS. hold , so that the memristor is closed again; when the CL loop continues to charge, even if the potential of node 2 reaches the threshold voltage V th Since the potential of node 3 also increases, the potential difference between the two ends of the memristor cannot reach its threshold voltage V again. th , so the memristor cannot be turned on again and cannot generate a current spike again, that is to say, the entire circuit will only generate one current spike, such as Figure 4The figure shows a simulation diagram of current spikes generated by different pulse inputs using LTspice software according to an embodiment of the present invention. For inputs with different pulse intensities, only one current spike is generated. The difference is that the time when the current spike arrives is different. Each pulse intensity corresponds to a current spike time, and each current spike time corresponds to an analog value, such as Figure 4 As shown in FIG, the input voltages are 1.8 V, 1.9 V, 1.95 V, 1.97 V, and 2.0 V. The larger the input signal, the earlier the current spike arrives. The input voltage signal can be encoded sequentially according to the time sequence of the current spikes.

[0027] In the specific implementation, the requirements for the pre-capacitor C1 are: in order to better distinguish the time when current spikes are generated by different pulse intensities, the charging time of the CL loop should be extended, thereby extending the time when the current spike arrives. In the specific implementation, the size of the capacitor C1 is selected to be 10n~15n, and 10n is selected in this example.

[0028] In addition, the value of the pre-resistor R1 is less than the low resistance state R of the threshold transition memristor TS. LRS This is because when the memristor is turned on, the pre-capacitor C1 will discharge, as shown in Figure 2 The DL circuit shown in the figure, at the same time, the input will charge the charging circuit; only when R1*C1 <R LRS * C1, there will be enough time for the post capacitor C2 to charge to a sufficiently high potential. Otherwise, the potential of the post capacitor C2 will not be high enough, causing the circuit to emit two or more current spikes, and the encoding function cannot be realized. In the specific implementation, the value of the resistor R1 is selected to be 100Ω.

[0029] Since the post-capacitor C2 needs to quickly raise the potential within a limited time so that the memristor cannot be reopened after being closed, the value range of the post-capacitor C2 is 0.8n to 1.2n. In a specific implementation, the capacitor C2 is selected to be 1n.

[0030] The circuit described in the embodiment of the present invention utilizes a threshold transition device with volatile resistance, which can be reset spontaneously like a biological neuron, thereby eliminating the auxiliary reset circuit relied on in the neuron module based on non-volatile memristors and better simulating the random excitation characteristics of biological neurons.

[0031] It should be noted that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.

[0032] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art.

Claims

1. A neuron circuit for time coding, characterized in that: The circuit includes a pre-resistor R1, a pre-capacitor C1, a post-capacitor C2, and a threshold-shift memristor TS, wherein: The pre-resistor R1 and the pre-capacitor C1 are connected in series to form a CL loop, which is used to charge the pre-capacitor C1 and increase the front-end potential of the threshold transition memristor TS; The threshold-shift memristor TS is connected in series with the pre-capacitor C1 to form a DL loop, which discharges the pre-capacitor C1. During the period when the threshold transition memristor TS is turned on, the post capacitor C2 is charged to increase the potential at the other end of the threshold transition memristor TS, thereby ensuring that TS is turned on only once; In the charging phase, when the pulse is input from the input signal access point, that is, node 1, it first passes through the CL loop and enters the charging phase. At this time, the threshold transition memristor TS is in the off state and has a large resistance value, which is recorded as R HRS , that is to say, the memristor at this time is equivalent to an open switch, with only a very small current flowing through it, which can be ignored, and no current flows through the post capacitor C2; when the CL loop makes the potential of the node on the right side of the pre resistor R1, that is, node 2, greater than the threshold voltage V of the threshold transition memristor TS th When , the charging phase ends; In the process of generating current spike, when the CL loop makes the potential of node 2 greater than the threshold voltage V of the threshold transition memristor TS, th When the memristor is turned on, the resistance becomes smaller, and its resistance is recorded as R LRS , due to the state transition of the memristor, from the high resistance state R HRS Transformed into low resistance state R LRS , which is equivalent to the switch being closed, and the memristor changes very quickly. The current flowing through the post-capacitor C2 suddenly increases, resulting in a current spike. After generating and emitting a current spike, the memristor will be closed again; In the encoding phase, when a current spike occurs, that is, when the memristor is turned on, the current flowing through the memristor and the post-capacitor C2 increases, charging the post-capacitor C2, causing the potential of the node where the threshold-shift memristor TS and the post-capacitor C2 are connected, that is, node 3, to rise, which will make the voltage across the memristor less than the holding voltage V of the threshold-shift memristor TS. hold , so that the memristor is closed again; when the CL loop continues to charge, even if the potential of node 2 reaches the threshold voltage V th Since the potential of node 3 also increases, the potential difference between the two ends of the memristor cannot reach its threshold voltage V again. th Therefore, the memristor cannot be turned on again and cannot generate a current spike again. In other words, the entire circuit will only generate one current spike. For inputs with different pulse intensities, only one current spike will be generated. The difference is that the time when the current spike arrives is different. Each pulse intensity corresponds to a current spike time, and each current spike time corresponds to an analog quantity. The input voltage signal is encoded in sequence according to the time sequence of the current spikes.

2. The neuron circuit for time coding according to claim 1, characterized in that: In order to better distinguish the time when current spikes are generated by different pulse intensities, a large-capacitance pre-capacitor C1 should be selected to extend the charging time of the CL loop, thereby extending the time when the current spike arrives.

3. The time-coded neuron circuit according to claim 2, characterized in that: The size of the pre-capacitor C1 is selected to be 10n.

4. The neuron circuit for time coding according to claim 1, characterized in that: The value of the pre-resistor R1 is less than the threshold transition memristor TS low resistance state R LRS value.

5. The neuron circuit for time coding according to claim 4, characterized in that: The value of the pre-resistor R1 is selected to be 100Ω.

6. The neuron circuit for time coding according to claim 1, characterized in that: Since the post-capacitor C2 needs to quickly increase the potential within a limited time so that the memristor cannot be turned on again after being turned off, the post-capacitor C2 should be as small as possible.

7. The neuron circuit for time coding according to claim 6, characterized in that: The post capacitor C2 is selected to have a size of 1n.

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