Method of manufacturing a semiconductor structure

Abstract

The application relates to a preparation method of a semiconductor structure, comprising the following steps: providing a substrate; forming a first contact layer, a sacrifice layer and a first mask layer which are sequentially stacked from bottom to top on the substrate, and forming a first pattern on the first mask layer; forming a first sidewall pattern on the sidewall of the first pattern; patterning the first mask layer based on the first pattern and the first sidewall pattern; removing the first pattern and the first sidewall pattern; patterning the sacrifice layer based on the first mask layer after patterning to form a first groove in the sacrifice layer; forming a second contact pattern in the first groove; removing the sacrifice layer; and patterning the first contact layer based on the second contact pattern to form a bit line contact structure. The preparation method of the semiconductor structure can avoid bridging between the subsequently formed bit line contact structures.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] Traditional semiconductor structure fabrication methods, particularly in bit line contact (BLC) etching processes, require first forming a BLC mask layer on the material to be etched. Then, dry etching is performed on the mask layer to transfer the mask pattern onto it. The mask layer can be a spin-on hard mask composition (SOH), etc. The material to be etched is subsequently etched using the mask layer to form the bit line contact structure.

[0003] However, during the process of transferring the mask pattern to the mask layer, lateral etching can easily be caused to form holes in the mask layer, which can lead to the mask layer bending. This can affect the subsequent transfer of the pattern to the material to be etched by the mask layer, and ultimately can easily lead to bridging between bit line contact structures. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure fabrication method to address the problem in the prior art that easily causes lateral etching of the mask layer, forming holes, which leads to mask layer bending, affects the subsequent transfer of the pattern to the material to be etched, and ultimately easily leads to bridging between bit line contact structures.

[0005] To achieve the above objectives, in one respect, the present invention provides a method for preparing a semiconductor structure, comprising:

[0006] Provide substrate;

[0007] A first contact layer, a sacrificial layer, and a first mask layer are formed on the substrate in a sequence from bottom to top;

[0008] A first pattern is formed on the first mask layer;

[0009] A first sidewall pattern is formed on the sidewall of the first pattern;

[0010] The first mask layer is patterned based on the first pattern and the first sidewall pattern;

[0011] Remove the first graphic and the first sidewall graphic;

[0012] The sacrificial layer is patterned based on the patterned first mask layer to form a first trench in the sacrificial layer;

[0013] A second contact pattern is formed within the first trench;

[0014] Remove the sacrificial layer;

[0015] The first contact layer is patterned based on the second contact pattern to form a bit line contact structure.

[0016] In one embodiment, prior to removing the sacrificial layer, the method further includes:

[0017] A second mask layer is formed, which covers the second contact pattern and the sacrificial layer;

[0018] A second pattern is formed on the second mask layer;

[0019] A second sidewall pattern is formed on the sidewall of the second pattern;

[0020] The second mask layer is patterned based on the second pattern and the second sidewall pattern;

[0021] Remove the second graphic and the second sidewall graphic;

[0022] The sacrificial layer is patterned based on the patterned second mask layer to form a second trench in the sacrificial layer;

[0023] A third contact pattern is formed within the second trench;

[0024] In the step of patterning the first contact layer based on the second contact pattern, the first contact layer is patterned based on the second contact pattern to form a first bit line contact structure, and the third contact pattern is patterned based on the first contact layer to form a second bit line contact structure.

[0025] In one embodiment, the first mask layer and / or the second mask layer comprises a carbon-containing layer.

[0026] In one embodiment, forming the first pattern on the first mask layer includes:

[0027] A first photoresist layer is formed on the first mask layer;

[0028] The first photoresist layer is patterned to form the first pattern;

[0029] The process of forming a second pattern on the second mask layer includes:

[0030] A second photoresist layer is formed on the second mask layer;

[0031] The second photoresist layer is patterned to form the second pattern.

[0032] In one embodiment, before forming the first pattern on the first mask layer, the method further includes forming a first buffer layer, the first buffer layer being located between the first mask layer and the first pattern;

[0033] Before the first mask layer is patterned based on the first pattern and the first sidewall pattern, the method further includes patterning the first buffer layer based on the first pattern and the first sidewall pattern.

[0034] After removing the first graphic and the first sidewall graphic, the method further includes removing the first buffer layer after graphicization.

[0035] Before forming the second pattern on the second mask layer, the method further includes forming a second buffer layer, wherein the second buffer layer is located between the second mask layer and the second pattern;

[0036] Before the second mask layer is patterned based on the second pattern and the second sidewall pattern, the method further includes patterning the second buffer layer based on the second pattern and the second sidewall pattern.

[0037] After removing the second graphic and the second sidewall graphic, the method further includes removing the graphicized second buffer layer.

[0038] In one embodiment, the first buffer layer, the second buffer layer, the first mask layer, and the second mask layer are patterned using a dry etching process.

[0039] In one embodiment, forming a first sidewall pattern on the sidewall of the first pattern includes:

[0040] A first sidewall layer is formed, which covers the sidewalls, top, and exposed first buffer layer of the first pattern;

[0041] Remove the first sidewall layer located at the top of the first pattern and the portion of the first sidewall layer covering the first buffer layer;

[0042] The process of forming a second sidewall pattern on the sidewall of the second pattern includes:

[0043] A second sidewall layer is formed, which covers the sidewalls, top, and exposed second buffer layer of the second pattern;

[0044] Remove the second sidewall layer located on top of the second pattern and the portion of the second sidewall layer covering the second buffer layer.

[0045] In one embodiment, the first sidewall layer and / or the second sidewall layer are formed using an atomic layer deposition process.

[0046] In one embodiment, a dry etching process is used to remove the first sidewall layer located on top of the first pattern and a portion of the first sidewall layer covering the first buffer layer, and a dry etching process is used to remove the second sidewall layer located on top of the second pattern and a portion of the second sidewall layer covering the second buffer layer.

[0047] In one embodiment, forming the second contact pattern within the first trench includes:

[0048] A second contact layer is formed, which fills the first trench and covers the top of the sacrificial layer, with each portion of the top of the second contact layer flush with the top.

[0049] The second contact layer outside the first trench is removed to form the second contact pattern, the top of the second contact pattern being flush with the top of the sacrificial layer;

[0050] The formation of the third contact pattern within the second trench includes:

[0051] A third contact layer is formed, which fills the second trench and covers the top of the sacrificial layer and the top of the second contact pattern, with each portion of the top of the third contact layer flush with the top.

[0052] The third contact layer outside the second trench is removed to form the third contact pattern, the top of the third contact pattern being flush with the top of the sacrificial layer.

[0053] In one embodiment, before forming the first contact layer, sacrificial layer, and first mask layer stacked sequentially from bottom to top on the substrate, the method further includes:

[0054] A third trench is formed within the substrate;

[0055] An insulating layer is formed, which fills the third trench and covers the upper surface of the substrate, with the first contact layer located on the insulating layer.

[0056] In one embodiment, the sacrificial layer is removed using a wet etching process.

[0057] In one embodiment, the carbon-containing layer comprises an amorphous carbon layer.

[0058] In one embodiment, the substrate includes a silicon substrate, the insulating layer includes an oxide layer, the first contact layer includes a first silicon nitride layer and a polysilicon layer, the first silicon nitride layer being located between the substrate and the polysilicon layer; the second contact pattern, the third contact pattern, the first sidewall pattern and the second sidewall pattern all include oxide patterns, the sacrificial layer includes a second silicon nitride layer, and the first buffer layer and the second buffer layer both include silicon oxynitride layers.

[0059] In one embodiment, each of the first grooves and each of the second grooves are arranged in an array with at least two rows; in the column direction, each row of the first grooves and each row of the second grooves are staggered; in the row direction, the center line of each column of the second grooves is located between the center lines of two adjacent columns of the first grooves.

[0060] In one embodiment, it further includes:

[0061] Multiple bit lines are formed, with two adjacent bit lines used to connect the first bit line contact structure and the second bit line contact structure in the same column, respectively.

[0062] The method for preparing the semiconductor structure of the present invention has the following beneficial effects:

[0063] The semiconductor structure fabrication method of the present invention forms a first sidewall pattern on the sidewall of the first pattern. The first sidewall pattern can protect the first pattern, so that the first mask layer is prevented from being laterally etched when the first pattern is transferred onto the first mask layer. Thus, the pattern formed after the first mask layer is patterned can be consistent with the preset pattern, avoiding bridging between the bit line contact structures formed subsequently. Attached Figure Description

[0064] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0065] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application;

[0066] Figures 2a to 14 This is a top view and a corresponding cross-sectional view of the structure obtained in each step of the semiconductor structure fabrication method provided in an embodiment of this application;

[0067] Figure 15 This is a flowchart of some steps in the method for fabricating a semiconductor structure according to another embodiment of this application.

[0068] Explanation of reference numerals in the attached figures:

[0069] 11. Substrate; 12. Insulating layer; 13. First contact layer; 131. First silicon nitride layer; 132. Polysilicon layer; 20. Sacrificial layer; 31. First mask layer; 32. First buffer layer; 33. First photoresist layer; 331. First pattern; 34. First sidewall layer; 341. First sidewall pattern; 40. Second contact layer; 41. Second contact pattern; 42. Third contact pattern; 51. Second mask layer; 52. Second buffer layer; 531. Second pattern; 54. Second sidewall layer. Detailed Implementation

[0070] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0071] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0072] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0073] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0074] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0075] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0076] Please see Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0077] Step S11: Provide a substrate.

[0078] Step S12: A first contact layer, a sacrificial layer, and a first mask layer are formed on the substrate in a sequence from bottom to top.

[0079] Step S13: Form the first pattern on the first mask layer.

[0080] Step S14: Form a first sidewall pattern on the sidewall of the first pattern.

[0081] Step S15: Pattern the first mask layer based on the first pattern and the first sidewall pattern.

[0082] Step S16: Remove the first graphic and the first sidewall graphic.

[0083] Step S17: The sacrificial layer is patterned based on the patterned first mask layer to form a first trench in the sacrificial layer.

[0084] Step S18: A second contact pattern is formed in the first groove.

[0085] Step S19: Remove the sacrificial layer.

[0086] Step S20: Pattern the first contact layer based on the second contact pattern to form a bit line contact structure.

[0087] The semiconductor structure fabrication method in the above embodiments forms a first sidewall pattern on the sidewall of the first pattern. The first sidewall pattern can protect the first pattern, so that the first mask layer is prevented from being laterally etched when the first pattern is transferred onto the first mask layer. Thus, the pattern formed after the first mask layer is patterned can be consistent with the preset pattern, avoiding bridging between the bit line contact structures formed subsequently.

[0088] In step S11, please refer to Figure 1 Step S11 in the middle and Figures 2a to 2b Substrate 11 is provided.

[0089] Specifically, substrate 11 may include a silicon substrate. In other examples, substrate 11 may also include a silicon dioxide substrate or a silicon-on-insulator substrate, etc.

[0090] In step S12, please refer to Figure 1 Step S12 in the middle and Figures 2a to 2b A first contact layer 13, a sacrificial layer 20, and a first mask layer 31 are formed on a substrate 11, stacked sequentially from bottom to top.

[0091] Specifically, when forming a bit line contact structure using a semiconductor structure fabrication method, the first contact layer 13 may include a first silicon nitride layer 131 and a polysilicon layer 132, with the first silicon nitride layer 131 located between the substrate 11 and the polysilicon layer 132. The sacrificial layer 20 may include a second silicon nitride layer. The first mask layer 31 may include a carbon-containing layer, which may further include an amorphous carbon layer (ALC). The first contact layer 13, the sacrificial layer 20, and the first mask layer 31 may be formed using atomic layer deposition processes or similar methods.

[0092] In step S13, please refer to Figure 1 Step S13 in the middle and Figure 3a and 3b A first pattern 331 is formed on the first mask layer 31.

[0093] Specifically, the shape of the first pattern 331 can be set according to the shape of the semiconductor structure formed. For example, when the semiconductor structure is fabricated to form a bit line contact structure, the first pattern 331 can form multiple circular vias at preset positions. The size of each via can be the same, and they can be arranged in an array with a certain distance between each via.

[0094] In step S14, please refer to Figure 1 Step S14 in the middle and Figures 4a to 5b A first sidewall pattern 341 is formed on the sidewall of the first pattern 331.

[0095] Specifically, the material of the first sidewall pattern 341 can be selected based on the material of the first pattern 331 and the material of the first mask layer 31, so that when the first mask layer 31 is patterned, it can protect the first pattern 331 and prevent the first mask layer 31 from being laterally etched. For example, the first sidewall pattern 341 may include an oxide pattern. The shape of the first sidewall pattern 341 can be set according to the shape of the formed semiconductor structure. For example, when the semiconductor structure is circular from a top view, the top view of the first sidewall pattern 341 can be annular, and the width of the annulus can be set according to the diameter of the via on the first pattern 331 and the diameter of the semiconductor structure, so that the diameter of the inner circle of the first sidewall pattern 341 is equal to the diameter of the semiconductor structure.

[0096] In step S15, please refer to Figure 1 Step S15 in the middle and Figure 6a and 6b The first mask layer 31 is patterned based on the first pattern 331 and the first sidewall pattern 341.

[0097] Specifically, dry etching or other processes can be used to etch the first mask layer 31 using the first pattern 331 and the first sidewall pattern 341 as masks. After patterning, the first pattern 331 is transferred onto the first mask layer 31. Due to the protective effect of the first sidewall pattern 341 on the first pattern 331, it is less likely to cause lateral etching and the formation of holes in the first mask layer 31 during the etching process, thus avoiding bending of the first mask layer 31. The pattern on the first mask layer 31 can remain consistent with the preset pattern.

[0098] In step S16, please refer to Figure 1 Step S16 in the middle and Figure 7a and 7bRemove the first graphic 331 and the first sidewall graphic 341.

[0099] Specifically, wet etching and other processes can be used to remove the first pattern 331 and the first sidewall pattern 341.

[0100] In step S17, please refer to Figure 1 Step S17 in the middle and Figures 7a to 8b The first mask layer 31 is patterned to form the sacrificial layer 20, thereby forming the first trench 21 in the sacrificial layer 20.

[0101] Specifically, dry etching or similar processes can be used to etch the sacrificial layer 20 onto the patterned first mask layer 31 to transfer the first pattern 331 onto the sacrificial layer 20. After patterning, a first trench 21 is formed in the sacrificial layer 20. The diameter of the first trench 21 can be equal to the diameter of the inner circle of the first sidewall pattern 341. After the first trench 21 is formed, wet etching or similar processes can be used to remove the first mask layer 31.

[0102] In step S18, please refer to Figure 1 Step S18 in the middle and Figures 9a to 10b A second contact pattern 41 is formed within the first groove 21.

[0103] Specifically, the second contact pattern 41 may include an oxide pattern. The second contact pattern 41 may fill the first trench 21, and the top of the second contact pattern 41 may be flush with the top of the sacrificial layer 20.

[0104] In step S19, please refer to Figure 1 Step S19 in the middle and Figures 13a to 13b Remove sacrificial layer 20.

[0105] Specifically, the sacrificial layer 20 can be removed using processes such as wet etching.

[0106] In step S20, please refer to Figure 1 Step S20 in the middle and Figure 14 The first contact layer 13 is patterned based on the second contact pattern 41 to form a bit line contact structure.

[0107] Specifically, the first contact layer 13 can be etched based on the second contact pattern 41 using processes such as dry etching. Specifically, the first silicon nitride layer 131 and the polysilicon layer 132 can be etched sequentially to form a bit line contact structure.

[0108] In some examples, please refer to Figure 15 The process may also include the following steps before step S19:

[0109] Step S31: Form a second mask layer, which covers the second contact pattern and the sacrificial layer.

[0110] Step S32: Form a second pattern on the second mask layer.

[0111] Step S33: A second sidewall pattern is formed on the sidewall of the second pattern.

[0112] Step S34: Pattern the second mask layer based on the second pattern and the second sidewall pattern.

[0113] Step S35: Remove the second graphic and the second sidewall graphic.

[0114] Step S36: The sacrificial layer is patterned based on the patterned second mask layer to form a second trench in the sacrificial layer.

[0115] Step S37: A third contact pattern is formed in the second trench.

[0116] For details, please refer to Figures 11a to 14 ( Figure 12b and 13b The ones are respectively Figure 12a and 13a (Cross-sectional view along the X direction) After forming the second contact pattern 41, a second mask layer 51 can be formed on the second contact pattern 41 and the sacrificial layer 20 using methods such as atomic layer deposition. The second mask layer 51 may include a carbon-containing layer, specifically an amorphous carbon layer. Then, a second pattern 531 is formed on the second mask layer 51. When the semiconductor structure fabrication method forms a bit line contact structure, multiple circular vias can be formed in the second pattern 531. These circular vias can be arranged in an array, and the vias in the second pattern 531 can be staggered with the vias in the first pattern 331. Figures 3a to 10aThe dashed circular vias in the figure can represent the circular vias in the unformed second pattern 531. A second sidewall pattern (not shown) is formed on the sidewall of the second pattern 531. The function of the second sidewall pattern is similar to that of the first sidewall pattern 341. The second sidewall pattern may include an oxide pattern. The second mask layer 51 can be patterned based on the second pattern 531 and the second sidewall pattern using a dry etching process or similar method. During the patterning process, the second sidewall pattern protects the second pattern 531, preventing the second mask layer 51 from forming holes through lateral etching, thereby preventing the second mask layer 51 from bending and ensuring that the pattern on the second mask layer 51 remains consistent with the preset pattern. Then, the second pattern 531 and the second sidewall pattern can be removed using a wet etching process or similar method. Then, the sacrificial layer 20 can be patterned based on the patterned second mask layer 51 using a dry etching process or similar method to form a second trench in the sacrificial layer 20. A third contact pattern 42 is formed in the second trench. The third contact pattern 42 may include an oxide pattern. The third contact pattern 42 can fill the second trench, and the top of the third contact pattern 42 can be flush with the top of the sacrificial layer 20. Thus, the second contact pattern 41 and the third contact pattern 42 are formed in the sacrificial layer 20. After removing the sacrificial layer 20, the second contact pattern 41 and the third contact pattern 42 are retained as a mask for the first contact layer 13. In this embodiment, the first contact layer 13 can be patterned based on the second contact pattern 41 to form a first bit-line contact structure, and the first contact layer 13 can be patterned based on the third contact pattern 42 to form a second bit-line contact structure. The first bit-line contact structure and the second bit-line contact structure can be arranged alternately.

[0117] For example only, each first groove 21 and each second groove are arranged in an array with at least two rows. In the column direction, each row of first grooves 21 and each row of second grooves are staggered. In the row direction, the center line of each column of second grooves is located between the center lines of two adjacent columns of first grooves 21.

[0118] In some examples, the first mask layer 31 and / or the second mask layer 51 may include a carbon-containing layer. The carbon-containing layer has higher hardness than SOH, which further protects the first mask layer 31 and the second mask layer 51 from lateral etching that forms holes during the patterning process. This prevents bridging between adjacent bit line contact structures after the subsequent formation of the first bit line contact structure and the second bit line contact structure.

[0119] In some examples, please refer to Figures 2a to 3b Step S13 may include: forming a first photoresist layer 33 on the first mask layer 31; and patterning the first photoresist layer 33 to form a first pattern 331. Please refer to [link to previous text]. Figure 11a and 11bStep S32 may include: forming a second photoresist layer on the second mask layer 51; and patterning the second photoresist layer to form a second pattern 531.

[0120] Specifically, the first photoresist layer 33 and the second photoresist layer can be formed by methods such as spin coating or slot coating. Then, the first photoresist layer 33 and the second photoresist layer are exposed, developed, and baked to form a first pattern 331 on the first photoresist layer 33 and a second pattern 531 on the second photoresist layer.

[0121] In some examples, please refer to Figures 5a to 7b Before step S13, a first buffer layer 32 may be formed, located between the first mask layer 31 and the first pattern 331. Before step S15, the first buffer layer 32 may be patterned based on the first pattern 331 and the first sidewall pattern 341. After step S16, the patterned first buffer layer 32 may be removed.

[0122] Before step S32, a second buffer layer 52 may be formed, located between the second mask layer 51 and the second pattern 531. Before step S34, the second buffer layer 52 may be patterned based on the second pattern 531 and the second sidewall pattern. After step S35, the patterned second buffer layer 52 may be removed.

[0123] Specifically, both the first buffer layer 32 and the second buffer layer 52 may include a silicon oxynitride layer. The first buffer layer 32 and the second buffer layer 52 can be formed using processes such as atomic layer deposition. The first buffer layer 32 and the second buffer layer 52 can be patterned using a dry etching process. The patterned first buffer layer 32 and the second buffer layer 52 can be removed using processes such as wet etching.

[0124] In some examples, please refer to Figures 4a to 5b Step S14 includes: forming a first sidewall layer 34, the first sidewall layer 34 covering the sidewalls, top, and exposed first buffer layer 32 of the first pattern 331. Removing the portion of the first sidewall layer 34 located on top of the first pattern 331 and covering the first buffer layer 32. See also... Figures 11a to 11b Step S33 includes: forming a second sidewall layer 54, the second sidewall layer 54 covering the sidewalls, top and exposed second buffer layer 52 of the second pattern 531; removing the second sidewall layer 54 located on the top of the second pattern 531 and the portion of the second sidewall layer 54 covering the second buffer layer 52.

[0125] Specifically, atomic layer deposition and other processes can be used to form the first sidewall layer 34 and / or the second sidewall layer 54. Dry etching and other methods can be used to remove the first sidewall layer 34 located on top of the first pattern 331 and the portion of the first sidewall layer 34 covering the first buffer layer 32, and to remove the second sidewall layer 54 located on top of the second pattern 531 and the portion of the second sidewall layer 54 covering the second buffer layer 52.

[0126] In some examples, please refer to Figures 9a to 10b Step S18 includes: forming a second contact layer 40, the second contact layer 40 filling the first trench 21 and covering the top of the sacrificial layer 20, with each portion of the top of the second contact layer 40 flush with the top; removing the second contact layer 40 outside the first trench 21 to form a second contact pattern 41, with the top of the second contact pattern 41 flush with the top of the sacrificial layer 20. Similarly, step S37 includes: forming a third contact layer (not shown), the third contact layer filling the second trench and covering the top of the sacrificial layer 20 and the top of the second contact pattern 41, with each portion of the top of the third contact layer flush with the top; removing the third contact layer outside the second trench to form a third contact pattern 42, with the top of the third contact pattern 42 flush with the top of the sacrificial layer 20.

[0127] Specifically, the second contact layer 40 and the third contact layer can be formed using processes such as atomic layer deposition. The second contact layer 40 outside the first trench 21 and the third contact layer outside the second trench can be removed using processes such as dry etching.

[0128] In some examples, please refer to Figure 2b Before step S12, the process further includes: forming a third trench within the substrate 11; forming an insulating layer 12 that fills the third trench and covers the upper surface of the substrate 11; and placing a first contact layer 13 on the insulating layer 12. The insulating layer 12 may include an oxide layer, etc. The third trench may be formed by etching the substrate 11 using a process such as dry etching. The insulating layer 12 may be formed using a process such as atomic layer deposition.

[0129] In some examples, the method for fabricating the semiconductor structure further includes forming multiple bit lines, wherein two adjacent bit lines are used to connect a first bit line contact structure in the same column and a second bit line contact structure in the same column, respectively.

[0130] It should be understood that, although Figure 1 and 15 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 and 15At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0131] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A first contact layer, a sacrificial layer, and a first mask layer are formed on the substrate in a sequence from bottom to top; A first pattern is formed on the first mask layer; A first sidewall pattern is formed on the sidewall of the first pattern; The first mask layer is patterned based on the first pattern and the first sidewall pattern; Remove the first graphic and the first sidewall graphic; The sacrificial layer is patterned based on the patterned first mask layer to form a first trench in the sacrificial layer; A second contact pattern is formed within the first trench; Remove the sacrificial layer; The first contact layer is patterned based on the second contact pattern to form a bit line contact structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before removing the sacrificial layer, the method further includes: A second mask layer is formed, which covers the second contact pattern and the sacrificial layer; A second pattern is formed on the second mask layer; A second sidewall pattern is formed on the sidewall of the second pattern; The second mask layer is patterned based on the second pattern and the second sidewall pattern; Remove the second graphic and the second sidewall graphic; The sacrificial layer is patterned based on the patterned second mask layer to form a second trench in the sacrificial layer; A third contact pattern is formed within the second trench; In the step of patterning the first contact layer based on the second contact pattern, the first contact layer is patterned based on the second contact pattern to form a first bit line contact structure, and the first contact layer is patterned based on the third contact pattern to form a second bit line contact structure.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The first mask layer and / or the second mask layer include a carbon-containing layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The carbon-containing layer includes an amorphous carbon layer.

5. The method for preparing a semiconductor structure according to claim 2, characterized in that, The process of forming the first pattern on the first mask layer includes: A first photoresist layer is formed on the first mask layer; The first photoresist layer is patterned to form the first pattern; The process of forming a second pattern on the second mask layer includes: A second photoresist layer is formed on the second mask layer; The second photoresist layer is patterned to form the second pattern.

6. The method for preparing a semiconductor structure according to claim 2, characterized in that, Before forming the first pattern on the first mask layer, the method further includes forming a first buffer layer, wherein the first buffer layer is located between the first mask layer and the first pattern; Before the first mask layer is patterned based on the first pattern and the first sidewall pattern, the method further includes patterning the first buffer layer based on the first pattern and the first sidewall pattern. After removing the first graphic and the first sidewall graphic, the method further includes removing the first buffer layer after graphicization. Before forming the second pattern on the second mask layer, the method further includes forming a second buffer layer, wherein the second buffer layer is located between the second mask layer and the second pattern; Before the second mask layer is patterned based on the second pattern and the second sidewall pattern, the method further includes patterning the second buffer layer based on the second pattern and the second sidewall pattern. After removing the second graphic and the second sidewall graphic, the method further includes removing the graphicized second buffer layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The first buffer layer, the second buffer layer, the first mask layer, and the second mask layer are patterned using a dry etching process.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that, The step of forming a first sidewall pattern on the sidewall of the first pattern includes: A first sidewall layer is formed, which covers the sidewalls, top, and exposed first buffer layer of the first pattern; Remove the first sidewall layer located at the top of the first pattern and the portion of the first sidewall layer covering the first buffer layer; The process of forming a second sidewall pattern on the sidewall of the second pattern includes: A second sidewall layer is formed, which covers the sidewalls, top, and exposed second buffer layer of the second pattern; Remove the second sidewall layer located on top of the second pattern and the portion of the second sidewall layer covering the second buffer layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The first sidewall layer and / or the second sidewall layer are formed using an atomic layer deposition process.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that, A dry etching process is used to remove the first sidewall layer located on top of the first pattern and a portion of the first sidewall layer covering the first buffer layer. A dry etching process is also used to remove the second sidewall layer located on top of the second pattern and a portion of the second sidewall layer covering the second buffer layer.

11. The method for preparing a semiconductor structure according to claim 6, characterized in that, Before forming the first contact layer, sacrificial layer, and first mask layer stacked sequentially from bottom to top on the substrate, the method further includes: A third trench is formed within the substrate; An insulating layer is formed, which fills the third trench and covers the upper surface of the substrate, with the first contact layer located on the insulating layer.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The substrate includes a silicon substrate, the insulating layer includes an oxide layer, the first contact layer includes a first silicon nitride layer and a polysilicon layer, the first silicon nitride layer being located between the substrate and the polysilicon layer; the second contact pattern, the third contact pattern, the first sidewall pattern and the second sidewall pattern all include oxide patterns, the sacrificial layer includes a second silicon nitride layer, and the first buffer layer and the second buffer layer both include silicon oxynitride layers.

13. The method for preparing a semiconductor structure according to claim 2, characterized in that, The process of forming a second contact pattern within the first trench includes: A second contact layer is formed, which fills the first trench and covers the top of the sacrificial layer, with each portion of the top of the second contact layer flush with the top. The second contact layer outside the first trench is removed to form the second contact pattern, the top of the second contact pattern being flush with the top of the sacrificial layer; The formation of the third contact pattern within the second trench includes: A third contact layer is formed, which fills the second trench and covers the top of the sacrificial layer and the top of the second contact pattern, with each portion of the top of the third contact layer flush with the top. The third contact layer outside the second trench is removed to form the third contact pattern, the top of the third contact pattern being flush with the top of the sacrificial layer.

14. The method for preparing a semiconductor structure according to claim 2, characterized in that, Also includes: Multiple bit lines are formed, with two adjacent bit lines used to connect the first bit line contact structure and the second bit line contact structure in the same column, respectively.

15. The method for preparing a semiconductor structure according to claim 1, characterized in that, The sacrificial layer was removed using a wet etching process.

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