A method for reducing current impact during motor speed switching

Abstract

The present invention relates to a method for reducing the current impact of motor speed switching, which is achieved by designing a direct digital frequency synthesizer DDS in an FPGA, combining a method of subdividing a reference frequency to generate an adjustable reference frequency, and matching a motor control power supply to make the speed change of a gyro motor smoother, thereby minimizing the current impact when the speed changes, so as to ultimately reduce the interference torque and reduce the gyro drift. It has been proved through experiments that in the process of mutual conversion between high and low speeds, the jump of the current is well suppressed, truly realizing the smooth transition of the speed, and effectively reducing the interference torque.

Description

Technical Field

[0001] The invention belongs to the technical field of motor control, and in particular to a method for reducing current impact of motor speed switching. Background Art

[0002] The motor speed control is to stabilize the motor at the set speed by phase locking. The motor speed is determined by the reference frequency, and the speed adjustment is also achieved by changing the reference frequency and the corresponding voltage. The reference frequency is generated by dividing the reference clock with a counter to obtain the reference frequency standard. The formula is as follows:

[0003]

[0004] It can be seen that the reference frequency Freq can be changed by changing the frequency division coefficient Divider, which is generated in the FPGA. When the motor speed is changed, directly changing Freq to the specified frequency will produce a large current jump, generate a large interference torque, and affect the accuracy of the gyroscope.

[0005] For voltage adjustment, FPGA can be used to generate a PWM width modulation wave with controllable duty cycle. The duty cycle of the width modulation wave can be adjusted by programming. The DC voltage generated after filtering is input into the adjustment end of the power module to control the output voltage of the power module to change according to the designed curve. The width modulation wave is generated by counting the input clock by the counter. Assuming that the width modulation wave period is x clocks and the positive pulse width is z clocks, the duty cycle is:

[0006] R=z / x

[0007] The corresponding output voltage function is V=K0×z / x, where K0 is the proportionality coefficient of the output voltage to the duty cycle.

[0008] It can be seen from the formula that the duty cycle can be adjusted by changing the positive pulse width n.

[0009] In order to ensure that the motor speed is always synchronized, the reference frequency and voltage should always maintain a certain proportional relationship. Because the reference frequency is adjusted by changing the Divider as the denominator, and the voltage is adjusted by changing the z as the numerator, this method is difficult to achieve the matching of the reference frequency and voltage. The mismatch between the reference frequency and voltage leads to unstable motor speed, which directly affects the momentum of the gyroscope and causes a large gyro drift. Summary of the invention

[0010] The purpose of the present invention is to overcome the shortcomings of the prior art and propose a method for reducing the current impact of motor speed switching. By constructing a direct digital frequency synthesizer DDS in an FPGA to generate an adjustable reference frequency and matching the motor control power supply, the speed change of the gyro motor is made smoother, thereby reducing the current impact when the speed changes, so as to ultimately reduce the interference torque.

[0011] The present invention solves the technical problem by adopting the following technical solutions:

[0012] A method for reducing the current impact of motor speed switching comprises the following steps:

[0013] Step 1: construct a direct digital frequency synthesizer (DDS) in FPGA to generate an adjustable reference frequency;

[0014] Step 2: Output a PWM width modulation wave with adjustable duty cycle in the FPGA to control the voltage output and match the motor control power supply;

[0015] Step 3: According to the relationship between the reference frequency and the power supply, adjust the speed change of the motor.

[0016] Moreover, the direct digital frequency synthesizer DDS includes a reference clock Fref, an n-bit phase accumulator and a memory ROM, wherein the input of the n-bit phase accumulator is a frequency control word K, the output of the n-bit phase accumulator is connected to the memory ROM, the reference clock Fref is connected to the n-bit phase accumulator, the output of the n-bit phase accumulator is n-bit wide data, the n-bit accumulator output is used as the addressing address of the ROM, and the data stored in the memory ROM is read.

[0017] Moreover, the method for reading the data stored in the memory ROM is to use the corresponding number of address lines for reading according to the number of bytes of data stored in the memory ROM, and at the same time take a number of bits of data corresponding to the n-bit phase accumulator as the addressing address, and read all the data in the memory ROM once every time the n-bit phase accumulator overflows, select any address line, and obtain a square wave, and the frequency of the square wave is the overflow rate of the n-bit phase accumulator.

[0018] Furthermore, the reference clock Fref is generated by: the clock input by the FPGA is frequency-multiplied by an enhanced phase-locked loop inside the FPGA to obtain a high-frequency clock.

[0019] Moreover, generating the reference frequency in step 1 comprises the following steps:

[0020] Step 1.1, reset the n-bit phase accumulator, and determine whether it is in the motor startup process. If it is in the motor startup process, the phase control word K is the high-speed control word, otherwise proceed to step 1.2;

[0021] Step 1.2, determine whether the frequency control signal is high, if the frequency control signal is high, proceed to step 1.3, otherwise proceed to step 1.4;

[0022] Step 1.3, determine whether the motor is in the acceleration stage, if it is in the acceleration stage, then set n = n + 1; the phase control word K = f (nT), otherwise the phase control word K is the high-speed control word;

[0023] Step 1.4, determine whether the motor is in the deceleration stage. If it is in the deceleration stage, set n=n+1; the phase control word K=f(nT); otherwise, the phase control word K is the low-speed control word.

[0024] Moreover, the specific implementation method of judging whether the frequency control signal is high in step 1.2 is: judging whether the reference frequency Freq is at a high level, if the reference frequency Freq is at a high level, the frequency control signal is high, otherwise the frequency control signal is low.

[0025] Moreover, the specific implementation method of step 2 is: according to the change ratio of the frequency change word K, the number of clocks z of the positive pulse width is changed by a corresponding ratio:

[0026]

[0027] Among them, x is the number of clocks in the width modulation wave period, z is the number of clocks in the positive pulse width, Fref is the reference clock, K0 is the proportional coefficient of the output voltage to the duty cycle, and K1 is the proportional coefficient of the motor voltage to the reference frequency.

[0028] Moreover, the specific implementation method of step 3 is: adjusting the rotation speed through the reference frequency generated in step 1 and the corresponding voltage in step 2.

[0029] The advantages and positive effects of the present invention are:

[0030] The present invention designs a direct digital frequency synthesizer DDS in FPGA, combines the method of subdividing the reference frequency to generate an adjustable reference frequency, and matches the motor control power supply at the same time, so that the speed change of the gyro motor is smoother, thereby minimizing the impact of the current when the speed changes, so as to ultimately reduce the interference torque and reduce the gyro drift. It is proved through experiments that in the process of mutual conversion between high and low speeds, the jump of the current is well suppressed, the smooth transition of the speed is truly realized, and the interference torque is effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is the basic structural block diagram of direct digital frequency synthesizer DDS;

[0032] Figure 2This is the block diagram of the internal phase-locked loop of the FPGA;

[0033] Figure 3 A schematic diagram of a program for realizing frequency multiplication of a phase-locked loop in an FPGA of the present invention;

[0034] Figure 4 A flow chart for generating a reference frequency of the present invention;

[0035] Figure 5 The current variation curve of the direct speed change in the embodiment of the present invention;

[0036] Figure 6 This is a curve showing the change of current using the method in the embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention is further described in detail below with reference to the accompanying drawings.

[0038] According to the prior art, it is necessary to control the change of the reference clock Freq so that the motor speed changes slowly and the current jump is small. At the same time, it is also necessary to match the motor voltage so as not to affect the gyroscope's momentum and reduce gyro drift.

[0039] A method for reducing the current impact of motor speed switching comprises the following steps:

[0040] Step 1: Build a direct digital frequency synthesizer (DDS) in FPGA to generate an adjustable reference frequency.

[0041] In FPGA, the Divider changes with integers, so the frequency change is large. For example, when the reference frequency changes around 10KHz (generally the reference frequency is between 8KHz-18KHz), fclk is 100MHz, and the Divider is 10000 and 9999, the generated frequency difference is 1.0001Hz, resulting in a large change in speed and a large change in motor current. In addition, it can be seen that in the process of the Divider changing with integers, it is very difficult to change the reference frequency at a uniform speed.

[0042] In order to make the reference frequency change at a uniform speed, a direct digital frequency synthesizer (DDS) is used to achieve this. Figure 1 As shown in Figure 1, the core of DDS is an n-bit phase accumulator. The input frequency control word K implements phase accumulation under the control of the reference clock. The magnitude of the phase increase is the input frequency control word K. When the accumulator count is greater than 2, nWhen the phase accumulator overflows, it is equivalent to doing a modulo remainder operation. The overflow rate is the frequency of the output signal. The larger the phase increase, the higher the overflow rate of the phase accumulator, and the higher the frequency of the output signal. The higher bits of the phase accumulator are intercepted as the reading address of the waveform memory, so that the pre-stored data can be read from the memory ROM.

[0043] For the generation of square waves, a digital-to-analog converter (DAC) and a filter (LPF) can be omitted. The direct digital frequency synthesizer DDS constructed by the present invention includes a reference clock Fref, an n-bit phase accumulator and a memory ROM, wherein the input of the n-bit phase accumulator is a frequency control word K, the output end of the n-bit phase accumulator is connected to the memory ROM, the reference clock Fref is connected to the n-bit phase accumulator, the n-bit phase accumulator outputs n-bit wide data, and the n-bit accumulator output is used as the addressing address of the ROM to read the data stored in the memory ROM.

[0044] The method of reading the data stored in the memory ROM is to use the corresponding number of address lines to read according to the number of bytes of data stored in the memory ROM, and take the corresponding bits of data of the n-bit phase accumulator as the addressing address. For example, 128 bytes of value '255' and 128 bytes of value '0' are stored in the 256-byte memory ROM. For the 256-byte memory ROM, 8 address lines are required. Take the high 8 bits of the n-bit accumulator output as the addressing address. Every time the accumulator overflows, all the data in the memory ROM is read once, that is, 128 bytes of "255" and 128 bytes of "0" will be output on the address line output by the memory ROM in sequence. Selecting any address line can get a square wave, and the square wave frequency is the overflow rate of the n-bit phase accumulator.

[0045] The waveform frequency Freq generated by the direct digital frequency synthesizer DDS is:

[0046] Freq=Fref*K / 2 n

[0047] Among them, Fref is the reference clock, n is the number of bits of the accumulator, and K is the frequency change word. It can be concluded that the frequency change is related to the reference clock Fref, the number of bits of the accumulator n, and the frequency control word K. In order to obtain a smaller frequency change, it is necessary to increase the reference clock Fref and the number of bits of the accumulator n, and reduce the change of K △K. Generally, the reference clock Fref and the number of bits of the accumulator n are fixed, and only K is relatively easy to change. Therefore, to change the reference frequency, it is necessary to change the frequency control word K.

[0048] Therefore, under the condition that the bit number n and the reference clock Fref are known, the frequency of the waveform can be changed by changing the frequency change word K. When K = 1, it is the lowest output frequency and the minimum frequency step. Assuming that the reference clock Fref is 100MHz and the bit number n is 32, the minimum step is 0.023Hz.

[0049] FPGA can generate 32-bit wide registers, so the number of bits of the accumulator can be set to 32, which can meet the requirements of frequency subdivision.

[0050] When the system clock is higher, the range of system phase variation is larger, so a higher system clock is needed. In the circuit, the input clock used by the FPGA is 20MHz, which can be multiplied to 100MHz through a phase-locked loop in the FPGA.

[0051] The FPGA chip used in the present invention is the Cyclone device Ep1c6 of ALTERA. It has two built-in enhanced phase-locked loops, and its structure is as follows Figure 2 As shown: FPGA can generate 32-bit wide registers, so the number of bits of the accumulator can be set to 32, which can meet the requirements of frequency subdivision.

[0052] The phase-locked loop circuit has a clock synthesis function, and the actual internal clock can be different from the input clock frequency. Each phase-locked loop can provide three outputs with different frequencies. The phase-locked loop provides two division counters with proportional factors a and b respectively, and the post-proportional counters (g0, g1, and e) of a and b can be set to any number between 1 and 32.

[0053] The method for generating the reference clock Fref is as follows: the clock input by the FPGA is multiplied by the enhanced phase-locked loop inside the FPGA to obtain a high-frequency clock. In order to provide a 100MHz clock as the reference clock of the DDS, the 20MHz input clock needs to be multiplied by 5. Here, the ratio of the phase-locked loop is set to 5. In the FPGA, the implementation of the phase-locked loop is as follows Figure 3 As shown in Figure 1. The C0 port can output 100MHz as the reference clock of DDS.

[0054] In the embedded memory ROM of FPGA, 256 bytes of data are stored, which are 128 bytes of data "255" and 128 bytes of data "0" to form a cycle of square wave. Design 32-bit counter to form phase accumulator, output the value of the accumulator with 32-bit width, of which the highest 8 bits are used as the address of memory ROM. When the accumulator increases with △K as the accumulation amount, in each cycle of phase accumulator overflow, 256 bytes of data in ROM are read cyclically. In this way, the output of ROM is 8-bit data, and the required square wave can be obtained by taking any data line as output. Among them, as the frequency control word changes, the frequency of the output square wave also changes accordingly.

[0055] In the program, the time interval T for speed change is designed. The speed change is controlled within each set time interval. In the nth time interval, the Freq signal is first detected. If it is a high level, that is, a high-speed control signal, it is determined whether it is in the acceleration period. If it is, the frequency is changed. If not, the speed is kept at a high speed and the reference frequency is kept at a stable state. The same is true for the deceleration and low-speed steady speed stages. In this way, several stages are separated and different operations are performed on the phase control word K. The process of generating the reference frequency is as follows Figure 4 As shown:

[0056] Step 1.1, reset the n-bit phase accumulator, and determine whether it is in the motor startup process. If it is in the motor startup process, the phase control word K is the high-speed control word, otherwise proceed to step 1.2.

[0057] Step 1.2: Determine whether the frequency control signal is high. If the frequency control signal is high, proceed to step 1.3; otherwise, proceed to step 1.4.

[0058] Step 1.3, determine whether the motor is in the acceleration stage, if it is in the acceleration stage, then set n=n+1; the phase control word K=f(nT), otherwise the phase control word K is the high-speed control word.

[0059] Step 1.4, determine whether the motor is in the deceleration stage. If it is in the deceleration stage, set n=n+1; the phase control word K=f(nT); otherwise, the phase control word K is the low-speed control word.

[0060] Through DDS technology, the reference frequency can be achieved by programming the frequency control word K. During the acceleration and deceleration stages, the minimum step size of the reference frequency change can be 0.023Hz, achieving the purpose of frequency subdivision.

[0061] Step 2: Output a PWM width modulation wave with adjustable duty cycle in the FPGA to control the voltage output and match the motor control power supply.

[0062] Assuming that the relationship between the motor voltage and the reference frequency is V = K1*Freq, the number of clocks z of the positive pulse width is changed by the change ratio of the frequency change word K:

[0063]

[0064] Among them, x is the number of clocks in the width modulation wave period, z is the number of clocks in the positive pulse width, Fref is the reference clock, K0 is the proportional coefficient of the output voltage to the duty cycle, and K1 is the proportional coefficient of the motor voltage to the reference frequency. The ratio of n to K is a constant, so when K changes, n is changed accordingly at the same time, which can easily adjust the duty cycle and ensure the matching of the reference frequency and the motor voltage.

[0065] Step 3: According to the relationship between the reference frequency and the power supply, the reference frequency generated in step 1 and the corresponding voltage in step 2 are used to adjust the rotation speed.

[0066] According to the above-mentioned method for reducing the current impact of motor speed switching, experiments were carried out using a method of directly changing the speed and a method of using a subdivided reference frequency, and the motor current was measured and recorded to prove the effect of the present invention.

[0067] like Figure 5 It is the current curve recorded during the high and low speed change of the motor under direct speed change, such as Figure 6 is the current curve recorded using the subdivided reference frequency method. Figure 6 It can be seen that in the process of directly changing the speed, the current changes dramatically, especially in the process from low to high, the maximum current jump reaches more than 300 mA. However, using the subdivided reference frequency method, the current changes more smoothly, there is no large current jump at the beginning and end of the speed change, and the maximum change does not exceed 2 mA.

[0068] Experiments have shown that the subdivision reference frequency method implemented by DDS has achieved significant results in improving the drastic changes in motor current during variable speed, and has a positive effect on reducing the influence of interference torque on gyroscope drift during variable speed.

[0069] The present invention uses a method of subdividing the reference frequency. Through circuit and program design, the minimum frequency change of the reference frequency can reach 0.023Hz, and it can completely match the voltage. Through experiments, it is proved that in the process of high and low speed conversion, the jump of current is well suppressed, the smooth transition of speed is truly realized, and the interference torque is effectively reduced.

[0070] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manner. Any other implementation manners derived by those skilled in the art based on the technical solution of the present invention also fall within the scope of protection of the present invention.

Claims

1. A method for reducing the current impact of motor speed switching, characterized in that: The following steps are involved: Step 1: construct a direct digital frequency synthesizer (DDS) in FPGA to generate an adjustable reference frequency; Generating the reference frequency includes the following steps: Step 1.1, reset the n-bit phase accumulator, and determine whether it is in the motor startup process. If it is in the motor startup process, the phase control word K is the high-speed control word, otherwise proceed to step 1.2; Step 1.2, determine whether the frequency control signal is high, if the frequency control signal is high, proceed to step 1.3, otherwise proceed to step 1.4; Step 1.3, determine whether the motor is in the acceleration stage, if it is in the acceleration stage, then set n = n + 1; the phase control word K = f (nT), otherwise the phase control word K is the high-speed control word; Step 1.4, determine whether the motor is in the deceleration stage, if it is in the deceleration stage, set n=n+1; the phase control word K=f(nT), otherwise the phase control word K is the low speed control word; Step 2: Output a PWM width modulation wave with adjustable duty cycle in the FPGA to match the motor control power supply; The number of clocks z of the positive pulse width is changed by the change ratio of the frequency change word K: Wherein, x is the number of clocks in the width modulation wave period, z is the number of clocks in the positive pulse width, Fref is the reference clock, K0 is the proportional coefficient of the output voltage to the duty cycle, and K1 is the proportional coefficient of the motor voltage to the reference frequency; Step 3: According to the relationship between the reference frequency and the power supply, adjust the speed change of the motor.

2. The method for reducing the current impact of motor speed switching according to claim 1, characterized in that: The direct digital frequency synthesizer DDS includes a reference clock Fref, an n-bit phase accumulator and a memory ROM, wherein the input of the n-bit phase accumulator is a frequency control word K, the output end of the n-bit phase accumulator is connected to the memory ROM, the reference clock Fref is connected to the n-bit phase accumulator, the output of the n-bit phase accumulator is n-bit wide data, the output of the n-bit accumulator is used as the addressing address of the ROM, and the data stored in the memory ROM is read.

3. The method for reducing the current impact of motor speed switching according to claim 2, characterized in that: The method for reading data stored in the memory ROM is to use a corresponding number of address lines to read according to the number of bytes of data stored in the memory ROM, and at the same time take a number of bits of data corresponding to the n-bit phase accumulator as the addressing address, and read all the data in the memory ROM once every time the n-bit phase accumulator overflows, select any address line, and obtain a square wave, and the frequency of the square wave is the overflow rate of the n-bit phase accumulator.

4. The method for reducing the current impact of motor speed switching according to claim 2, characterized in that: The method for generating the reference clock Fref is as follows: the clock input to the FPGA is frequency-multiplied by an enhanced phase-locked loop inside the FPGA to obtain a high-frequency clock.

5. The method for reducing the current impact of motor speed switching according to claim 1, characterized in that: The specific implementation method of judging whether the frequency control signal is high in step 1.2 is: judging whether the reference frequency Freq is at a high level, if the reference frequency Freq is at a high level, the frequency control signal is high, otherwise the frequency control signal is low.

6. The method for reducing the current impact of motor speed switching according to claim 1, characterized in that: The specific implementation method of step 3 is: adjusting the rotation speed through the reference frequency generated in step 1 and the corresponding voltage in step 2.

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