Memory element and method for manufacturing the same

Abstract

The present application provides a kind of storage element, comprising: laminated structure, multiple channel layers, source line, bit line, switching layer and dielectric column.Laminated structure has the multiple dielectric layers and multiple conductor layers of alternative stacking.Channel layer is respectively embedded in conductor layer.Source line is through laminated structure, to be electrically connected in the first side of channel layer with channel layer.Bit line is through laminated structure, to be coupled in the second side of channel layer with channel layer.Switching layer covers bit line, to be contacted in the second side of channel layer with channel layer.Dielectric column is through channel layer, to divide each channel layer into doughnut shape.Another kind of manufacturing method of storage element is provided.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory element and a manufacturing method thereof. BACKGROUND

[0002] With the advancement of semiconductor technology, various electronic products are developed towards high speed, high performance, and light and thin. Under this trend, the demand for higher storage capacity memory also increases. Therefore, the design of memory has been developed towards three-dimensional memory structure with high integration density and high density. SUMMARY

[0003] The present application provides a memory element and a manufacturing method thereof, in which a gate at the same level surrounds a plurality of memory cells, so that the plurality of memory cells share the same gate voltage, thereby simplifying the layout of gate wiring.

[0004] The present application provides a memory element and a manufacturing method thereof, in which the thickness of the channel layer in the vertical direction is increased to increase the current of the memory cell. In this case, the present application can effectively utilize the area of the chip in the horizontal direction to improve the integration density of the memory element, thereby facilitating the miniaturization of the chip.

[0005] The present application provides a memory element comprising a stack structure, a plurality of channel layers, a source line, a bit line, a switching layer, and a dielectric column. The stack structure has a plurality of dielectric layers and a plurality of conductor layers alternately stacked. The plurality of channel layers are respectively embedded in the plurality of conductor layers. The source line penetrates the stack structure to electrically connect the plurality of channel layers at a first side of the plurality of channel layers. The bit line penetrates the stack structure to couple the plurality of channel layers at a second side of the plurality of channel layers. The switching layer covers the bit line to contact the plurality of channel layers at the second side of the plurality of channel layers. The dielectric column penetrates the plurality of channel layers to divide each channel layer into a donut shape.

[0006] The present application provides a manufacturing method of a memory element, comprising: forming a stack structure having a plurality of dielectric layers and a plurality of conductor layers alternately stacked; forming a first opening in the stack structure to penetrate the stack structure; laterally etching the plurality of conductor layers exposed to the first opening to form a plurality of first recesses; forming a gate dielectric layer on the sidewalls of the plurality of conductor layers exposed to the plurality of first recesses; forming a plurality of channel layers in the plurality of first recesses, respectively; forming a dielectric column in the first opening to contact the plurality of channel layers; forming a source line penetrating the stack structure at a first side of the plurality of channel layers; forming a bit line penetrating the stack structure at a second side of the plurality of channel layers; and forming a switching layer covering the bit line.

[0007] To make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figures 1A-1S is a plan view of a manufacturing process of a memory element according to a first embodiment of the present application;

[0009] Figures 2A-2S is a cross-sectional view of a manufacturing process of a memory element according to a first embodiment of the present application;

[0010] Figure 3 is a perspective view of a memory cell of Figure 1S

[0011] Figure 4 is a cross-sectional view of a memory element according to a second embodiment of the present application. DETAILED DESCRIPTION

[0012] The present application is described more fully with reference to the accompanying drawings. The present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of the layers and regions in the drawings can be exaggerated for clarity. Like reference numerals in the drawings denote like components, and the following paragraphs will not be repeated.

[0013] Figures 1A-1S is a plan view of a manufacturing process of a memory element according to a first embodiment of the present application. Figures 2A-2S is a cross-sectional view of a manufacturing process of a memory element according to a first embodiment of the present application. In the following embodiments, Figures 1A-1S are plan views taken along lines I-I of Figures 2A-2S For brevity, only line I-I is shown in Figure 2A and the illustration in Figures 2B-2S is omitted.

[0014] First, refer to Figure 1A and Figure 2A to form a stack structure 102 having a plurality of dielectric layers 104 and a plurality of conductor layers 106 stacked alternately. In some embodiments, the material of the dielectric layers 104 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The material of the conductor layers 106 includes doped polysilicon, undoped polysilicon, or a combination thereof. In the present embodiment, the dielectric layers 104 can be silicon oxide layers, and the conductor layers 106 can be heavily doped P-type (P+) polysilicon layers. Although Figure 2A only 3 dielectric layers 104 and 2 conductor layers 106 are shown, the present application is not limited thereto. In other embodiments, the number of dielectric layers 104 and conductor layers 106 can be adjusted as desired. ​

[0015] Referring to Figure 1B and Figure 2B A plurality of openings 10 are formed in the stack structure 102 to penetrate the stack structure 102.

[0016] Referring to Figure 1C and Figure 2C A first etching process is performed to laterally recess the conductor layer 106 exposed in the openings 10 (i.e., first openings) to form a plurality of recesses 11 (i.e., first recesses). In some embodiments, the first etching process includes a wet etching process using a suitable etchant to selectively etch the conductor layer 106 without etching or with minimal etching of the dielectric layer 104. For example, when the dielectric layer 104 is a silicon oxide layer and the conductor layer 106 is a P-type polysilicon layer, an etchant containing chlorine can be used. In this case, the sidewalls 106s of the conductor layer 106 are recessed from the sidewalls 104s of the dielectric layer 104 such that the recesses 11 are formed between adjacent dielectric layers 104.

[0017] Referring to Figure 1D and Figure 2D A thermal oxidation process is performed to form a gate dielectric layer 108 on the sidewalls 106s of the conductor layer 106 exposed in the recesses 11. In this case, as shown in Figure 1D , the gate dielectric layer 108 laterally surrounds the composite openings formed by the recesses 11 and the openings 10. In some embodiments, the gate dielectric layer 108 can be a silicon oxide layer.

[0018] Referring to Figure 1E and Figure 2E A channel material layer 110 is formed to fill in the recesses 11 and the openings 10. In some embodiments, the channel material layer 110 includes polysilicon, epitaxial silicon, indium gallium zinc oxide (IGZO), or a combination thereof. In the present embodiment, the channel material layer 110 can be a lightly doped P-type (P-) polysilicon with a doping concentration less than that of the conductor layer 106 (a P+ polysilicon layer). That is, the channel material layer 110 and the conductor layer 106 can have the same conductivity type.

[0019] Referring to Figure 1F and Figure 2F Excess channel material layer 110 on the sidewalls 104s of the dielectric layer 104 is removed to form a plurality of channel layers 120 in the recesses 11, respectively. In this case, as shown in Figure 2F , the sidewalls 120s of the channel layers 120 can be aligned with the sidewalls 104s of the dielectric layer 104. However, the present application is not limited thereto, and in other embodiments, the sidewalls 120s of the channel layers 120 can be slightly recessed from the sidewalls 104s of the dielectric layer 104.

[0020] Referring to Figure 1G andFigure 2G A dielectric pillar 111 is formed in the opening 10 to contact the channel layer 120 having a donut shape, such that the dielectric pillar 111 is surrounded by the channel layer 120 and the dielectric layer 104. The dielectric pillar 111 can have the same or different dielectric material as the dielectric layer 104.

[0021] Referring to Figure 1H With Figure 2H An opening 12 is formed through the stack structure 102 at the first side S1 of the channel layer 120, and an opening 14 is formed through the stack structure 102 at the second side S2 of the channel layer 120. The first side S1 of the channel layer 120 is opposite to the second side S2 of the channel layer 120. In particular, the gate dielectric layer 108 can be considered as a stop layer for forming the openings 12, 14. Thus, the first side S1 of the channel layer 120 can protrude and extend into the opening 12, and the second side S2 of the channel layer 120 can protrude and extend into the opening 14.

[0022] Referring to Figure 1I With Figure 2I The isolation material is filled into the openings 12 and 14, respectively, to form an isolation structure 112 at the first side S1 of the channel layer 120 and an isolation structure 114 at the second side S2 of the channel layer 120. In this case, the isolation structures 112, 114 are formed through the stack structure 102, respectively, to contact the channel layer 120. In the present embodiment, the isolation structures 112, 114 are used to electrically isolate the channel layer 120 at the same level. In some embodiments, the isolation material includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0023] Referring to Figure 1J With Figure 2J An opening 16 (i.e., a second opening) is formed through the isolation structure 112 at the first side S1 of the channel layer 120, and an opening 18 (i.e., a third opening) is formed through the isolation structure 114 at the second side S2 of the channel layer 120. In particular, a portion of the gate dielectric layer 108 at the first side S1 of the channel layer 120 can be further removed to allow the opening 16 to contact the first side S1 of the channel layer 120. On the other hand, a portion of the gate dielectric layer 108 at the second side S2 of the channel layer 120 can be further removed to allow the opening 18 to contact the second side S2 of the channel layer 120. In addition, each of the openings 16 and 18 is surrounded by the isolation structures 112a, 114a and the channel layer 120, and after the openings 16, 18 are formed, each of the isolation structures 112a and each of the isolation structures 114a become an "I" shape.

[0024] Referring to Figure 1K With Figure 2KA second etching process is performed to laterally recess a portion of the channel layer 120 exposed on the first side S1 of the opening 16, thereby forming a plurality of recesses 17 (i.e., second recesses) in communication with the opening 16, and to laterally recess a portion of the channel layer 120 exposed on the second side S2 of the opening 18, thereby forming a plurality of recesses 19 (i.e., third recesses) in communication with the opening 18. In some embodiments, the second etching process includes a wet etching process using a suitable etchant to selectively etch the channel layer 120. For example, when the dielectric layer 104 and the isolation structures 112a, 114a are silicon oxide layers and the channel layer 120 is a P-poly silicon layer, an etchant containing chlorine can be used.

[0025] Referring to Figure 1L and Figure 2L , a plurality of first contact layers 117 are formed in the recesses 17, and a plurality of second contact layers 119 are formed in the recesses 19. In some embodiments, the first contact layers 117 and the second contact layers 119 can be formed by forming a contact material layer to fill the recesses 17, 19 and cover the sidewalls 104s of the dielectric layer 104, and then removing the excess contact material layer on the sidewalls 104s of the dielectric layer 104. In the present embodiment, the contact material layer can be a heavily doped N-type (N+) poly silicon layer. That is, the first contact layers 117 and the second contact layers 119 have the same conductivity type, but different from the conductivity type of the channel layer 120 (or the conductor layer 106). After the first contact layers 117 and the second contact layers 119 are formed, as shown in Figure 2L , the sidewalls 117s of the first contact layers 117 can be aligned with the sidewalls 104s1 of the dielectric layer 104, and the sidewalls 119s of the second contact layers 119 can be aligned with the sidewalls 104s2 of the dielectric layer 104. However, the present application is not limited thereto, and in other embodiments, the sidewalls 117s of the first contact layers 117 can be slightly recessed from the sidewalls 104s1 of the dielectric layer 104, and the sidewalls 119s of the second contact layers 119 can be slightly recessed from the sidewalls 104s2 of the dielectric layer 104. In the present embodiment, the first contact layers 117 and the second contact layers 119 can be formed in the same step.

[0026] Referring to Figure 1M and Figure 2M , isolation materials are filled in the openings 16, 18, respectively, such that each of the first contact layers 117 and each of the second contact layers 119 are surrounded by one of the dielectric layer 104, the channel layer 120, and the isolation structures 112a, 114a. In some embodiments, the isolation materials include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In the present embodiment, the isolation materials can be the same film layer as the isolation structures 112a, 114a and the gate dielectric layer 108, and thus are shown as the same film layer in Figure 1M and Figure 2M .

[0027] Referring to Figure 1N and Figure 2N An opening 20 (i.e., a fourth opening) is formed through the isolation structure 114b (or 112b) at the outer side (sidewall) 119s of the second contact layer 119. In this case, as shown in Figure 2N , the opening 20 exposes the outer side 119s of the second contact layer 119, and the opening 20 is surrounded by the isolation structure 114b (or 112b), in which the isolation structure 114b (or 112b) becomes a U-shape after the opening 20 is formed.

[0028] Referring to Figure 1O and Figure 2O , a third etching process is performed to laterally etch the exposed portion of the second contact layer 119 in the opening 20, thereby forming a plurality of recesses 21 (i.e., fourth recesses) in communication with the opening 20. In some embodiments, the third etching process includes a wet etching process using a suitable etchant to selectively etch the second contact layer 119. For example, when the dielectric layer 104 and the isolation structures 112b, 114b are silicon oxide layers and the second contact layer 119 is an N+ polysilicon layer, an etchant containing chlorine can be used.

[0029] Referring to Figure 1P and Figure 2P , a plurality of electrode layers 121 are formed in the recesses 21, respectively. In some embodiments, the electrode layers 121 can be formed by forming an electrode material layer (e.g., a TiN layer) to fill the recesses 21 and cover the sidewalls 104s2 of the dielectric layer 104 using, for example, a chemical vapor deposition (CVD) method, and then removing the excess electrode material layer on the sidewalls 104s2 of the dielectric layer 104. In this case, as shown in Figure 2P , the sidewalls 121s of the electrode layers 121 can be aligned with the sidewalls 104s2 of the dielectric layer 104. However, the present application is not limited thereto, and in other embodiments, the sidewalls 121s of the electrode layers 121 can also be slightly recessed from the sidewalls 104s2 of the dielectric layer 104.

[0030] Referring to Figure 1Q and Figure 2Q , an isolation material is filled into the opening 20 such that the electrode layers 121 are surrounded by the dielectric layer 104, the second contact layer 119, and the isolation structures 112b, 114b. In some embodiments, the isolation material includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In the present embodiment, the isolation material can have the same material as the isolation structures 112b, 114b, and thus is shown as the same film layer in Figure 1Q and Figure 2Q .

[0031] Referring to Figure 1R and Figure 2RAn opening 22 (i.e., a fifth opening) is formed through the isolation structure 112b (or 114b) at the outer side (sidewall) 117s of the first contact layer 117. Then, a source line material (e.g., W with a TiN liner) is filled in the opening 22 to form a source line 122 that contacts the first contact layer 117.

[0032] Referring to Figure 1S With Figure 2S An opening 24 (i.e., a sixth opening) is formed through the isolation structure 114b (or 112b) at the outer side (sidewall) 121s of the electrode layer 121. Then, a switching layer 124 is formed on the inner surface 24s of the opening 24 to contact the electrode layer 121. Then, a bit line material (e.g., Ti or other suitable conductive material) is filled in the opening 24 to form a bit line 126 that is covered by the switching layer 124, thereby completing the memory element 1.

[0033] Referring to Figure 1S With Figure 2S The present disclosure provides a memory element 1 including a stack structure 102, a plurality of channel layers 120, a source line 122, a bit line 126, a switching layer 124, and a dielectric pillar 111. The stack structure 102 has a plurality of dielectric layers 104 and a plurality of conductor layers 106 stacked alternately. The channel layers 120 are respectively embedded in the conductor layers 106. The source line 122 penetrates the stack structure 102 to electrically connect with the channel layers 120 at a first side S1 of the channel layers 120. The bit line 126 penetrates the stack structure 102 to couple with the channel layers 120 at a second side S2 of the channel layers 120. The switching layer 124 covers the bit line 126 to contact the channel layers 120 at the second side S2 of the channel layers 120. The dielectric pillar 111 penetrates the channel layers 120 to divide each of the channel layers 120 into a donut shape.

[0034] In some embodiments, the switching layer 124 can include one or more layers. The bit line 126 can include one or more layers.

[0035] In some embodiments, the material of the switching layer 124 comprises a variable resistance material, a phase change material, a ferroelectric material, a capacitive material, or a combination thereof. That is, depending on the material of the switching layer 124, the memory element 1 can be a resistive random access memory (RRAM), a phase change random access memory (PCRAM), a ferroelectric random access memory (FeRAM), a dynamic random access memory (DRAM), or a combination thereof. Specifically, the memory cell MC can comprise a portion of the source line 122 and a portion of the bit line 126 coupled with the channel layer 120. When the memory element 1 is a RRAM, the memory cell MC can comprise a 1 transistor 1 resistor (1T1R) configuration. As shown in FIG. 1A, the 1 transistor (1T) comprises a first contact layer 117 to serve as a source, a second contact layer 119 to serve as a drain, and a conductor layer 106 to serve as a gate or word line. The 1 resistor (1R) comprises the switching layer 124 to serve as a variable resistance layer, which can change the resistance value by changing an applied bias voltage to place the component in a high resistance state or a low resistance state, and thereby interpret a digital signal of 0 or 1. The switching layer 124 can comprise sub-layers to regulate the movement of charged species (e.g., ions, electrons, holes), and the sub-layers support an actual resistance varying structure, such as a filament. In some embodiments, the bit line 126 can include a sub-layer in contact with the switching layer 124, and the sub-layer serves as a reservoir for the charged species. In other embodiments, the entire bit line 126 can be considered as a reservoir. In some embodiments, as shown in FIG. 1B, the source line 122 of one memory cell MC and the bit line 126 of an adjacent memory cell MC are configured in the same isolation structure 112b or 114b. In other words, the isolation structures 112b, 114b can be used to electrically isolate the memory cells MC at the same level to prevent sneak current or other memory cell interference phenomena. Figure 1S Figure 1S

[0036] Figure 3 is a perspective view of a memory cell. Figure 1S

[0037] as shown in FIG. 1A, the 1 transistor (1T) comprises a first contact layer 117 to serve as a source, a second contact layer 119 to serve as a drain, and a conductor layer 106 to serve as a gate or word line. The 1 resistor (1R) comprises the switching layer 124 to serve as a variable resistance layer, which can change the resistance value by changing an applied bias voltage to place the component in a high resistance state or a low resistance state, and thereby interpret a digital signal of 0 or 1. The switching layer 124 can comprise sub-layers to regulate the movement of charged species (e.g., ions, electrons, holes), and the sub-layers support an actual resistance varying structure, such as a filament. In some embodiments, the bit line 126 can include a sub-layer in contact with the switching layer 124, and the sub-layer serves as a reservoir for the charged species. In other embodiments, the entire bit line 126 can be considered as a reservoir. In some embodiments, as shown in FIG. 1B, the source line 122 of one memory cell MC and the bit line 126 of an adjacent memory cell MC are configured in the same isolation structure 112b or 114b. In other words, the isolation structures 112b, 114b can be used to electrically isolate the memory cells MC at the same level to prevent sneak current or other memory cell interference phenomena. Figure 3 ​​​As shown, the embodiment of the present application can increase the current of the memory cell MC by increasing the thickness 120t of the channel layer 120 in the vertical direction. That is, the thicker the thickness 120t of the channel layer 120, the greater the current of the memory cell MC. In this case, the embodiment of the present application can effectively utilize the area of the chip in the horizontal direction to improve the integration density of the memory element 1, thereby facilitating the miniaturization of the chip. In addition, the electrode layer 121 can not be embedded in the second contact layer 119, but can be disposed between the switching layer 124 and the channel layer 120 and between the switching layer 124 and the second contact layer 119, as shown in Figure 3

[0038] Figure 4 is a cross-sectional view of a memory element according to a second embodiment of the present application.

[0039] As shown, the conductor layer 106 (i.e., the gate or word line) of the memory element 2 of the second embodiment horizontally surrounds the plurality of memory cells MC, so that the plurality of memory cells MC share the same gate voltage. In this case, the layout of the gate at the same level can be simplified to reduce the manufacturing steps and manufacturing cost of the memory element. Figure 4

[0040] Although the present application has been disclosed in the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application, so the scope of protection of the present application shall be subject to the claims.​​

Claims

1. A memory element characterized by, The method comprises: forming a stack structure having a plurality of dielectric layers and a plurality of conductor layers stacked alternately, wherein the plurality of conductor layers are etched laterally to form a plurality of first recesses; forming a plurality of channel layers in the plurality of first recesses, respectively; forming a source line through the stack structure to electrically connect the plurality of channel layers at a first side of the plurality of channel layers; forming a bit line through the stack structure to couple the plurality of channel layers at a second side of the plurality of channel layers, wherein the first side of the plurality of channel layers is opposite to the second side of the plurality of channel layers; forming a switching layer to cover the bit line to contact the plurality of channel layers at the second side of the plurality of channel layers; and forming a dielectric pillar through the plurality of channel layers to divide each channel layer into a donut shape. The method further comprises:

2. The storage element according to claim 1, wherein forming a gate dielectric layer between the plurality of conductor layers and the plurality of channel layers; forming a plurality of first contact layers embedded in the first side of the plurality of channel layers, respectively, to contact the source line; forming a plurality of second contact layers embedded in the second side of the plurality of channel layers, respectively, to contact the switching layer; and forming a plurality of electrode layers embedded in the plurality of second contact layers, respectively, to contact the switching layer. wherein the plurality of first contact layers and the plurality of second contact layers have a same conductivity type, and the plurality of channel layers and the plurality of first contact layers have a different conductivity type. wherein the plurality of channel layers and the plurality of conductor layers have a same conductivity type, and a doping concentration of the plurality of channel layers is less than a doping concentration of the plurality of conductor layers.

3. The storage element according to claim 2, wherein wherein a portion of the source line and a portion of the bit line coupled to one of the plurality of channel layers form a memory cell, and one of the plurality of conductor layers horizontally surrounds a plurality of memory cells such that the plurality of memory cells share a same gate voltage.

4. The storage element according to claim 1, wherein The method comprises:

5. The storage element according to claim 1, wherein forming a stack structure having a plurality of dielectric layers and a plurality of conductor layers stacked alternately; 6. A method for manufacturing a memory element, characterized by, forming a first opening in the stack structure to pass through the stack structure; etching the plurality of conductor layers exposed to the first opening laterally to form a plurality of first recesses; forming a gate dielectric layer on sidewalls of the plurality of conductor layers exposed to the plurality of first recesses; forming a plurality of channel layers in the plurality of first recesses, respectively; forming a dielectric pillar in the first opening to contact the plurality of channel layers; forming a source line through the stack structure at a first side of the plurality of channel layers; forming a bit line through the stack structure at a second side of the plurality of channel layers, wherein the first side of the plurality of channel layers is opposite to the second side of the plurality of channel layers; and forming a switching layer to cover the bit line. wherein before forming the source line, the method further comprises: forming a second opening through the stack structure at the first side of the plurality of channel layers; forming a third opening through the stack structure at the second side of the plurality of channel layers; 7. The method of producing a memory element according to claim 6, wherein etching the plurality of channel layers exposed to the second opening laterally to form a plurality of second recesses; etching the plurality of channel layers exposed to the third opening laterally to form a plurality of third recesses; ​ ​ ​ forming a plurality of first contact layers in the plurality of second recesses, respectively; and forming a plurality of second contact layers in the plurality of third recesses, respectively.

8. The method for manufacturing a memory element according to claim 7, wherein wherein the plurality of first contact layers and the plurality of second contact layers are formed in a same step.

9. The method for manufacturing a memory element according to claim 7, wherein wherein after forming the plurality of first contact layers and the plurality of second contact layers, the manufacturing method further comprises: forming fourth openings through the stack structure at an outer side of the plurality of second contact layers; laterally etching back the plurality of second contact layers exposed to the fourth openings to form a plurality of fourth recesses; and forming a plurality of electrode layers in the plurality of fourth recesses, respectively.

10. The method of producing a memory element according to claim 9, wherein wherein after forming the plurality of electrode layers, the manufacturing method further comprises: forming fifth openings through the stack structure at an outer side of the plurality of first contact layers; and filling the fifth openings with a source line material to form the source line contacting the plurality of first contact layers.

11. The method of producing a memory element according to claim 10, wherein wherein after forming the source line, the manufacturing method further comprises: forming sixth openings through the stack structure at an outer side of the plurality of electrode layers; forming the switching layer on sidewalls of the sixth openings to contact the plurality of electrode layers; and filling the sixth openings with a bit line material to have the switching layer wrap around the bit line.

12. The method of producing a memory element according to claim 6, wherein wherein after forming the dielectric pillars, the manufacturing method further comprises: forming isolation structures through the stack structure at the first side and the second side of the plurality of channel layers, respectively, wherein the source line and the bit line are configured in the isolation structures.

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