A Single Event Upset Recovery Analysis Method Combining Experiment and Simulation

Abstract

The present invention relates to the field of space radiation effects and reinforcement technology, specifically to a single-particle upset recovery analysis method that combines experiments and simulations. This method addresses the shortcomings of existing numerical simulations of single-particle upset recovery, which fail to consider the coupling effects of surrounding storage cells and cannot accurately predict the impact of upset recovery on multi-cell upsets. Furthermore, due to the random location of single-particle upset recovery in the storage array and its short duration, the response process is difficult to directly capture experimentally. This combined experimental and simulation single-particle upset recovery analysis method organically combines experiments and simulations, leveraging the complementary advantages of heavy ion broad-beam experiments, heavy ion microbeam experiments, and numerical simulations to more comprehensively and meticulously reveal the mechanisms and influencing factors of single-particle upset recovery.

Description

Technical Field

[0001] The present invention relates to the field of space radiation effects and reinforcement technology, and in particular to a single event upset recovery analysis method combining experiment and simulation. Background Art

[0002] Single Event Effects (SEE) in space radiation refer to temporary or permanent errors in spacecraft electronic systems caused by the incidence of a single high-energy particle in outer space. These errors can cause abnormal satellite attitude control, degradation of telemetry functions, abnormal shutdown of power modules, and loss of scientific data, seriously affecting the reliable operation of spacecraft on orbit.

[0003] As semiconductor process sizes approach the nanometer scale, the critical charge for single-event effects (SPEs) in memory devices decreases, the spacing between sensitive cells decreases, and charge sharing intensifies. This increases the probability that a single particle incident on a memory device will cause multiple memory cells to flip simultaneously, a phenomenon known as multi-cell flipping. Multi-cell flipping significantly increases the SPE error rate. Furthermore, charge sharing also gives rise to a unique SPE phenomenon called SPE recovery. SPE recovery occurs when the logic state of a memory cell flips and then returns to its original state before the particle impact. Although a flip occurs during the SPE recovery process, the effect is ultimately characterized as non-flipping. The emergence of SPE recovery results in a discontinuous topology for multi-cell flipping, weakening the dependence of the flip rate on the ion linear energy transfer value. This provides new insights into the design of SPE hardening for nanoscale integrated circuits. Therefore, research on the mechanism of SPE recovery plays an important role in supporting the radiation hardening design of nanoscale integrated circuits for aerospace applications.

[0004] At present, the research work on single-particle flip recovery in nano-memory still has the following problems to be studied and solved: (1) The current numerical simulation of single-particle flip recovery mainly focuses on a single storage unit, without considering the coupling effect of surrounding storage units, and cannot accurately predict the impact of flip recovery on multi-unit flip. The revelation of the factors affecting flip recovery is not comprehensive, which is not conducive to the construction of the flip recovery effect damage model; (2) The occurrence position of single-particle flip recovery in the storage array is random, and its process duration is very short (ns level and below), and the response process is difficult to obtain directly through experiments. Therefore, combining experiments and simulations to establish a scientific and reasonable single-particle flip recovery analysis method is of great significance to the study of the effect mechanism of flip recovery. Summary of the Invention

[0005] The purpose of the present invention is to address the shortcomings of existing numerical simulations of single-particle upset recovery, such as the failure to consider the coupling effect of surrounding storage cells and the inability to accurately predict the impact of upset recovery on multi-cell upsets. In addition, the present invention provides a single-particle upset recovery analysis method that combines experiments and simulations, as the occurrence location of single-particle upset recovery in the storage array is random and the duration of the process is very short, making the response process difficult to directly obtain through experiments.

[0006] In order to solve the deficiencies of the above-mentioned prior art, the present invention provides the following technical solutions:

[0007] A single event upset recovery analysis method combining experiments and simulations is unique in that it includes the following steps:

[0008] Step 1: Using the test system, a heavy ion wide beam experiment of single event upset recovery is performed on the memory to be tested at a heavy ion accelerator single event effect experiment terminal to obtain single event upset recovery topology graphs of the memory to be tested under different test conditions;

[0009] The test system includes a DC power supply, a test mainboard, a control computer and an irradiation plate; the heavy ion accelerator single particle effect experiment terminal includes a heavy ion beam output end and a sample rack; the DC power supply output end is connected to the first input end of the test mainboard, the first output end of the test mainboard and the second output end of the test mainboard are respectively connected to the control computer and the irradiation plate input end, the bottom surface of the irradiation plate is fixed on the sample rack, and the top surface of the irradiation plate is plugged into or welded to the memory to be tested, and the wafer of the memory to be tested is located within the ion beam spot coverage range of the heavy ion beam output end; the memory to be tested includes a storage array and a peripheral circuit, and the storage array is composed of a plurality of identical storage units arranged according to certain rules; the test conditions include a memory working state and an ion incident condition, the memory working state includes a voltage bias and a test pattern, and the ion incident condition includes an ion linear energy transfer value and an ion incident angle; the heavy ion wide beam experiment includes multiple rounds of tests, and a new round of tests is performed each time a test condition parameter value is changed until all preset test condition parameter values ​​are replaced;

[0010] Step 2: For each round of testing in Step 1, plotting the memory array position corresponding to the obtained single event upset recovery topology in the memory array bitmap; comparing the single event upset recovery conditions in different areas of the memory array, and calculating a typical single event upset recovery topology; the typical single event upset recovery topology refers to a topology exhibiting a discontinuous feature;

[0011] Step 3: Based on the typical SEP recovery topology graphs collected in Step 2, locate the region in the storage array where the SEP occurs, i.e., the local storage array; in combination with the heavy ion broad beam experimental test conditions, use the test system to perform a heavy ion microbeam experiment on the local storage array where the typical SEP recovery topology graphs are located, and obtain the precise sensitive position of the SEP recovery in each local storage array;

[0012] Step 4: Construct and calibrate local memory array device simulation models corresponding to each local memory array located in step 3, following the progressive hierarchy of transistor → memory cell → local memory array; add a physical model of the single event effect caused by heavy ions to each local memory array device simulation model, perform single event upset recovery numerical simulation for each local memory array, and analyze the generation mechanism of the single event upset recovery;

[0013] Step 5: Combine the heavy ion broad beam experimental results of step 1 and the single event upset recovery numerical simulation results of step 4 to analyze the key influencing factors of single event upset recovery.

[0014] Furthermore, the step 1 is specifically as follows:

[0015] Step 1.1. Setting the initial test conditions of the memory to be tested, conducting a round of heavy ion wide beam experiments, monitoring the single particle upset data in real time through the test system, and saving the single particle upset data after the end of the round of irradiation. The specific implementation process of setting the initial test conditions of the memory to be tested is: setting the working state of the memory to be tested through the control computer, and the professional personnel of the heavy ion accelerator maintenance team setting the ion incidence conditions; the single particle upset data includes the time when the single particle upset is detected, the data bit information of the upset, and the logical address information of the upset;

[0016] Step 1.2: Change one of the initial test conditions and complete a new round of testing according to the test method described in step 1.1.

[0017] Step 1.3: If all preset test conditions have been changed, proceed to step 1.4; otherwise, return to step 1.2;

[0018] Step 1.4: Compile a mapping program based on the mapping relationship between the logical address and the physical address of the memory. Through the mapping program and the test data of each round, obtain the single event upset of the memory in each test round and then restore the topology graph.

[0019] Furthermore, the step 3 is specifically as follows:

[0020] Step 3.1. Select a typical single-event upset and then recover topological graph obtained in step 2, set the test conditions of the heavy ion microbeam experiment based on its corresponding heavy ion broad-beam experiment test conditions, and simultaneously locate the corresponding local storage array. Use the local storage array as the scanning area of ​​the heavy ion microbeam experiment, focus the heavy ion microbeam on the surface of the scanning area layout, and perform point-by-point traversal irradiation. The irradiation points cover the entire scanning area. The test system monitors the upset data of the memory at all irradiation points in real time. After the scan is completed, save the test data. At this point, a round of heavy ion microbeam experiment testing is completed.

[0021] Step 3.2: Conduct a new round of heavy ion microbeam experimental tests for other typical single-event upset recovery topologies according to the method described in step 3.1 until all the tests for the typical single-event upset recovery topologies obtained in step 2 are completed.

[0022] Step 3.3: Obtain the precise sensitive location of the SEU recovery in each test round using the test data from each round and the mapping program compiled in step 1.4.

[0023] Furthermore, the step 4 is specifically as follows:

[0024] Step 4.1, select a local storage array located in step 3.1, and build and calibrate a device simulation model of the local storage array according to the progressive hierarchy of transistor → memory cell → local storage array;

[0025] Step 4.2: Add a physical model of the single-event effect caused by heavy ions to the local storage array device simulation model obtained in step 4.1, simulate the local storage array, and set simulation conditions based on the heavy ion microbeam experiment performed in step 3: the simulation conditions of the local storage array are consistent with the test conditions set for this round of testing in the heavy ion microbeam experiment, and the ion incident position in the simulation is the precise sensitive position obtained in this round of testing in the heavy ion microbeam experiment and its adjacent transistors;

[0026] After the simulation conditions are set, a single-event upset recovery numerical simulation is performed to obtain the single-event response waveform of each storage unit in the local storage array under different ion incident positions, and the single-event upset recovery topology of the local storage array is obtained. At the same time, the electrode voltage, electrode current and well potential data of each transistor in the local storage array are monitored and saved;

[0027] The physical model of the single event effect caused by heavy ions is: G(l,w,t)=G LET (l)×R(w,l)×T(t),

[0028] Where: G(l,w,t) is the carrier generation rate caused by heavy ions; G LET(l) is the carrier generation density of ion linear energy transfer; R(w,l) is the spatial distribution function of carriers; T(t) is the time distribution function of carriers;

[0029] Step 4.3: Repeat steps 4.1 to 4.2 to sequentially perform the following single-event upset and recovery numerical simulations for each local storage array until all simulations corresponding to all local storage arrays of the heavy ion microbeam experiment are completed.

[0030] Step 4.4: Analyze the generation mechanism of the single event upset recovery based on the changes in the electrode voltage, electrode current, and well potential of each transistor in each local memory array device simulation model obtained from the single event upset recovery numerical simulation.

[0031] Furthermore, the step 4.1 is specifically as follows:

[0032] Step 4.1.1, constructing a transistor device simulation model, solving the semiconductor device numerical calculation model equation to obtain an IV characteristic curve of the transistor device simulation model, comparing the IV characteristic curve of the transistor device simulation model with the IV characteristic curve of the transistor SPICE intensive model, and if the IV characteristic curve is inconsistent, adjusting the transistor device simulation model parameters until the IV characteristic curve is consistent, thereby completing the electrical characteristic calibration of the transistor device simulation model; the IV characteristic curve includes a transistor transfer characteristic curve and an output characteristic curve;

[0033] The semiconductor numerical calculation model equation includes

[0034] Poisson's equation:

[0035] Drift-diffusion equation:

[0036] Carrier continuity equation:

[0037] in:

[0038] ε is the dielectric constant of silicon; is the electric potential; q is the electron charge; p is the hole density; n is the electron density; is the ionized donor impurity concentration; is the concentration of ionized acceptor impurities; G n , G p are the generation rates of electrons and holes, respectively; R n 、R p are the recombination rates of electrons and holes, respectively; are the current densities of electrons and holes, respectively; μ n 、μ p are the mobility of electrons and holes, respectively; is the electric field density; D n 、D p are the diffusion coefficients of electrons and holes, respectively;

[0039] Step 4.1.2: Build a memory cell device simulation model based on the transistor device simulation model, solve the semiconductor device numerical calculation model equation to obtain the butterfly characteristic curve of the memory cell device simulation model, compare the butterfly characteristic curve of the memory cell device simulation model with the butterfly characteristic curve of the SPICE intensive model of the memory cell, and if the two are inconsistent, adjust the memory cell device simulation model parameters until they are consistent, thereby completing the electrical characteristic calibration of the memory cell device simulation model;

[0040] Step 4.1.3. According to the number of rows and columns of the local storage array, a local storage array device simulation model is established based on the storage cell device simulation model, and the semiconductor device numerical calculation model equation is solved to obtain the butterfly characteristic curve of each storage cell device simulation model in the local storage array. The butterfly characteristic curve of each storage cell device simulation model is compared with the butterfly characteristic curve of the SPICE intensive model of the storage cell. If the two are inconsistent, the parameters of the storage cell device simulation model are adjusted until the two are consistent. At this point, the electrical characteristic calibration of the local storage array device simulation model is completed.

[0041] Furthermore, the step 5 is specifically as follows: according to the results of the heavy ion wide beam experiment in step 1, the effect of different test conditions on the single particle upset recovery is analyzed; through the single particle upset recovery numerical simulation of the local storage array in step 4, the degree of influence of changes in different simulation conditions on the electrode voltage, electrode current and well potential parameters of each transistor in the local storage array is analyzed; and finally the key influencing factors of the single particle upset recovery are obtained.

[0042] Furthermore, in step 1, the ion beam spot size of the heavy ion wide beam experiment is in the centimeter range, the beam spot covers the entire wafer of the memory to be tested, and the ion incident position is randomly distributed within the wafer of the memory to be tested; in step 3, the ion beam spot size of the heavy ion microbeam experiment is in the micron range, and the ion incident position is precisely positioned on the memory wafer to be tested.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] (1) The present invention provides a single particle flip recovery analysis method that combines experiments with simulations. The heavy ion wide beam experiment provides typical single particle flip recovery topological graphic statistical information and global sensitive position information for the heavy ion microbeam experiment, which simplifies the heavy ion microbeam experiment process and reduces the heavy ion microbeam experiment time. The heavy ion microbeam experiment uses the advantage of controllable ion incident position to obtain accurate sensitive position information of single particle flip recovery, providing supplementary data for the heavy ion wide beam experiment. The results of the heavy ion wide beam experiment and the heavy ion microbeam experiment provide guidance for the simulation setting, and the simulation overcomes the shortcoming that the experiment cannot measure the internal node voltage, current and its components of the device. The present invention organically combines experiments and simulations to achieve the complementary advantages of heavy ion wide beam experiments, heavy ion microbeam experiments and numerical simulations, and can reveal the generation mechanism and influencing factors of single particle flip recovery in a more comprehensive and detailed manner.

[0045] (2) The present invention provides a single-particle upset recovery analysis method that combines experiments with simulations. In the simulation, the effect of the coupling between adjacent memory cells on the single-particle upset recovery is fully considered. The local memory array device simulation model is used instead of the memory cell device simulation model used in the traditional single-particle upset recovery simulation, resulting in more accurate simulation results.

[0046] (3) The single-particle upset recovery analysis method of the present invention, which combines experiments with simulations, is of great significance for the optimization design of single-particle effect reinforcement based on enhanced upset recovery, and provides important support for the development of radiation-hardened integrated circuits for aerospace use. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic flow chart of a single event upset recovery analysis method combining experiment and simulation according to the present invention;

[0048] Figure 2 Schematic diagram of the test system and heavy ion accelerator single event effect experimental terminal of the present invention;

[0049] Figure 3 Schematic diagram of the single event upset data tested in step 1.1 of the present invention;

[0050] Figure 4 A schematic diagram of test condition parameter values ​​set for different test rounds in step 1 of the present invention;

[0051] Figure 5 Schematic diagram of the single event upset recovery topology obtained in step 1.4 of the present invention;

[0052] Figure 6 A schematic diagram of drawing a single event upset recovery topology graph in a storage array bitmap in step 2 of the present invention;

[0053] Figure 7 Schematic diagram of the local storage array device simulation model constructed in step 4 of the present invention;

[0054] Figure 8 A schematic diagram of the process of constructing and calibrating a simulation model of a local storage array device corresponding to step 4.1 of the present invention;

[0055] Figure 9 Schematic diagram of the butterfly characteristic curve of the memory cell device simulation model in steps 4.1.2 and 4.1.3 of the present invention;

[0056] Figure 10 Schematic diagram of single particle response waveform of each storage unit in the local storage array obtained in step 4.2 of the present invention.

[0057] The reference numerals are as follows: 1-DC power supply; 2-test main board; 3-control computer; 4-irradiation board; 5-heavy ion beam output terminal; 6-sample rack; 7-memory to be tested. DETAILED DESCRIPTION

[0058] The present invention will be further described below with reference to the accompanying drawings and exemplary embodiments.

[0059] Reference Figure 1 A single event upset recovery analysis method combining experiments and simulations includes the following steps:

[0060] Pre-preparation: Uncap the memory device 7 to ensure that it is functioning properly. Uncapping involves removing the top package of the memory device 7 to expose the wafer of the memory device 7. This ensures that the bonding wires and pins of the memory device 7 are intact and function properly. Ceramic packaged memory devices are typically uncapped mechanically, while plastic packaged memory devices are typically uncapped using chemical etching.

[0061] Step 1: Using the test system, perform a heavy ion wide beam experiment of single event upset recovery on the memory device 7 at a heavy ion accelerator single event effect experiment terminal to obtain single event upset recovery topology graphs of the memory device 7 under different test conditions.

[0062] Reference Figure 2The test system includes a DC power supply 1, a test mainboard 2, a control computer 3 and an irradiation plate 4; the heavy ion accelerator single particle effect experiment terminal includes a heavy ion beam lead-in terminal 5 and a sample holder 6; the output end of the DC power supply 1 is connected to the first input end of the test mainboard 2, the first output end of the test mainboard 2 and the second output end of the test mainboard 2 are respectively connected to the control computer 3 and the input end of the irradiation plate 4, the bottom surface of the irradiation plate 4 is fixed on the sample holder 6, and the top surface of the irradiation plate 4 is plugged into or welded with a memory to be tested 7, and the wafer of the memory to be tested 7 is located within the ion beam spot coverage range of the heavy ion beam lead-in terminal 5; the memory to be tested 7 includes a storage array and peripheral circuits, and the storage array is composed of a plurality of identical storage cells arranged according to a certain rule; the test conditions include a memory working state and an ion incident condition, the memory working state includes a voltage bias and a test pattern, and the ion incident condition includes an ion linear energy transfer value and an ion incident angle; the heavy ion wide beam experiment includes multiple rounds of tests, and a new round of tests is performed each time a test condition parameter value is changed until all preset test condition parameter values ​​are replaced;

[0063] The single event upset recovery topology is a geometric figure remaining after removing the physical positions of individual storage units from the geometric figure formed by the physical positions of a plurality of adjacent storage units;

[0064] The ion beam spot size of the heavy ion wide beam experiment is on the order of centimeters, the beam spot covers the entire wafer of the memory device 7 to be tested, and the ion incident positions are randomly distributed within the wafer of the memory device 7 to be tested;

[0065] The test pattern refers to the data pattern written into the memory array. If all the memory cells of the memory array are written with the logic value "1", then the test pattern is all "1"; if all the memory cells of the memory array are written with the logic value "0", then the test pattern is all "0". In addition, there are many other types of test patterns.

[0066] Step 1.1, set the initial test conditions of the memory 7 to be tested, carry out a round of heavy ion broad beam experiment, monitor the single event upset data in real time through the test system, and save the single event upset data after the round of irradiation is completed. The upset data format is as follows: Figure 3 As shown; the specific implementation process of setting the initial test conditions of the memory to be tested 7 is: setting the working state of the memory to be tested 7 by the control computer 3, and setting the ion incidence conditions by the professionals of the heavy ion accelerator maintenance team; the single event upset data includes the time when the single event upset is detected, the data bit information of the upset, and the logical address information of the upset;

[0067] Step 1.2: Change one of the initial test conditions and complete a new round of testing according to the test method described in step 1.1. Figure 4 Shown is a schematic diagram of test condition parameter values ​​set for different test rounds;

[0068] Step 1.3: If all preset test conditions have been changed, proceed to step 1.4; otherwise, return to step 1.2;

[0069] Step 1.4: Compile a mapping program based on the mapping relationship between the memory logical address and the physical address. Through the mapping program and the test data of each round, obtain the single event upset of the memory in each round of testing and then restore the topology graph. Figure 5 The figure shows one of the single event upset recovery topologies;

[0070] The mapping relationship between the memory logical address and the physical address is provided by the memory design manufacturer; the logical address is a string of binary codes, and the physical address is the intuitive location information of the memory unit in the memory array, such as the block, row, and column;

[0071] The mapping program is an automatic processing program, the input value is a logical address, and the output value is a physical address;

[0072] Step 2: For each round of testing in step 1, the storage array position corresponding to the obtained single event upset and recovery topology graph is drawn in the storage array bitmap, such as Figure 6 As shown, the solid box topology graph in the figure represents that one of the three storage cells is flipped and then recovered, and the remaining two storage cells are flipped. The hollow box topology graph in the figure represents that one of the four storage cells is flipped and then recovered, and the remaining three storage cells are flipped. By comparing the single-particle upset and recovery situations in different areas of the memory array, typical single-particle upset and recovery topology graphs are statistically calculated; the typical single-particle upset and recovery topology graph refers to a topology graph that presents a discontinuous feature;

[0073] Step 3: Based on the typical SEP recovery topology graphs collected in Step 2, locate the region in the storage array where the SEP occurs, i.e., the local storage array; in combination with the heavy ion broad beam experimental test conditions, use the test system to perform a heavy ion microbeam experiment on the local storage array where the typical SEP recovery topology graphs are located, and obtain the precise sensitive position of the SEP recovery in each local storage array;

[0074] The ion beam spot size of the heavy ion microbeam experiment is on the order of micrometers, and the ion incident position is precisely located on the memory wafer to be tested.

[0075] Step 3.1. Select a typical single-event upset and then recover topological graph obtained in step 2, set the test conditions of the heavy ion microbeam experiment based on its corresponding heavy ion broad-beam experiment test conditions, and simultaneously locate the corresponding local storage array. Use the local storage array as the scanning area of ​​the heavy ion microbeam experiment, focus the heavy ion microbeam on the surface of the scanning area layout, and perform point-by-point traversal irradiation. The irradiation points cover the entire scanning area. The test system monitors the upset data of the memory at all irradiation points in real time. After the scan is completed, save the test data. At this point, a round of heavy ion microbeam experiment testing is completed.

[0076] The point-by-point traversal irradiation is achieved by sequentially setting the scanning area, scanning step length, and moving speed of the sample holder 6 using the control computer 3;

[0077] Step 3.2: Conduct a new round of heavy ion microbeam experimental tests for other typical single-event upset recovery topologies according to the method described in step 3.1 until all the tests for the typical single-event upset recovery topologies obtained in step 2 are completed.

[0078] Step 3.3: Using the test data from each round and the mapping program compiled in step 1.4, obtain the precise sensitive location of the SEU recovery in each test round.

[0079] Step 4: According to the progressive hierarchy of transistor → memory cell → local memory array, construct and calibrate the local memory array device simulation model corresponding to each local memory array located in step 3, such as Figure 7 As shown in the figure, a physical model of single event effect caused by heavy ions is added to the simulation model of each local storage array device, and a numerical simulation of single event upset and recovery is carried out for each local storage array to analyze the generation mechanism of single event upset and recovery;

[0080] Step 4.1, reference Figure 8 , select a local storage array located in step 3.1, and build and calibrate the local storage array device simulation model according to the progressive hierarchy of transistor → storage cell → local storage array;

[0081] Step 4.1.1, constructing a transistor device simulation model, solving the semiconductor device numerical calculation model equation to obtain an IV characteristic curve of the transistor device simulation model, comparing the IV characteristic curve of the transistor device simulation model with the IV characteristic curve of the transistor SPICE intensive model, and if the IV characteristic curve is inconsistent, adjusting the transistor device simulation model parameters until the IV characteristic curve is consistent, thereby completing the electrical characteristic calibration of the transistor device simulation model; the IV characteristic curve includes a transistor transfer characteristic curve and an output characteristic curve;

[0082] The semiconductor numerical calculation model equation includes:

[0083] Poisson's equation:

[0084] Drift-diffusion equation:

[0085] Carrier continuity equation:

[0086] in:

[0087] ε is the dielectric constant of silicon; is the electric potential; q is the electron charge; p is the hole density; n is the electron density; is the ionized donor impurity concentration; is the concentration of ionized acceptor impurities; G n , G p are the generation rates of electrons and holes, respectively; R n 、R p are the recombination rates of electrons and holes, respectively; are the current densities of electrons and holes, respectively; μ n 、μ p are the mobility of electrons and holes, respectively; is the electric field density; D n 、D p are the diffusion coefficients of electrons and holes, respectively;

[0088] Step 4.1.2: Build a memory cell device simulation model based on the transistor device simulation model, and solve the semiconductor device numerical calculation model equation to obtain the butterfly characteristic curve of the memory cell device simulation model, such as Figure 9 As shown, the butterfly characteristic curve of the memory cell device simulation model is compared with the butterfly characteristic curve of the SPICE intensive model of the memory cell. If the two are inconsistent, the parameters of the memory cell device simulation model are adjusted until the two are consistent. At this point, the electrical characteristic calibration of the memory cell device simulation model is completed.

[0089] Step 4.1.3: Establish a local memory array device simulation model based on the memory cell device simulation model according to the number of rows and columns of the local memory array, solve the semiconductor device numerical calculation model equation to obtain the butterfly characteristic curve of each memory cell device simulation model in the local memory array, compare the butterfly characteristic curve of each memory cell device simulation model with the butterfly characteristic curve of the SPICE intensive model of the memory cell, and if the two are inconsistent, adjust the parameters of the memory cell device simulation model until they are consistent, thereby completing the electrical characteristic calibration of the local memory array device simulation model;

[0090] Step 4.2: Add a physical model of the single-event effect caused by heavy ions to the local storage array device simulation model obtained in step 4.1, simulate the local storage array, and set simulation conditions based on the heavy ion microbeam experiment performed in step 3: the simulation conditions of the local storage array are consistent with the test conditions set for this round of testing in the heavy ion microbeam experiment, and the ion incident position in the simulation is the precise sensitive position obtained in this round of testing in the heavy ion microbeam experiment and its adjacent transistors;

[0091] After the simulation conditions are set, a single-event upset and recovery numerical simulation is performed to obtain the single-event response waveform of each storage unit in the local storage array under different ion incident positions, such as Figure 10 As shown, the single event upset and recovery topology of the local storage array is obtained, and the electrode voltage, electrode current and well potential data of each transistor in the local storage array are monitored and saved;

[0092] The physical model of the single event effect caused by heavy ions is: G(l,w,t)=G LET (l)×R(w,l)×T(t),

[0093] Where: G(l,w,t) is the carrier generation rate caused by heavy ions; G LET (l) is the carrier generation density of ion linear energy transfer; R(w,l) is the spatial distribution function of carriers; T(t) is the time distribution function of carriers;

[0094] Step 4.3: Repeat steps 4.1 to 4.2 to sequentially perform the following single-event upset and recovery numerical simulations for each local storage array until all simulations corresponding to all local storage arrays of the heavy ion microbeam experiment are completed.

[0095] Step 4.4, analyzing the generation mechanism of the single event upset recovery based on the changes in the electrode voltage, electrode current, and well potential of each transistor in each local memory array device simulation model obtained from the single event upset recovery numerical simulation;

[0096] Step 5: Analyze the key factors affecting the SEE recovery by combining the heavy ion broad beam experimental results of step 1 and the SEE recovery numerical simulation results of step 4.

[0097] Based on the results of the heavy ion wide beam experiment in step 1, the effect of different test conditions on the single-particle upset recovery is analyzed; through the numerical simulation of the single-particle upset recovery of the local storage array in step 4, the degree of influence of changes in different simulation conditions on parameters such as the electrode voltage, electrode current and well potential of each transistor in the local storage array is analyzed; finally, the key influencing factors of single-particle upset recovery are obtained.

[0098] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. For ordinary professional and technical personnel in this field, the specific technical solutions recorded in the above embodiments can be modified, or some of the technical features therein can be replaced by equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions protected by the present invention.

Claims

1. A single event upset recovery analysis method combining experiments and simulations, characterized in that: The following steps are involved: Step 1: Using a test system, a heavy ion wide beam experiment of single-particle upset and recovery is performed on the memory to be tested (7) on a heavy ion accelerator single-particle effect experiment terminal, and a single-particle upset and recovery topological graph of the memory to be tested (7) under different test conditions is obtained; The test system comprises a direct current power supply (1), a test mainboard (2), a control computer (3) and an irradiation plate (4); the heavy ion accelerator single-particle effect experimental terminal comprises a heavy ion beam lead-out terminal (5) and a sample holder (6); the output terminal of the direct current power supply (1) is connected to the first input terminal of the test mainboard (2), the first output terminal of the test mainboard (2) and the second output terminal of the test mainboard (2) are respectively connected to the control computer (3) and the input terminal of the irradiation plate (4); the bottom surface of the irradiation plate (4) is fixed on the sample holder (6), the top surface of the irradiation plate (4) is plugged or welded with a memory to be tested (7), and the memory to be tested (7) is connected to the sample holder (6). The wafer is located within the ion beam spot coverage range of the heavy ion beam outlet end (5); the memory to be tested (7) includes a memory array and peripheral circuits, and the memory array is composed of a plurality of identical memory cells arranged according to a certain rule; the test conditions include a memory working state and an ion incident condition, the memory working state includes a voltage bias and a test pattern, and the ion incident condition includes an ion linear energy transfer value and an ion incident angle; the heavy ion wide beam experiment includes multiple rounds of tests, and each time a test condition parameter value is changed, a new round of tests is performed until all preset test condition parameter values ​​are replaced; Step 2: For each round of testing in Step 1, plotting the memory array position corresponding to the obtained single event upset recovery topology in the memory array bitmap; comparing the single event upset recovery conditions in different areas of the memory array, and calculating a typical single event upset recovery topology; the typical single event upset recovery topology refers to a topology exhibiting a discontinuous feature; Step 3: Based on the typical SEP recovery topology graphs collected in Step 2, locate the region in the storage array where the SEP occurs, i.e., the local storage array; in combination with the heavy ion broad beam experimental test conditions, use the test system to perform a heavy ion microbeam experiment on the local storage array where the typical SEP recovery topology graphs are located, and obtain the precise sensitive position of the SEP recovery in each local storage array; Step 4: Construct and calibrate local memory array device simulation models corresponding to each local memory array located in step 3, following the progressive hierarchy of transistor → memory cell → local memory array; add a physical model of the single event effect caused by heavy ions to each local memory array device simulation model, perform single event upset recovery numerical simulation for each local memory array, and analyze the generation mechanism of the single event upset recovery; Step 5: Combine the heavy ion broad beam experimental results of step 1 and the single event upset recovery numerical simulation results of step 4 to analyze the key influencing factors of single event upset recovery.

2. The single event upset recovery analysis method combining experiment and simulation according to claim 1, characterized in that: The step 1 is specifically as follows: Step 1.1, setting the initial test conditions of the memory to be tested (7), carrying out a round of heavy ion wide beam experiments, monitoring the single particle upset data in real time through the test system, and saving the single particle upset data after the round of irradiation is completed; the specific implementation process of setting the initial test conditions of the memory to be tested (7) is: setting the working state of the memory to be tested (7) through the control computer (3), and the professional personnel of the heavy ion accelerator maintenance team setting the ion incidence conditions; the single particle upset data includes the time when the single particle upset is detected, the data bit information of the upset, and the logical address information of the upset; Step 1.2: Change one of the initial test conditions and complete a new round of testing according to the test method described in step 1.

1. Step 1.3: If all preset test conditions have been changed, proceed to step 1.4; otherwise, return to step 1.2; Step 1.4: Compile a mapping program based on the mapping relationship between the logical address and the physical address of the memory. Through the mapping program and the test data of each round, obtain the single event upset of the memory in each test round and then restore the topology graph.

3. The single event upset recovery analysis method combining experiment and simulation according to claim 2, characterized in that: The step 3 is specifically as follows: Step 3.

1. Select a typical single-event upset and recovery topology obtained in step 2, set the test conditions of the heavy ion microbeam experiment based on its corresponding heavy ion broad-beam experiment test conditions, and simultaneously locate the corresponding local storage array. Use the local storage array as the scanning area of ​​the heavy ion microbeam experiment, focus the heavy ion microbeam on the surface of the scanning area layout, and perform point-by-point traversal irradiation. The irradiation points cover the entire scanning area. The test system monitors the upset data of the memory at all irradiation points in real time. After the scan is completed, save the test data. At this point, a round of heavy ion microbeam experiment testing is completed. Step 3.2: Conduct a new round of heavy ion microbeam experimental tests for other typical single-event upset recovery topologies according to the method described in step 3.1 until all the tests for the typical single-event upset recovery topologies obtained in step 2 are completed. Step 3.3: Obtain the precise sensitive location of the SEU recovery in each test round using the test data from each round and the mapping program compiled in step 1.

4.

4. The single event upset recovery analysis method combining experiment and simulation according to claim 3, characterized in that: The step 4 is specifically as follows: Step 4.1, select a local storage array located in step 3.1, and build and calibrate a device simulation model of the local storage array according to the progressive hierarchy of transistor → memory cell → local storage array; Step 4.2: Add a physical model of the single-event effect caused by heavy ions to the local storage array device simulation model obtained in step 4.1, simulate the local storage array, and set simulation conditions based on the heavy ion microbeam experiment performed in step 3: the simulation conditions of the local storage array are consistent with the test conditions set for this round of testing in the heavy ion microbeam experiment, and the ion incident position in the simulation is the precise sensitive position obtained in this round of testing in the heavy ion microbeam experiment and its adjacent transistors; After the simulation conditions are set, a single-event upset recovery numerical simulation is performed to obtain the single-event response waveform of each storage unit in the local storage array under different ion incident positions, and the single-event upset recovery topology of the local storage array is obtained. At the same time, the electrode voltage, electrode current and well potential data of each transistor in the local storage array are monitored and saved; The physical model of the single event effect caused by heavy ions is: G(l,w,t)=G LET (l)×R(w,l)×T(t), Where: G(l,w,t) is the carrier generation rate caused by heavy ions; G LET (l) is the carrier generation density of ion linear energy transfer; R(w,l) is the spatial distribution function of carriers; T(t) is the time distribution function of carriers; Step 4.3: Repeat steps 4.1 to 4.2 to sequentially perform the single event upset and recovery numerical simulations for each of the following local storage arrays until all simulations corresponding to all local storage arrays of the heavy ion microbeam experiment are completed. Step 4.4: Analyze the generation mechanism of the single event upset recovery based on the changes in the electrode voltage, electrode current, and well potential of each transistor in each local memory array device simulation model obtained from the single event upset recovery numerical simulation.

5. The single event upset recovery analysis method combining experiment and simulation according to claim 4, characterized in that: The step 4.1 is specifically as follows: Step 4.1.1, constructing a transistor device simulation model, solving the semiconductor device numerical calculation model equation to obtain an IV characteristic curve of the transistor device simulation model, comparing the IV characteristic curve of the transistor device simulation model with the IV characteristic curve of the transistor SPICE intensive model, and if the IV characteristic curve is inconsistent, adjusting the transistor device simulation model parameters until the IV characteristic curve is consistent, thereby completing the electrical characteristic calibration of the transistor device simulation model; the IV characteristic curve includes a transistor transfer characteristic curve and an output characteristic curve; The semiconductor numerical calculation model equation includes Poisson's equation: Drift-diffusion equation: Carrier continuity equation: in: ε is the dielectric constant of silicon; is the electric potential; q is the electron charge; p is the hole density; n is the electron density; is the ionized donor impurity concentration; is the concentration of ionized acceptor impurities; G n , G p are the generation rates of electrons and holes, respectively; R n 、R p are the recombination rates of electrons and holes, respectively; are the current densities of electrons and holes, respectively; μ n 、μ p are the mobility of electrons and holes, respectively; is the electric field density; D n 、D p are the diffusion coefficients of electrons and holes, respectively; Step 4.1.2: Build a memory cell device simulation model based on the transistor device simulation model, solve the semiconductor device numerical calculation model equation to obtain the butterfly characteristic curve of the memory cell device simulation model, compare the butterfly characteristic curve of the memory cell device simulation model with the butterfly characteristic curve of the SPICE intensive model of the memory cell, and if the two are inconsistent, adjust the memory cell device simulation model parameters until they are consistent, thereby completing the electrical characteristic calibration of the memory cell device simulation model; Step 4.1.

3. According to the number of rows and columns of the local storage array, a local storage array device simulation model is established based on the storage cell device simulation model, and the semiconductor device numerical calculation model equation is solved to obtain the butterfly characteristic curve of each storage cell device simulation model in the local storage array. The butterfly characteristic curve of each storage cell device simulation model is compared with the butterfly characteristic curve of the SPICE intensive model of the storage cell. If the two are inconsistent, the parameters of the storage cell device simulation model are adjusted until the two are consistent. At this point, the electrical characteristic calibration of the local storage array device simulation model is completed.

6. The single event upset recovery analysis method combining experiment and simulation according to claim 5, characterized in that: The specific steps of step 5 are as follows: based on the results of the heavy ion wide beam experiment in step 1, analyzing the effect of different test conditions on the single particle upset recovery; through the single particle upset recovery numerical simulation of the local storage array in step 4, analyzing the degree of influence of changes in different simulation conditions on the electrode voltage, electrode current and well potential parameters of each transistor in the local storage array; and finally obtaining the key influencing factors of single particle upset recovery.

7. The single event upset recovery analysis method combining experiment and simulation according to any one of claims 1 to 6, characterized in that: In step 1, the ion beam spot size of the heavy ion wide beam experiment is on the order of centimeters, the beam spot covers the entire wafer of the memory to be tested (7), and the ion incident position is randomly distributed within the wafer of the memory to be tested (7); in step 3, the ion beam spot size of the heavy ion microbeam experiment is on the order of micrometers, and the ion incident position is precisely positioned on the wafer of the memory to be tested (7).

Images