A verification method, device, equipment and readable storage medium

By constructing write attributes, read attributes, and comparison attributes, the timing and data consistency of bus interface signals are automatically verified, solving the problems of low efficiency and easy error in the existing technology, and realizing efficient and accurate signal timing and data consistency verification.

CN115640173BActive Publication Date: 2026-06-23SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
Filing Date
2022-09-09
Publication Date
2026-06-23

AI Technical Summary

Technical Problem

Existing technologies are inefficient and prone to errors when verifying the timing of bus interface signals and the correctness of read and write data, especially when performing read and write operations and random data tests within the memory address range, which is particularly time-consuming and labor-intensive.

Method used

By constructing write attributes, read attributes, and comparison attributes, the timing and data consistency of bus interface signals are automatically verified. Assertion attributes are set using an assertion language for automatic verification, reducing manual intervention.

Benefits of technology

It improves verification efficiency and accuracy, reduces the time and error rate of manual observation of simulation waveforms, and realizes automated signal timing and data consistency verification.

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Abstract

The application discloses a verification method, device and equipment and a readable storage medium. The method comprises the following steps: constructing a write attribute, a read attribute and a comparison attribute according to operation representation bus interface signals and time sequences corresponding to write data and read data; binding the operation representation bus interface signals with corresponding bus interface signals of a to-be-tested module; judging whether signals corresponding to write data in bus interface signals of the to-be-tested module satisfy the write attribute and whether signals corresponding to read data satisfy the read attribute according to a binding relationship, so as to verify whether the time sequence is correct; and comparing write data and corresponding read data of the to-be-tested module according to the comparison attribute, so as to verify the consistency of the read-write data. The technical scheme disclosed by the application constructs the write attribute, the read attribute and the comparison attribute, automatically verifies corresponding time sequences by using the write attribute and the read attribute, and automatically verifies read-write data by using the comparison attribute, so that the verification efficiency and the verification accuracy are improved.
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Citation Information

Patent Citations

  • Hardware Monitor to Verify Memory Units

    US20170133104A1