A method and apparatus for driving modulation

Abstract

The application provides a driving modulation method and device applied to a liquid crystal on silicon (LCoS), the driving modulation method comprising: receiving first information, the first information comprising indication information of a first logic sequence, the first logic sequence comprising a first digital logic and / or a second digital logic, the first digital logic corresponding to a first pulse waveform signal, the second digital logic sequence corresponding to a second pulse waveform signal, at least one of the first pulse waveform signal and the second pulse waveform signal comprising a high level and a low level, the first pulse waveform signal being different from the second pulse waveform signal; and outputting a liquid crystal driving voltage of the LCoS according to the first information. The method realizes dithering suppression through a lower frequency refreshed logic sequence, and reduces the data transmission bandwidth required by a backplane chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of optical communication, and more particularly, to a driving modulation method and device. BACKGROUND

[0002] At present, optical networks are continuously evolving towards large capacity, low latency and intelligentization. Optical switching technologies such as large-scale reconfigurable optical add-drop multiplexer (ROADM) and optical cross-connect (OXC) not only support current commercial optical networks, but also are one of the key technologies to realize the next generation of optical networks.

[0003] Among them, the wavelength selective switch (WSS) as the core device in the ROADM networking has the functions of controlling the on-off of services, wavelength switching, channel changing, etc., which can alleviate the wavelength competition of complex networks and significantly improve the network configuration flexibility. As the core device of OXC, the port / channel expansion of WSS has important value for realizing more integrated multi-dimensional network scheduling, its fast switching capability for realizing stronger scheduling and protection capability of complex networks, and its complexity reduction for realizing higher reliability and lower cost.

[0004] The WSS can realize the function of distributing any wavelength service to any port with any attenuation through software-controlled optical paths. The liquid crystal on silicon (LCoS), or LCoS array, is one of the devices for realizing the above function. With the expansion of WSS port / channel and the improvement of switching speed, LCoS needs to realize the expansion of pixel scale and the improvement of liquid crystal response speed, which makes the contradiction between jitter suppression and interface data bandwidth more obvious.

[0005] Therefore, how to reduce the interface data transmission bandwidth under the premise of ensuring reliable signal quality and then realize higher performance WSS is an urgent problem to be solved. SUMMARY

[0006] The present application provides a driving modulation method and device, which can reduce the interface data transmission bandwidth under the premise of ensuring reliable signal quality and then realize higher performance WSS.

[0007] In a first aspect, a driving modulation method is provided, which is applied to a liquid crystal on silicon (LCoS) and includes: receiving first information, the first information including indication information of a first logic sequence, the first logic sequence including a first digital logic and / or a second digital logic, the first digital logic corresponding to a first pulse waveform signal, the second digital logic sequence corresponding to a second pulse waveform signal, at least one of the first pulse waveform signal and the second pulse waveform signal including a high level and a low level, the first pulse waveform signal being different from the second pulse waveform signal; and outputting a liquid crystal driving voltage of the LCoS according to the first information.

[0008] For example, the first logic sequence can be "1010", or "1111", or "0000", etc. In this case, "1" is the first digital logic, and "0" is the second digital logic. The logic "1" is used to indicate the first pulse waveform signal (for example, pattern A), and the logic "0" is used to indicate the second pulse waveform signal (for example, pattern B).

[0009] In the embodiments of the present application, the logic "1" and the logic "0" correspond to two different high-low level pulse waveform signals (absolute values) of the liquid crystal driving voltage, respectively. Alternatively, the logic "1" corresponds to the pulse waveform signal including the high-low level, and the logic "0" corresponds to the low level; or the logic "1" corresponds to the high level, and the logic "0" corresponds to the pulse waveform signal including the high-low level, etc. The present application does not make a specific limitation in this regard.

[0010] It should be noted that in the output of the liquid crystal driving voltage of the LCoS according to the first information, the pixel of the LCoS needs to determine the corresponding common voltage V com and the pixel voltage V pix , and calculate the absolute value of the difference between the common voltage and the pixel voltage to further output the liquid crystal driving voltage V. Generally, the common voltage is fixed.

[0011] For example, the first pulse waveform signal (for example, pattern A) can be a square wave with a duty cycle of 90%, and the second pulse waveform signal (for example, pattern B) can be a square wave with a duty cycle of 10%; or the first pulse waveform signal (for example, pattern A) can be a square wave with a duty cycle of 90%, and the second pulse waveform signal (for example, pattern A) can be a square wave with a duty cycle of 20%; or the first pulse waveform signal (for example, pattern A) can be a square wave with a duty cycle of 90%, and the second pulse waveform signal (for example, pattern B) can be a square wave with a duty cycle of 0%, i.e. only pattern A can be directly set, etc. The present application does not make a specific limitation in this regard.

[0012] According to the scheme provided in the application, a driving modulation method is adopted, in which logical "1" and logical "0" correspond to two different high-low level pulse waveforms of liquid crystal driving voltage (absolute value), so that the jitter is inhibited through a lower frequency refresh logical sequence, and the data transmission bandwidth required by the backplane chip is reduced.

[0013] In combination with the first aspect, in some implementations of the first aspect, the first information further includes a first pulse waveform signal and a second pulse waveform signal.

[0014] In this implementation, the pixels of the LCoS further receive the first pulse waveform signal and the second pulse waveform signal, and output corresponding liquid crystal driving voltages through the received first logical sequence.

[0015] In combination with the first aspect, in some implementations of the first aspect, the first pulse waveform signal and the second pulse waveform signal are pre-configured.

[0016] In this implementation, the pixels of the LCoS do not need to receive the first pulse waveform signal and the second pulse waveform signal, and the data transmission bandwidth requirement of the backplane chip can be reduced to a certain extent.

[0017] In combination with the first aspect, in some implementations of the first aspect, the repetition frequency of the first pulse waveform signal is an integer multiple of the first sub-frame frequency, and the repetition frequency of the second pulse waveform signal is an integer multiple of the second sub-frame frequency.

[0018] In this implementation, the first pulse waveform signal and the second pulse waveform signal are adjusted in real time. For example, the repetition frequency of the first pulse waveform signal and the second pulse waveform signal is determined according to the corresponding sub-frame frequency. Generally, the sub-frame frequency is fixed at 3600HZ, and the repetition frequency of the first pulse waveform signal and the second pulse waveform signal is an integer multiple of the corresponding sub-frame frequency. In particular, the repetition frequency of the pulse waveform signal is an exponential multiple of the sub-frame frequency, for example, 32 times, etc.

[0019] In combination with the first aspect, in some implementations of the first aspect, the first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; wherein the first pulse waveform signal is input to each pixel of the LCoS backplane chip through a first interface, the second pulse waveform signal is input to each pixel of the LCoS backplane chip through a second interface, and the first interface is different from the second interface.

[0020] In this implementation, the waveform generator is placed in the external circuit of the LCoS pixel array, and the first pulse waveform signal and the second pulse waveform signal need to be connected to the LCoS through two chip ports. This implementation can effectively drive the voltage swing to be reduced, for example, 0.5V to 4.5V, etc.

[0021] In some implementations of the first aspect, the first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator, and the waveform generator is integrated in the LCoS backplane chip.

[0022] In this implementation, the waveform generator is further integrated in the LCoS backplane chip, which can generate a signal with high rate, reduce noise interference of signal transmission, and reduce complexity of the interface.

[0023] Further, an exclusive-OR logic (XOR) is configured in the waveform generator. For example, the LCoS interface inputs a pattern A waveform, and the waveform generator is further located in the backplane chip, and the core of the waveform generator is an exclusive-OR logic (XOR). Then, for a logic "1", the first pulse waveform signal (e.g., pattern A) and the XOR operation thereof directly generate the pattern A; for a logic "0", the first pulse waveform signal (e.g., pattern A) and the XOR operation thereof generate the second pulse waveform signal (e.g., pattern B); and the pattern A and the pattern B are transmitted to each pixel. For example, the pattern A is a square wave with a duty cycle of 90%, and the pattern B is a square wave with a duty cycle of 10% obtained through the XOR operation.

[0024] In this implementation, the patterns of all the pixels are generated by a signal source, and the patterns of all the pixels have mutual time delay but the duty cycles are unchanged in the process of pixel scanning. Since the patterns are generated by a unified signal source, the complexity of the internal circuit of the chip can be further reduced.

[0025] In some implementations of the first aspect, an exclusive-OR logic (XOR) is configured in each pixel of the LCoS backplane chip.

[0026] In this implementation, since the patterns are generated by a unified signal source, the complexity of the interface of the chip can be further reduced, and the integration of the internal circuit of the pixel can be realized.

[0027] For example, the interface inputs a pattern A waveform, and the exclusive-OR logic (XOR) is further located in the pixel circuit. For a logic "1", the pattern A and the XOR operation thereof directly generate the pattern A; for a logic "0", the pattern A and the XOR operation thereof generate a pattern B.

[0028] With reference to the first aspect, in some implementations of the first aspect, when the absolute value of the liquid crystal driving voltage of the LCoS changes, the first information further comprises a third pulse pattern signal and a fourth pulse pattern signal, the third pulse pattern signal corresponds to the first digital logic, the fourth pulse pattern signal corresponds to the second digital logic sequence, at least one of the third pulse pattern signal and the fourth pulse pattern signal comprises a high level and a low level, the third pulse pattern signal is different from the first pulse pattern signal, and the fourth pulse pattern signal is different from the second pulse pattern signal.

[0029] In this implementation, a special pattern is used in the switching process, which can achieve the effect of overshoot or undershoot, and improve the response speed of the switching process.

[0030] With reference to the first aspect, in some implementations of the first aspect, the LCoS comprises a plurality of pixels, the plurality of pixels comprising a first pixel and a second pixel, the first pixel being an i-th row and m-th column pixel, and the second pixel being a j-th row and m-th column pixel, and a relative time delay when the first pulse pattern signal is simultaneously input to the first pixel and the second pixel being (j-i)T, wherein i, j, and m are positive integers greater than or equal to 1, i is different from j, T is a time of one row scanning.

[0031] Taking the first pulse pattern signal pattern A as an example, pattern A is uniformly input to the LCoS backplane chip, and each row is delayed. Taking the pattern A of the 1st row and the Nth row, the pattern A of the Nth row is delayed relative to the 1st row by (N-1)T, wherein T is a time of one row scanning.

[0032] In this implementation, the pattern between the rows of pixels can be aligned with the logic refresh.

[0033] The second aspect provides a driving modulation device, which comprises a transceiver unit configured to: receive first information, the first information comprising indication information of a first logic sequence, the first logic sequence comprising a first digital logic and / or a second digital logic, the first digital logic corresponding to a first pulse pattern signal, the second digital logic sequence corresponding to a second pulse pattern signal, at least one of the first pulse pattern signal and the second pulse pattern signal comprising a high level and a low level, the first pulse pattern signal being different from the second pulse pattern signal; and output a liquid crystal driving voltage of an LCoS according to the first information.

[0034] For example, the first logic sequence can be "1010", or "1111", or "0000", etc. Here, "1" is the first digital logic, and "0" is the second digital logic. The logic "1" is used to indicate the first pulse waveform signal (e.g., pattern A), and the logic "0" is used to indicate the second pulse waveform signal (e.g., pattern B).

[0035] In the embodiments of the present application, the logic "1" and the logic "0" respectively correspond to two different high-low level pulse waveform signals in terms of the absolute value of the liquid crystal driving voltage. Alternatively, the logic "1" corresponds to a pulse waveform signal including high and low levels, and the logic "0" corresponds to a low level; or the logic "1" corresponds to a high level, and the logic "0" corresponds to a pulse waveform signal including high and low levels, etc., which are not limited in the present application.

[0036] It should be noted that, in the liquid crystal driving voltage of the LCoS output according to the first information, the pixel of the LCoS needs to determine the corresponding common voltage V com and the pixel voltage V pix , and calculate the absolute value of the difference between the common voltage and the pixel voltage to further output the liquid crystal driving voltage V. Generally, the common voltage is fixed.

[0037] For example, the first pulse waveform signal (e.g., pattern A) can be a square wave with a duty cycle of 90%, and the second pulse waveform signal (e.g., pattern B) can be a square wave with a duty cycle of 10%; or the first pulse waveform signal (e.g., pattern A) can be a square wave with a duty cycle of 90%, and the second pulse waveform signal (e.g., pattern A) can be a square wave with a duty cycle of 20%; or the first pulse waveform signal (e.g., pattern A) can be a square wave with a duty cycle of 90%, and the second pulse waveform signal (e.g., pattern B) can be a square wave with a duty cycle of 0%, i.e., only pattern A can be directly set, etc., which are not limited in the present application.

[0038] According to the scheme provided in the present application, the logic "1" and the logic "0" respectively correspond to two different high-low level pulse waveform driving modulation methods in terms of the absolute value of the liquid crystal driving voltage, so as to realize dithering suppression through a logic sequence with a lower refresh frequency, and reduce the data transmission bandwidth required by the backplane chip.

[0039] In combination with the second aspect, in some implementations of the second aspect, the first information further includes the first pulse waveform signal and the second pulse waveform signal.

[0040] In the implementation, the pixel of the LCoS further receives the first pulse waveform signal and the second pulse waveform signal, and outputs a corresponding liquid crystal driving voltage through the received first logic sequence.

[0041] In combination with the second aspect, in some implementations of the second aspect, the first pulse waveform signal and the second pulse waveform signal are pre-configured.

[0042] In the implementation, the pixel of the LCoS does not need to receive the first pulse waveform signal and the second pulse waveform signal, which can reduce the data transmission bandwidth requirement of the backplane chip to some extent.

[0043] In combination with the second aspect, in some implementations of the second aspect, the repetition frequency of the first pulse waveform signal is an integer multiple of the first sub-frame frequency, and the repetition frequency of the second pulse waveform signal is an integer multiple of the second sub-frame frequency.

[0044] In the implementation, the first pulse waveform signal and the second pulse waveform signal are adjusted in real time. For example, the repetition frequency of the first pulse waveform signal and the second pulse waveform signal is determined according to the corresponding sub-frame frequency. Generally, the sub-frame frequency is fixed at 3600HZ, and the repetition frequency of the first pulse waveform signal and the second pulse waveform signal is an integer multiple of the corresponding sub-frame frequency. In particular, the repetition frequency of the pulse waveform signal is an exponential multiple of the sub-frame frequency, for example, 32 times, etc.

[0045] In combination with the second aspect, in some implementations of the second aspect, the first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; wherein the first pulse waveform signal is input to each pixel of the LCoS backplane chip through a first interface, the second pulse waveform signal is input to each pixel of the LCoS backplane chip through a second interface, and the first interface is different from the second interface.

[0046] In the implementation, the waveform generator is placed in the external circuit of the LCoS pixel array, and the first pulse waveform signal and the second pulse waveform signal need to be connected to the LCoS through two chip ports. This implementation can effectively drive the voltage swing to be reduced, for example, 0.5V to 4.5V, etc.

[0047] In combination with the second aspect, in some implementations of the second aspect, the first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; wherein the waveform generator is integrated in the LCoS backplane chip.

[0048] In the implementation, the waveform generator is further integrated in the LCoS backplane chip, which has high signal generation rate, reduces noise interference of signal transmission, and reduces the complexity of the packaging interface.

[0049] Further, an XOR logic is configured in the waveform generator. For example, the LCoS interface inputs a pattern A waveform, and a further waveform generator is located in the backplane chip, and the core of the waveform generator is an XOR logic. Then, for a logic "1", the first pulse waveform signal (e.g., pattern A) is directly generated by the XOR operation of the first pulse waveform signal (e.g., pattern A) to generate the pattern A; for a logic "0", the first pulse waveform signal (e.g., pattern A) is directly generated by the XOR operation of the first pulse waveform signal (e.g., pattern A) to generate the second pulse waveform signal (e.g., pattern B); and the pattern A and the pattern B are transmitted to each pixel. For example, the pattern A is a square wave with a duty cycle of 90%, and the pattern B is a square wave with a duty cycle of 10% obtained by the XOR operation.

[0050] In the implementation, the patterns of all the pixels are generated by a unified signal source, and the patterns of all the pixels have a mutual time delay in the process of pixel scanning, but the duty cycles are unchanged. Since the patterns are generated by the unified signal source, the complexity of the internal circuit of the chip can be further reduced.

[0051] With reference to the second aspect, in some implementations of the second aspect, an XOR logic is configured in each pixel of the LCoS backplane chip.

[0052] In the implementation, since the patterns are generated by the unified signal source, the complexity of the chip interface can be further reduced, and the integration of the internal circuit of the pixel can be realized.

[0053] For example, the interface inputs a pattern A waveform, and a further XOR logic is located in the pixel circuit. For a logic "1", the pattern A is directly generated by the XOR operation of the pattern A to generate the pattern A; for a logic "0", the pattern A is directly generated by the XOR operation of the pattern A to generate the pattern B.

[0054] With reference to the second aspect, in some implementations of the second aspect, when the absolute value of the liquid crystal driving voltage of the LCoS changes, the first information further includes a third pulse waveform signal and a fourth pulse waveform signal, the third pulse waveform signal corresponds to the first digital logic, the fourth pulse waveform signal corresponds to the second digital logic sequence, at least one of the third pulse waveform signal and the fourth pulse waveform signal includes a high level and a low level, the third pulse waveform signal is different from the first pulse waveform signal, and the fourth pulse waveform signal is different from the second pulse waveform signal.

[0055] In the implementation, a special pattern is used in the switching process, and the effects of overshoot or undershoot can be realized to improve the response speed of the switching process.

[0056] With reference to the second aspect, in some implementations of the second aspect, the LCoS includes a plurality of pixels, the plurality of pixels including a first pixel and a second pixel, the first pixel being an i-th row and m-th column pixel, the second pixel being a j-th row and m-th column pixel, and a relative time delay when the first pulse waveform signal is simultaneously input to the first pixel and the second pixel being (j-i)T, where i, j, and m are positive integers greater than or equal to 1, i is different from j, T is a time of one row scanning.

[0057] Taking the first pulse waveform signal pattern A as an example, pattern A is uniformly input to the LCoS backplane chip, and each row is delayed. Taking the pattern A of the 1st row and the Nth row, the pattern A of the Nth row is delayed relative to the 1st row by (N-1)T, where T is a time of one row scanning.

[0058] In this implementation, the patterns between the rows of pixels can be aligned with the logical refresh.

[0059] In a third aspect, a liquid crystal on silicon (LCoS) is provided, including: a liquid crystal modulator including a plurality of pixels, each pixel of the plurality of pixels receiving a logic sequence and at least one pulse waveform signal, wherein the logic sequence corresponding to any two pixels is different, and the at least one pulse waveform signal includes a high level and a low level; an interface configured to obtain the at least one pulse waveform signal; and a controller configured to control a phase state of the plurality of pixels of the liquid crystal modulator according to the at least one pulse waveform signal, so as to output a liquid crystal driving voltage of the LCoS.

[0060] In a fourth aspect, a liquid crystal on silicon (LCoS) is provided, including: a liquid crystal modulator including a plurality of pixels, each pixel of the plurality of pixels receiving a logic sequence and at least one pulse waveform signal, wherein the logic sequence corresponding to any two pixels is different, and the at least one pulse waveform signal includes a high level and a low level; a waveform generator configured to generate the at least one pulse waveform signal; an interface configured to obtain the at least one pulse waveform signal; and a controller configured to control a phase state of the plurality of pixels of the liquid crystal modulator according to the at least one pulse waveform signal, so as to output a liquid crystal driving voltage of the LCoS.

[0061] In a fifth aspect, a wavelength selective switch (WSS) is provided, including: an input port configured to input an optical signal, the optical signal having a plurality of wavelength channels; a liquid crystal on silicon (LCoS) configured to drive and modulate the optical signal input by the input port; and an output port configured to output the optical signal after being driven and modulated by the LCoS.

[0062] In a sixth aspect, a processing apparatus is provided, including various modules or units for performing the method in the first aspect and any possible implementation manner thereof.

[0063] A seventh aspect provides a processing apparatus including a processor coupled to a memory, which can be used to perform the methods of the first aspect and its possible implementations. Optionally, the processing apparatus further includes a memory. Optionally, the processing apparatus further includes a communication interface, to which the processor is coupled.

[0064] In one implementation, the processing device is a processing apparatus. In this case, the communication interface can be a transceiver, or an input / output interface. In another implementation, the processing device is a chip or a chip system. In this case, the communication interface can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip or chip system. The processor can also be embodied as processing circuitry or logic circuitry.

[0065] Eighthly, a processing apparatus is provided, comprising: an input circuit, an output circuit, and a processing circuit. The processing circuit is configured to receive signals through the input circuit and transmit signals through the output circuit, thereby enabling the method of the first aspect and any possible implementation thereof to be implemented.

[0066] In specific implementation, the aforementioned processing device can be a chip, the input circuit can be an input pin, the output circuit can be an output pin, and the processing circuit can be a transistor, gate circuit, flip-flop, and various logic circuits, etc. The input signal received by the input circuit can be received and input by, for example, but not limited to, a receiver, and the signal output by the output circuit can be, for example, but not limited to, output to a transmitter and transmitted by the transmitter. The input circuit and output circuit can be different circuits or the same circuit, in which case the circuit is used as the input circuit and output circuit at different times. This application does not limit the specific implementation of the processor and various circuits.

[0067] Ninthly, this application provides a communication device, including a processor and a communication interface, the communication interface being used to receive signals and transmit the received signals to the processor, the processor processing the signals to cause the communication device to perform the method as described in the first aspect or any possible implementation thereof.

[0068] Optionally, the aforementioned communication interface can be an interface circuit, an input / output interface, etc., and the processor can be a processing circuit, a logic circuit, etc.

[0069] Optionally, the communication device in the ninth aspect can be a chip or an integrated circuit.

[0070] In a tenth aspect, this application provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the method as described in the first aspect or any possible implementation thereof to be performed.

[0071] In an eleventh aspect, the present application provides a computer program product, which comprises computer program codes, when the computer program codes are run on a computer, make the method as in the first aspect or any possible implementation manner thereof be executed.

[0072] In a twelfth aspect, the present application provides a chip, comprising: a processor, configured to call and run a computer program from a memory, so that a communication device installed with the chip executes the method as in the first aspect or any possible implementation manner of the first aspect.

[0073] According to the scheme of the embodiments of the present application, the logical "1" and the logical "0" correspond to two different high-low level pulse waveforms of the liquid crystal driving voltage (absolute value) respectively, so that the dithering is inhibited by the logical sequence of the lower frequency refresh, and the data transmission bandwidth required by the backplane chip is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0074] Figure 1 is an example schematic diagram of a wavelength selective switch WSS device to which the present application is applied.

[0075] Figure 2 is an example schematic diagram of a conventional liquid crystal on silicon LCoS driving modulation method.

[0076] Figure 3 is an example schematic diagram of a driving modulation method for liquid crystal on silicon LCoS to which the present application is applied.

[0077] Figure 4 is an example schematic diagram of a driving modulation method for liquid crystal on silicon LCoS to which the present application is applied.

[0078] Figure 5 is an example schematic diagram of a driving modulation method for liquid crystal on silicon LCoS to which the present application is applied.

[0079] Figure 6 is another example schematic diagram of a driving modulation method for liquid crystal on silicon LCoS to which the present application is applied.

[0080] Figure 7 is still another example schematic diagram of a driving modulation method for liquid crystal on silicon LCoS to which the present application is applied.

[0081] Figure 8 is still another example schematic diagram of a driving modulation method for liquid crystal on silicon LCoS to which the present application is applied.

[0082] Figure 9 is still another example schematic diagram of a driving modulation method for liquid crystal on silicon LCoS to which the present application is applied.

[0083] Figure 10is another example schematic diagram of a driving modulation method for a liquid crystal on silicon (LCoS) applicable to the present application.

[0084] Figure 11 is an example schematic diagram of a driving modulation device for a liquid crystal on silicon (LCoS) applicable to the present application.

[0085] Figure 12 is another example schematic diagram of a driving modulation device for a liquid crystal on silicon (LCoS) applicable to the present application. DETAILED DESCRIPTION

[0086] The technical solutions in the present application will be described below in conjunction with the accompanying drawings.

[0087] The technical solutions in the present application can be applied to various communication systems capable of transmitting data using light beams (or signal light), and can be applied to the fields of optical communication, optical switching, digital center network, microwave photonics, liquid crystal antenna, optical phased array, beamforming, beam scanning, laser radar, laser projection, laser television, holographic display, adaptive optics, laser beam shaping, laser processing, ultrafast laser pulse shaping, laser active imaging, optical tomography, and retinal imaging. For example, the technical solutions in the present application can be used in optical switching devices (or optical switching structures) in these fields, such as the core devices of reconfigurable optic add-drop multiplexer (ROADM) and optical cross-connect (OXC) equipment, such as WSS devices.

[0088] Figure 1 is an example schematic diagram of a wavelength selective switch (WSS) device applicable to the present application, i.e., an application scenario of the LCoS driving modulation method. In the WSS, the phase-type LCoS is the core switching engine of the WSS, and the main function is to realize a reflection-type diffraction grating with a specific phase distribution to deflect the incident light beam to the corresponding exit direction. Due to the dynamic response of the liquid crystal to the change in driving voltage, the driving modulation mode of the LCoS pixel has a direct impact on the retention of the local liquid crystal deflection. Correspondingly, the jitter of the liquid crystal at the deflection position will introduce a dynamic deviation of the phase modulation (phase flicker), and then cause the light power coupled to the output port to fluctuate (power flicker), ultimately affecting the signal transmission quality.

[0089] As Figure 1As shown, it is a front view of a 1xN WSS device, i.e. having 1 input port and N output ports, realizing full optical connection between any pair of input port and output port. In other words, for the multi-wavelength mixed optical signal incident on the same input port, it can be output from any one of the N output ports. The lens group and grating in the WSS spatially separate each wavelength in the multi-wavelength mixed signal, and project different wavelength signals to different regions (or different regions of pixels) of the LCoS. Each pixel supports independent adjustment, controlling the liquid crystal phase in the pixel point to adjust the deflection angle of the light beam (or optical signal), thereby realizing optical switching function.

[0090] It should be understood that Figure 1 The number of input ports and the number of output ports are not equal, and are 1xN. This is only illustrative as an example. In specific implementation, the number of input ports and the number of output ports can be equal or not equal, for example, NxN, NxZ, N and Z are both positive integers, etc.

[0091] Specifically, the main components of the WSS device include: input / output port (or input / output fiber array) 101, main lens 102, and LCoS 103. For the outgoing light beam of the input port, after collimation by the main lens 102, it is irradiated on the LCoS 103. The LCoS 103 deflects and reflects the corresponding light beam, and focuses it to the corresponding output port again through the main lens 102. Among them, the LCoS 103 is a pixelated reflective device. In each pixel, the driving electrode generates an electric field to control the arrangement of liquid crystal molecules, thereby forming a specific phase distribution pattern. The driving modulation method of the technical solution of the present application is used to control the LCoS 103.

[0092] It should be understood that for different input ports, the LCoS 103 can independently deflect the corresponding light beam. For different output ports, the LCoS 103 can independently deflect the corresponding light beam.

[0093] In addition, the LCoS driving modulation method of the technical solution of the present application can also be applied to other application scenarios, such as other types of WSS, laser display and other systems / fields involving LCoS, and other types of liquid crystal spatial light modulators, such as transmissive liquid crystal spatial light modulation, etc.

[0094] It should be understood that Figure 1 The structure of the WSS shown is only illustrative as an example, and the present application is not limited thereto. For example, the WSS can also include optical path changing devices such as optical gratings, mirrors, etc.

[0095] For example, a light splitting grating can be arranged between the LCoS 103 and the input / output ports 101. Assume that the multi-wavelength mixed signal incident on the input port 101 includes multiple wavelengths (e.g., M), i.e., λ1~λM. M The light splitting grating is used to split the M single-wavelength signals from the multiple-wavelength signal. The LCoS 103 is used to switch the optical path of each single-wavelength signal to the corresponding output port 101. The light splitting grating is used to combine the multiple single-wavelength signals switched to the same output port and output from the output port 101, thereby realizing the switching of the optical signals. The light splitting grating can be a reflective grating, a transmissive grating, a dispersive prism, or a planar waveguide grating. In addition, to increase the dispersion effect, multiple gratings can be combined, or the optical path of the target signal light can be adjusted to pass through the same grating multiple times.

[0096] Figure 2 is an example schematic diagram of a conventional driving modulation method for a liquid crystal on silicon (LCoS), i.e., a conventional digital driving method (or pulse width modulation (PWM)). Assume that the WSS device has N ports in total, and each port supports M wavelength channels, thereby forming an N x M spot array. The N x M spot array corresponds to modulation by the LCoS 103 of the WSS device, which is divided into N x M pixel regions to adjust the deflection of the corresponding light beams. As shown in (a) in FIG. 1, Figure 2 The left graph in (a) in FIG. 1 is an N x M LCoS pixel array.

[0097] The LCoS can also be referred to as an LCoS array, which includes multiple pixel points, each of which supports independent adjustment and control of the liquid crystal phase in the pixel point, i.e., adjustment of the reflection angle and reflection intensity of the wavelength irradiated by the pixel point, thereby realizing software-controllable wavelength port scheduling or switching. In the industry, the set of states of all pixel points on the LCoS array is generally referred to as an LCoS image, i.e., a LCoS image determines the result of the allocation and attenuation applied by the WSS to all incident wavelength ports.

[0098] The LCoS technology uses the principle of a liquid crystal grating to adjust the reflection angle of light of different wavelengths to separate the light. Since there are no moving parts, the LCoS technology has considerable reliability. The LCoS technology uses the variation of the refractive index of a liquid crystal unit to control the reflection angle, which can be easily expanded and upgraded. Different channels correspond to different regions of the spatial light modulator (liquid crystal) array, and the transmission direction of the light is changed by adjusting the phase of the light spot, thereby achieving the purpose of switching different ports and adjusting the attenuation.

[0099] It should be noted that the term "image" in this application can be understood as information used to control the LCoS (e.g., the process of controlling the attenuation value or deflection angle of the wavelength channel performed by the LCoS), that is, the "image" can be understood as a collection of the states of all pixels on the LCoS array (e.g., the phase of the pixels).

[0100] The solution provided in this application is applicable to the above-mentioned "image" generation process. By adjusting the deflection angle (or attenuation) of the wavelength channel based on the "image" generated by LCoS in the manner provided in this application, crosstalk between ports can be effectively reduced, especially crosstalk between output ports corresponding to the same wavelength.

[0101] The example diagram in the middle is a cross-sectional view of a pixel 201 in an LCoS pixel array. Its main components include a common electrode 202, a liquid crystal layer 203, and a backplane pixel electrode 204. The common electrode 202 is connected to a common voltage signal source 205, providing a common voltage V. com The backplate pixel electrode 204 is connected to the pixel signal source 206 to provide pixel voltage V. pix The angle between the direction of the liquid crystal molecules and the z-direction is defined as the liquid crystal deflection angle.

[0102] The liquid crystal driving voltage V for the corresponding pixel of the loaded liquid crystal layer 203 is a common voltage V. com and pixel voltage V pix The difference, i.e., V = V com –V pix Liquid crystal molecules deflect under the influence of the liquid crystal driving voltage, resulting in corresponding phase modulation. The right figure shows the relationship between the liquid crystal deflection or phase modulation and the liquid crystal driving voltage; that is, as the absolute value of the liquid crystal driving voltage V increases, the liquid crystal deflection angle... The phase modulation amount increases accordingly. When the liquid crystal driving voltage V changes dynamically, the liquid crystal deflection angle... As the liquid crystal molecules interact with each other, their deflection angle changes with the driving voltage, resulting in a certain response time.

[0103] In particular, for digitally driven methods, such as Figure 2 As shown in (b), logic "1" or logic "0" is defined, corresponding to the absolute value |V| of the liquid crystal driving voltage V being high or low, respectively. To avoid ion aggregation and ensure a long lifespan for the liquid crystal molecules, the polarity of the liquid crystal driving electric field needs to be periodically reversed, i.e., the sign of the liquid crystal driving voltage. Correspondingly, the pixel voltage and the common voltage undergo periodic reversals (between high and low levels).

[0104] For example, for logic "1", the absolute value of the liquid crystal driving voltage V H The voltage is 5V. For logic "0", the absolute value of the LCD driving voltage is V. L (0V); correspondingly, the common voltage toggles once each for logic "1" and logic "0". For example, |V| = V H At that time, V com From the initial V comH (5V) Flip to V comL (0V), correspondingly V pix From the initial V pixL (0V) Flip to V pixH (5V), while ensuring the absolute value of the liquid crystal driving voltage remains unchanged, its positive and negative values ​​are flipped. Similarly, for |V|=V L V com From the initial V comH (5V) Flip to V comL (0V), correspondingly V pix Flip from the initial VpixH (5V) to V pixL (0V), while ensuring that the absolute value of the liquid crystal driving voltage remains unchanged, its positive and negative values ​​are flipped.

[0105] like Figure 2 As shown in (c), the LCoS backplane chip interface receives the transmitted logic sequence ("1" or "0") and, according to the common voltage V, com (For example, 5V or 0V), synchronously generating the corresponding pixel voltage V pix (For example, 5V or 0V), forming the liquid crystal driving voltage (for example, ±5V or 0V, i.e., absolute value 5V or 0V). The root mean square (RMS) value (V) corresponding to the absolute value of the liquid crystal driving voltage. rms The average angle corresponding to the liquid crystal deflection is When the logic sequence switches between "1" and "0", the liquid crystal deflects at a certain maximum angle. and a certain minimum angle The amplitude of the oscillation between relaxation and oscillation is... This characterizes the degree of flicker in liquid crystal deflection around the average position.

[0106] For example, the logical sequence contains "1" and "0" with a duty cycle of 50%, V rms= 2.5V, corresponding to the angle of liquid crystal deflection of 30°. When the logic sequence frequency is low (for example, 60Hz), the deflection angle jitter amplitude is 90 degrees; when the logic sequence frequency is increased (for example, 180Hz), the deflection angle jitter amplitude is reduced, and the corresponding flicker is suppressed. In addition, for the liquid crystal with shorter response time, it is easier to produce flicker, that is, the higher logic sequence frequency is required.

[0107] As shown in (d) in FIG. 1, Figure 2 For a large-scale pixel array, the logic sequence of each pixel is refreshed synchronously. At present, it is divided into subframes (bit-planes) for refreshing, and the logic received in the same subframe (‘1’ or ‘0’) is maintained unchanged.

[0108] In summary, Figure 2 The LCoS driving modulation method shown in FIG. 1 has the following disadvantages:

[0109] 1) Single pulse method is adopted, that is, there is only one set of ‘0’ and ‘1’ in each frame, and the flicker is serious, which cannot be applied to application scenarios such as WSS that require stable phase modulation;

[0110] 2) Multi-pulse method is adopted, that is, there are multiple ‘0’ and ‘1’ in each frame, or multiple subframes, and the chip transmission bandwidth requirement is greatly improved by writing the ‘1’ or ‘0’ pulse sequence at a high frequency;

[0111] 3) In order to meet the demand of WSS application for flicker suppression, the interface bandwidth required by the current 4K scale (~8M pixels) digital driving LCoS reaches ~50Gbps, which has approached the limit of high-speed interface (LVDS, 1Gbps) and backplane chip packaging (~200-300PIN), and it will be more difficult to further expand the pixel scale or improve the liquid crystal response speed.

[0112] In other words, for the current digital driving type LCoS, the driving modulation method that uses logic ‘1’ and logic ‘0’ to correspond to the high level or low level of the liquid crystal driving voltage (absolute value) respectively, often needs to use a higher subframe (bit-plane) refresh frequency to suppress flicker, which leads to the need of the LCoS backplane chip interface to provide a very high data transmission bandwidth, hindering the further improvement of the performance of LCoS pixel scale, liquid crystal response speed, phase modulation stability, etc.

[0113] With the expansion of WSS port / channel and the improvement of switching speed, the LCoS needs to realize the expansion of pixel scale and the improvement of liquid crystal response speed accordingly. The contradiction between flicker suppression and interface data bandwidth will be more obvious. Therefore, in order to realize a higher performance WSS under the premise of ensuring reliable signal quality (low flicker), a more effective LCoS driving modulation method needs to be proposed.

[0114] Therefore, in order to realize a higher performance WSS under the premise of ensuring reliable signal quality, a more effective LCoS driving modulation method is proposed in the present application, which adopts a driving modulation method of two different high-low level pulse waveforms corresponding to the driving voltage (absolute value) of liquid crystal of logic "1" and logic "0" respectively, so as to realize flicker suppression through a lower frequency refresh logic sequence, reduce the data transmission bandwidth required by the backplane chip, and further improve the performance of LCoS pixel scale, liquid crystal response speed, phase modulation stability, etc.

[0115] In order to facilitate the understanding of the embodiments of the present application, the following points are explained:

[0116] In various embodiments of the present application, the terms and / or descriptions of different embodiments are consistent and can be mutually referred to if there is no special description and logical conflict. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0117] In the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" describes the association between the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. In the textual description of the present application, the character " / ", generally represents that the front and rear associated objects are in an "or" relationship; in the formula of the present application, the character " / ", represents that the front and rear associated objects are in a "division" relationship.

[0118] It can be understood that the various numbers involved in the embodiments of the present application are only for convenient differentiation, and do not limit the scope of the embodiments of the present application. The size of the serial number of the above processes does not mean the execution order, and the execution order of the processes should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0119] In the embodiments of the present application, "first", "second", and various numbers are used for differentiation for convenience of description, and do not limit the scope of the embodiments of the present application. For example, different indication information is distinguished.

[0120] In the present application, "for indicating" can include for directly indicating and for indirectly indicating. When describing that certain indication information is for indicating A, it can include that the indication information directly indicates A or indirectly indicates A, and does not mean that A must be carried in the indication information.

[0121] In addition, the specific indication manner can also be various existing indication manners, for example but not limited to, the above indication manners and various combinations thereof, etc. The specific details of various indication manners can refer to the prior art, and will not be described herein. As can be known from the above, for example, when multiple information of the same type needs to be indicated, the indication manners of different information can be different. In the specific implementation process, the required indication manner can be selected according to the specific needs, and the selected indication manner is not limited by the embodiments of the present application, so that the indication manners involved in the embodiments of the present application should be understood as covering various methods that can enable the to-be-indicated party to know the to-be-indicated information.

[0122] In the embodiments of the present application, "when", "in the case of", "if", and the like all refer to the device making corresponding processing under certain objective circumstances, and are not limited by time, and do not require the device to have a judgment action when implemented, nor does it mean that there are other limitations.

[0123] The method provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0124] Figure 3 is an example schematic diagram of a driving modulation method for a silicon-based liquid crystal LCoS applicable to the present application. As shown in Figure 3 For any one pixel 301 of the LCoS pixel array, its pixel circuit receives a logic sequence "1" and a pulse waveform signal, that is, pattern A. For another pixel 302, its pixel circuit receives a logic sequence "2" and a pulse waveform signal, that is, pattern B. Among them, on the backplane chip, the logic sequence of each pixel can be introduced by different chip interfaces; the pulse waveform signal of each pixel is introduced through the same (group) interface. In addition, the backplane chip has a synchronous interface with the V com signal.

[0125] Among them, logic "1" corresponds to one pulse waveform signal pattern A, and logic "0" corresponds to another pulse waveform signal pattern B. For each pixel, by a specific logic sequence, that is, a logic sequence corresponding to a gray scale, a corresponding pattern is selected to be output to a liquid crystal driving voltage (absolute value), and then the deflection of the corresponding pixel liquid crystal is driven. Among them, in the LCoS operation, the pattern can be pre-configured to be fixed and unchanged, or can be adjusted in real time.

[0126] It should be understood that for different public voltages V com The pattern or logic sequence needs to be correspondingly inverted, i.e., the sign of the liquid crystal driving voltage is inverted, to ensure a long enough service life of the liquid crystal in the LCoS.

[0127] Figure 4 is an example schematic diagram of a driving modulation method for a silicon-based liquid crystal LCoS according to an embodiment of the present application, and the specific implementation steps 400 include:

[0128] S410, the silicon-based liquid crystal LCoS receives first information.

[0129] The first information includes indication information of a first logic sequence, the first logic sequence includes a first digital logic and / or a second digital logic, the first digital logic corresponds to a first pulse waveform signal, the second digital logic sequence corresponds to a second pulse waveform signal, at least one of the first pulse waveform signal and the second pulse waveform signal includes a high level and a low level, the first pulse waveform signal is different from the second pulse waveform signal.

[0130] For example, the first logic sequence can be "1010", or "1111", or "0000", etc. Wherein "1" is the first digital logic, and "0" is the second digital logic. The logic "1" is used to indicate the first pulse waveform signal (for example, pattern A), and the logic "0" is used to indicate the second pulse waveform signal (for example, pattern B).

[0131] In the embodiments of the present application, the logic "1" and the logic "0" correspond to two different high-low level pulse waveform signals of the liquid crystal driving voltage (absolute value) respectively. Alternatively, the logic "1" corresponds to the pulse waveform signal including high and low levels, and the logic "0" corresponds to the low level; or the logic "1" corresponds to the high level, and the logic "0" corresponds to the pulse waveform signal including high and low levels, etc., which are not limited in the present application.

[0132] For example, the first pulse waveform signal (for example, pattern A) can be a square wave with a duty cycle of 90%, and the second pulse waveform signal (for example, pattern B) can be a square wave with a duty cycle of 10%; or the first pulse waveform signal (for example, pattern A) can be a square wave with a duty cycle of 90%, and the second pulse waveform signal (for example, pattern A) can be a square wave with a duty cycle of 20%; or the first pulse waveform signal (for example, pattern A) can be a square wave with a duty cycle of 90%, and the second pulse waveform signal (for example, pattern B) can be a square wave with a duty cycle of 0%, i.e., only pattern A can be directly set, etc., which are not limited in the present application.

[0133] According to the scheme provided in the present application, the logical "1" and the logical "0" correspond to two different high-low level pulse waveforms of the liquid crystal driving voltage (absolute value) respectively, so that the jitter suppression is realized through the lower frequency refresh logical sequence, and the data transmission bandwidth required by the backplane chip is reduced.

[0134] In an implementation, the first information further includes a first pulse waveform signal and a second pulse waveform signal.

[0135] In the implementation, the pixels of the LCoS further receive the first pulse waveform signal and the second pulse waveform signal, and output corresponding liquid crystal driving voltages through the received first logical sequence.

[0136] In another implementation, the first pulse waveform signal and the second pulse waveform signal are pre-configured.

[0137] In the implementation, the pixels of the LCoS do not need to receive the first pulse waveform signal and the second pulse waveform signal, and the data transmission bandwidth requirement of the backplane chip can be reduced to a certain extent.

[0138] In yet another implementation, the repetition frequency of the first pulse waveform signal is an integer multiple of the first sub-frame frequency, and the repetition frequency of the second pulse waveform signal is an integer multiple of the second sub-frame frequency.

[0139] In the implementation, the first pulse waveform signal and the second pulse waveform signal are adjusted in real time. For example, the repetition frequency of the first pulse waveform signal and the second pulse waveform signal is determined according to the corresponding sub-frame frequency. Generally, the sub-frame frequency is fixed at 3600HZ, and the repetition frequency of the first pulse waveform signal and the second pulse waveform signal is an integer multiple of the corresponding sub-frame frequency. In particular, the repetition frequency of the pulse waveform signal is an exponential multiple of the sub-frame frequency, for example, 32 times, etc.

[0140] By way of example and not limitation, the first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; wherein the first pulse waveform signal is input to each pixel of the LCoS backplane chip through a first interface, the second pulse waveform signal is input to each pixel of the LCoS backplane chip through a second interface, and the first interface is different from the second interface.

[0141] In the implementation, the waveform generator is placed in the external circuit of the LCoS pixel array, and the first pulse waveform signal and the second pulse waveform signal need to be connected to the LCoS through two chip ports. This implementation can effectively reduce the driving voltage swing, for example, 0.5V to 4.5V, etc.

[0142] By way of example and not limitation, the first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; wherein the waveform generator is integrated in the LCoS backplane chip.

[0143] In this implementation, the waveform generator is further integrated in the LCoS backplane chip, which generates a high signal rate, reduces noise interference of signal transmission, and reduces the complexity of the package interface.

[0144] Further, an XOR logic is configured in the waveform generator. For example, the LCoS interface input pattern A waveform, and the further waveform generator is located in the backplane chip, which is a core of an XOR logic. Then, for logic “1”, the first pulse waveform signal (e.g., pattern A) and its XOR operation directly generates pattern A; for logic “0”, the first pulse waveform signal (e.g., pattern A) and its XOR operation generates a second pulse waveform signal (e.g., pattern B); pattern A and pattern B are transmitted to each pixel. For example, pattern A is a square wave with a duty cycle of 90%, and pattern B is a square wave with a duty cycle of 10% obtained by XOR operation.

[0145] In this implementation, all patterns of the pixels are generated by a unified signal source, and all patterns of the pixels have mutual time delay but unchanged duty cycle in the process of pixel scanning. Since the unified signal source generates the pattern, the complexity of the internal circuit of the chip can be further reduced.

[0146] As an example but not limitation, an XOR logic is configured in each pixel of the LCoS backplane chip.

[0147] In this implementation, since the unified signal source generates the pattern, the complexity of the chip interface can be further reduced, and the integration of the internal circuit of the pixel can be realized.

[0148] For example, the interface input pattern A waveform, and the further XOR logic (XOR) is located in the pixel circuit. For logic “1”, pattern A and its XOR operation directly generates pattern A; for logic “0”, pattern A and its XOR operation generates pattern B.

[0149] In a possible implementation, when the absolute value of the liquid crystal driving voltage of the LCoS changes, the first information further includes a third pulse waveform signal and a fourth pulse waveform signal, the third pulse waveform signal corresponds to the first digital logic, the fourth pulse waveform signal corresponds to the second digital logic sequence, at least one of the third pulse waveform signal and the fourth pulse waveform signal includes a high level and a low level, the third pulse waveform signal is different from the first pulse waveform signal, and the fourth pulse waveform signal is different from the second pulse waveform signal.

[0150] In this implementation, a special pattern is used in the switching process, which can achieve the effect of overshoot or undershoot, and improve the response speed of the switching process.

[0151] In another possible implementation, the LCoS includes a plurality of pixels, the plurality of pixels including a first pixel and a second pixel, the first pixel being an i-th row and m-th column pixel, and the second pixel being a j-th row and m-th column pixel, and a relative time delay when the first pulse waveform signal is simultaneously input to the first pixel and the second pixel being (j-i)T, where i, j, and m are positive integers greater than or equal to 1, i is different from j, T is a time of one row scanning.

[0152] Taking the first pulse waveform signal pattern A as an example, pattern A is uniformly input to the LCoS backplane chip, and the pattern A of the first row and the Nth row is taken, and the pattern A of the Nth row is delayed relative to the first row by (N-1)T, where T is a time of one row scanning.

[0153] In this implementation, the pattern between the rows of pixels can be synchronized and aligned with the logical refresh.

[0154] S420, the LCoS outputs a liquid crystal driving voltage according to the first information.

[0155] It should be noted that the main components of the LCoS include a common electrode, a liquid crystal layer, and a backplane pixel electrode. Among them, the common electrode is connected to a common voltage signal source to provide a common voltage V com , and the backplane pixel electrode is connected to a pixel signal source to provide a pixel voltage V pix . The liquid crystal driving voltage V of the liquid crystal layer corresponding to the pixel is the difference between the common voltage V com and the pixel voltage V pix , that is, V=V com -V pix . The liquid crystal molecules deflect under the action of the liquid crystal driving voltage, and then generate corresponding phase modulation. Generally, the common voltage is fixed.

[0156] Figure 5 is an example of a driving modulation method for a silicon-based liquid crystal LCoS according to an embodiment of the present application. Compared with the traditional LCoS driving modulation method, the driving modulation method uses logic "1" and logic "0" to correspond to two different high and low level pulse waveforms of liquid crystal driving voltage (absolute value), and the accumulation of liquid crystal single direction flicker is interrupted at the same level, so that stronger flicker suppression can be achieved under the same logic sequence.

[0157] like Figure 5 As shown in (a), for any pixel 501 in the LCoS pixel array, its pixel circuit receives a logic sequence and a pulse waveform signal pattern. The waveform generator produces pattern A and pattern B, which are transmitted to each pixel of the LCoS backplane chip, such as pixel 501, via an interface. A logic "1" corresponds to one pulse waveform signal pattern A, and a logic "0" corresponds to another pulse waveform signal pattern B. Simultaneously, each pixel receives its corresponding logic sequence. For different V... com The level, pattern, or logic corresponding to the input is toggled.

[0158] For example, such as Figure 5 As shown in (b), pattern A is a square wave with a 90% duty cycle, and pattern B is a square wave with a 10% duty cycle. The subframe frequency is fixed at 3600Hz, and the repetition frequency of the square wave is an integer multiple of the subframe frequency. For example, the repetition frequencies of both pattern A and pattern B are powers of 2 (e.g., 32 times) of the subframe frequency. Where V H =5V, V L =0V.

[0159] Optionally, pattern A is a square wave with a 90% duty cycle, and pattern B is a square wave with a 20% duty cycle. The subframe frequency is fixed at 3600Hz, and the repetition frequency of the square wave is an integer multiple of the subframe frequency. For example, the repetition frequencies of both pattern A and pattern B are powers of 2 (e.g., 32 times) of the subframe frequency. Where V H =5V, V L =0V.

[0160] Optionally, pattern A is a square wave with a 90% duty cycle, and pattern B is a square wave with a 0% duty cycle (or pattern A can be set to be the only one). The subframe frequency is fixed at 3600Hz, and the repetition frequency of the square wave is an integer multiple of the subframe frequency. For example, the repetition frequency of pattern A is a power of 2 (e.g., 32 times) of the subframe frequency. Where V H =5V, V L =0V.

[0161] Optionally, pattern A is a square wave with a 90% duty cycle, and pattern B is a square wave with a 10% duty cycle. The subframe frequency is fixed at 3600Hz, and the repetition frequency of the square wave is an integer multiple of the subframe frequency. For example, the repetition frequency of pattern A is 32 times the subframe frequency, and the repetition frequency of pattern B is 16 times the subframe frequency. Wherein, V H =5V, V L =0V.

[0162] It should be understood that the above-mentioned pattern A and pattern B are examples of adjusting the pattern duty cycle and the pattern cycle period, respectively. They are merely illustrative examples. In reality, there may be many other forms of pattern, which are not listed here and should not constitute any limitation on the scheme of this application.

[0163] For example, such as Figure 5 As shown in (c), the absolute value of the liquid crystal driving voltage |V| = 2.5V is achieved. In the example in the left figure, it can be regarded as a single pulse sequence, t = 1 / 60 microseconds, with the logic sequence of "0" and "1" appearing at a duty cycle of 50% and a repetition frequency of 60Hz. Due to the method of this embodiment, the logic sequences "1" and "0" correspond to pulse waveform pattern A or pattern B respectively, thereby suppressing flicker. In the example in the right figure, it can be regarded as a multi-pulse sequence, t = 1 / 60 microseconds, with the logic sequence of "0" and "1" appearing at a duty cycle of 50% and a repetition frequency of 120Hz. Due to the method of this embodiment, the logic sequences "1" and "0" correspond to pulse waveform pattern A or pattern B respectively, thereby further suppressing flicker. For example, when the repetition frequency changes from 60Hz to 120Hz, the liquid crystal flicker suppression of the existing solution may change from 0.1 to 0.05, while with the method of this application, the liquid crystal flicker suppression can change from 0.07 to 0.035. Clearly, the higher the repetition frequency, the better the jitter suppression effect. Therefore, based on the solution of this application, jitter suppression can be further improved.

[0164] Furthermore, the method of this embodiment can be combined with a specific PWM encoding method of "0" and "1" logic sequences, such as thermometer code, binary code, etc. The corresponding interface transmission sequence can be irregular and non-cyclic, such as "1", "1", "0", "1".

[0165] In summary, this implementation reduces the effective drive voltage swing flicker. Figure 5The effective driving voltage swing is 0.5V-4.5V. Although the effective driving voltage swing is reduced, the method can be applied to more liquid crystal types.

[0166] In summary, Figure 5 The liquid crystal driving modulation method provided can achieve stronger flicker suppression under the same logic sequence. In addition, the same effect of flicker suppression can be achieved by a logic sequence with lower frequency refresh, so as to reduce the data transmission bandwidth required by the backplane chip and improve the performance of the LCoS pixel size, liquid crystal response speed, phase modulation stability and the like.

[0167] Figure 6 is another schematic diagram of the driving modulation method for the silicon-based liquid crystal LCoS applicable to the embodiments of the present application. Unlike the method shown in Figure 5 The difference lies in that Figure 5 The waveform generator of is located outside the LCoS pixel array, and two additional interfaces are required to connect the two. While Figure 6 The waveform generator shown in is located in the backplane chip, and no additional interface is required between the outside and the LCoS pixel array. The generated signal rate is relatively strong, and further integration is achieved.

[0168] As shown in (a) in Figure 6 , for any pixel of the LCoS pixel array, the pixel circuit receives a logic sequence and a pulse waveform signal pattern. Logic "1" corresponds to a pulse waveform signal pattern A, and logic "0" corresponds to another pulse waveform signal pattern B. Among them, the waveform generator generates pattern A and pattern B, which are transmitted to each pixel of the LCoS backplane chip through an interface, and the waveform generator (circuit) is located in the backplane chip.

[0169] This embodiment further integrates the waveform generator (circuit) in the backplane chip, reducing the noise interference of signal transmission and the complexity of the packaging interface.

[0170] As shown in (b) in Figure 6 , the waveform generator is located in the backplane chip, and the core of the waveform generator is an exclusive OR logic XOR. In this embodiment, a unified signal source generates the patterns of all pixels, which can further reduce the complexity of the internal circuit of the chip.

[0171] For any pixel in the LCoS pixel array, its pixel circuit receives a logic sequence and a pulse waveform signal pattern. Logic "1" corresponds to one pulse waveform signal pattern A, and logic "0" corresponds to another pulse waveform signal pattern B. In this implementation, an interface is needed to input one pulse waveform signal pattern A, and output pattern A and pattern B through XOR in the waveform generator. For logic "1", pattern A and its XOR operation directly generates pattern A; for logic "0", pattern A and its XOR operation generates pattern B; pattern A and pattern B are further transmitted to each pixel. For example, input pattern A is a square wave with a duty cycle of 90%, and after XOR operation, pattern B is a square wave with a duty cycle of 10%.

[0172] In this implementation, all patterns of the pixels are generated by one signal source, and in the process of pixel scanning, all patterns of the pixels have mutual time delay, but the duty cycle is unchanged.

[0173] As shown in (c) of FIG. 1, the XOR logic XOR is located in the pixel circuit. In this implementation, all patterns of the pixels are generated by one signal source, which can further reduce the complexity of the internal circuit of the chip and realize the integration of the internal circuit of the pixel. Figure 6

[0174] For any pixel in the LCoS pixel array, its pixel circuit receives a logic sequence and a pulse waveform signal pattern. Logic "1" corresponds to one pulse waveform signal pattern A, and logic "0" corresponds to another pulse waveform signal pattern B. In this implementation, an interface is needed to input one pulse waveform signal pattern A, and output pattern A and pattern B through XOR in the waveform generator. For logic "1", pattern A and its XOR operation directly generates pattern A; for logic "0", pattern A and its XOR operation generates pattern B.

[0175] Figure 7 is another schematic diagram of the driving and modulation method for the LCoS according to the embodiments of the present application. In this implementation, pattern A or pattern B is adjusted in real time during the operation of the LCoS.

[0176] For example, as shown in (c) of FIG. 1, the XOR logic XOR is located in the pixel circuit. In this implementation, all patterns of the pixels are generated by one signal source, which can further reduce the complexity of the internal circuit of the chip and realize the integration of the internal circuit of the pixel. Figure 7 ​As shown in (a), pattern A is a square wave with a 90% duty cycle, and pattern B is a square wave with a 10% duty cycle, generated through XOR operation (e.g., Figure 6 (c) In this context, the repetition frequency of the square wave is adjusted in real time to an integer multiple of the corresponding subframe frequency, for example, 3 times. The hold time for subframes 1 to 3 is 20µs, and the hold time for subframe 4 is 40µs. Correspondingly, the period duration of pattern B in subframe 4 is adjusted to twice the period duration in subframe 1.

[0177] For example, such as Figure 7 As shown in (b) and (c), pattern A is a square wave with a duty cycle of 90% (tA2 ≤ tA1, for example, the period of pattern A is 20µs, tA2 = 2µs, tA1 = 2µs), and pattern B is a square wave with a duty cycle of 10% (t... B2 ≥t B1 For example, the period of pattern B is 20µs, tB2 = 2µs, tB1 = 2µs, which are generated by waveform generators (e.g., Figure 5 In (a) of the diagram, pattern A and pattern B have opposite waveform directions. The repetition frequency of the square wave is adjusted in real time to the corresponding subframe frequency. The holding time for subframes 1 to 3 is 20µs, and the holding time for subframe 4 is 40µs. Correspondingly, the period duration of pattern B in subframe 4 is adjusted to twice the period duration in subframe 2.

[0178] For example, such as Figure 7 As shown in (d), pattern A is a square wave with a duty cycle of 90% or 70%, and pattern B is a square wave with a duty cycle of 10% or 30%, which are generated by waveform generators (e.g., Figure 5 In (a) of the diagram, the waveforms of pattern A and pattern B are in opposite directions. For subframes 1 and 2, the duty cycle of pattern A is 90% and that of pattern B is 10%; for subframes 3 and 4, the duty cycle of pattern A is 70% and that of pattern B is 30%. Furthermore, the repetition frequency of the square wave is adjusted in real time to the corresponding subframe frequency. The hold time for subframes 1 to 3 is 20µs, and the hold time for subframe 4 is 40µs. Correspondingly, the period duration of pattern B in subframe 4 is adjusted to twice the period duration in subframe 2.

[0179] In summary, Figure 7The liquid crystal driving modulation method provided uses real-time adjustable patterns, and further optimizes in combination with sub-frame coding definition and logical sequence, so that stronger flicker suppression can be realized.

[0180] Figure 8 is another example schematic diagram of a driving modulation method for a silicon-based liquid crystal LCoS according to an embodiment of the present application. In this implementation, when the port is kept, i.e., the absolute value of the required liquid crystal driving voltage is unchanged, pattern A or pattern B is used, and when the port is switched, i.e., the absolute value of the required liquid crystal driving voltage changes, pattern C or pattern D is used.

[0181] For example, in a 5x5 LCoS pixel array, any pixel in which can display 256 gray scales, assuming that the 128th gray scale of a certain pixel corresponds to the logical sequence of "1", "0", "1", "0"; due to system requirements, the pixel needs to switch from the 128th gray scale to the 256th gray scale. The 256th gray scale corresponds to the logical sequence of "1", "1", "1", "1". Before switching, the pattern corresponding to the logical sequence "1", "0", "1", "0" is used, for example, logical "1" corresponds to pattern A, and logical "0" corresponds to pattern B; during switching, pattern C and pattern D are used; after switching, the pattern corresponding to the logical sequence "1", "1", "1", "1" is used, for example, logical "1" corresponds to pattern A, and logical "0" corresponds to pattern B, and so on.

[0182] As shown in (a) of FIG. 8, Figure 8 The waveform generator generates pattern A and pattern B, and pattern C and pattern D. For any pixel 801 of the LCoS pixel array, when the corresponding port is kept, the pixel corresponds to the absolute value of the required liquid crystal driving voltage unchanged, and the pixel circuit receives the logical sequence and the pulse waveform signal (for example, pattern A or pattern B). For any pixel 802 of the LCoS pixel array, when the corresponding port is switched, the pixel corresponds to the absolute value of the required liquid crystal driving voltage changed, and the pixel circuit receives the logical sequence and the pulse waveform signal (for example, pattern C or pattern D).

[0183] For example, as shown in (a) of FIG. 8, Figure 8pattern C is a square wave with a duty cycle of 90%, and pattern D is a square wave with a duty cycle of 10%; pattern A is a square wave with a duty cycle of 70%, and pattern B is a square wave with a duty cycle of 30%.

[0184] For example, pattern C is a square wave with a duty cycle of 100% (high level), and pattern D is a square wave with a duty cycle of 0% (low level); pattern A is a square wave with a duty cycle of 70%, and pattern B is a square wave with a duty cycle of 30%.

[0185] It should be understood that the above several provided pattern A and pattern B are examples of adjusting the duty cycle of the pattern, and are only illustrative. There can be many other pattern forms, which are not listed one by one here and should not constitute any limitation on the scheme of the present application.

[0186] In summary, Figure 8 The provided liquid crystal driving modulation method uses a special pattern in the port switching process to achieve the effects of overshoot or undershoot, and improves the response speed of the switching process.

[0187] Figure 9 is another example of a driving modulation method for a silicon-based liquid crystal LCoS according to an embodiment of the present application. In this implementation, the patterns between the rows of pixels can be aligned with the logical refresh.

[0188] As Figure 9 As shown in (a), pattern A or pattern B is uniformly input to the LCoS backplane chip, and the corresponding rows are delayed, such as synchronous scanning of each row.

[0189] As Figure 9 As shown in (b), take pattern A as an example. As an example, take the pattern A of the first row and the Nth row, and the delay of the pattern A of the Nth row relative to the first row is (N-1)T, where T is the scanning time of one row.

[0190] Figure 10 is another example of a driving modulation method for a silicon-based liquid crystal LCoS according to an embodiment of the present application. This implementation provides a scenario of applying the above-mentioned driving modulation method of LCoS to WSS.

[0191] As Figure 10As shown in (a), the device is a 1x4 WSS simplified optical path, that is, it has one input port and four output ports, realizing an all-optical connection between any pairing of the input and output ports. Only one wavelength is used as an example, such as a center wavelength of 1550nm.

[0192] The main components of this device include: an input / output fiber optic array 1001, a main lens 1002, and an LCoS 1003. The beam emitted from the input port is collimated by the main lens 1002 and then illuminates the LCoS 1003. The LCoS 1003 deflects and reflects the corresponding beam, which is then focused again by the main lens 1002 onto the corresponding output port. The LCoS 1003 is a pixelated reflective device. In each pixel, a driving electrode generates an electric field to control the alignment of liquid crystal molecules, thereby forming a specific phase distribution pattern. The driving modulation method of this application is used to control the LCoS 1003.

[0193] For example, when the beam from input port 1 needs to be deflected and output to output port 4, the LCoS1003 needs to generate a beam as shown in the figure. Figure 10 The holographic phase diagram shown in (b) is a one-dimensional blazed grating. For example, the LCoS 903 has a pixel size of 600x600, a blazed grating period of 100, and a phase modulation depth of 0 to 2π.

[0194] For example, such as Figure 10 As shown in (c), for any pixel 905 in the LCoS pixel array, its pixel circuit receives a logic sequence and a pulse waveform signal pattern. The waveform generator produces pattern A and pattern B, which are transmitted to each pixel of the LCoS backplane chip, such as pixel 1005, via an interface. A logic "1" corresponds to one pulse waveform signal pattern A, and a logic "0" corresponds to another pulse waveform signal pattern B. Simultaneously, each pixel receives its corresponding logic sequence. For different V... com The level, pattern, or logic corresponding to the toggles.

[0195] Further modulation methods such as Figure 10In (d) shown in the figure, the phase modulation amount of the first row of the interface transmission sequence is 0, the corresponding liquid crystal driving voltage absolute value |V| = 0.5V, and the logic sequence of "0" and "1" is according to the duty cycle 100%; the phase modulation amount of the 50th row of the interface transmission sequence is π, the corresponding liquid crystal driving voltage absolute value |V| = 2.5V, and the logic sequence of "0" and "1" is according to the duty cycle 50% with a repetition frequency of 1200Hz; the phase modulation amount of the 100th row of the interface transmission sequence is 2π, the corresponding liquid crystal driving voltage absolute value |V| = 4.5V, and the logic sequence of "0" and "1" is according to the duty cycle 0%.

[0196] In summary, Figures 5 to 10 The LCoS driving modulation method provided in the present application is used to generate pixel driving voltage, that is, different pulse waveforms pattern corresponding to logic "1" and logic "0". In the present application, the pattern or logic corresponds to the voltage of the common electrode. In the working of the LCoS, the pattern can be pre-configured to be fixed or adjusted in real time. In the image switching process of the LCoS, the pattern can be adjusted in real time.

[0197] In summary, the driving modulation method of the present application is used to generate pixel driving voltage, that is, different pulse waveforms pattern corresponding to logic "1" and logic "0". In the present application, the pattern or logic corresponds to the voltage of the common electrode. In the working of the LCoS, the pattern can be pre-configured to be fixed or adjusted in real time. In the image switching process of the LCoS, the pattern can be adjusted in real time.

[0198] In the embodiments of the present application, the length (modulation frequency) of the logic "1" or "0" sequence is reduced, thereby reducing the chip transmission bandwidth requirement, further reducing the number of driving pins and the packaging complexity; or supporting further expansion of the pixel scale under the existing mature interface-packaging technology; or supporting further reduction of flicker under the premise of existing optimized driving algorithm. Further, using a specific pattern in the switching process can also improve the switching response speed.

[0199] The driving modulation method of the present application is described in detail above, and the driving modulation device of the present application will be described in detail below. Figures 1 to 10 , the driving modulation method of the present application is described in detail above, and the driving modulation device of the present application will be described in detail below. Figure 11 and Figure 12 The driving modulation device of the present application will be described in detail below. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment, and therefore, the parts not described in detail can be referred to the foregoing method embodiment.

[0200] Figure 11This is a schematic block diagram of a driving modulation device for a silicon-based liquid crystal (LCoS) provided in an embodiment of this application. Figure 11 As shown, the communication device 1000 may include a processing unit 1100 and a transceiver unit 1200.

[0201] It should be understood that the communication device 1000 may include units for performing the method 400 described above. Furthermore, each unit in the communication device 1000 and the other operations and / or functions described above respectively implement the corresponding process of method 400.

[0202] For example, the transceiver unit 1200 is used to receive first information, the first information including indication information of a first logic sequence, the first logic sequence including first digital logic and / or second digital logic, the first digital logic corresponding to a first pulse waveform signal, the second digital logic sequence corresponding to a second pulse waveform signal, at least one of the first pulse waveform signal and the second pulse waveform signal including a high level and a low level, the first pulse waveform signal and the second pulse waveform signal being different; and outputting the liquid crystal driving voltage of LCoS according to the first information.

[0203] For example, the first information also includes a first pulse waveform signal and a second pulse waveform signal.

[0204] Optionally, the first pulse waveform signal and the second pulse waveform signal are pre-configured.

[0205] Optionally, the repetition frequency of the first pulse waveform signal is an integer multiple of the first subframe frequency, and the repetition frequency of the second pulse waveform signal is an integer multiple of the second subframe frequency.

[0206] For example, the first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator;

[0207] The first pulse waveform signal is input to each pixel of the LCoS backplane chip through the first interface, and the second pulse waveform signal is input to each pixel of the LCoS backplane chip through the second interface. The first interface and the second interface are different.

[0208] Optionally, the first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; wherein the waveform generator is integrated into the LCoS backplane chip.

[0209] Optionally, the waveform generator is configured with XOR logic.

[0210] Optionally, XOR logic is configured in each pixel of the LCoS backplane chip.

[0211] Exemplarily, when the absolute value of the liquid crystal driving voltage of the LCoS changes, the first information further comprises a third pulse waveform signal and a fourth pulse waveform signal, the third pulse waveform signal corresponds to the first digital logic, the fourth pulse waveform signal corresponds to the second digital logic sequence, at least one of the third pulse waveform signal and the fourth pulse waveform signal comprises a high level and a low level, the third pulse waveform signal is different from the first pulse waveform signal, and the fourth pulse waveform signal is different from the second pulse waveform signal.

[0212] Exemplarily, the LCoS comprises a plurality of pixels, the plurality of pixels comprises a first pixel and a second pixel, the first pixel is an i-th row and m-th column pixel, and the second pixel is a j-th row and m-th column pixel, the relative time delay of the first pulse waveform signal input to the first pixel and the second pixel is (j-i)T, wherein i, j and m are positive integers greater than or equal to 1, i is different from j, and T is the time of one row scanning.

[0213] It should also be understood that when the communication apparatus 1000 is an LCoS, the transceiver unit 1200 in the communication apparatus 1000 can be implemented by a transceiver, and the processing unit 1100 in the communication apparatus 1000 can be implemented by at least one processor.

[0214] It should also be understood that when the communication apparatus 1000 is a chip or a chip system configured in an LCoS, the transceiver unit 1200 in the communication apparatus 1000 can be implemented by an input / output interface, a circuit or the like, and the processing unit 1100 in the communication apparatus 1000 can be implemented by a processor, a microprocessor or an integrated circuit integrated on the chip or the chip system or the like.

[0215] Figure 12 is another schematic block diagram of the communication apparatus 2000 provided by an embodiment of the present application. As shown in Figure 12 The communication apparatus 2000 comprises a processor 2010, a transceiver 2020 and a memory 2030. The processor 2010, the transceiver 2020 and the memory 2030 communicate with each other through an internal connection path. The memory 2030 is used to store instructions, and the processor 2010 is used to execute the instructions stored in the memory 2030 to control the transceiver 2020 to send and / or receive signals.

[0216] The transceiver 2020 is configured to receive first information, the first information comprising indication information of a first logical sequence, the first logical sequence comprising a first digital logic and / or a second digital logic sequence, the first digital logic corresponding to a first pulse waveform signal, the second digital logic sequence corresponding to a second pulse waveform signal, at least one of the first pulse waveform signal and the second pulse waveform signal comprising a high level and a low level, the first pulse waveform signal being different from the second pulse waveform signal; and output a liquid crystal driving voltage of the LCoS according to the first information.

[0217] The first information further comprises the first pulse waveform signal and the second pulse waveform signal.

[0218] Optionally, the first pulse waveform signal and the second pulse waveform signal are preconfigured.

[0219] Optionally, a repetition frequency of the first pulse waveform signal is an integer multiple of a first subframe frequency, and a repetition frequency of the second pulse waveform signal is an integer multiple of a second subframe frequency.

[0220] The first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator.

[0221] The first pulse waveform signal is input to each pixel of the LCoS backplane chip through a first interface, and the second pulse waveform signal is input to each pixel of the LCoS backplane chip through a second interface, the first interface being different from the second interface.

[0222] Optionally, the first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; and the waveform generator is integrated in the LCoS backplane chip.

[0223] Optionally, an exclusive-OR logic XOR is configured in the waveform generator.

[0224] Optionally, an exclusive-OR logic XOR is configured in each pixel of the LCoS backplane chip.

[0225] The first information further comprises a third pulse waveform signal and a fourth pulse waveform signal, the third pulse waveform signal corresponding to the first digital logic, the fourth pulse waveform signal corresponding to the second digital logic sequence, at least one of the third pulse waveform signal and the fourth pulse waveform signal comprising a high level and a low level, the third pulse waveform signal being different from the first pulse waveform signal, and the fourth pulse waveform signal being different from the second pulse waveform signal, when an absolute value of the liquid crystal driving voltage of the LCoS changes.

[0226] For example, the LCoS includes a plurality of pixels, the plurality of pixels include a first pixel and a second pixel, the first pixel is an i-th row and m-th column pixel, the second pixel is a j-th row and m-th column pixel, and a relative time delay of the first pulse waveform signal input to the first pixel and the second pixel is (j-i)T, where i, j, and m are positive integers greater than or equal to 1, i is different from j, T is a time of one row scanning.

[0227] It should be understood that the communication apparatus 2000 can correspond to the LCoS in the above method embodiments, and can be used to perform each step and / or procedure of the LCoS performed in the above method embodiments. Optionally, the memory 2030 can include a read-only memory and a random access memory, and provide instructions and data for the processor. A part of the memory can also include a non-volatile random access memory. The memory 2030 can be one separate device, or can be integrated in the processor 2010. The processor 2010 can be used to execute the instructions stored in the memory 2030, and when the processor 2010 executes the instructions stored in the memory, the processor 2010 is used to perform each step and / or procedure of the above method embodiments corresponding to the LCoS.

[0228] Optionally, the communication apparatus 2000 is the LCoS in the above embodiments.

[0229] Optionally, the transceiver 2020 can include a transmitter and a receiver. The transceiver 2020 can further include an antenna, and the number of the antenna can be one or more. The processor 2010 and the memory 2030 and the transceiver 2020 can be devices integrated on different chips. For example, the processor 2010 and the memory 2030 can be integrated in a baseband chip, and the transceiver 2020 can be integrated in a radio frequency chip. The processor 2010 and the memory 2030 and the transceiver 2020 can also be devices integrated on the same chip. The present application does not make any limitation in this regard.

[0230] Optionally, the communication apparatus 2000 is a component configured in the LCoS, such as a circuit, a chip, a chip system, etc.

[0231] Optionally, the transceiver 2020 can also be a communication interface, such as an input / output interface, a circuit, etc. The transceiver 2020, the processor 2010 and the memory 2030 can be integrated in the same chip, such as a baseband chip.

[0232] Optionally, the memory and the processor in each of the above apparatus embodiments can be physically independent units, or the memory can also be integrated with the processor. The present application does not make any limitation in this regard.

[0233] Further, the present application also provides a computer readable storage medium, wherein computer instructions are stored in the computer readable storage medium, and when the computer instructions are run on a computer, the computer is caused to perform operations and / or processes performed by the controller in any one of the method embodiments of the present application.

[0234] Further, the present application also provides a computer program product, wherein the computer program product comprises computer program codes or instructions, and when the computer program codes or instructions are run on a computer, operations and / or processes performed by the controller in any one of the method embodiments of the present application are performed.

[0235] Further, the present application also provides a chip, wherein the chip comprises a processor, and a memory for storing a computer program is arranged independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the controller installed with the chip performs operations and / or processes performed by the controller in any one of the method embodiments.

[0236] Further, the chip can further comprise a communication interface. The communication interface can be an input / output interface, or an interface circuit, etc. Further, the chip can further comprise a memory.

[0237] Further, the present application also provides a communication device (for example, the chip), comprising a processor and a communication interface, wherein the communication interface is configured to receive a signal and transmit the signal to the processor, and the processor processes the signal, so that operations and / or processes performed by the controller in any one of the method embodiments are performed.

[0238] Further, the present application also provides a communication device, comprising at least one processor and at least one memory coupled to the at least one processor, and the at least one processor is configured to execute a computer program or instructions stored in the at least one memory, so that operations and / or processes performed by the controller in any one of the method embodiments are performed.

[0239] Further, the present application also provides an LCoS device having a function of the controller in any one of the embodiments of the present application.

[0240] The present application also provides a WSS device, comprising the LCoS device and the controller in any one of the embodiments of the present application.

[0241] The controller and the LCoS device can be independently configured or integrally configured, for example, the controller itself is a part of the LCoS device.

[0242] The present application also provides an optical switching device, comprising the WSS device.

[0243] It should be understood that the specific examples in the embodiments of the present application are only to help those skilled in the art better understand the technical solutions of the present application, and the above specific implementation manners can be considered as the optimal implementation manners of the present application, but not limit the scope of the embodiments of the present application.

[0244] Optionally, the memory and the processor in each of the above device embodiments can be physically independent units, or the memory can also be integrated with the processor, which is not limited in the present application.

[0245] The processor in the embodiments of the present application can be an integrated circuit chip with the ability to process signals. In the implementation process, each step of the above method embodiments can be completed by the integrated logic circuit of hardware in the processor or the instruction in the form of software. The processor can be a general processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware coding processor to execute, or be executed by a combination of hardware and software modules in the coding processor. The software module can be located in the random access memory, the flash memory, the read-only memory, the programmable read-only memory or the electrically erasable programmable memory, the register or other mature storage media in the field. The storage medium is located in the storage memory, and the processor reads the information in the storage memory to combine the hardware to complete the steps of the above method.

[0246] The memory in the embodiments of the present application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory of the system and method described herein is intended to include, but not be limited to, these and any other suitable types of memory.

[0247] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0248] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0249] In the embodiments of the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the embodiments of the device described above are merely schematic; the division of the units is merely logical function division; an actual implementation can be another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, or the among different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electric, mechanical or other forms.

[0250] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0251] In addition, each functional unit in the embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art, or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various other media that can store program codes.

[0252] The above describes only the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A driving modulation method applied to silicon-based liquid crystal (LCoS), characterized in that, The method includes: Receive first information, the first information including indication information of a first logic sequence, the first logic sequence including first digital logic and / or second digital logic, the first digital logic corresponding to a first pulse waveform signal, the second digital logic sequence corresponding to a second pulse waveform signal, at least one of the first pulse waveform signal and the second pulse waveform signal including a high level and a low level, and the first pulse waveform signal being different from the second pulse waveform signal; The liquid crystal driving voltage of the LCoS is output based on the first information; Wherein, the first pulse waveform signal is different from the second pulse waveform signal, including: the first pulse waveform signal and the second pulse waveform signal are square waves with different duty cycles, and the second pulse waveform signal is obtained by XORing the first pulse waveform signal.

2. The method according to claim 1, characterized in that, The first information also includes the first pulse waveform signal and the second pulse waveform signal.

3. The method according to claim 1, characterized in that, The first pulse waveform signal and the second pulse waveform signal are pre-configured.

4. The method according to any one of claims 1 to 3, characterized in that, The repetition frequency of the first pulse waveform signal is an integer multiple of the first subframe frequency, and the repetition frequency of the second pulse waveform signal is an integer multiple of the second subframe frequency.

5. The method according to any one of claims 1 to 3, characterized in that, The first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; The first pulse waveform signal is input to each pixel of the LCoS backplane chip through a first interface, and the second pulse waveform signal is input to each pixel of the LCoS backplane chip through a second interface. The first interface and the second interface are different.

6. The method according to any one of claims 1 to 3, characterized in that, The first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; The waveform generator is integrated into the LCoS backplane chip.

7. The method according to claim 6, characterized in that, The waveform generator is configured with XOR logic.

8. The method according to any one of claims 1 to 3, characterized in that, Each pixel of the LCoS backplane chip is configured with XOR logic.

9. The method according to any one of claims 1 to 3, characterized in that, When the absolute value of the liquid crystal driving voltage of the LCoS changes, the first information also includes a third pulse waveform signal and a fourth pulse waveform signal. The third pulse waveform signal corresponds to the first digital logic, and the fourth pulse waveform signal corresponds to the second digital logic sequence. At least one of the third pulse waveform signal and the fourth pulse waveform signal includes a high level and a low level. The third pulse waveform signal is different from the first pulse waveform signal, and the fourth pulse waveform signal is different from the second pulse waveform signal.

10. The method according to any one of claims 1 to 3, characterized in that, The LCoS includes multiple pixels, including a first pixel and a second pixel. The first pixel is the pixel in the i-th row and m-th column, and the second pixel is the pixel in the j-th row and m-th column. The relative time delay of the first pulse waveform signal being simultaneously input to the first pixel and the second pixel is (ji)T, where i, j, and m are positive integers greater than or equal to 1, i and j are different, and T is the time for scanning one line.

11. A driving modulation device, characterized in that, The device is a silicon-based liquid crystal (LCoS), and the device includes a transceiver unit for: Receive first information, the first information including indication information of a first logic sequence, the first logic sequence including first digital logic and / or second digital logic, the first digital logic corresponding to a first pulse waveform signal, the second digital logic sequence corresponding to a second pulse waveform signal, at least one of the first pulse waveform signal and the second pulse waveform signal including a high level and a low level, and the first pulse waveform signal being different from the second pulse waveform signal; The liquid crystal driving voltage of the LCoS is output based on the first information; Wherein, the first pulse waveform signal is different from the second pulse waveform signal, including: the first pulse waveform signal and the second pulse waveform signal are square waves with different duty cycles, and the second pulse waveform signal is obtained by XORing the first pulse waveform signal.

12. The apparatus according to claim 11, characterized in that, The first information also includes the first pulse waveform signal and the second pulse waveform signal.

13. The apparatus according to claim 11, characterized in that, The first pulse waveform signal and the second pulse waveform signal are pre-configured.

14. The apparatus according to any one of claims 11 to 13, characterized in that, The repetition frequency of the first pulse waveform signal is an integer multiple of the first subframe frequency, and the repetition frequency of the second pulse waveform signal is an integer multiple of the second subframe frequency.

15. The apparatus according to any one of claims 11 to 13, characterized in that, The first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; The first pulse waveform signal is input to each pixel of the LCoS backplane chip through a first interface, and the second pulse waveform signal is input to each pixel of the LCoS backplane chip through a second interface. The first interface and the second interface are different.

16. The apparatus according to any one of claims 11 to 13, characterized in that, The first pulse waveform signal and the second pulse waveform signal are generated by a waveform generator; The waveform generator is integrated into the LCoS backplane chip.

17. The apparatus according to claim 16, characterized in that, The waveform generator is configured with XOR logic.

18. The apparatus according to any one of claims 11 to 13, characterized in that, Each pixel of the LCoS backplane chip is configured with XOR logic.

19. The apparatus according to any one of claims 11 to 13, characterized in that, When the absolute value of the liquid crystal driving voltage of the LCoS changes, the first information also includes a third pulse waveform signal and a fourth pulse waveform signal. The third pulse waveform signal corresponds to the first digital logic, and the fourth pulse waveform signal corresponds to the second digital logic sequence. At least one of the third pulse waveform signal and the fourth pulse waveform signal includes a high level and a low level. The third pulse waveform signal is different from the first pulse waveform signal, and the fourth pulse waveform signal is different from the second pulse waveform signal.

20. The apparatus according to any one of claims 11 to 13, characterized in that, The LCoS includes multiple pixels, including a first pixel and a second pixel. The first pixel is the pixel in the i-th row and m-th column, and the second pixel is the pixel in the j-th row and m-th column. The relative time delay when the first pulse waveform signal is simultaneously input to the first pixel and the second pixel is (ji)T, where i, j, and m are positive integers greater than or equal to 1, i and j are different, and T is the time for scanning one line.

21. A silicon-based liquid crystal (LCoS), characterized in that, include: A liquid crystal modulator includes multiple pixels, each of which receives a logic sequence and at least one pulse waveform signal, wherein any two pixels correspond to different logic sequences, and the at least one pulse waveform signal includes a high level and a low level, and the at least one pulse waveform signal is a square wave with a different duty cycle; An interface for acquiring the at least one pulse waveform signal; A controller is configured to control the phase state of multiple pixels of the liquid crystal modulator according to the at least one pulse waveform signal, so as to output the liquid crystal driving voltage of the LCoS; The liquid crystal modulator, the interface, and the controller are configured to perform the method as described in any one of claims 1 to 10.

22. A silicon-based liquid crystal (LCoS), characterized in that, include: A liquid crystal modulator includes multiple pixels, each of which receives a logic sequence and at least one pulse waveform signal, wherein any two pixels correspond to different logic sequences, the at least one pulse waveform includes a high level and a low level, and the at least one pulse waveform signal is a square wave with a different duty cycle. A waveform generator is used to generate the at least one pulse waveform signal; An interface for acquiring the at least one pulse waveform signal; A controller is configured to control the phase state of multiple pixels of the liquid crystal modulator according to the at least one pulse waveform signal, so as to output the liquid crystal driving voltage of the LCoS; The liquid crystal modulator, the waveform generator, the interface, and the controller are used to perform the method as described in any one of claims 1 to 10.

23. A wavelength selective switch (WSS), characterized in that, include: An input port is used to input optical signals, which have multiple wavelength channels; The silicon-based liquid crystal LCoS as described in claim 21 or 22 is used to drive and modulate the optical signal input to the input port; The output port is used to output the optical signal modulated by the LCoS driver.

24. A computer storage medium, characterized in that, The computer storage medium stores computer instructions, which, when executed on the computer, cause the computer to perform the method as described in any one of claims 1 to 10.

25. A computer program product, characterized in that, When the computer program code or instructions are executed on a computer, the computer causes the computer to perform the method as described in any one of claims 1 to 10.

26. A communication device, characterized in that, The device includes a processing circuit and a communication interface, wherein the processing circuit is configured to perform the method as described in any one of claims 1 to 10 to generate data and / or signals to be transmitted, and the communication interface is configured to transmit the data and / or signals.

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