Drc test pattern generation method and device, electronic equipment and storage medium

Abstract

The application discloses a DRC test pattern generation method and device, electronic equipment and a storage medium. The DRC test pattern generation method comprises the following steps: receiving a DRC test pattern generation request, wherein the DRC test pattern generation request carries a correct pattern quantity and an error pattern quantity; obtaining layout design rule information and corresponding hierarchical configuration information, wherein the hierarchical configuration information comprises process layer configuration parameter information set according to a process type; analyzing each parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the hierarchical configuration information; based on each parameter information corresponding to each rule, the process layer configuration parameter information associated with each rule, the correct pattern quantity and the error pattern quantity, respectively generating formatted parameter information corresponding to each rule; and generating a corresponding quantity of correct patterns and error patterns corresponding to each rule according to the formatted parameter information corresponding to each rule.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and more particularly to a method, apparatus, electronic device, and storage medium for generating DRC test patterns. Background Technology

[0002] Integrated circuit layout design refers to mapping integrated circuit design diagrams or circuit description languages ​​to a physical description layer, thereby enabling the designed integrated circuits to be manufactured on wafers. A layout is a graphic representation of the physical information of an integrated circuit, including its device type, device size, relative positions between devices, and interconnections. It consists of graphics located on different drawing layers. In integrated circuit manufacturing, wafer foundries need to define geometric constraints for the same process layer and between different process layers to meet chip manufacturing yields based on various process parameters. This collection of geometric constraints forms the Design Rule Manual, which layout designers use to design the layout according to the rules outlined in the Design Rule Manual.

[0003] After the layout design is completed, the layout data must be checked through DRC (Design Rule Check). Graphics that do not conform to the layout design rules cannot be guaranteed to be implemented on the wafer. DRC must cover every rule in the layout design rule manual. Since DRC is a crucial step in determining whether the layout design can be successfully fabricated, a large number of test patterns need to be created to test the correctness of DRC.

[0004] Currently, the correctness of DRC is mainly tested by manually constructing correct and incorrect graphs. Using DRC to check for incorrect graphs should report the corresponding errors, and using DRC to check for correct graphs should report no errors. Otherwise, it indicates that DRC is incorrect. If DRC is incorrect, it is adjusted until DRC is ensured to be accurate.

[0005] However, manually constructing DRC test graphics is not only time-consuming, but the correct and incorrect graphics cannot cover all design rules in the layout design rule manual, thus failing to guarantee the accuracy of DRC. Summary of the Invention

[0006] To address the issues of time-consuming manual construction of DRC test graphics in layout design and the inability to guarantee the accuracy of DRC files, embodiments of the present invention provide a method, apparatus, electronic device, and storage medium for generating DRC test graphics.

[0007] In a first aspect, embodiments of the present invention provide a method for generating DRC test graphics, including:

[0008] Receive a DRC test graph generation request, wherein the DRC test graph generation request carries the number of correct graphs and the number of incorrect graphs;

[0009] Obtain layout design rule information and corresponding hierarchical configuration information, wherein the hierarchical configuration information includes process layer configuration parameter information set according to process type;

[0010] The parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the hierarchical configuration information are analyzed. Based on the parameter information corresponding to each rule, the process layer configuration parameter information associated with each rule, the number of correct graphics and the number of incorrect graphics, the formatted parameter information corresponding to each rule is generated respectively.

[0011] Based on the formatting parameter information corresponding to each rule, generate the corresponding number of correct and incorrect graphics for each rule.

[0012] In one possible implementation, the formatting parameters include rule parameters, rule-related process layer configuration parameters, and DRC test pattern generation step size parameters.

[0013] In one possible implementation, the rule parameters include at least the rule type, the rule constraint range, the type of the rule check trigger condition, and the constraint range of the level in the rule check trigger condition; the rule-associated process layer configuration parameters include the level of the rule check, the level attribute parameters, and the level in the rule check trigger condition; the DRC test pattern generation step size parameters include the gradient value corresponding to the rule type and the gradient value corresponding to the type of the rule check trigger condition.

[0014] In one possible implementation, the gradient value corresponding to the rule type is determined based on the rule constraint interval and the number of correct graphics and the number of incorrect graphics; the gradient value corresponding to the type of the rule check trigger condition is determined based on the constraint interval of the level in the rule check trigger condition and the number of correct graphics and the number of incorrect graphics.

[0015] Based on the formatting parameter information corresponding to each rule, generate a corresponding number of correct and incorrect graphics for each rule, specifically including:

[0016] The preset test graph generation engine corresponding to the rule type of each rule is invoked. According to the gradient value corresponding to the rule type and the gradient value corresponding to the type of rule check trigger condition, the corresponding number of correct graphs that satisfy the rule constraint interval and the corresponding number of incorrect graphs that do not satisfy the rule constraint interval are generated for each rule.

[0017] In one possible implementation, the gradient value corresponding to the rule type is determined in the following manner:

[0018] When it is determined that the rule constraint interval contains only the lower limit value of the interval, the ratio of the lower limit value of the interval to the number of erroneous graphics is determined as the gradient value corresponding to the rule type;

[0019] When it is determined that the rule constraint interval contains an upper limit value, the ratio of the upper limit value to the number of correct graphics is determined as the gradient value corresponding to the rule type.

[0020] In one possible implementation, the gradient value corresponding to the type of the rule check trigger condition is determined as follows:

[0021] When it is determined that the constraint interval of the level in the rule check trigger condition contains only the lower limit value of the interval, the ratio of the lower limit value of the interval to the number of error graphics is determined as the gradient value corresponding to the type of the rule check trigger condition.

[0022] When it is determined that the constraint interval of the level in the rule check trigger condition contains a lower limit value and an upper limit value, the ratio of the difference between the upper limit value and the lower limit value to the number of error graphics is determined as the gradient value corresponding to the type of the rule check trigger condition.

[0023] Secondly, embodiments of the present invention provide a DRC test graphic generation device, including...

[0024] The receiving unit is used to receive a DRC test pattern generation request, wherein the DRC test pattern generation request carries the number of correct patterns and the number of incorrect patterns;

[0025] The acquisition unit is used to acquire layout design rule information and corresponding hierarchical configuration information, wherein the hierarchical configuration information includes process layer configuration parameter information set according to process type;

[0026] The parsing unit is used to parse the parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the hierarchical configuration information. Based on the parameter information corresponding to each rule, the process layer configuration parameter information associated with each rule, the number of correct graphics and the number of incorrect graphics, the unit generates the formatted parameter information corresponding to each rule.

[0027] The generation unit is used to generate a corresponding number of correct and incorrect graphics for each rule based on the formatting parameter information corresponding to each rule.

[0028] In one possible implementation, the formatting parameters include rule parameters, rule-related process layer configuration parameters, and DRC test pattern generation step size parameters.

[0029] In one possible implementation, the rule parameters include at least the rule type, the rule constraint range, the type of the rule check trigger condition, and the constraint range of the level in the rule check trigger condition; the rule-associated process layer configuration parameters include the level of the rule check, the level attribute parameters, and the level in the rule check trigger condition; the DRC test pattern generation step size parameters include the gradient value corresponding to the rule type and the gradient value corresponding to the type of the rule check trigger condition.

[0030] In one possible implementation, the gradient value corresponding to the rule type is determined based on the rule constraint interval and the number of correct graphics and the number of incorrect graphics; the gradient value corresponding to the type of the rule check trigger condition is determined based on the constraint interval of the level in the rule check trigger condition and the number of correct graphics and the number of incorrect graphics.

[0031] The generation unit is specifically used to call the preset test graph generation engine corresponding to the rule type of each rule, and generate a corresponding number of correct graphs that satisfy the rule constraint interval and a corresponding number of incorrect graphs that do not satisfy the rule constraint interval according to the gradient value corresponding to the rule type and the gradient value corresponding to the type of the rule check trigger condition.

[0032] In one possible implementation, the parsing unit is specifically configured to determine the gradient value corresponding to the rule type in the following manner: when it is determined that the rule constraint interval contains only the lower limit value of the interval, the ratio of the lower limit value of the interval to the number of erroneous graphics is determined as the gradient value corresponding to the rule type; when it is determined that the rule constraint interval contains the upper limit value of the interval, the ratio of the upper limit value of the interval to the number of correct graphics is determined as the gradient value corresponding to the rule type.

[0033] In one possible implementation, the parsing unit is specifically configured to determine the gradient value corresponding to the type of the rule check trigger condition in the following manner: when it is determined that the constraint interval of the hierarchy in the rule check trigger condition contains only the lower limit value of the interval, the ratio of the lower limit value of the interval to the number of error graphics is determined as the gradient value corresponding to the type of the rule check trigger condition; when it is determined that the constraint interval of the hierarchy in the rule check trigger condition contains both the lower limit value of the interval and the upper limit value of the interval, the ratio of the difference between the upper limit value of the interval and the lower limit value of the interval to the number of error graphics is determined as the gradient value corresponding to the type of the rule check trigger condition.

[0034] Thirdly, embodiments of the present invention provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the DRC test pattern generation method of the present invention.

[0035] Fourthly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the DRC test graphic generation method of the present invention.

[0036] The DRC test pattern generation scheme provided in this embodiment of the invention receives a DRC test pattern generation request, which carries the number of correct and incorrect patterns to be generated. It then obtains layout design rule information and corresponding hierarchical configuration information. The layout design rule information refers to each rule contained in the layout design rule manual file, and the hierarchical configuration information refers to the process layer configuration parameter information contained in the hierarchical configuration file, which is set according to the process type. Furthermore, it parses the parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the hierarchical configuration information. Based on the parameter information corresponding to each rule, the process layer configuration parameter information associated with each rule, the number of correct patterns, and the number of incorrect patterns, it generates formatted parameter information corresponding to each rule. Based on the formatted parameter information corresponding to each rule, it generates the corresponding number of correct and incorrect patterns for each rule. In this invention, it can be used by... The user pre-specifies the number of correct and incorrect DRC test patterns to be generated. The electronic device simultaneously parses the parameter information corresponding to each layout design rule in the layout design rule manual, as well as the process layer configuration parameter information in the hierarchical configuration file corresponding to the layout design rule. Combining the parsed parameter information for each rule in the layout design rule manual, along with the associated process layer configuration parameters, the number of correct patterns, and the number of incorrect patterns, it generates formatted parameter information for each rule in the layout design rule manual. The generated formatted parameter information contains more complete and standardized parameters. For each rule, based on the formatted parameter information corresponding to each rule, it automatically batch-generates a specified number of correct and incorrect patterns. Thus, while improving the efficiency of DRC test pattern generation, the generated correct and incorrect patterns cover every design rule in the layout design rule manual, further improving the accuracy of the DRC file.

[0037] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0039] Figure 1 This is a schematic diagram of an application scenario of the DRC test graphic generation method provided in an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram illustrating the implementation process of the DRC test graphic generation method provided in this embodiment of the invention;

[0041] Figure 3 This is a structural diagram of the parametric image generator provided in an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of the distance test graph corresponding to rule Metal1_R4 provided in an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of the width test graphic corresponding to rule Metal1_R1 provided in an embodiment of the present invention;

[0044] Figure 6 This is a schematic diagram of the 3D edge binding test graphic corresponding to rule V1_R2 provided in the embodiments of the present invention;

[0045] Figure 7 A schematic diagram of the DRC test graph set generated by the parametric graph generator provided in this embodiment of the invention;

[0046] Figure 8 This is a schematic diagram of the structure of the DRC test pattern generation device provided in an embodiment of the present invention;

[0047] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0048] To address the problems in the background art, embodiments of the present invention provide a method, apparatus, electronic device, and storage medium for generating DRC test graphics.

[0049] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0050] First refer to Figure 1 This is a schematic diagram of an application scenario of the DRC test graphic generation method provided in the embodiment of the present invention. It may include a terminal 110 and a server 120. When the server 120 receives a DRC test graphic generation request sent by the terminal 110, the server 120 can generate a number of correct and incorrect graphics corresponding to each rule in the layout design rule manual in batches according to the DRC test graphic generation request. Furthermore, the generated correct and incorrect graphics can be sent to the terminal 110 and displayed to the user by the terminal 110.

[0051] Server 120 can be a standalone physical server or a cloud server providing basic cloud computing services such as cloud servers, cloud databases, and cloud storage. Terminal 110 can be, but is not limited to, smartphones, tablets, laptops, desktop computers, etc. Server 120 and terminal 110 can be connected via a network; this embodiment of the invention does not limit this connection.

[0052] In another application scenario, it may only include terminal 110. The user inputs the number of correct and incorrect graphics to be generated in the terminal device 110 to trigger the DRC test graphics generation request. Terminal 110 can generate the user-specified number of correct and incorrect graphics corresponding to each rule in the layout design rule manual according to the DRC test graphics generation request and display them to the user.

[0053] The embodiments of the present invention will only use the first application scenario described above as an example for illustration.

[0054] Based on the above application scenarios, the following will refer to the appendix. Figures 2-7 The exemplary embodiments of the present invention will be described in more detail below. It should be noted that the above application scenarios are shown only to facilitate understanding of the spirit and principles of the present invention, and the embodiments of the present invention are not limited in any way. On the contrary, the embodiments of the present invention can be applied to any applicable scenario.

[0055] like Figure 2 The diagram shown illustrates the implementation flow of the DRC test graph generation method provided in this embodiment of the invention. This DRC test graph generation method can be applied to the server 120 described above, and specifically includes the following steps:

[0056] S21. Receive DRC test graph generation request. The DRC test graph generation request carries the number of correct graphs and the number of incorrect graphs.

[0057] In practice, the server receives a DRC test graphic generation request sent by the terminal. The DRC test graphic generation request carries the number of correct graphics and the number of incorrect graphics to be generated as specified by the user.

[0058] S22. Obtain layout design rule information and corresponding hierarchical configuration information. The hierarchical configuration information includes process layer configuration parameter information set according to process type.

[0059] In practice, the terminal can send a layout design rule manual and a corresponding hierarchical configuration file to the server. The server receives the layout design rule manual and the hierarchical configuration file sent by the terminal. The layout design rule manual is a file that records layout design rule information. The hierarchical configuration file contains hierarchical configuration information, which includes process layer configuration parameter information set according to the process type. The process layer configuration parameter information may include at least the following: attribute information of each process layer (i.e., inherent attribute information of each process layer) and connection relationship information between different process layers.

[0060] S23. Analyze the parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the hierarchical configuration information. Based on the parameter information corresponding to each rule, the process layer configuration parameter information associated with each rule, the number of correct graphics and the number of incorrect graphics, generate the formatted parameter information corresponding to each rule.

[0061] In practice, the server is equipped with a parameter parser. The function of the parameter parser is to generate a new, uniformly formatted layout design rule parameter file, i.e. a formatted parameter file, based on the layout design rule information recorded in the layout design rule manual and the hierarchical configuration information contained in the hierarchical configuration file. The formatted parameter file contains the formatted parameter information corresponding to each layout design rule.

[0062] During implementation, the parameter parser analyzes the parameter information corresponding to each rule in the layout design rule manual and the process layer configuration parameter information in the hierarchical configuration file. Based on the parameter information corresponding to each rule, the process layer configuration parameter information associated with each rule, the number of correct graphics, and the number of incorrect graphics, it generates formatted parameter information (also known as standardized parameter information) for each rule. The formatted parameter information for each rule forms a formatted parameter file (also known as a standardized parameter file). The formatted parameters include rule parameters, rule-associated process layer configuration parameters, and DRC test graphic generation step size parameters. The rule parameters are extracted from the parameters corresponding to the rules in the layout design rule manual, and the rule-associated process layer configuration parameters are extracted from the process layer configuration parameters in the hierarchical configuration file. The rule parameters may include at least the following parameters: rule identifier, rule type, rule constraint range, and rule check trigger condition parameters. The rule check trigger condition parameters may include the rule check trigger condition type and the constraint range of the level in the rule check trigger condition. The rule-associated process layer configuration parameters include the rule check level, the level attribute parameters, and the level in the rule check trigger condition. When the trigger condition type feature of the level specified in the rule check trigger condition meets the constraint range, the DRC rule check is triggered. The DRC test pattern generation step size parameters include: the gradient value corresponding to the rule type and the gradient value corresponding to the rule check trigger condition type. The gradient value corresponding to the rule type determines the gradient value corresponding to the rule type of the generated DRC test pattern. For example, the rule type may include: width, area, space, and enclosing edge, representing width check, area check, distance check, and enclosing edge check, respectively. When the rule type of a rule is width check, the gradient value corresponding to that rule type determines the width gradient value of the generated DRC test pattern. The gradient value corresponding to the rule check trigger condition type determines the gradient value corresponding to the rule check trigger condition type of the layer within the rule check trigger condition in the generated DRC test pattern. For example, when the rule check trigger condition type is width, this type indicates that the width of the layer within the rule check trigger condition must meet a condition to trigger the DRC rule check. In this case, the gradient value corresponding to the rule check trigger condition type determines the width gradient value of the layer within the rule check trigger condition in the generated DRC test pattern.

[0063] During implementation, the gradient value corresponding to the rule type is determined based on the rule constraint interval and the number of correct graphics and the number of incorrect graphics; the gradient value corresponding to the type of the rule check trigger condition is determined based on the constraint interval of the level in the rule check trigger condition and the number of correct graphics and the number of incorrect graphics.

[0064] Specifically, the gradient value corresponding to the rule type can be determined in the following manner:

[0065] When it is determined that the rule constraint interval contains only the lower limit value, the ratio of the lower limit value to the number of erroneous graphics is determined as the gradient value corresponding to the rule type; when it is determined that the rule constraint interval contains the upper limit value, the ratio of the upper limit value to the number of correct graphics is determined as the gradient value corresponding to the rule type.

[0066] The gradient value corresponding to the type of the rule check trigger condition can be determined as follows:

[0067] When it is determined that the constraint interval of the level in the rule check trigger condition contains only the lower limit value, the ratio of the lower limit value to the number of erroneous graphics is determined as the gradient value corresponding to the type of the rule check trigger condition. When it is determined that the constraint interval of the level in the rule check trigger condition contains both the lower limit value and the upper limit value, the ratio of the difference between the upper limit value and the lower limit value to the number of erroneous graphics is determined as the gradient value corresponding to the type of the rule check trigger condition. Here, "the constraint interval of the level in the rule check trigger condition contains only the lower limit value" means that the lower limit value is greater than or equal to the lower limit value.

[0068] The following example illustrates this point. The rules in a layout design rule manual are shown in Table 1:

[0069]

[0070] Table 1

[0071] For ease of explanation, the above layout design rule manual only shows a portion of the rule content, totaling 7 rules. The first column is the serial number (#No), the second column is the rule name (DRC_RULE_NAME), the third column is the rule description (DESCRIPTION), the fourth column is the rule check triggering condition (CONDITION), and the fifth column is the rule constraint.

[0072] The first rule, Metal1_R1, represents rule 1 for metal 1. The rule description is: Metal1 min width, which represents the minimum width of metal 1; the rule check trigger condition is: no, which means none; the rule constraint is: ≥0.55, which means the minimum width of metal 1 is ≥0.55 (i.e., Metal1 min width ≥0.55).

[0073] The second rule, Metal1_R2, represents rule 2 for metal 1. The rule description is: Metal1 max width, which means the maximum width of metal 1; the rule check trigger condition is: none; the rule constraint is: ≤7, which means the maximum width of metal 1 is ≤7 (i.e., Metal1 max width ≤ 7).

[0074] The third rule, Metal1_R3, represents rule 3 for metal 1. The rule description is: Metal1 min area, which represents the minimum area of ​​metal 1; the rule check trigger condition is: none; the rule constraint is: ≥0.04, which means that the minimum area of ​​metal 1 is ≥0.04 (i.e., Metal1 min area ≥0.04).

[0075] The fourth rule, Metal1_R4, represents rule 4 for metal 1. The rule description is: Metal1 minspacing, which represents the minimum distance of metal 1. The rule check trigger condition is: 0.8 < width ≤ 1.1, which means that the rule check is triggered when the width meets the condition 0.8 < width ≤ 1.1. The rule constraint is: ≥ 0.11, which means that the minimum distance of metal 1 is ≥ 0.11 (i.e., Metal1 min spacing ≥ 0.11).

[0076] Rule 5, Metal1_R5, represents rule 5 for metal 1. The rule description is: Metal1 min lineend to line spacing, which represents the distance between the end of a line of metal 1 and another line of metal 1. The rule check trigger condition is: line end width ≥ 0.5, which means that the check of this rule is triggered when the line end width is ≥ 0.5. The rule constraint is: ≥ 0.33, which means that the distance between the end of a line of metal 1 and another line of metal 1 is ≥ 0.33 (i.e., Metal1 min line end to line spacing ≥ 0.33).

[0077] Rule V1_R1 in the sixth rule represents rule 1 for Via 1. The rule description is: Metal1min encloseV1, which means the minimum enclosed edge from metal 1 to via 1. The rule check trigger condition is: none. The rule constraint is: ≥0.55, which means the minimum enclosed edge from metal 1 to via 1 is ≥0.55 (i.e., Metal1min enclose V1≥0.55).

[0078] Rule V1_R2, the seventh rule, represents rule 2 for via 1. The rule description is: Metal1 3D min encloseV1, which means the minimum enclosed margin of metal 1 related to 3D to via 1. The rule check trigger condition is: line end length < 0.88, which means that the check of this rule is triggered when the line end length is < 0.88. The rule constraint is: ≥ 2.11, which means that the minimum enclosed margin of metal 1 related to 3D to via 1 is ≥ 2.11 (i.e., Metal1 3D min enclose V1 ≥ 2.11).

[0079] The hierarchical configuration file corresponding to the above-mentioned layout design rule manual is not shown. In this embodiment of the invention, the process layer configuration parameter information associated with each rule in the layout design rule manual is extracted from the hierarchical configuration file. Based on the parameter information corresponding to each rule in the layout design rule manual, the process layer configuration parameter information associated with each rule, the number of correct graphics and the number of incorrect graphics specified by the user, the formatted parameter information corresponding to each rule is generated. The formatted parameter file is shown in Table 2. The following is a detailed introduction to each formatted parameter.

[0080] In Table 2, the first column is the serial number (#No), corresponding to the first column in the layout design rule manual of Table 1. The second column is the rule identifier: DRC_RULE_ID, using the rule name (i.e., DRC_RULE_NAME in Table 1) as the rule identifier, corresponding to the second column in the layout design rule manual of Table 1; the third column is the rule type: RULE_TYPE, including: WIDTH - width check, AREA - area check, SPACE - distance check, ENC - edge check; the fourth column is 3D, indicating whether the rule is related to 3D, with a value of 1 when related and 0 when unrelated. 3D refers to dimension checks on the same level in more than one direction; the fifth column is the level of the DRC rule check: LAYERS, which is extracted from the layer configuration file. The sixth column is the layer orientation: LAYER_ORIENTATION. This parameter determines whether the generated correct and incorrect graphics are horizontal (HORI) or vertical (VERTI), and it is also extracted from the layer configuration file. The seventh column, MIN_MAX, indicates whether the rule constraint is a maximum (MAX) or a minimum (MIN), which is obtained from the description of DESCRIPT in Table 1. The eighth column is the rule constraint range (i.e., the constraint range of DRC rule checking): CONSTRAINTS, which corresponds to CONSTRAINTS in the fifth column of Table 1. The parameterized graphics generator uses... The process involves causing the test graphic to violate this constraint range and generating an incorrect graphic, and causing the test graphic to conform to this constraint range and generate a correct graphic. If the rule type RULE_TYPE in the third column is SPACE (distance check), then this constraint range is the distance constraint range, which will not be elaborated further here. Columns nine to twelfth are the gradient values ​​corresponding to the rule types, namely: width gradient value WIDTH_STEP, area gradient value AREA_STEP, distance gradient value SPACE_STEP, and edge gradient value ENC_STEP. The parameter WIDTH_STEP determines the width gradient value of the generated DRC test graphic, and the parameter AREA_STEP... This determines the area gradient value of the generated DRC test graphic. The parameter SPACE_STEP determines the distance gradient value of the generated DRC test graphic, and the parameter ENC_STEP determines the edge gradient value of the generated DRC test graphic. The gradient values ​​corresponding to each rule type are determined based on the interval values ​​(upper limit and lower limit) of their respective rule constraint intervals and the number of correct and incorrect graphics specified by the user. For example, in the first rule Metal1_R1, the rule type is width check, and the width constraint interval is [0.55,). This constraint interval only contains the lower limit value of 0.55, so the width gradient value is 0.55 / B_P_NUM, where B_P_NUM represents the number of incorrect graphics. The second rule in Metal1_R2 is a width check with a width constraint range of [0, 7] and an upper limit of 7. The width gradient value is 7 / G_P_NUM, where G_P_NUM represents the number of correct graphics. The third rule in Metal1_R3 is an area check with an area constraint range of [0.04, ), and the area gradient value is 0.04 / B_P_NUM; Column 13 is the layer in the (DRC) rule check trigger condition: COND_LAYER, which is extracted from the layer configuration file; Column 14 is the type of the (DRC) rule check trigger condition: COND_CHARACTOR, including: width, line end width, and line end length, which are obtained from the rule check trigger condition CONDITION in Table 1. When the type of the rule check trigger condition is width, it means that the width of the layer in the rule check trigger condition must meet the condition to trigger the DRC rule check. When the type of the rule check trigger condition is line end width, it means that the line end width of the layer in the rule check trigger condition must meet the condition to trigger the DRC rule check. When the type of the rule check trigger condition is line end length... When specifying `length`, it indicates that the line end length of the level in the rule check trigger condition must meet a condition to trigger the DRC rule check. This condition is the constraint interval of the level in the (DRC) rule check trigger condition, as shown in column 15: `COND_DONSTRAINTS`. The DRC rule check is triggered if the `COND_CHARACTER` feature of the level specified by `COND_LAYER` in the rule check trigger condition meets this constraint interval. `COND_DONSTRAINTS` is obtained from the rule check trigger condition `CONDITION` in Table 1. Columns 16 and 17 show the gradient values ​​corresponding to the `COND_CHARACTER` type of the rule check trigger condition. The gradient value corresponding to `width` and `line end width` is `COND_WIDTH_STEP` (column 16). `COND_WIDTH_STEP` determines the width gradient value of the level in the rule check trigger condition in the generated DRC test graph. The gradient value corresponding to `length` is `COND_LENGTH_STEP` (column 17). `COND_LENGTH_STEP` determines the gradient value of the hierarchy in the rule check trigger condition of the generated DRC test graph. For example, in the fourth rule, the type of the rule check trigger condition `COND_CHARACTER` is `width`, and the constraint interval of the hierarchy in the rule check trigger condition `COND_DONSTRAINTS` is (0.8, 1.1]. Then, the gradient value `COND_WIDTH_STEP` corresponding to `width` is the ratio of the difference between the upper limit value of the interval (1.1) and the lower limit value of the interval (0.8) to the number of error graphs: (1.1-0.8).8) / B_P_NUM, In the fifth rule, the type of the rule check trigger condition COND_CHARACTER is line end width, and the constraint interval COND_DONSTRAINTS of the level in the rule check trigger condition is [0.5,). Then the gradient value COND_WIDTH_STEP corresponding to line end width is the ratio of the lower limit value of the interval 0.5 to the number of error graphics: 0.5 / B_P_NUM. In the sixth rule, the type of the rule check trigger condition COND_CHARACTER is line end length, and the constraint interval COND_DONSTRAINTS of the level in the rule check trigger condition is (0,0.88). Then the gradient value COND_WIDTH_STEP corresponding to line end length is the ratio of the difference between the lower limit value of the interval 0.88 and the lower limit value of the interval 0 to the number of error graphics: 0.88 / B_P_NUM. The eighteenth column is the maximum number of rows and columns of vias VIA MAX. `row / column`: The parametric pattern generator uses this parameter to determine the number of rows and columns of vias (VIAs) in the generated test pattern. This number is a maximum value, and the number of vias in the generated test pattern can be progressively varied below this maximum value. (Note that in Table 2, `nil` represents empty; the values ​​of irrelevant formatting parameters in each rule are all empty.)

[0081]

[0082] S24. Based on the formatting parameter information corresponding to each rule, generate the corresponding number of correct and incorrect graphics for each rule.

[0083] In practice, the server calls the preset test graph generation engine corresponding to the rule type of each rule, and generates the corresponding number of correct graphs that meet the rule constraint range and the corresponding number of incorrect graphs that do not meet the rule constraint range for each rule according to the gradient value corresponding to the rule type and the gradient value corresponding to the type of rule check trigger condition.

[0084] Specifically, the server is pre-configured with a parametric graphics generator to generate DRC test graphics. The parametric graphics generator has corresponding test graphics generation engines for different rule types. For example, a width check rule corresponds to a width test graphics generation engine, a distance check rule corresponds to a distance test graphics generation engine, an area check rule corresponds to an area test graphics generation engine, a border check rule corresponds to a border check rule, a 3D border check rule corresponds to a 3D border check rule, a multiple exposure check rule corresponds to a multiple exposure test graphics generation engine, and so on. The structure diagram of the parametric graphics generator is shown below. Figure 3As shown.

[0085] During implementation, assuming the user specifies 3 correct and 3 incorrect graphics, 3 correct graphics and 3 incorrect graphics can be generated for each rule. If there are 7 rules in Table 2, 21 correct graphics and 21 incorrect graphics can be automatically generated in batches.

[0086] The following explanation uses the generation of DRC test graphics corresponding to the distance check of rule 4 Metal1_R4, the width check of rule 1 Metal1_R1, and the 3D ENC check of rule 7 V1_R2 in Table 2 as examples.

[0087] like Figure 4As shown, this is a schematic diagram of the distance test graph corresponding to the fourth rule, Metal1_R4. During implementation, the distance test graph generation engine is called to automatically generate a set of error graphs and a set of correct graphs based on the formatting parameters corresponding to the fourth rule, Metal1_R4, from the formatting parameter file. These parameters are the ones in Table 2 where each value is not empty or 0. The formatting parameters for the fourth rule, Metal1_R4, include: rule identifier DRC_RULE_ID: Metal1_R4; rule type RULE_TYPE: SPACE, i.e., distance check; rule check layer LAYERS: M1, i.e., metal 1; layer direction LAYER_ORIENTATION: HORI (vertical); MIN_MAX: min, i.e., the rule constraint is the minimum value; rule constraint interval CONSTRAINTS: ≥0.11; and distance gradient value SP. ACE_STEP = 0.11 / B_P_NUM = 0.11 / 3; The level in the rule check trigger condition COND_LAYER: M1; The type of the rule check trigger condition COND_CHARACTOR: width; The constraint interval of the level in the rule check trigger condition COND_DONSTRAINTS: >cond_val1 <= cond_val2, where cond_val1 is the lower limit of the interval of COND_CONSTRAINTS, i.e., 0.8, and cond_val2 is the upper limit of the interval of COND_CONSTRAINTS, i.e., 1.1; The gradient value COND_WIDTH_STEP corresponding to the type width of the rule check trigger condition is: |cond_val2-cond_val1| / B_P_NUM = (1.1-0.8) / 3 = 0.1.Given SPACE_STEP = 0.11 / 3 and COND_WIDTH_STEP = 0.1, in one set of incorrect graphics and one set of correct graphics, the line width at the top of layer M1 is set to cond_val1 = 0.8, cond_val1 + COND_WIDTH_STEP = 0.8 + 0.1 = 0.9, and cond_val1 + 2*COND_WIDTH_STEP = 0.8 + 2*0.1 = 1, respectively. In the incorrect graphics, the distance between the lower and upper lines in layer M1 is set to SPACE_STEP = 0.11 / 3, 2*SPACE_STEP = 0.22 / 3, and 3*SPACE_STEP = 0.11, respectively. In the correct graphics, the distance between the lower and upper lines in layer M1 is set to 4*SPACE_STEP. P = 0.44 / 3, 5*SPACE_STEP = 0.55 / 3, 6*SPACE_STEP = 0.22. It can be seen that in the first two incorrect graphics, the distance between the lower and upper lines does not satisfy the rule constraint interval CONSTRAINTS:[0.11,). However, in the third incorrect graphic, the distance between the lower and upper lines is 0.11, satisfying the rule constraint interval CONSTRAINTS:[0.11,). Therefore, it is the correct graphic. In a preferred implementation, to avoid this situation, when setting the distance between the two lines in the incorrect graphic, a small preset value can be subtracted from the SPACE_STEP value. This ensures that the third graphic is an incorrect graphic. The preset value can be set according to requirements, and this embodiment does not limit this. Based on this, similar settings can be made for the gradient values ​​corresponding to other rule types during the generation of test graphics, and this embodiment will not elaborate further.

[0088] like Figure 5As shown, this is a schematic diagram of the width test graphic corresponding to the first rule Metal1_R1. During implementation, the width test graphic generation engine is called to automatically generate a set of error graphics and a set of correct graphics based on the formatting parameters corresponding to the first rule Metal1_R1 in the formatting parameter file, which are the parameters in Table 2 where each value is not empty or 0. The formatting parameters of the first rule Metal1_R1 include: rule identifier DRC_RULE_ID: Metal1_R1; rule type RULE_TYPE: WIDTH, i.e., width check; rule check layer LAYERS: M1, i.e., metal 1; layer direction LAYER_ORIENTATION: HORI (vertical); MIN_MAX: min, i.e., the rule constraint is the minimum value; rule constraint range CONSTRAINTS: ≥0.55; width gradient value WIDTH_STEP = 0.55 / B_P_NUM = 0.55 / 3. In the set of incorrect graphics on the left, the line widths in layer M1 are set sequentially to WIDTH_STEP = 0.55 / 3, 2*WIDTH_STEP = 1.1 / 3, and 3*WIDTH_STEP = 0.55. The line widths set in the first and second incorrect graphics do not satisfy CONSTRAINTS: [0.55, ), while the line width set in the third incorrect graphics does satisfy CONSTRAINTS. Similar to the distance test graphics generation, a smaller preset value can be subtracted from WIDTH_STEP to ensure that the last incorrect graphics does not satisfy CONSTRAINTS, thus ensuring that this set of graphics are all incorrect graphics. In the set of correct graphics on the right, the line widths in layer M1 are set sequentially to 4*WIDTH_STEP = 2.2 / 3, 5*WIDTH_STEP = 2.75 / 3, and 6*WIDTH_STEP = 1.1. The line width of M1 in each correct graphic satisfies CONSTRAINTS: [0.55, ).

[0089] like Figure 6As shown, this is a schematic diagram of the 3D edge binding test graphic corresponding to the seventh rule V1_R2. During implementation, the width test graphic generation engine is called to automatically generate a set of error graphics and a set of correct graphics based on the formatting parameters corresponding to the first rule V1_R2 in the formatting parameter file, which are the parameters in Table 2 where each value is not empty or 0. The formatting parameters of the seventh rule V1_R2 include: rule identifier DRC_RULE_ID: V1_R2; rule type RULE_TYPE: ENC, 3D: 1, i.e., 3D edge binding. Check; Rule check levels LAYERS: M1, V1, M2; Level direction LAYER_ORIENTATION: HORI (vertical); MIN_MAX: min, i.e., the rule constraint is the minimum value; Rule constraint interval CONSTRAINTS: ≥2.11; Edge gradient value ENC_STEP = 2.11 / B_P_NUM = 2.11 / 3; Level in rule check trigger condition COND_LAYER: M1; Type of rule check trigger condition COND_CHARACTOR: line end length, i.e., line end length; Constraint interval of level in rule check trigger condition COND_DONSTRAINTS: <0.88; Gradient value corresponding to the type of rule check trigger condition line end length COND_LENGTH_STEP = 0.88 / B_P_NUM = 0.88 / 3; VIA MAX row / column is 3:3, i.e., the maximum number of rows and columns of vias is 3.Where ENC_STEP = 2.11 / 3, COND_LENGTH_STEP = 0.88 / B_P_NUM = 0.88 / 3, in the set of erroneous graphics on the left, the line widths in layer M1 are set sequentially to COND_LENGTH_STEP = 0.88 / 3, 2*COND_LENGTH_STEP = 1.76 / 3, and 3*COND_LENGTH_STEP = 0.88. The line end lengths in layers M1 and M2 are then adjusted. The length is set sequentially as follows: ENC_STEP = 2.11 / 3, 2*ENC_STEP = 4.22 / 3, 3*ENC_STEP = 2.11. The through-hole V1 between layer M1 and layer M2 is set sequentially to 1, 2*2 (two rows, two columns), and 3*3 (three rows, three columns). In the correct set of graphics on the right, the line width in layer M1 is set sequentially as COND_LENGTH_STEP = 0.88 / 3, 2*COND_LENGTH_STEP = 1.76 / 3, 3*COND_LENGTH_STEP = 0.88. The line end lengths between layers M1 and M2 are set sequentially as follows: The length is set sequentially as follows: 4*ENC_STEP = 8.44 / 3, 5*ENC_STEP = 10.55 / 3, 6*ENC_STEP = 4.22. The number of through holes between layer M1 and layer M2 is set to 1, 2*2 (i.e., two rows and two columns), and 3*3 (i.e., three rows and three columns). To ensure that the last erroneous image does not meet CONSTRAINTS, the value of ENC_STEP can be subtracted by a smaller preset value.

[0090] In practical implementation, to improve the efficiency of DRC test graphic generation, the aforementioned test image generation engines can be executed in parallel when generating the corresponding test graphics, and the output DRC test graphic set is as follows: Figure 7 As shown, this is the set of DRC test graphs generated by the parametric graph generator. It should be noted that the final generated test graphs are a set of correct test graphs and a set of incorrect test graphs corresponding to each rule in Table 2. Figure 7 Only the test graphs corresponding to the above three rules are shown; the test graphs corresponding to other rules are not shown.

[0091] The DRC test pattern generation method provided in this embodiment of the invention allows the user to pre-specify the number of correct and incorrect DRC test patterns to be generated. The parameter parser simultaneously parses the parameter information corresponding to each rule in the layout design rule manual, as well as the process layer configuration parameter information in the hierarchical configuration file corresponding to the layout design rule manual. Combining the parsed parameter information corresponding to each rule in the layout design rule manual, along with the associated process layer configuration parameter information, the number of correct patterns, and the number of incorrect patterns, it generates formatted parameter information corresponding to each rule in the layout design rule manual. The generated formatted parameter information contains more complete and standardized parameters. For each rule, the parameterized image generator automatically generates a specified number of correct and incorrect DRC test patterns in batches based on the formatted parameter information corresponding to each rule. Thus, while improving the efficiency of DRC test pattern generation, the generated correct and incorrect patterns cover every design rule in the layout design rule manual, further improving the accuracy of the DRC file.

[0092] Based on the same inventive concept, this embodiment of the invention also provides a DRC test pattern generation device. Since the principle of the above-mentioned DRC test pattern generation device in solving the problem is similar to that of the above-mentioned DRC test pattern generation method, the implementation of the above-mentioned device can refer to the implementation of the method, and the repeated parts will not be described again.

[0093] like Figure 8 As shown, it is a structural schematic diagram of the DRC test pattern generation device 300 provided in an embodiment of the present invention, which may include:

[0094] Receiving unit 31 is used to receive a DRC test pattern generation request, wherein the DRC test pattern generation request carries the number of correct patterns and the number of incorrect patterns;

[0095] The acquisition unit 32 is used to acquire layout design rule information and corresponding hierarchical configuration information, wherein the hierarchical configuration information includes process layer configuration parameter information set according to process type.

[0096] The parsing unit 33 is used to parse the parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the hierarchical configuration information. Based on the parameter information corresponding to each rule, the process layer configuration parameter information associated with each rule, the number of correct graphics and the number of incorrect graphics, the formatted parameter information corresponding to each rule is generated respectively.

[0097] The generation unit 34 is used to generate a corresponding number of correct and incorrect graphics for each rule based on the formatting parameter information corresponding to each rule.

[0098] In one possible implementation, the formatting parameters include rule parameters, rule-related process layer configuration parameters, and DRC test pattern generation step size parameters.

[0099] In one possible implementation, the rule parameters include at least the rule type, the rule constraint range, the type of the rule check trigger condition, and the constraint range of the level in the rule check trigger condition; the rule-associated process layer configuration parameters include the level of the rule check, the level attribute parameters, and the level in the rule check trigger condition; the DRC test pattern generation step size parameters include the gradient value corresponding to the rule type and the gradient value corresponding to the type of the rule check trigger condition.

[0100] In one possible implementation, the gradient value corresponding to the rule type is determined based on the rule constraint interval and the number of correct graphics and the number of incorrect graphics; the gradient value corresponding to the type of the rule check trigger condition is determined based on the constraint interval of the level in the rule check trigger condition and the number of correct graphics and the number of incorrect graphics.

[0101] The generation unit 34 is specifically used to call the preset test graph generation engine corresponding to the rule type of each rule, and generate a corresponding number of correct graphs that satisfy the rule constraint interval and a corresponding number of incorrect graphs that do not satisfy the rule constraint interval according to the gradient value corresponding to the rule type and the gradient value corresponding to the type of the rule check trigger condition.

[0102] In one possible implementation, the parsing unit 33 is specifically used to determine the gradient value corresponding to the rule type in the following manner: when it is determined that the rule constraint interval contains only the lower limit value of the interval, the ratio of the lower limit value of the interval to the number of erroneous graphics is determined as the gradient value corresponding to the rule type; when it is determined that the rule constraint interval contains the upper limit value of the interval, the ratio of the upper limit value of the interval to the number of correct graphics is determined as the gradient value corresponding to the rule type.

[0103] In one possible implementation, the parsing unit 33 is specifically configured to determine the gradient value corresponding to the type of the rule check triggering condition in the following manner: when it is determined that the constraint interval of the hierarchy in the rule check triggering condition contains only the lower limit value of the interval, the ratio of the lower limit value of the interval to the number of error graphics is determined as the gradient value corresponding to the type of the rule check triggering condition; when it is determined that the constraint interval of the hierarchy in the rule check triggering condition contains both the lower limit value of the interval and the upper limit value of the interval, the ratio of the difference between the upper limit value of the interval and the lower limit value of the interval to the number of error graphics is determined as the gradient value corresponding to the type of the rule check triggering condition.

[0104] Based on the same technical concept, this invention also provides an electronic device 400, see reference. Figure 9 As shown, the electronic device 400 is used to implement the DRC test pattern generation method or DRC test pattern generation apparatus described in the above-described method embodiments. The electronic device 400 in this embodiment may include: a memory 401, a processor 402, and a computer program stored in the memory and executable on the processor, such as a DRC test pattern generation program or a data packet transmission program. When the processor executes the computer program, it implements the steps in the various DRC test pattern generation method embodiments described above, for example... Figure 2 Step S21 is shown.

[0105] The specific connection medium between the memory 401 and the processor 402 described above is not limited in the embodiments of this invention. This application embodiment... Figure 9 The memory 401 and the processor 402 are connected via a bus 403, and the bus 403 is in Figure 9 The connections between other components are shown in bold lines only and are not intended to be limiting. The bus 403 can be divided into address bus, data bus, control bus, etc. For ease of illustration, Figure 9 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0106] Memory 401 may be volatile memory, such as random-access memory (RAM); memory 401 may also be non-volatile memory, such as read-only memory, flash memory, hard disk drive (HDD), or solid-state drive (SSD); or memory 401 may be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 401 may be a combination of the above-described memories.

[0107] Processor 402, used to implement such Figure 2 This illustrates a method for generating DRC test graphics.

[0108] This application also provides a computer-readable storage medium storing computer-executable instructions required to execute the processor, including a program required to execute the processor.

[0109] In some possible implementations, various aspects of the DRC test pattern generation method provided by the present invention can also be implemented as a program product comprising program code that, when the program product is run on an electronic device, causes the electronic device to perform the steps in the DRC test pattern generation method according to various exemplary embodiments of the present invention described above.

[0110] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0111] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0112] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0113] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0114] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0115] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for generating DRC test graphics, characterized in that, include: Receive a DRC test graph generation request, wherein the DRC test graph generation request carries the number of correct graphs and the number of incorrect graphs; Obtain layout design rule information and corresponding hierarchical configuration information, wherein the hierarchical configuration information includes process layer configuration parameter information set according to process type; The parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the hierarchical configuration information are analyzed. Based on the parameter information corresponding to each rule, the process layer configuration parameter information associated with each rule, the number of correct graphics and the number of incorrect graphics, the formatted parameter information corresponding to each rule is generated respectively. Based on the formatting parameter information corresponding to each rule, generate the corresponding number of correct and incorrect graphics for each rule; The formatting parameters include rule parameters, rule-related process layer configuration parameters, and DRC test pattern generation step size parameters. The rule parameters include at least the rule type, rule constraint range, type of rule check trigger condition, and constraint range of the level in the rule check trigger condition; the rule-related process layer configuration parameters include the level of rule check, level attribute parameters, and the level in the rule check trigger condition; the DRC test pattern generation step size parameters include the gradient value corresponding to the rule type and the gradient value corresponding to the type of rule check trigger condition. The gradient value corresponding to the rule type is determined based on the rule constraint interval and the number of correct graphics and the number of incorrect graphics; the gradient value corresponding to the type of the rule check trigger condition is determined based on the constraint interval of the level in the rule check trigger condition and the number of correct graphics and the number of incorrect graphics. Based on the formatting parameter information corresponding to each rule, generate a corresponding number of correct and incorrect graphics for each rule, specifically including: The preset test graph generation engine corresponding to the rule type of each rule is invoked. According to the gradient value corresponding to the rule type and the gradient value corresponding to the type of rule check trigger condition, the corresponding number of correct graphs that satisfy the rule constraint interval and the corresponding number of incorrect graphs that do not satisfy the rule constraint interval are generated for each rule.

2. The method as described in claim 1, characterized in that, The gradient value corresponding to the rule type is determined in the following manner: When it is determined that the rule constraint interval contains only the lower limit value of the interval, the ratio of the lower limit value of the interval to the number of erroneous graphics is determined as the gradient value corresponding to the rule type; When it is determined that the rule constraint interval contains an upper limit value, the ratio of the upper limit value to the number of correct graphics is determined as the gradient value corresponding to the rule type.

3. The method as described in claim 2, characterized in that, The gradient value corresponding to the type of the rule check trigger condition is determined as follows: When it is determined that the constraint interval of the level in the rule check trigger condition contains only the lower limit value of the interval, the ratio of the lower limit value of the interval to the number of error graphics is determined as the gradient value corresponding to the type of the rule check trigger condition. When it is determined that the constraint interval of the level in the rule check trigger condition contains a lower limit value and an upper limit value, the ratio of the difference between the upper limit value and the lower limit value to the number of error graphics is determined as the gradient value corresponding to the type of the rule check trigger condition.

4. A DRC test graphic generation device, characterized in that, include: The receiving unit is used to receive a DRC test pattern generation request, wherein the DRC test pattern generation request carries the number of correct patterns and the number of incorrect patterns; The acquisition unit is used to acquire layout design rule information and corresponding hierarchical configuration information, wherein the hierarchical configuration information includes process layer configuration parameter information set according to process type; The parsing unit is used to parse the parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the hierarchical configuration information. Based on the parameter information corresponding to each rule, the process layer configuration parameter information associated with each rule, the number of correct graphics and the number of incorrect graphics, the unit generates the formatted parameter information corresponding to each rule. The generation unit is used to generate a corresponding number of correct and incorrect graphics for each rule based on the formatting parameter information corresponding to each rule. The formatting parameters include rule parameters, rule-related process layer configuration parameters, and DRC test pattern generation step size parameters. The rule parameters include at least the rule type, rule constraint range, type of rule check trigger condition, and constraint range of the level in the rule check trigger condition; the rule-related process layer configuration parameters include the level of rule check, level attribute parameters, and the level in the rule check trigger condition; the DRC test pattern generation step size parameters include the gradient value corresponding to the rule type and the gradient value corresponding to the type of rule check trigger condition. The gradient value corresponding to the rule type is determined based on the rule constraint interval and the number of correct graphics and the number of incorrect graphics; the gradient value corresponding to the type of the rule check trigger condition is determined based on the constraint interval of the level in the rule check trigger condition and the number of correct graphics and the number of incorrect graphics. The generation unit is specifically used to call the preset test graph generation engine corresponding to the rule type of each rule, and generate a corresponding number of correct graphs that satisfy the rule constraint interval and a corresponding number of incorrect graphs that do not satisfy the rule constraint interval according to the gradient value corresponding to the rule type and the gradient value corresponding to the type of the rule check trigger condition.

5. The apparatus as described in claim 4, characterized in that, The parsing unit is specifically used to determine the gradient value corresponding to the rule type in the following manner: when it is determined that the rule constraint interval contains only the lower limit value of the interval, the ratio of the lower limit value of the interval to the number of erroneous graphics is determined as the gradient value corresponding to the rule type; when it is determined that the rule constraint interval contains the upper limit value of the interval, the ratio of the upper limit value of the interval to the number of correct graphics is determined as the gradient value corresponding to the rule type.

6. The apparatus as claimed in claim 5, characterized in that, The parsing unit is specifically used to determine the gradient value corresponding to the type of the rule check trigger condition in the following manner: when it is determined that the constraint interval of the level in the rule check trigger condition contains only the lower limit value of the interval, the ratio of the lower limit value of the interval to the number of error graphics is determined as the gradient value corresponding to the type of the rule check trigger condition; when it is determined that the constraint interval of the level in the rule check trigger condition contains both the lower limit value of the interval and the upper limit value of the interval, the ratio of the difference between the upper limit value of the interval and the lower limit value of the interval to the number of error graphics is determined as the gradient value corresponding to the type of the rule check trigger condition.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the DRC test graph generation method as described in any one of claims 1 to 3.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps in the DRC test graph generation method as described in any one of claims 1 to 3.

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