In-memory associative processing system

Abstract

This application is directed to an in-memory associative processing system. An apparatus can receive a set of instructions indicating a first vector and a second vector as operands for a compute operation. The apparatus can select a vector mapping scheme from a set of vector mapping schemes for performing the compute operation using associative processing. The apparatus can write the first vector and the second vector to a set of planes each including an array of content-addressable memory cells based on the selected vector mapping scheme.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 577,977, filed January 18, 2022, entitled “In-Memory Associetal Processing System”, and U.S. Provisional Patent Application No. 63 / 239,103, filed August 31, 2021, entitled “In-Memory Associetal Processing System”, each of which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to in-memory associative processing systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. For example, volatile memory devices like DRAM may lose their stored state when disconnected from external power. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a memory die comprising a plurality of tiles, each of the plurality of tiles comprising a plurality of planes, wherein each plane comprises a corresponding content-addressable memory cell array; and logic coupled to the memory die and configured to: receive signaling from a host device indicating a set of instructions, the set of instructions indicating a first vector and a second vector as operands for computational operations; select a vector mapping scheme from a set of vector mapping schemes for performing the computational operations using associative processing; and write data representing the first vector and the second vector to a set of planes of one or more tiles, at least in part based on the selected vector mapping scheme.

[0007] Describe an apparatus. The apparatus may include a memory die comprising a plurality of tiles, each of the plurality of tiles comprising a plurality of planes, wherein each plane comprises a corresponding content-addressable memory cell array; and logic coupled to the memory die and configured to: receive signaling from a host device indicating a set of instructions, the set of instructions indicating a vector as operands for computational operations, the vector comprising a plurality of elements each having a corresponding bit length; write data representing a first contiguous bit set of the plurality of elements to a first plane of the tile and write data representing a second contiguous bit set of the at least one element to a second plane of the tile; and perform the computational operations using associative processing, at least in part based on the writing of the data representing the first contiguous bit set to the first plane and at least in part based on the writing of the data representing the second contiguous bit set to the second plane.

[0008] Describe an apparatus. The apparatus may include a memory die comprising a plurality of tiles, each tile comprising a plurality of planes, wherein each plane comprises a corresponding content-addressable memory cell array; and logic coupled to the memory die and configured to: receive signaling from a host device indicating a set of instructions, the set of instructions indicating a vector as operands for computational operations, the vector comprising a plurality of elements each having a corresponding bit length; write data representing a first contiguous bit set of the plurality of elements to a first plane of the first tile and write data representing a second contiguous bit set of the at least one element to a second plane of the second tile; and perform the computational operations using associative processing, at least in part based on the writing of the data representing the first contiguous bit set to the first plane and at least in part based on the writing of the data representing the second contiguous bit set to the second plane.

[0009] Describe an apparatus. The apparatus may include a host device configured to transmit signaling indicating a set of instructions, the set of instructions indicating a vector as operands for computational operations, the vector comprising a plurality of elements each having a corresponding bit length; an apparatus coupled to the host device and configured to perform associative processing, the apparatus comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a corresponding array of content-addressable memory cells; and logic coupled to the apparatus and configured to: receive the signaling indicating the set of instructions from the host device; select between a first vector mapping scheme and a second vector mapping scheme for writing the vector to a plane of the apparatus; write data of a first contiguous bit set representing the elements of the vector to a first plane and data of a second contiguous bit set representing the elements to a second plane, at least in part based on the selected vector mapping scheme; and perform the computational operation using associative processing, at least based on the data written representing the first and second contiguous bit sets.

[0010] Describe a method. The method may include, at a device, receiving signaling of an instruction set indicating a first vector and a second vector as operands for a computational operation; selecting a vector mapping scheme from a set of vector mapping schemes for performing the computational operation using associative processing; and, at least in part based on the selected vector mapping scheme, writing data representing the first vector and data representing the second vector to a plane set, each comprising an array of content-addressable memory cells. Attached Figure Description

[0011] Figure 1 This document describes examples of systems that support in-memory associative processing, based on the examples disclosed herein.

[0012] Figure 2 This document describes an example of vector computation using in-memory associative processing, based on the examples disclosed herein.

[0013] Figure 3 This describes an instance of a plane that supports in-memory associative processing, based on the examples disclosed herein.

[0014] Figure 4 This document describes an example of calculating the association of tiles configured according to a vector mapping scheme, based on the examples disclosed herein.

[0015] Figure 5 This document describes an example of calculating the association of tiles configured according to a vector mapping scheme, based on the examples disclosed herein.

[0016] Figure 6 This document describes an example of a process flow that supports in-memory associative processing, based on the examples disclosed herein.

[0017] Figure 7 A block diagram of an apparatus supporting in-memory associative processing according to an example disclosed herein is shown.

[0018] Figures 8 to 12 Flowcharts illustrating one or more methods for supporting in-memory associative processing according to the examples disclosed herein are shown. Detailed Implementation

[0019] In some systems, the host device can offload various processing tasks to electronic devices, such as accelerators. For example, the host device can offload vector computations to electronic devices that can perform vector computations using computing engines and processing techniques. This offloading of vector computations may involve passing vectors or vector information from the host device to the electronic device, and then passing the results from the electronic device back to the host device. Therefore, the bandwidth of the electronic device can be constrained by the communication interface between the electronic device and the host device, as well as the size of the computing engine and serial processing. According to the techniques described herein, the host device can essentially increase processing bandwidth by offloading processing tasks to an associative processor memory (APM) system that performs vector computations in parallel using in-memory associative processing and other methods.

[0020] In some instances, an APM system can support multiple different vector mapping schemes, where a vector mapping scheme can refer to the organization of vectors written into the APM system's memory. For example, an APM system can support a first vector mapping scheme and a second vector mapping scheme. The APM system can select between vector mapping schemes (e.g., select one of the vector mapping schemes), and then write the vectors into the APM system's memory according to the selected vector mapping scheme. After the vectors are written into memory, the APM system can use associative processing to perform computational operations on the vectors according to the selected vector mapping scheme.

[0021] First, as referenced Figure 1 and 2 The features of this disclosure are described within the context of the system and vector computation described herein. (See references...) Figure 3-6 The features of this disclosure are described in the context of the plane, vector mapping scheme, and process flow. References refer to, as in, [references to, and may include, other references to ... Figures 7 to 12 The device diagrams and flowcharts of the described in-memory associative processing system further illustrate and describe these and other features of this disclosure.

[0022] Figure 1This document describes an example of a system 100 supporting in-memory associative processing, based on the examples disclosed herein. System 100 may include a host device 105 and an associative processing memory (APM) system 110. Host device 105 may interact with (e.g., communicate with, or control) the APM system 110 and other components of a device containing the APM system 110. In some instances, host device 105 and APM system 110 may interact via interface 115, which may be an example of a compute high-speed link (CXL) interface or other types of interfaces.

[0023] In some instances, system 100 may be contained in, or coupled to, a computing device, electronic device, mobile computing device, or wireless device. The device may be a portable electronic device. For example, the device may be a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, etc. Host device 105 may be or contain a system-on-a-chip (SoC), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or may be a combination of these types of components. In some instances, host device 105 may be referred to as a host, host system, or other suitable terms.

[0024] APM system 110 can be used as an accelerator (e.g., a high-speed processor) for host device 105 to offload various processing tasks to APM system 110, which can be configured to execute processing tasks faster than host device 105. For example, device 105 can send a program (e.g., an instruction set, such as Reduced Instruction Set Computing V (RISC-V), vector instructions) to APM system 110 for execution. As part of, or guided by, the program, APM system 110 can perform various computational operations on vectors (e.g., APM system 110 can perform vector computations). Computational operations can refer to logical operations, arithmetic operations, or other types of operations involving vector manipulation. A vector can contain one or more elements, each having a corresponding number of bits. The length or size of the vector can refer to the number of elements in the vector, and the length or size of the element can refer to the number of bits in the element.

[0025] APM controller 120 may be configured to interface with host device 105 on behalf of APM device 125. Upon receiving a program from host device 105, APM controller 120 may immediately parse the program and guide or otherwise prompt APM device 125 to perform various computational operations associated with or instructed by the program. In some instances, APM controller 120 may (e.g., from memory 130) retrieve vectors for computational operations and may communicate these vectors to APM device 125 for associated processing. In some instances, APM controller 120 may indicate vectors for computational operations to APM device 125 so that APM device 125 can retrieve the vectors from memory 130. In some instances, host device 105 may provide vectors to APM system 110. Therefore, memory 130 may be configured to store vectors accessible by APM controller 120, APM device 125, host device 105, or a combination thereof.

[0026] Vectors used for computational operations at APM device 125 may be indicated (or accompanied by) a program received from host device 105 or by other control signaling associated with the program (e.g., other separate control signaling). For example, a program indicating computational operations for a pair of vectors may include memory 130 containing one or more addresses of the vectors (or one or more pointers to one or more addresses). Although shown as included within APM system 110, memory 130 may be external to APM system 110 but still coupled to it. Although shown as a single component, the functionality of memory 130 may be provided by multiple memories 130.

[0027] APM device 125 may include memory units, such as content-addressable memory units (CAMs) configured to store vectors (e.g., vector operands, vector results) associated with computational operations. A vector operand may be a vector, i.e., an operand used for a computational operation (e.g., a vector operand may be a vector to which a computational operation is performed). A vector result may be a vector generated from a vector computation.

[0028] The APM system 110 can be configured to store information for various computational operations, such as truth tables, wherein the information for a given computational operation (e.g., the truth table) can indicate the result of the computational operation for various combinations of logical values. For example, the APM system 110 can store information (e.g., one or more truth tables) for logical operations (e.g., AND, OR, XOR, NOT, NAND, NOR, XNOR) and arithmetic operations (e.g., addition, subtraction) and other types of operations. Memory units storing information for computational operations (e.g., one or more truth tables) can store various combinations of logical values ​​of the operands of the computational operation, as well as the corresponding result and carry bit (if applicable) for each combination of logical values. The APM system 110 can store truth tables for associative processing in one or more memories (e.g., one or more on-die mask ROMs) that can be coupled to or included in the APM system 110. For example, the truth table may be stored in memory 130, in local memory of APM device 125, or both. In either instance, APM device 125 may cache common instructions on the device (e.g., instead of fetching or receiving the common instructions).

[0029] At least some (if not all) of the APM devices 125 can use associative processing to perform computational operations on vectors stored in that APM device 125. Unlike serial processing (where vectors move back and forth between the processor and memory), associative processing may involve searching and writing vectors in memory (also referred to as "in-situ"), which allows for increased parallelism in processing bandwidth. Performing computational operations in-situ also allows system 100 to bypass bottlenecks at the interface between host device 105 and APM system 110, and offers other advantages such as reduced latency and power consumption compared to other processing techniques (e.g., serial processing). Associative processing may also be referred to as associative computation or other suitable terms.

[0030] In some instances, the APM device 125, which performs computational operations using associative processing, can utilize information (e.g., a truth table) to perform computational operations bit-by-bit using techniques such as "search and write". For example, if the APM device 125 includes a CAM unit storing vector operands for computational operations, the APM device 125 can search in the CAM unit for a bit of the vector operand that matches an entry in the truth table corresponding to that computational operation, determine the result of the computational operation for that bit based on the matching entry in the truth table, and write the result back to content-addressable memory. The APM device 125 can then proceed to the next significant bit of the vector and perform computational operations on those bits using associative processing. In some instances, the computational operation for the bit may involve a carry bit determined as part of the computational operation on a less significant bit.

[0031] Each APM device 125 may include one or more dies 135, which may also be referred to as memory dies, semiconductor dies, or other suitable terms. Dies 135 may include multiple tiles 140, each of which may in turn include multiple planes 145. In some instances, tiles 140 may be configured such that individual planes 145 of each tile can operate simultaneously or be activated simultaneously (e.g., one plane of each tile can perform associative computations simultaneously). However, any number of tiles 140 may be active simultaneously (e.g., any number of tiles can perform associative computations simultaneously). Therefore, tiles 140 can operate in parallel, which can increase the number of computational operations that can be performed during a time interval, thereby increasing the bandwidth of the APM device 125 relative to other technologies. Using multiple APM devices 125 can further increase the bandwidth of the APM system 110 relative to other systems compared to using a single APM device 125. Each APM device 125 may include a local controller or logic for controlling the operation of the APM device 125.

[0032] Each plane 145 may contain a memory array comprising memory cells, such as CAM cells. The memory cells in the memory array may be arranged in columns and rows and may be non-volatile or volatile memory cells. A memory array containing CAM cells may be configured to search for CAM cells by content rather than by address. For example, a memory array containing CAM cells storing vectors used for computational operations may compare the logical values ​​of the operands of the vector with entries in a truth table associated with the computational operations to determine which results correspond to those logical values.

[0033] As mentioned, the APM device 125 can be configured to store vectors associated with computational operations in the memory cells of that APM device 125. To facilitate associative processing, vectors can be stored in a column-wise manner across multiple planes. For example, given multiple n-bit (e.g., n = 32) elements (denoted as E0 to E... N For a vector v0, the APM device 125 can partition each element into a set of contiguous bits (e.g., four sets of eight contiguous bits). The APM device 125 can store the first set of contiguous bits (e.g., the least significant set of contiguous bits) of each element of vector v0 in a first plane 145, where each row of plane 145 stores the first set of contiguous bits of the corresponding element of vector v0. Thus, in some instances, column 150 can store the first eight bits of each element of vector v0 (e.g., column 150 can span eight columns). In a similar manner, the APM device 125 can store the second most significant set of contiguous bits from each element of vector v0 in a second plane 145. This continues in the form of the remaining set of contiguous bits of vector v0. Therefore, vector v0 can be stored in a column-split manner across multiple planes. Bits of other vectors v1 to vn can be stored in a similar column-split manner across plane 145.

[0034] Using a split-storage technique to distribute vectors across multiple planes allows the APM device 125 to store more vectors per plane 145 compared to other techniques. This, in turn, allows the APM device 125 to operate on more vector combinations compared to other techniques. For example, consider a 256-row × 256-column plane. Instead of storing eight vectors with 32-bit elements across a single plane, which would limit the APM device 125 to operating on those eight vectors (no time-consuming vector moves), the APM device 125 can store 32 vectors with 32-bit elements across four planes. This allows the APM device 125 to operate on those 32 bit vectors (e.g., one plane at a time) without performing time-consuming vector moves.

[0035] In some instances, the APM device 125 may store vectors according to a vector mapping scheme, which may be one of several vector mapping schemes supported by the APM device 125. A vector mapping scheme may refer to a scheme used to map (and write) vectors to plane 145 of the APM device 125. For example, the APM device 125 may support a first vector mapping scheme, referred to as vector mapping scheme 1, and a second vector mapping scheme, referred to as vector mapping scheme 2. In vector mapping scheme 1, vectors may be distributed across the plane of the same tile 140. In vector mapping scheme 2, vectors may be distributed across the planes of different tiles 140. A vector mapping scheme may also be referred to as a storage scheme, a layout scheme, or other suitable terms.

[0036] APM system 110 can select from among vector mapping schemes, and then write vectors to APM device 125 according to the selected vector mapping scheme. For example, APM system 110 can select a vector mapping scheme for the set of computational operations based on the size of the vector associated with the set of computational operations, the type of computational operations in the set of operations (e.g., arithmetic comparison logic), the number of computational operations in the set, or combinations thereof, and other aspects. In some instances, APM system 110 can select a vector mapping scheme in response to an instruction for a vector mapping scheme provided by host device 105. For example, host device 105 can indicate a vector mapping scheme associated with an instruction set used for the set of computational operations. After the selected vector mapping scheme has written vectors to APM device 125, APM device 125 can perform computational operations on the vectors according to the selected vector mapping scheme using associative processing. Alternatively, a compiler or preprocessor can determine the vector mapping scheme.

[0037] The associated processing of the techniques described herein may be implemented by logic at APM system 110, logic at APM device 125, or logic distributed between APM system 110 and APM device 125. The logic may include one or more controllers, access circuitry systems, communication circuitry, or combinations thereof, as well as other components and circuitry. The logic may be configured to perform aspects of the techniques described herein, causing components of APM system 110 and / or APM device 125 to perform aspects of the techniques described herein, or both.

[0038] Figure 2 This document describes an example of a vector computation 200 supporting in-memory associative processing, based on the examples disclosed herein. The vector computation 200 may be an example of vector addition and may be performed on operand vectors vA and vB, which may be stored in a planar memory cell (e.g., a CAM cell) of an APM device. The result of the vector addition may be a vector vD. Each operand vector may contain four bits (e.g., an operand vector may contain a single 4-bit element), and the position of each bit may be labeled i. The operand vector may be as described in reference... Figure 1 The discussion is stored in the plane of the APM device and can be associated with a set of vector instructions (e.g., RISC-V vector instructions). Vector computation 200 can be performed using truth table 205, which can be a truth table for adding two bits and a potential carry bit. Truth table 205 can be stored in memory coupled to or contained within the APM device, and CAM technology can be used to compare entries (e.g., rows) of truth table 205 with the operand bits of vectors vA and vB.

[0039] The examples provided of using associative processing for computational operations on vectors are for illustrative purposes only and are not intended to be limiting in any way.

[0040] To perform addition of vectors vA and vB using associative processing, the APM device can retrieve entries from memory (e.g., using a sequencer) from truth table 205 and compare the entries with the operands of vectors vA and vB (e.g., in-situ using CAM technology). Upon finding a match, the APM device can immediately add the corresponding results of the matching entries (e.g., vDi and carry c). i+1 The data is written to the plane where the vector is stored (or a different plane), and then moved to the second most significant operand of the vector.

[0041] For example, for i = 0, the APM device can compare the entry in truth table 205 with the corresponding operand bits from vectors vA and vB (e.g., c0 = 0, vA0 = 1, and vB0 = 0). After detecting a match between the operand bits and the entry in truth table 205, the APM device can immediately write the result corresponding to the matching entry (e.g., vD0 = 0 and carry c1 = 1) to the plane storing the operand vectors (or the device can compare the entry from truth table 205 with the operand bits serially for i = 0 (e.g., starting from the top entry and moving down one entry at a time in truth table 205). In some instances, the APM device can compare the entry from truth table 205 with multiple operand bits in parallel (e.g., simultaneously).

[0042] After determining the result of the i-th operand, the APM device can continue to the next valid operand (which may contain the carry-in bit i+1 determined from the i-th operand). For example, after determining the result of the i=0 operand, the APM device can continue to the i=1 operand (which may contain the carry-in bit c1 determined from the i=0 operand). However, in some situations (e.g., when the computation operation is a logical operation), the APM device can perform the computation operation on some or all of the operands in parallel.

[0043] For i=1, the APM device can compare the entry in truth table 205 with the corresponding operand bits from vectors vA and vB (e.g., c1=1, vA1=0, and vB1=0). After detecting a match between the operand bits and the entry in truth table 205, the APM device can immediately write the result corresponding to the matching entry (e.g., vD1=1 and carry c2=0) to the plane storing the operand vectors (or a different plane). The APM device can compare the entry from truth table 205 with the operand bits serially for i=1 (e.g., starting from the top entry and moving down one entry at a time in truth table 205). After determining the result of operand bit i=1, the APM device can continue to operand bit i=2 (which may include the carry c2 determined from operand bit i=1).

[0044] For i=2, the APM device can compare the entry in truth table 205 with the corresponding operand bits from vectors vA and vB (e.g., c2=0, vA2=0, and vB2=0). After detecting a match between the operand bits and the entry in truth table 205, the APM device can immediately write the result corresponding to the matching entry (e.g., vD2=0 and carry c3=0) to the plane storing the operand vectors (or a different plane). The APM device can compare the entry from truth table 205 with the operand bits serially for i=2 (e.g., starting from the top entry and moving down one entry at a time in truth table 205). After determining the result for operand bit i=2, the APM device can continue to operand bit i=3 (which may contain the carry c3 determined from operand bit i=2).

[0045] For i=3, the APM device can compare the entries in truth table 205 with the corresponding operand bits from vectors vA and vB (e.g., c3=0, vA3=0, and vB3=1). After detecting a match between the operand bits and the entries in truth table 205, the APM device can immediately write the result corresponding to the matching entry (e.g., vD3=1 and carry c4=0) to the plane storing the operand vectors (or a different plane). The APM device can compare the entries from truth table 205 with the operand bits serially for i=3 (e.g., starting from the top entry and moving down one entry at a time in truth table 205).

[0046] Therefore, the APM device can use correlation processing to determine that adding vA (e.g., 0b0001) and vB (e.g., 0b1001) results in vD = 0b1010. After completing the addition operation, the APM device can transmit the vector vD to the host device, using the resulting vector vD to perform other computational operations, or combinations thereof.

[0047] An APM device can use associative processing for computational operations on vectors regardless of the vector mapping scheme. However, the propagation of carry bits caused by associative processing can vary between vector mapping schemes. For example, if vector mapping scheme 1 is chosen, then specific carry bits (e.g., those applicable to the second-most-valid sets of adjacent bits) can be propagated between planes of the same tile. If vector mapping scheme 2 is chosen, then specific carry bits (e.g., those applicable to the second-most-valid sets of adjacent bits) can be propagated between different tiles.

[0048] Figure 3 This describes an instance of plane 300 that supports in-memory associative processing, based on the examples disclosed herein. Plane 300 may be used as a reference. Figure 1An instance of plane 145 is described. Therefore, plane 300 can be configured to store vectors of computational operations performed using associative processing. In some instances, plane 300 may be in the same tile, as discussed in Reference Vector Mapping Scheme 1. In other instances, plane 300 may be in different tiles, as discussed in Reference Vector Mapping Scheme 2.

[0049] In a given instance, n vectors with multiple (e.g., 256) multi-bit elements (e.g., 32-bit elements) are mapped to four planes. However, other numbers of these factors are considered and are within the scope of this disclosure.

[0050] The APM device can handle n vectors (denoted as v0 to v1). n-1 The vector is mapped and written to four planes. The number of planes to which a vector is mapped can be a function of the element length and the number of bits mapped to each plane. For example, the number of planes to which a vector is mapped can be equal to the element length divided by the number of bits mapped to each plane. In a given instance, the number of planes to which a vector is mapped is four, equal to the element length (e.g., 32) divided by the number of bits mapped to each plane (e.g., eight).

[0051] At least some (if not all) planes can store connected bit sets of at least some (if not all) elements from at least some (if not all) vectors. For example, plane 0 can store connected bits 0-7 of each element of each vector; plane 1 can store connected bits 8-15 of each element of each vector; plane 2 can store connected bits 16-23 of each element of each vector; and plane 3 can store connected bits 24-31 of each element of each vector. Bits from different vectors can be stored in different columns of the plane, while bits from different elements can be stored in different rows of the plane. For example, bits from vector 0 can be stored in the first set of eight columns of each plane; bits from vector 1 can be stored in the second set of eight columns of each plane; bits from vector 2 can be stored in the third set of eight columns of each plane; and so on. For each vector, bits from element 0 can be stored in the first row of a given plane; bits from element 1 can be stored in the second row of the plane; bits from element 2 can be stored in the third row of the plane, and so on.

[0052] Therefore, a plane with x rows (e.g., 256 rows) may be able to store vectors with x elements or fewer (vectors with a length of 256 or less). If a vector has more than x elements, then the elements of the vector can be distributed across multiple planes (e.g., the elements of a vector with a length of 512 can be stored in two planes, where the first plane stores bits from the first 256 elements and the second plane stores bits from the last 256 elements). Thus, a system using the vector mapping scheme described herein can support vectors larger than those of other systems (e.g., serial processing systems) that may be constrained by the size of the processing circuitry system (e.g., a computing engine).

[0053] Vectors can be stored according to either vector mapping scheme 1 or vector mapping scheme 2. In vector mapping scheme 1, the planes to which vectors are mapped can be in the same tile. For example, planes 0 to 3 can be in tile A. In vector mapping scheme 2, the planes to which vectors are mapped can be in different tiles. For example, plane 0 can be in tile A, plane 1 can be in tile B, plane 2 can be in tile C, and plane 3 can be in tile D. Commonly, tiles A to D (e.g., tiles with vectors scattered on them) can be called hyperplanes. These two vector mapping schemes allow an APM device to perform computational operations on multiple vectors in parallel (e.g., during partially or fully overlapping time periods). For example, given h tiles, an APM device can perform h different computational operations at once.

[0054] Therefore, in vector mapping scheme 1, the APM device can perform computational operations on a vector using a single tile. For example, the APM device can use tile A to perform computational operations on bits 0-7 of the elements in the vector, use tile A to perform computational operations on bits 8-15 of the elements in the vector, use tile A to perform computational operations on bits 16-23 of the elements in the vector, and use tile A to perform computational operations on bits 24-31 of the elements in the vector. If a carry bit is generated by a computational operation, the APM device can transfer the carry bit (denoted as 'C') between tiles A in the plane. For example, if a carry bit is generated by a computational operation on bits 0-7, the APM device can transfer that carry bit from plane 0 in tile A to plane 1.

[0055] In vector mapping scheme 2, the APM device can use multiple tiles to perform computational operations on a vector. For example, the APM device can use tile A to perform computational operations on bits 0-7 of the elements in the vector, tile B to perform computational operations on bits 8-15, tile C to perform computational operations on bits 16-23, and tile D to perform computational operations on bits 24-31. If a carry is generated by a computational operation, the APM device can transfer the carry between tiles. For example, if a carry is generated by a computational operation on bits 0-7, the APM device can transfer that carry from tile A to tile B.

[0056] The associated processing of the techniques described herein can be implemented by logic at the APM system, logic at the APM device, or logic distributed between the APM system and the APM device. The logic may include one or more controllers, access circuitry systems, communication circuitry, or combinations thereof, as well as other components and circuitry. The logic may be configured to perform aspects of the techniques described herein, causing components of the APM system and / or the APM device to perform aspects of the techniques described herein, or both.

[0057] Figure 4 This describes an example of a tile 400 supporting in-memory associative processing, based on the examples disclosed herein. Tile 400 may include tile A, tile B, and tile C. Each tile may store a corresponding vector set on three planes, and said vectors may contain n multi-bit (e.g., 24-bit) elements. For example, the three planes of tile A may store one or more vectors V for a first computational operation (referred to as computational operation I). I And other information. The three planes of patch B can store one or more vectors V for the second computational operation (referred to as computational operation II). II And other information. Furthermore, the three planes of the puzzle C can store one or more vectors V for the third computational operation (referred to as computational operation III). III And other information. Although referencing different vectors V I V II and V III The description is provided, but two or more of the computational operations may involve the same vector (e.g., different computational operations may be performed on the same vector in parallel).

[0058] Between time t0 and time t1, piece A can be used to compute the vector V used for operation I. I The elements 0-7 of the vector V are used to perform computation operation I, where vector V is used to perform computation operation I. I Bits 0-7 are stored in the first plane of tile A; tile B can store the vector V used for computation operation II. IIThe elements 0-7 of the vector V are used to perform computation operation II, where vector V is used to perform computation operation II. II Bits 0-7 are stored in the first plane of tile B; and tile C can be used to compute the vector V used for operation III. III The elements 0-7 of the vector V are used to perform computation operation III, where vector V is used to perform computation operation III. III Bits 0-7 are stored in the first plane of tile C. Computational operations can be performed using associative processing as described in this document.

[0059] The result of a computation operation on bits 0-7 can be stored in the same plane as the operands or in a different plane. For example, vector V I The result of the computation operation I on bits 0-7 can be stored (e.g., as a vector) in the first plane of patch A. Similarly, vector V II The result of computation operation II on bits 0-7 can be stored (e.g., as a vector) in the first plane of patch B. And vector V III The result of computation operation III on bits 0-7 can be stored (e.g., as a vector) in the first plane of the puzzle C.

[0060] In some instances (e.g., where the computation operation is arithmetic), computation operations on bits 0-7 can produce a carry bit. In such scenarios, the carry bit (denoted as 'C') can be propagated from the plane storing bits 0-7 to the plane storing bits 8-15 (e.g., the second most contiguous set of bits). For example, if vector V I If the computation operation I on bits 0-7 generates a carry bit, then the carry bit can be transmitted from the first plane of tile A to the second plane of tile A (storage vector V). I (8-15 bits). Therefore, in vector mapping scheme 1, carry bits can be propagated between planes of the same piece.

[0061] Between time t1 and time t2, piece A can be used to compute the vector V for operation I. I The elements 8-15 of the vector V are computed using operation I, where vector V is used to compute the vector V. I Bits 8-15 are stored in the second plane of tile A; tile B can store the vector V used for computation operation II. II The elements 8-15 of the vector V undergo computation operation II, where vector V... II Bits 8-15 are stored in the second plane of tile B; and tile C can be used to compute the vector V used for operation III. III The elements 8-15 of the vector V undergo computation operation III, where the vector V... III Bits 8-15 are stored in the second plane of tile C. Computational operations can be performed using associative processing as described herein, and these operations can be based on any carry bits received from the first plane.

[0062] The result of a computation operation on bits 8-15 can be stored in the same plane as the operand bits or in a different plane. For example, vector V I The result of the computation operation I on bits 8-15 can be stored (e.g., as a vector) in the second plane of patch A. Similarly, vector V II The result of computational operation II on bits 8-15 can be stored (e.g., as a vector) in the second plane of patch B. And vector V... III The result of computation operation III on bits 8-15 can be stored (e.g., as a vector) in the second plane of the puzzle C.

[0063] In some instances (e.g., where the computation operation is an arithmetic operation), computation operations on bits 8-15 can produce a carry bit. In such scenarios, the carry bit (denoted as 'C') can be propagated from the plane storing bits 8-15 to the plane storing bits 16-23 (e.g., the second most contiguous set of bits). For example, if vector V I The computational operation I on bits 8-15 generates a carry bit, which can then be propagated from the second plane of tile A to the third plane of tile A (storage vector V). I (positions 16-23).

[0064] Between time t2 and time t3, piece A can be used to compute the vector V for operation I. I The elements 16-23 of the vector V are computed using operation I, where the vector V is... I Bits 16-23 are stored in the third plane of tile A; tile B can store the vector V used for computation operation II. II The elements 16-23 of the vector V are computed using operation II, where vector V is used for computation. II Bits 16-23 are stored in the third plane of tile B; and tile C can be used to compute the vector V for operation III. III The elements 16-23 of the vector V are computed using operation III, where vector V is used for computation. III Bits 16-23 are stored in the third plane of tile C. Computational operations can be performed using associative processing as described herein, and these operations can be based on any carry bit received from the first plane.

[0065] The result of a computation operation on bits 16-23 can be stored in the same plane as the operand bits or in a different plane. For example, vector V I The result of the computation operation I on bits 16-23 can be stored (e.g., as a vector) in the third plane of patch A. Similarly, vector V II The result of computational operation II on bits 16-23 can be stored (e.g., as a vector) in the third plane of patch B. And vector V...III The result of computation operation III on bits 16-23 can be stored (e.g., as a vector) in the third plane of the puzzle C.

[0066] Therefore, the APM device can perform computational operations using associative processing and tiles configured according to vector mapping scheme 1. After completing the computational operation, the APM device can communicate the result of the computational operation to the host device, using the result to perform one or more additional computational operations, or both.

[0067] Compared to vector mapping scheme 2, vector mapping scheme 1 allows the APM device to process longer vectors. Therefore, the APM device can choose vector mapping scheme 1 instead of vector mapping scheme 2 based on the length of the vector it will process. For example, if the threshold quantity of a vector has a length that satisfies (e.g., is greater than) a threshold length, then the APM device can choose vector mapping scheme 1. In some instances, the threshold length can be equal to the number of rows per plane.

[0068] Compared to other vector mapping schemes (such as vector mapping scheme 2), vector mapping scheme 1 allows the APM device to process arithmetic vectors more efficiently. Therefore, the APM device can choose vector mapping scheme 1 over vector mapping scheme 2 based on the type of computational operations it will perform. For example, if the ratio of arithmetic operations to logical operations meets (e.g., is greater than) a threshold ratio, then the APM device can choose vector mapping scheme 1. Vector mapping scheme 1 also allows the APM device to execute multiple vector execution threads in parallel (e.g., multiple disparate computational operations) because the splices are not limited to executing the same instruction.

[0069] Figure 5 This describes an example of a tile 500 supporting in-memory associative processing, based on the examples disclosed herein. Tile 500 may include tile A, tile B, and tile C. Each tile may store three distinct vector sets on three distinct planes, and each vector may contain n multi-bit (e.g., 24-bit) elements. For example, the first plane of tile A may store one or more vectors V from a first computational operation (referred to as computational operation I). I The elements are bits 0-7, and other information; the second plane of patch A may store one or more vectors V from the second computational operation (referred to as computational operation II). II The elements are bits 0-7, and other information; and the third plane of patch A can store one or more vectors V from the third computational operation (referred to as computational operation III). III The elements are stored in bits 0-7, along with other information. Puzzle B and puzzle C can be configured similarly, except that puzzle B can store bits 8-15 of the vector and puzzle C can store bits 16-23 of the vector.

[0070] Between time t0 and time t1, piece A can be used to compute the vector V used for operation I. I The elements 0-7 of the vector are used to perform computational operations II. Associative processing, as described herein, can be used to perform computational operations. Vector V I The result of the computation operation I on bits 0-7 of an element can be stored in the same plane as the operand bits or in a different plane. For example, vector V I The result of the computation operation I on bits 0-7 of the element can be stored (e.g., as a vector) in the first plane of the puzzle A.

[0071] In some instances (e.g., where computation operation I is an arithmetic operation), vector V I Computational operations on bits 0-7 can produce carry bits. In this type of scenario, the carry bit (denoted as 'C') can be obtained from the storage vector V. I The 0-7 bit pieces (e.g., piece A) are communicated to the 8-15 bit pieces (e.g., the second most contiguous set of bits) (e.g., piece B). Therefore, in vector mapping scheme 2, carry bits can be communicated between pieces (e.g., between planes of different pieces).

[0072] Between time t1 and time t2, piece A can be used to compute the vector V for operation II. II The elements 0-7 of the array are used to perform computation operation II. Additionally, piece B can be used on the vector V used for computation operation I. I The calculation operation I is performed on bits 8-15 of the element. The calculation operation can be performed using the association processing described herein, and the calculation operation can be based on any carry bit received from other pieces.

[0073] Vector V II The result of operation II on bits 0-7 can be stored in the same plane as the operand bits or in a different plane. For example, vector V II The result of computation operation II on bits 0-7 can be stored (e.g., as a vector) in the second plane of patch A. Similarly, vector V I The result of computation operation I on bits 8-15 can be stored (e.g., as a vector) in the first plane of patch B.

[0074] In some instances (e.g., where the computation operation is arithmetic), the computation performed between t1 and t2 may produce one or more carry bits. For example, vector V... II The computational operation II on bits 0-7 can generate carry bits, vector V I Computational operation I on bits 8-15 can produce a carry bit, or both. In this type of scenario, the carry bit from computational operation II can be obtained from the storage vector V.II The bits 0-7 of the puzzle (e.g., puzzle A) are conveyed to the storage vector V. II The 8th to 15th bits of the puzzle (e.g., puzzle B); the carry bit from computation operation I can be obtained from the storage vector V. I The bits 8-15 of the puzzle (e.g., puzzle B) are conveyed to the storage vector V. I Pieces in positions 16-23 (e.g., puzzle C), or both.

[0075] Between time t2 and time t3, piece A can be used to compute vector V for operation III. III Operation III is performed on bits 0-7 of the elements. Additionally, piece B can be used on the vector V used for operation II. II The elements 8-15 of the array are used to perform computation operation II. Furthermore, the piece C can be used on the vector V used for computation operation I. I The calculation operation I is performed on bits 16-23 of the element. The calculation operation can be performed using the association processing described herein, and the calculation operation can be based on any carry bit received from other tiles.

[0076] Vector V III The result of a computation operation on bits 0-7 can be stored in the same plane as the operand bits or in a different plane. For example, vector V III The result of computation operation III on bits 0-7 can be stored (e.g., as a vector) in the third plane of patch A. Similarly, vector V II The result of computational operation II on bits 8-15 can be stored (e.g., as a vector) in the second plane of patch B. And vector V... I The result of computation operation I on bits 16-23 can be stored (e.g., as a vector) in the first plane of the puzzle C.

[0077] Therefore, the APM device can perform computational operations using associative processing and tiles configured according to vector mapping scheme 2. After completing the computational operation, the APM device can communicate the result of the computational operation to the host device, using the result to perform one or more additional computational operations, or both.

[0078] Vector mapping scheme 2 allows the APM device to interleave (or “pipeline”) computational operations in a manner not supported by vector mapping scheme 1, and is therefore more efficient for a particular processing task. However, vector mapping scheme 2 supports smaller vector lengths compared to vector mapping scheme 1. Therefore, the APM device can select vector mapping scheme 2 based on the length of the vectors it will process. For example, the APM device can select vector mapping scheme 2 if the vector has a threshold quantity that satisfies (e.g., is less than) a threshold length.

[0079] Compared to other vector mapping schemes (such as vector mapping scheme 1), vector mapping scheme 2 allows APM devices to process logic vectors more efficiently. For example, vector mapping scheme 2 allows APM devices to process logic vectors more efficiently by mapping vector V... I The entire 24 bits are executed in parallel (e.g., using pieces A, B, and C) to fully complete the vector V between time t0 and time t1. I Logical operations on top of each other. This type of parallelism is possible for logical operations because, unlike arithmetic operations, logical operations do not generate carry bits. Therefore, each piece in vector mapping scheme 2 can operate on the lower-order (e.g., less efficient) connected bit set without waiting for the lower-order pieces to complete. Thus, the APM device can select vector mapping scheme 1 over vector mapping scheme 2 based on the type of computational operations the APM device will perform. For example, the APM device can select vector mapping scheme 2 if the ratio of logical operations to arithmetic operations meets (e.g., is greater than) a threshold ratio.

[0080] Vector mapping scheme 2 can also implement "pipelines" for different computational operations on the same plane (as opposed to creating such pipelines by joining different planes in each tile). For example, at time t0, plane 0 in tile A can perform computational operation 1 (e.g., logical operation 1); at time t1, plane 0 in tile A can perform computational operation 2 (e.g., logical operation 2) and plane 0 in tile B can perform computational operation 1 (e.g., logical operation 1), and so on.

[0081] Figure 6 This describes an example of a process flow 600 supporting in-memory associative processing, based on the examples disclosed herein. Process flow 600 may be implemented by means of, for example, an APM system or APM device as described herein. The device may support multiple vector mapping schemes, such as vector mapping scheme 1 and vector mapping scheme 2. In some instances, the device may switch between vector mapping schemes (e.g., for different instruction sets).

[0082] At 605, the device may receive a set of instructions (e.g., a program, a vector instruction set) from a host device. The instruction set may indicate or be associated with a set of computational operations. In some instances, the host device may communicate the instruction set via a CXL interface. In some instances, the instruction set may indicate the memory address of a set of vectors, which are operands used for computational operations. Alternatively, the instruction set may be accompanied by a vector set. In some instances, the instruction set may indicate one of the vector mapping schemes supported by the device.

[0083] At 610, the device may retrieve a vector set from memory coupled to the device. For example, the device may retrieve the vector set from a memory address indicated by an instruction set. Alternatively, the device may receive the vector set from a host device or determine that the vector set is already stored in the device's APM die.

[0084] At 615, the device may determine various characteristics of the set of computational operations, various characteristics of the vector set, or both, and other aspects. For example, the device may determine the length of the vector set (e.g., the number of elements per vector). Alternatively or additionally, it may determine the number of arithmetic operations in the set of computational operations, the number of logical operations in the set of computational operations, or both. In some instances, the device may determine the ratio of arithmetic operations to logical operations.

[0085] At 620, the device can select a vector mapping scheme from a set of vector mapping schemes supported by the device. For example, the device can select vector mapping scheme 1 or vector mapping scheme 2. In some instances, the device can select a vector mapping scheme indicated by the host device at 605. In other instances, the device can select a vector mapping scheme based on one or more characteristics. In some instances, the device can select vector mapping scheme 1 based on one or more vectors in a set with a length greater than a threshold length (e.g., greater than the number of rows per plane). In some instances, the device can select vector mapping scheme 1 based on a set of computational operations where the ratio of arithmetic operations to logical operations satisfies a threshold ratio. In some instances, the device can select vector mapping scheme 2 based on one or more vectors in a set with a length less than the threshold length. In some instances, the device can select vector mapping scheme 2 based on a set of computational operations where the ratio of logical operations to arithmetic operations satisfies a threshold ratio.

[0086] At 625, the device can write a vector set according to a selected vector mapping scheme. For example, if the device selects vector mapping scheme 1, then the device can write a vector set according to as described herein and as... Figure 3 and 4 The vector mapping scheme 1 shown writes the vector set onto the plane of the device. If the device selects vector mapping scheme 2, then the device can, according to as described herein and as... Figure 3 and 5 The vector mapping scheme 2 shown writes the vector set onto the plane of the device.

[0087] At 630, the device can use associative processing and perform a set of computational operations on the vector set according to the selected vector mapping scheme. For example, if the device selects vector mapping scheme 1, then the device can use associative processing and perform computational operations according to as described herein and as... Figure 3 and4 The vector mapping scheme 1 shown performs a set of computational operations on the vector set. If the device selects vector mapping scheme 2, then the device can use associative processing and, according to as described herein and as... Figure 3 and 5 The vector mapping scheme 2 shown performs a set of computational operations on the vector set.

[0088] At 635, the device may write the results of the computational operation set to the device plane. At 640, the device may transmit some or all of the results to the host device. Alternatively, the device may use some or all of the results to perform additional processing tasks.

[0089] Therefore, the device can use association processing to perform a set of computational operations on a vector set.

[0090] Figure 7 A block diagram 700 illustrates an apparatus 720 supporting in-memory associative processing according to an example disclosed herein. Apparatus 720 may be referenced. Figures 1 to 6 Examples of aspects of the described apparatus. Apparatus 720 or its various components may be examples of apparatus for performing various aspects of in-memory associative processing as described herein. For example, apparatus 720 may include receiving circuitry 725, logic 730, access circuitry 735, memory interface 740, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0091] The receiving circuitry 725 may be configured or otherwise supported to provide means for receiving signaling from a host device indicating a set of instructions, the set of instructions indicating a first vector and a second vector as operands for a computational operation. The logic 730 may be configured or otherwise supported to provide means for selecting from a set of vector mapping schemes a vector mapping scheme for performing the computational operation using associative processing. The access circuitry 735 may be configured or otherwise supported to provide means for writing data representing the first vector and the second vector to a set of one or more planar tiles, at least in part based on the selected vector mapping scheme.

[0092] In some instances, the access circuitry 735 may be configured or otherwise support means for performing the computational operation on the data representing the first and second vectors using association processing. In some instances, the access circuitry 735 may be configured or otherwise support means for writing data representing a third vector, which is the result of the computational operation, into the plane set.

[0093] In some instances, the access circuitry 735 may be configured or otherwise supported as means for comparing data representing bits of the first vector and the second vector with memory cell bits storing a truth table indicating the result of the computation operation for various combinations of logical values, wherein the performance of the computation operation is at least in part based on the comparison.

[0094] In some instances, the receiving circuitry 725 may be configured or otherwise supported as means for receiving an indication of the selected vector mapping scheme from the host device, wherein the selected vector mapping scheme is selected at least in part based on the indication.

[0095] In some instances, logic 730 may be configured or otherwise support means for determining the number of elements in the first vector, the number of elements in the second vector, or both, wherein the selected vector mapping scheme is selected based on the number of elements in the first vector, the number of elements in the second vector, or both.

[0096] In some instances, logic 730 may be configured or otherwise support means for determining the ratio of logical operations to arithmetic operations associated with the instruction set, wherein the selected vector mapping scheme is selected based on the ratio of the logical operations to the arithmetic operations.

[0097] In some instances, to support writing, the access circuitry 735 may be configured or otherwise supported for the means to write the data representing the first vector to a different set of columns of the plane set than the set to which the data representing the second vector is written.

[0098] In some instances, to support write operations, the access circuitry 735 may be configured or otherwise supported to support means for writing data representing different connected bit sets of elements of the first vector to different planes in the plane set. In some instances, to support write operations, the access circuitry 735 may be configured or otherwise supported to support means for writing data representing different connected bit sets of elements of the second vector to the different planes in the plane set.

[0099] In some instances, to support write operations, the access circuitry 735 may be configured or otherwise supported to support means for writing data of a first contiguous bit set representing an element of the first vector and data of a first contiguous bit set representing an element of the second vector to a first plane of the plane set in the tile. In some instances, to support write operations, the access circuitry 735 may be configured or otherwise supported to support means for writing data of a second contiguous bit set representing an element of the first vector and data of a second contiguous bit set representing an element of the second vector to a second plane of the plane set in the tile.

[0100] In some instances, to support write operations, the access circuitry 735 may be configured or otherwise supported to support means for writing data of a first contiguous bit set representing an element of the first vector and data of a first contiguous bit set representing an element of the second vector to a first plane of the plane set in the first tile. In some instances, to support write operations, the access circuitry 735 may be configured or otherwise supported to support means for writing data of a second contiguous bit set representing an element of the first vector and data of a second contiguous bit set representing an element of the second vector to a second plane of the plane set in the second tile.

[0101] In some instances, the memory interface 740 may be configured or otherwise support means for retrieving the first vector and the second vector from a memory coupled to the logic, at least in part based on the instruction set.

[0102] In some instances, the receiving circuitry 725 may be configured or otherwise supported to provide means for receiving signaling from a host device indicating a set of instructions, the set of instructions indicating a vector of operands for computational operations, the vector containing a plurality of elements, each having a corresponding bit length. In some instances, the access circuitry 735 may be configured or otherwise supported to provide means for writing data representing a first contiguous bit set of the plurality of elements to a first plane of the tile and writing data representing a second contiguous bit set of the at least one element to a second plane of the tile. In some instances, the access circuitry 735 may be configured or otherwise supported to provide means for performing the computational operation using associative processing, at least in part based on writing the data representing the first contiguous bit set to the first plane and at least in part based on writing the data representing the second contiguous bit set to the second plane.

[0103] In some instances, the instruction set indicates a second vector as a second operand for the computational operation, and the access circuitry 735 may be configured or otherwise support means for writing data of a first contiguous bit set representing an element of the second vector to the first plane of the tile and for writing data of a second contiguous bit set representing an element of the second vector to the second plane of the tile.

[0104] In some instances, the access circuitry 735 may be configured or otherwise support means for writing data of a first contiguous bit set representing a second element of the vector to the first plane of the tile and for writing data of a second contiguous bit set representing the second element of the vector to the second plane of the tile.

[0105] In some instances, to support writing, the access circuitry 735 may be configured or otherwise supported for means of writing the data representing the first connected bit set to a column subset of the first plane and writing the data representing the second connected bit set to a column subset of the second plane.

[0106] In some instances, logic 730 may be configured or otherwise supported for means of selecting the vector mapping scheme based at least in part on the fact that the number of the plurality of elements of the vector is greater than the number of rows in each of the plurality of planes. In some instances, logic 730 may be configured or otherwise supported for means of selecting the vector mapping scheme based at least in part on the association of the instruction set with a ratio of arithmetic and logical operations greater than a threshold ratio.

[0107] In some instances, to support write operations, the access circuitry 735 may be configured or otherwise supported to provide means for comparing data representing bits of the vector and bits of the second vector with memory cell bits storing a truth table indicating the result of the computation operation for various combinations of logical values. In some instances, to support write operations, the access circuitry 735 may be configured or otherwise supported to provide means for writing data representing a third vector, the result of the computation operation, to the plane set, at least in part based on the comparison.

[0108] In some instances, the receiving circuitry 725 may be configured or otherwise supported to provide means for receiving signaling from a host device indicating a set of instructions, the set of instructions indicating a vector of operands for computational operations, the vector containing a plurality of elements, each having a corresponding bit length. In some instances, the access circuitry 735 may be configured or otherwise supported to provide means for writing data representing a first contiguous bit set of at least one of the plurality of elements to a first plane of a first tile and data representing a second contiguous bit set of the at least one element to a second plane of a second tile. In some instances, the access circuitry 735 may be configured or otherwise supported to provide means for performing the computational operation using associative processing, at least in part based on writing the data representing the first contiguous bit set to the first plane and at least in part based on writing the data representing the second contiguous bit set to the second plane.

[0109] In some instances, the instruction set indicates a second vector as a second operand for the computational operation, and the access circuitry 735 may be configured or otherwise support means for writing data of a first contiguous bit set representing an element of the second vector to the first plane of the first tile and for writing data of a second contiguous bit set representing an element of the second vector to the second plane of the second tile.

[0110] In some instances, the access circuitry 735 may be configured or otherwise support means for writing data of a first contiguous bit set representing a second element of the vector to the first plane of the first tile and for writing data of a second contiguous bit set representing the second element to the second plane of the second tile.

[0111] In some instances, to support writing, the access circuitry 735 may be configured or otherwise supported for means of writing the data representing the first connected bit set to a column subset of the first plane and writing the data representing the second connected bit set to a column subset of the second plane.

[0112] In some instances, logic 730 may be configured or otherwise supported for means of selecting the vector mapping scheme based at least in part on the fact that the number of the plurality of elements of the vector is greater than the number of rows in each of the plurality of planes. In some instances, logic 730 may be configured or otherwise supported for means of selecting the vector mapping scheme based at least in part on the association of the instruction set with a ratio of arithmetic and logical operations greater than a threshold ratio.

[0113] In some instances, to support write operations, the access circuitry 735 may be configured or otherwise supported to provide means for comparing data representing bits of the vector and bits of the second vector with memory cell bits storing a truth table indicating the result of the computation operation for various combinations of logical values. In some instances, to support write operations, the access circuitry 735 may be configured or otherwise supported to provide means for writing data representing a third vector, the result of the computation operation, to the plane set, at least in part based on the comparison.

[0114] In some instances, the receiving circuitry 725 may be configured or otherwise supported to support means for receiving signaling indicating the instruction set from the host device. In some instances, the logic 730 may be configured or otherwise supported to support means for selecting between a first vector mapping scheme and a second vector mapping scheme for writing vectors to a plane of the device. In some instances, the access circuitry 735 may be configured or otherwise supported to support means for writing data representing a first contiguous bit set of elements of the vector to a first plane and data representing a second contiguous bit set of elements to a second plane, at least in part based on the selected vector mapping scheme. In some instances, the access circuitry 735 may be configured or otherwise supported to support means for performing the computational operation using association processing, at least based on writing the data representing the first and second contiguous bit sets.

[0115] In some instances, logic 730 may be configured or otherwise support means for determining the ratio of arithmetic and logical operations associated with the instruction set, at least in part based on the length of the vector of the plurality of elements, or both, wherein the selected vector mapping scheme is selected at least in part based on the ratio, the length of the vector, or both.

[0116] In some instances, the instruction set indicates a second vector as operands for the computational operation, and the access circuitry 735 may be configured or otherwise support means for writing data of a first contiguous bit set representing the elements of the second vector to the first plane and writing data of a second contiguous bit set representing the elements of the second vector to the second plane, at least in part based on the selected vector mapping scheme.

[0117] In some instances, the access circuitry 735 may be configured or otherwise support means for writing data of a first contiguous bit set representing a second element of the vector to the first plane and writing data of a second contiguous bit set representing the second element of the vector to the second plane, at least in part based on the selected vector mapping scheme.

[0118] In some instances, the receiving circuitry 725 may be configured or otherwise supported to provide means for receiving, at the device, signaling of an instruction set indicating a first vector and a second vector as operands for a computational operation. In some instances, the logic 730 may be configured or otherwise supported to provide means for selecting, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operation using associative processing. In some instances, the access circuitry 735 may be configured or otherwise supported to provide means for writing data representing the first vector and data representing the second vector, at least in part based on the selected vector mapping scheme, to respective plane sets comprising arrays of content-addressable memory cells.

[0119] In some instances, the receiving circuitry 725 may be configured or otherwise supported as means for receiving an indication of the selected vector mapping scheme from the host device, wherein the selected vector mapping scheme is selected at least in part based on the indication.

[0120] In some instances, logic 730 may be configured or otherwise support means for determining the number of elements in the first vector, the number of elements in the second vector, or both, wherein the selected vector mapping scheme is selected based on the number of elements in the first vector, the number of elements in the second vector, or both.

[0121] In some instances, logic 730 may be configured or otherwise support means for determining the ratio of logical operations to arithmetic operations associated with the instruction set, wherein the selected vector mapping scheme is selected based on the ratio of the logical operations to the arithmetic operations.

[0122] In some instances, the plane set is located within a tile, and the access circuitry 735 may be configured or otherwise supported to provide means for writing data of a first contiguous bit set representing an element of the first vector and data of a first contiguous bit set representing an element of the second vector to a first plane of the plane set within the tile. In some instances, the plane set is located within a tile, and the access circuitry 735 may be configured or otherwise supported to provide means for writing data of a second contiguous bit set representing an element of the first vector and data of a second contiguous bit set representing an element of the second vector to a second plane of the plane set within the tile.

[0123] In some instances, the access circuitry 735 may be configured or otherwise support means for writing data of a first contiguous bit set representing an element of the first vector and data of a first contiguous bit set representing an element of the second vector to a first plane of the plane set in the first tile. In some instances, the access circuitry 735 may be configured or otherwise support means for writing data of a second contiguous bit set representing an element of the first vector and data of a second contiguous bit set representing an element of the second vector to a second plane of the plane set in the second tile.

[0124] In some instances, logic 730 may include a receiving circuitry 725, an access circuitry 735, and a memory interface 740, as well as other components and circuitry. This logic may be included in an APM system, within an APM device, or distributed between an APM system and an APM device. Logic 730 may be configured to perform aspects of the techniques described herein, causing components of the APM system and / or the APM device to perform aspects of the techniques described herein, or both.

[0125] Figure 8 A flowchart illustrating a method 800 supporting in-memory associative processing according to an example disclosed herein is shown. Operation of method 800 may be implemented by means or components thereof as described herein. For example, operation of method 800 may be performed by reference to... Figures 1 to 7 The described APM system or APM device performs the function. In some instances, the device may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the device may use dedicated hardware to perform aspects of the described function.

[0126] At 805, the method may include receiving signaling from a host device indicating a set of instructions, the set of instructions indicating a first vector and a second vector as operands for computation operations. The operation at 805 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described receiving circuit system 725 performs the operation of 805.

[0127] At 810, the method may include selecting a vector mapping scheme from a set of vector mapping schemes for performing the computational operation using association processing. The operation at 810 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described logic 730 performs the operation of 810.

[0128] At 815, the method may include writing data representing the first vector and the second vector to a set of planes of one or more pieces, at least in part based on the selected vector mapping scheme. The operation at 815 can be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described access circuit system 735 performs the operation of 815.

[0129] In some instances, such as the device described herein, method 800 is executable. The device may include a memory die comprising a plurality of tiles, each tile including a plurality of planes, wherein each plane includes a corresponding content-addressable memory cell array. The device may also include logic coupled to the memory die and configured to cause the device to perform a method, including method 800, as described herein.

[0130] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving signaling from a host device indicating a set of instructions, the set of instructions indicating a first vector and a second vector as operands for a computational operation; selecting a vector mapping scheme from a set of vector mapping schemes for performing the computational operation using associative processing; and writing data representing the first vector and the second vector to a set of one or more planar pieces, at least in part based on the selected vector mapping scheme.

[0131] Some examples of the methods 800 and devices described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for performing the computational operation on the data representing the first vector and the second vector using associative processing; and writing data representing a third vector into the plane set, the third vector being the result of the computational operation.

[0132] Some examples of the methods 800 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for comparing data representing bits of the first vector and the second vector with memory cell bits storing a truth table indicating the result of the computation operation for various combinations of logical values, wherein the performance of the computation operation may be based at least in part on the comparison.

[0133] Some examples of the methods 800 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for receiving an indication of the selected vector mapping scheme from the host device, wherein the selected vector mapping scheme may be selected at least in part based on the indication.

[0134] Some examples of the methods 800 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining the number of elements in the first vector, the number of elements in the second vector, or both, wherein the selected vector mapping scheme may be selected based on the number of elements in the first vector, the number of elements in the second vector, or both.

[0135] Some examples of the methods 800 and devices described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for determining a ratio of logical operations to arithmetic operations associated with the instruction set, wherein the selected vector mapping scheme may be selected based on the ratio of the logical operations to the arithmetic operations.

[0136] In some instances of the method 800 and apparatus described herein, writing may include operations, features, circuitry, logic, means, or instructions for writing the data representing the first vector to a different set of columns than the set to which the data representing the second vector is written.

[0137] In some instances of the method 800 and apparatus described herein, writing may include operations, features, circuitry, logic, means, or instructions for: writing data representing different connected bit sets of elements of the first vector to different planes in the plane set; and writing data representing different connected bit sets of elements of the second vector to the different planes in the plane set.

[0138] In some instances of the method 800 and apparatus described herein, writing may include operations, features, circuitry, logic, means, or instructions for: writing data representing a first connected bit set of elements of the first vector and data representing a first connected bit set of elements of the second vector into a first plane of the plane set in the tile; and writing data representing a second connected bit set of elements of the first vector and data representing a second connected bit set of elements of the second vector into a second plane of the plane set in the tile.

[0139] In some instances of the method 800 and apparatus described herein, writing may include operations, features, circuitry, logic, means, or instructions for: writing data of a first connected bit set representing an element of the first vector and data of a first connected bit set representing an element of the second vector into a first plane of the plane set in a first tile; and writing data of a second connected bit set representing an element of the first vector and data of a second connected bit set representing an element of the second vector into a second plane of the plane set in a second tile.

[0140] In some instances of the method 800 and device described herein, the first vector and the second vector are retrieved from a memory coupled to the logic, at least in part, based on the instruction set.

[0141] Figure 9 A flowchart illustrating a method 900 supporting in-memory associative processing according to an example disclosed herein is shown. Operation of method 900 may be implemented by means or components thereof as described herein. For example, operation of method 900 may be performed by reference to... Figures 1 to 7 The described APM system or APM device performs the function. In some instances, the device may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the device may use dedicated hardware to perform aspects of the described function.

[0142] At 905, the method may include receiving signaling from a host device indicating a set of instructions, the set of instructions indicating a vector of operands for computational operations, the vector containing a plurality of elements, each having a corresponding bit length. The operation at 905 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference. Figure 7 The described receiver circuit system 725 performs the operation of 905.

[0143] At 910, the method may include writing data representing a first contiguous bit set of the plurality of elements to a first plane of the tile and writing data representing a second contiguous bit set of the at least one element to a second plane of the tile. The operation at 910 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference. Figure 7 The described access circuit system 735 performs the operation of 910.

[0144] At 915, the method may include performing the computational operation using association processing, at least partially based on writing the data representing the first connected bit set to the first plane and at least partially based on writing the data representing the second connected bit set to the second plane. The operation at 915 may be performed according to the examples disclosed herein. In some instances, it may be performed using references... Figure 7The described access circuit system 735 performs the operation of 915.

[0145] In some instances, such as the device described herein, method 900 is executable. The device may include a memory die comprising a plurality of tiles, each tile including a plurality of planes, wherein each plane includes a corresponding content-addressable memory cell array. The device may also include logic coupled to the memory die and configured to cause the device to perform a method, including method 900, as described herein.

[0146] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving signaling from a host device instructing a set of instructions, the set of instructions indicating a vector as operands for a computational operation, the vector containing multiple elements, each having a corresponding bit length, writing data representing a first contiguous bit set of at least one of the multiple elements to a first plane of the tile and writing data representing a second contiguous bit set of the at least one element to a second plane of the tile; and performing the computational operation using associative processing, at least in part based on writing the data representing the first contiguous bit set to the first plane and at least in part based on writing the data representing the second contiguous bit set to the second plane.

[0147] In some instances of the method 900 and apparatus described herein, the instruction set indicates a second vector as a second operand for the computational operation, and the method, apparatus, and non-transitory computer-readable medium may additionally include operations, features, circuitry, logic, means, or instructions for: writing data of a first contiguous bit set representing an element of the second vector to a first plane of the tile and writing data of a second contiguous bit set representing an element of the second vector to a second plane of the tile.

[0148] Some examples of the method 900 and apparatus described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for writing data of a first connected bit set representing a second element of the vector to a first plane of the tile and writing data of a second connected bit set representing the second element of the vector to a second plane of the tile.

[0149] In some instances of the method 900 and apparatus described herein, writing may include operations, features, circuitry, logic, means, or instructions for: writing the data representing the first connected bit set to a column subset of the first plane and writing the data representing the second connected bit set to a column subset of the second plane.

[0150] In some instances of the method 900 and apparatus described herein, the method, apparatus, and non-transitory computer-readable medium may additionally include operations, features, circuit systems, logic, means, or instructions for selecting the vector mapping scheme based at least in part on the fact that the number of the plurality of elements of the vector is greater than the number of rows in each of the plurality of planes.

[0151] In some instances of the methods 900 and apparatus described herein, the methods, apparatus, and non-transitory computer-readable media may additionally include operations, features, circuit systems, logic, means, or instructions for selecting the vector mapping scheme based at least in part on the association of the instruction set with a ratio of arithmetic and logical operations that may be greater than a threshold ratio.

[0152] In some instances of the method 900 and apparatus described herein, the execution may include operations, features, circuitry, logic, means, or instructions for: comparing data representing bits of the vector and bits of the second vector with addressable memory cells containing the contents of a truth table indicating the result of the computational operation for various combinations of logical values; and writing data representing a third vector, which may be the result of the computational operation, to the plane set based at least in part on the comparison.

[0153] Figure 10 A flowchart illustrating a method 1000 supporting in-memory associative processing according to an example disclosed herein is shown. Operation of method 1000 may be implemented by means or components thereof as described herein. For example, operation of method 1000 may be performed by reference to... Figures 1 to 7 The described APM system or APM device performs the function. In some instances, the device may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the device may use dedicated hardware to perform aspects of the described function.

[0154] At 1005, the method may include receiving signaling from a host device indicating a set of instructions, the set of instructions indicating a vector of operands for computational operations, the vector containing a plurality of elements, each having a corresponding bit length. The operation at 1005 can be performed according to the examples disclosed herein. In some instances, it may be performed by reference... Figure 7 The described receiving circuit system 725 performs the operation of 1005.

[0155] At 1010, the method may include writing data representing a first contiguous bit set of the plurality of elements to a first plane of a first tile and writing data representing a second contiguous bit set of the at least one element to a second plane of a second tile. The operation at 1010 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 7 The described access circuit system 735 performs the operation of 1010.

[0156] At 1015, the method may include performing the computational operation using associative processing, based at least in part on writing the data representing the first connected bit set to the first plane and at least in part on writing the data representing the second connected bit set to the second plane. The operation at 1015 can be performed according to the examples disclosed herein. In some instances, it may be performed using references... Figure 7 The described access circuit system 735 performs the operation of 1015.

[0157] In some instances, as described herein, the device can execute method 1000. The device may include a memory die comprising a plurality of tiles, each tile including a plurality of planes, wherein each plane includes a corresponding content-addressable memory cell array. The device may also include logic coupled to the memory die and configured to cause the device to execute a method, including method 1000, as described herein.

[0158] In some instances, the device as described herein may perform one or more methods, such as method 1000. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving signaling from a host device indicating a set of instructions, the set of instructions indicating a vector as operands for computational operations, the vector containing a plurality of elements, each having a corresponding bit length; writing data representing a first contiguous bit set of the plurality of elements to a first plane of a first tile and writing data representing a second contiguous bit set of the at least one element to a second plane of a second tile; and performing the computational operation using associative processing, at least in part based on writing the data representing the first contiguous bit set to the first plane and at least in part based on writing the data representing the second contiguous bit set to the second plane.

[0159] In some instances of the method 1000 and apparatus described herein, the instruction set indicates a second vector as a second operand for the computational operation, and the method, apparatus, and non-transitory computer-readable medium may additionally include operations, features, circuitry, logic, means, or instructions for: writing data of a first contiguous bit set representing elements of the second vector to a first plane of a first tile and writing data of a second contiguous bit set representing elements of the second vector to a second plane of a second tile.

[0160] Some examples of the methods 1000 and devices described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for writing data representing a first connected bit set of a second element of the vector to the first plane of the first tile and writing data representing a second connected bit set of the second element to the second plane of the second tile.

[0161] In some instances of the method 1000 and apparatus described herein, writing may include operations, features, circuitry, logic, means, or instructions for: writing the data representing the first connected bit set to a column subset of the first plane and writing the data representing the second connected bit set to a column subset of the second plane.

[0162] In some instances of the methods 1000 and apparatus described herein, the methods, apparatus, and non-transitory computer-readable media may additionally include operations, features, circuit systems, logic, means, or instructions for selecting the vector mapping scheme based at least in part on the fact that the number of the plurality of elements of the vector is greater than the number of rows in each of the plurality of planes.

[0163] In some instances of the methods 1000 and apparatus described herein, the methods, apparatus, and non-transitory computer-readable media may additionally include operations, features, circuit systems, logic, means, or instructions for selecting the vector mapping scheme based at least in part on the association of the instruction set with a ratio of arithmetic and logical operations greater than a threshold ratio.

[0164] In some instances of the method 1000 and apparatus described herein, the execution may include operations, features, circuit systems, logic, means, or instructions for: comparing data representing bits of the vector and bits of a second vector with memory cell bits storing a truth table indicating the result of the computation operation for various combinations of logic values; and writing data representing a third vector, which is the result of the computation operation, to the plane set based at least in part on the comparison.

[0165] Figure 11 A flowchart illustrating a method 1100 supporting in-memory associative processing according to an example disclosed herein is shown. Operation of method 1100 may be implemented by means of apparatus or components thereof as described herein. For example, operation of method 1100 may be performed by reference to... Figures 1 to 7 The described system 100 is executed. In some instances, the device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the device may use dedicated hardware to perform aspects of the described functions.

[0166] At 1105, the method may include receiving signaling from a host device indicating a set of instructions. The operation of 1105 can be performed according to the examples disclosed herein. In some instances, it may be performed by reference... Figure 7 The described receiving circuit system 725 performs the operation of 1105.

[0167] At 1110, the method may include selecting between a first vector mapping scheme and a second vector mapping scheme for writing vectors to the plane of the device. The operation at 1110 can be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described logic 730 is the aspect that performs the operation of 1110.

[0168] At 1115, the method may include, at least in part, writing data of a first contiguous bit set representing the elements of the vector into a first plane and writing data of a second contiguous bit set representing the elements into a second plane, based on the selected vector mapping scheme. The operation at 1115 can be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described access circuit system 735 performs the operation of 1115.

[0169] At 1120, the method may include performing the computational operation using associative processing, at least based on writing the data representing the first and second contiguous bit sets. The operation at 1120 can be performed according to the examples disclosed herein. In some instances, it may be performed by reference... Figure 7 The described access circuit system 735 performs the operation of 1120.

[0170] In some instances, as described herein, the device can perform method 1100. The device may include a host device configured to transmit signaling indicating a set of instructions that indicates a vector of operands for computational operations, the vector comprising multiple elements each having a corresponding bit length. The device may also include means coupled to the host device and configured to perform associative processing, the means comprising multiple tiles each comprising multiple planes, wherein each plane includes a corresponding array of content-addressable memory cells. The device may also include logic coupled to the means and configured to cause the means to perform the method as described herein, including method 1100.

[0171] In some instances, the device as described herein may perform one or more methods, such as method 1100. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving signaling indicating a set of instructions from a host device; selecting between a first vector mapping scheme and a second vector mapping scheme for writing vectors to a plane of the device; writing data representing a first contiguous bit set of elements of the vectors to a first plane and data representing a second contiguous bit set of elements to a second plane, at least in part based on the selected vector mapping scheme; and performing the computational operation using associative processing, at least based on the data representing the first and second contiguous bit sets.

[0172] Some examples of the methods 1100 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining a ratio of arithmetic and logical operations associated with the instruction set, at least in part based on the length of the vector of the plurality of elements, or both, wherein the selected vector mapping scheme may be selected at least in part based on the ratio, the length of the vector, or both.

[0173] In some instances of the method 1100 and apparatus described herein, the instruction set indicates a second vector as operands for the computational operation, and the method, apparatus, and non-transitory computer-readable medium may additionally include operations, features, circuitry, logic, means, or instructions for writing data of a first contiguous bit set representing elements of the second vector to the first plane and writing data of a second contiguous bit set representing elements of the second vector to the second plane, at least in part based on the selected vector mapping scheme.

[0174] Some examples of the method 1100 and apparatus described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for writing data of a first contiguous bit set representing a second element of the vector to the first plane and writing data of a second contiguous bit set representing the second element of the vector to the second plane, at least in part based on the selected vector mapping scheme.

[0175] Figure 12 A flowchart illustrating a method 1200 supporting in-memory associative processing according to an example disclosed herein is shown. Operation of method 1200 may be implemented by means of apparatus or components thereof as described herein. For example, operation of method 1200 may be performed by reference to... Figures 1 to 7 The described APM system or APM device performs the function. In some instances, the device may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the device may use dedicated hardware to perform aspects of the described function.

[0176] At 1205, the method may include receiving signaling at the device indicating a set of instructions, the set of instructions indicating a first vector and a second vector as operands for computational operations. The operation at 1205 can be performed according to the examples disclosed herein. In some instances, it may be provided by reference. Figure 7 The described receiving circuit system 725 performs the operation of 1205.

[0177] At 1210, the method may include selecting a vector mapping scheme from a set of vector mapping schemes for performing the computational operation using association processing. The operation at 1210 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described logic 730 performs the operation of 1210.

[0178] At 1215, the method may include writing data representing the first vector and data representing the second vector to plane sets, each comprising an array of content-addressable memory cells, at least in part based on the selected vector mapping scheme. The operation at 1215 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 7 The described access circuit system 735 performs the operation of 1215.

[0179] In some instances, the device as described herein may perform one or more methods, such as method 1200. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving, at the device, signaling an instruction set indicating a first vector and a second vector as operands for computational operations; selecting, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operations using associative processing; and, at least in part based on the selected vector mapping scheme, writing data representing the first vector and data representing the second vector to respective plane sets comprising arrays of content-addressable memory cells.

[0180] Some examples of the methods 1200 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for receiving an indication of the selected vector mapping scheme from a host device, wherein the selected vector mapping scheme may be selected at least in part based on the indication.

[0181] Some examples of the method 1200 and apparatus described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for determining the number of elements in the first vector, the number of elements in the second vector, or both, wherein the selected vector mapping scheme may be selected based on the number of elements in the first vector, the number of elements in the second vector, or both.

[0182] Some examples of the methods 1200 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining a ratio of logical operations to arithmetic operations associated with the instruction set, wherein the selected vector mapping scheme may be selected based on the ratio of the logical operations to the arithmetic operations.

[0183] In some instances of the method 1200 and apparatus described herein, the plane set may be located in a tile, and the method, apparatus, and non-transitory computer-readable medium may additionally include operations, features, circuitry, logic, means, or instructions for: writing data representing a first connected bit set of elements of the first vector and data representing a first connected bit set of elements of the second vector into a first plane of the plane set in the tile; and writing data representing a second connected bit set of elements of the first vector and data representing a second connected bit set of elements of the second vector into a second plane of the plane set in the tile.

[0184] In some instances of the method 1200 and apparatus described herein, the method, apparatus, and non-transitory computer-readable medium may additionally include operations, features, circuit systems, logic, means, or instructions for: writing data representing a first connected bit set of elements of the first vector and data representing a first connected bit set of elements of the second vector into a first plane of the plane set in a first tile; and writing data representing a second connected bit set of elements of the first vector and data representing a second connected bit set of elements of the second vector into a second plane of the plane set in a second tile.

[0185] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0186] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, signals may represent buses of signals, which may have various bit widths.

[0187] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0188] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0189] Two or more actions may be performed "in parallel" if the actions are simultaneous, substantially simultaneous, occur at partially overlapping times, or occur at fully overlapping times.

[0190] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0191] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0192] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For instance, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0193] For example, the various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0194] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list followed by phrases such as "at least one of..." or "one or more of..."), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0195] Computer-readable media includes both non-transitory computer-readable storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0196] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A memory die comprising multiple dies, each of the multiple dies comprising multiple planes, wherein each plane comprises a corresponding content-addressable memory cell array; and Logic, which is coupled to the memory die and configured to: Receive signaling from the host device indicating a set of instructions, the set of instructions indicating a first vector and a second vector as operands for computation operations; Select a vector mapping scheme from the set of vector mapping schemes for performing the computational operation using association processing; and Based at least in part on the selected vector mapping scheme, data representing the first vector and the second vector are written into a planar set of one or more tiles.

2. The device according to claim 1, wherein the logic is further configured to: The computational operation is performed on the data representing the first vector and the second vector using association processing; and The data representing the third vector is written into the plane set, where the third vector is the result of the computation operation.

3. The device according to claim 2, wherein the logic is further configured to: Data representing bits of the first and second vectors are compared with memory cell bits storing a truth table indicating the result of the computation operation for various combinations of logical values, wherein the computation operation is performed at least in part based on the comparison.

4. The device according to claim 1, wherein the logic is further configured to: The host device receives an indication of the selected vector mapping scheme, wherein the selected vector mapping scheme is selected at least in part based on the indication.

5. The device according to claim 1, wherein the logic is further configured to: The number of elements in the first vector, the number of elements in the second vector, or both are determined, wherein the selected vector mapping scheme is selected based on the number of elements in the first vector, the number of elements in the second vector, or both.

6. The device of claim 1, wherein the logic is further configured to: Determine the ratio of logical operations to arithmetic operations associated with the instruction set, wherein the selected vector mapping scheme is chosen based on the ratio of logical operations to arithmetic operations.

7. The device of claim 1, wherein the writing further includes the logic configured to: The data representing the first vector is written to a column set that is different from the column set to which the data representing the second vector is written.

8. The device of claim 1, wherein the writing further includes the logic configured to: Write data representing different contiguous bit sets of elements of the first vector into different planes of the plane set; and Data representing different connected bit sets of elements of the second vector are written into the different planes of the plane set.

9. The device of claim 1, wherein the plane set is located in one of the plurality of tiles, and wherein the writing further includes the logic configured to: The data of the first contiguous bit set representing the elements of the first vector and the data of the first contiguous bit set representing the elements of the second vector are written into the first plane of the plane set in the mosaic; and The data of the second connected bit set representing the element of the first vector and the data of the second connected bit set representing the element of the second vector are written into the second plane of the plane set in the puzzle.

10. The device of claim 1, wherein the writing further includes the logic configured to: The data of the first contiguous bit set representing the elements of the first vector and the data of the first contiguous bit set representing the elements of the second vector are written into the first plane of the plane set in the first piece; and The data of the second connected bit set representing the element of the first vector and the second connected bit set representing the element of the second vector are written into the second plane of the plane set in the second puzzle.

11. The device of claim 1, wherein the logic is further configured to: The first vector and the second vector are retrieved from the memory coupled to the logic, based at least in part on the instruction set.

12. An apparatus comprising: A memory die comprising multiple dies, each of the multiple dies comprising multiple planes, wherein each plane comprises a corresponding content-addressable memory cell array; and Logic, which is coupled to the memory die and configured to: Receive signaling from the host device indicating a set of instructions, the set of instructions indicating a vector of operands for computation operations, the vector comprising multiple elements each having a corresponding bit length; Data representing a first connected bit set of at least one of the plurality of elements is written to the first plane of the puzzle, and data representing a second connected bit set of the at least one element is written to the second plane of the puzzle; and The computational operation is performed using association processing, based at least in part on writing the data representing the first connected bit set to the first plane and at least in part on writing the data representing the second connected bit set to the second plane.

13. The apparatus of claim 12, wherein the instruction set indicates a second vector as a second operand for the computational operation, and wherein the logic is further configured to: Data representing the first connected bit set of the elements of the second vector is written into the first plane of the puzzle, and data representing the second connected bit set of the elements of the second vector is written into the second plane of the puzzle.

14. The device of claim 12, wherein the logic is further configured to: Data representing the second element of the vector is written into the first plane of the puzzle, and data representing the second element of the vector is written into the second plane of the puzzle.

15. The device of claim 12, wherein the writing logic is further configured to: The data representing the first connected bit set is written to a column subset of the first plane, and the data representing the second connected bit set is written to a column subset of the second plane.

16. The device of claim 12, wherein the writing is based on a vector mapping scheme, and wherein the logic is further configured to: The vector mapping scheme is selected based at least in part on the fact that the number of the plurality of elements of the vector is greater than the number of rows in each of the plurality of planes.

17. The device of claim 12, wherein the writing is based on a vector mapping scheme, and wherein the logic is further configured to: The vector mapping scheme is selected based at least in part on the ratio of the instruction set to arithmetic and logical operations that are greater than a threshold ratio.

18. The device of claim 12, wherein the execution of the logic is further configured to: The data representing the bits of the first vector and the bits of the second vector are compared with memory cell bits storing a truth table indicating the result of the computation operation for various combinations of logical values; and Based at least in part on the comparison, data representing a third vector is written into the first plane and the second plane, the third vector being the result of the computation operation.

19. An apparatus comprising: A memory die comprising multiple dies, each of the multiple dies comprising multiple planes, wherein each plane comprises a corresponding content-addressable memory cell array; and Logic, which is coupled to the memory die and configured to: Receive signaling from the host device indicating a set of instructions, the set of instructions indicating a vector of operands for computation operations, the vector comprising multiple elements each having a corresponding bit length; Data representing a first connected bit set of at least one of the plurality of elements is written to the first plane of the first tile and data representing a second connected bit set of the at least one element is written to the second plane of the second tile; and The computational operation is performed using association processing, based at least in part on writing the data representing the first connected bit set to the first plane and at least in part on writing the data representing the second connected bit set to the second plane.

20. The apparatus of claim 19, wherein the instruction set indicates a second vector as a second operand for the computational operation, and wherein the logic is further configured to: Data representing the first connected bit set of the elements of the second vector is written to the first plane of the first piece, and data representing the second connected bit set of the elements of the second vector is written to the second plane of the second piece.

21. The device of claim 19, wherein the logic is further configured to: Data representing the second element of the vector is written to the first plane of the first piece and data representing the second element of the second piece is written to the second plane of the second piece.

22. The device of claim 19, wherein the writing logic is further configured to: The data representing the first connected bit set is written to a column subset of the first plane, and the data representing the second connected bit set is written to a column subset of the second plane.

23. The device of claim 19, wherein the writing is based on a vector mapping scheme, and wherein the logic is further configured to: The vector mapping scheme is selected based at least in part on the fact that the number of the plurality of elements of the vector is greater than the number of rows in each of the plurality of planes.

24. The device of claim 19, wherein the writing is based on a vector mapping scheme, and wherein the logic is further configured to: The vector mapping scheme is selected based at least in part on the ratio of the instruction set to arithmetic and logical operations that are greater than a threshold ratio.

25. The device of claim 19, wherein the execution of the logic is further configured to: The data representing the bits of the first vector and the bits of the second vector are compared with memory cell bits storing a truth table indicating the result of the computation operation for various combinations of logical values; and Based at least in part on the comparison, data representing a third vector is written into the first plane and the second plane, the third vector being the result of the computation operation.

26. An apparatus comprising: A host device configured to transmit signaling of an instruction set indicating a vector of operands for computation operations, the vector comprising multiple elements each having a corresponding bit length; A device coupled to the host device and configured to perform association processing, the device comprising multiple tiles, each comprising multiple planes, wherein each plane comprises a corresponding content-addressable memory cell array. and Logic, which is coupled to the device and configured to: Receive the signaling indicating the instruction set from the host device; A choice is made between a first vector mapping scheme and a second vector mapping scheme for writing vectors onto the plane of the device. Based at least in part on the selected vector mapping scheme, data representing a first contiguous bit set of elements of the vector is written into a first plane and data representing a second contiguous bit set of elements is written into a second plane; and The computational operation is performed using association processing, based at least on the data representing the first and second connected bit sets.

27. The device of claim 26, wherein the logic is further configured to: Determine the ratio of arithmetic and logical operations associated with the instruction set, at least in part based on the length of the vector of the plurality of elements, or both, wherein the selected vector mapping scheme is selected at least in part based on the ratio, the length of the vector, or both.

28. The apparatus of claim 26, wherein the instruction set indicates a second vector as operands for the computational operation, wherein the logic is further configured to: Based at least in part on the selected vector mapping scheme, data of a first contiguous bit set representing the elements of the second vector is written into the first plane and data of a second contiguous bit set representing the elements of the second vector is written into the second plane.

29. The device of claim 26, wherein the logic is further configured to: Based at least in part on the selected vector mapping scheme, data of a first contiguous bit set representing a second element of the vector is written into the first plane and data of a second contiguous bit set representing a second element of the vector is written into the second plane.

30. A method comprising: At the device, a signaling instruction set is received, the instruction set indicating a first vector and a second vector as operands for computational operations; Select a vector mapping scheme from the set of vector mapping schemes for performing the computational operation using association processing; and Based at least in part on the selected vector mapping scheme, data representing the first vector and data representing the second vector are written to their respective plane sets comprising content-addressable memory cell arrays.

31. The method of claim 30, further comprising: The host device receives an indication of the selected vector mapping scheme, wherein the selected vector mapping scheme is selected at least in part based on the indication.

32. The method of claim 30, further comprising: Determine the number of elements in the first vector, the number of elements in the second vector, or both, wherein the selected vector mapping scheme is selected based on the number of elements in the first vector, the number of elements in the second vector, or both.

33. The method of claim 30, further comprising: Determine the ratio of logical operations to arithmetic operations associated with the instruction set, wherein the selected vector mapping scheme is chosen based on the ratio of logical operations to arithmetic operations.

34. The method of claim 30, wherein the planar set is in a mosaic, the method further comprising: The data of the first contiguous bit set representing the elements of the first vector and the data of the first contiguous bit set representing the elements of the second vector are written into the first plane of the plane set in the mosaic; and The data of the second connected bit set representing the element of the first vector and the data of the second connected bit set representing the element of the second vector are written into the second plane of the plane set in the puzzle.

35. The method of claim 30, further comprising: The data of the first contiguous bit set representing the elements of the first vector and the data of the first contiguous bit set representing the elements of the second vector are written into the first plane of the plane set in the first piece; and The data of the second connected bit set representing the element of the first vector and the data of the second connected bit set representing the element of the second vector are written into the second plane of the plane set in the second piece.

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