A general multi-master parallel on-chip bus supporting x86 architecture

Abstract

The application discloses a general multi-master parallel on-chip bus supporting X86 architecture and belongs to the field of data transmission buses. The general on-chip bus supports parallel data transmission between multiple master processing devices and multiple slave devices, supports IO and memory space access, multiple priority arbitration strategies, multiple waiting states, an on-chip shared address multi-path data (SAMD) topology structure and three-state multiplexing of a bus data external interface, read and write data are multiplexed, and PPGA pin resources are saved. Through testing and simulation, a general IP core is formed, can be applied in different EDA development tools and development environments, has strong generalization, can effectively avoid repeated work, improve work efficiency, and further reduce research and development cost and research and development time.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of data transmission bus, and more particularly relates to a universal multi-master parallel on-chip bus supporting X86 architecture. BACKGROUND

[0002] In IC and FPGA design, on-chip communication in a shared bus mode is widely used, and on-chip bus is becoming more and more important, so on-chip transmission bus design is the most critical problem.

[0003] The transmission bus widely used at present is AXI bus IP core combination (AXI bus interface + AXI Interconnect IP) provided by Xilnx, which is contained in Vivado design suite, and it can be compatible with AMBA bus, is a multi-channel transmission bus, and is an on-chip bus facing high performance, high bandwidth and low delay.

[0004] However, the bus only supports the AMBA special AXI interface proposed by ARM Company, provides a development environment of bundled special IP core with EDA tools, and cannot support other types of CPUs such as X86 architecture bus and other development environments. Meanwhile, in the arbitration mechanism, the decision strategy is relatively single; only memory access mode; read and write data are separated, and occupy valuable pin resources of PPGA. SUMMARY

[0005] In view of the defects of the prior art, the purpose of the present application is to provide a universal multi-master parallel on-chip bus supporting X86 architecture, which aims to solve the problem that the existing bus cannot support other types of CPUs such as X86 architecture bus and other development environments.

[0006] To achieve the above purpose, the present application provides a universal multi-master parallel on-chip bus supporting X86 architecture, which is realized based on IP core mode, supports multi-master device access, bus interface multiplexing and multiple priority decision strategies, and comprises a master device interface unit, a slave device interface unit, a bus arbitrator, a logic control unit, an address router, a read data router, a write data router, a control signal router, an address channel, a read data channel, a write data channel and a control signal channel.

[0007] The master device interface unit is used for receiving addresses, data and control signals sent by the master device, and sending them to the logic control unit and the corresponding router, respectively, and the data transceiving is multiplexed in the same pin.

[0008] The slave device interface unit is used for receiving addresses, data and control signals sent by the logic control unit, and sending them to the slave device, and the data transceiving is multiplexed in the same pin.

[0009] The bus arbiter is configured to determine that the master device with the highest priority obtains the control right of the bus, and ensure that only one bus master device initiates bus transmission at a time.

[0010] The logic control unit is configured to generate timing logic signals according to the master device address, the control signal, the response signal of the slave device and the bus arbiter signal, to control other units.

[0011] The address router is configured to select the address signal of the master device with the highest priority and send the address signal to the address channel.

[0012] The read data router is configured to select the data signal of the corresponding slave device and send the data signal to the read data channel.

[0013] The write data router is configured to select the data signal of the master device with the highest priority and send the data signal to the write data channel.

[0014] The control signal router is configured to select the control signal of the master device with the highest priority and send the control signal to the control signal channel.

[0015] The address channel is configured to carry the address information of the on-chip bus.

[0016] The read data channel is configured to carry the data information of the slave device of the on-chip bus to the master device.

[0017] The write data channel is configured to carry the data information of the master device of the on-chip bus to the slave device.

[0018] The control signal channel is configured to carry the control signal of the on-chip bus, including IO read / write, memory read / write, bus ready, bus busy.

[0019] Preferably, the bus arbiter comprises a serial priority, specifically, the bus grant signal is transmitted from one device to the next device in series, if the arrived device has no bus request, the next device is queried, if the arrived device has a bus request, the next device is not queried, and the device obtains the control right of the bus.

[0020] Preferably, the bus arbiter comprises a parallel priority mode, specifically, the logic control unit and the arbiter combine the master device request line and the bus grant line, when the device requests the bus access, the request signal of the device is generated, the arbitration circuit of the arbiter determines which device request is responded preferentially, and the device is sent the grant signal.

[0021] Preferably, the logic control unit implements the control of the IO read operation in the following manner:

[0022] The bus master device initiates the IO read operation.

[0023] The address, control signal, read transmission direction and data width of the master device obtaining the bus control right are sent to the address channel and control signal channel to form an effective address and IO read signal through the logic control unit and corresponding router.

[0024] The selected slave device sends the effective data to the read data channel through the read data router after address decoding, and sets the data ready signal to low, indicating that the data is ready, so that the master device can read the data on the read data channel. If the data ready signal is high, it indicates that the data is not ready, so that the master device is in a waiting state.

[0025] Preferably, the logic control unit controls the IO write operation in the following way:

[0026] The bus master initiates an IO write operation;

[0027] The address, control signal, write transmission direction and data width of the master device obtaining the bus control right are sent to the address channel and control signal channel to form an effective address and IO write signal through the logic control unit and corresponding router.

[0028] The selected slave device sends the effective data to the write data channel through the write data router after address decoding.

[0029] After the slave device receives the write data, it sets the data ready signal to low to inform the master device that the data has been received and the next transmission can be performed. If the data ready signal is high, it indicates that the data has not been received, so that the master device is in a waiting state.

[0030] Preferably, the logic control unit controls the memory read operation in the following way:

[0031] The bus master initiates a memory read operation;

[0032] The address, control signal, read transmission direction and data width of the master device obtaining the bus control right are sent to the address channel and control signal channel to form an effective address and memory read signal through the logic control unit and corresponding router.

[0033] The selected slave device sends the effective data to the read data channel through the read data router after address decoding, and sets the data ready signal to low, indicating that the data is ready, so that the master device can read the data on the read data channel. If the data ready signal is high, it indicates that the data is not ready, so that the master device is in a waiting state.

[0034] Preferably, the logic control unit controls the memory write operation in the following way:

[0035] The bus master initiates a memory write operation;

[0036] The address, control signal, write transmission direction and data width of the master device obtaining the bus control right are sent to the address channel and control signal channel to form effective address and memory write signal through the logic control unit and the corresponding router;

[0037] The selected slave device sends effective data to the write data channel through the write data router through address decoding, and the slave device sets the data ready signal to low after receiving the write data, to inform the master device that the data has been received and the next transmission can be performed; if the data ready signal is high, it indicates that the data has not been received, and the master device is in a waiting state.

[0038] Overall, compared with the prior art, the above technical solutions conceived by the present application have the following beneficial effects:

[0039] The present application provides a general-purpose multi-master parallel on-chip bus supporting X86 architecture, which realizes the functions of general-purpose on-chip bus such as supporting parallel data transmission between multiple master processing devices and multiple slave devices, supporting access to IO and memory space, multiple priority decision strategies, multiple waiting states, on-chip shared address multi-channel data SAMD topology, three-state multiplexing of bus data external interface, and the like. The read and write data are multiplexed, which saves PPGA pin resources. Through testing and simulation, a general-purpose IP core is formed, which can be applied in different EDA development tools and development environments, has strong universality, can effectively avoid repeated work and improve work efficiency, and further reduces research and development cost and time. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 A general-purpose multi-master parallel on-chip bus structure diagram supporting X86 architecture is provided.

[0041] Figure 2 A master device interface principle schematic diagram is provided.

[0042] Figure 3 A slave device interface principle schematic diagram is provided.

[0043] Figure 4 An address router principle schematic diagram is provided.

[0044] Figure 5 A read data router principle schematic diagram is provided.

[0045] Figure 6 A write data router principle schematic diagram is provided.

[0046] Figure 7A logical control unit principle schematic diagram provided for the embodiment of the present application.

[0047] Figure 8 A bus arbitrator principle schematic diagram provided for the embodiment of the present application.

[0048] Figure 9 A control signal router principle schematic diagram provided for the embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0050] Figure 1 A general multi-master device parallel on-chip bus structure block diagram supporting X86 architecture provided by the present application. As shown in the figure, Figure 1 the parallel on-chip bus contains: master device interface, slave device interface, address multiplexer, read data multiplexer, write data multiplexer, control signal multiplexer, address channel, read data channel, write data channel, control signal channel, control logic unit and bus arbitrator and other units.

[0051] Bus transmission is initiated by a master device, and multiple master devices can simultaneously access the same slave device. The bus arbitrator determines the master device with high priority to obtain the bus control right, and ensures that only one bus master device initiates bus transmission each time. The master device that obtains the authorization sends address, control signal, transmission direction (read or write), and data width. The bus uniformly plans the address of the slave device. The logical control unit determines which slave device communicates data with the master device according to the address, control signal, etc. After the slave device receives the data, it sends a ready signal to tell the host that the data has been received (host write) and the data is ready (host read). If the data is not ready, the master device is notified to wait. There are two states including no waiting and waiting.

[0052] Serial priority mode: the bus authorization signal is transmitted from one device to the next device in series. If the arrived device has no bus request, it continues to query down. If there is a bus request, it will no longer query down, and the device obtains the bus control right. Only a few lines are needed to access the bus according to a certain priority, which is relatively easy to expand, and is suitable for systems with fewer master devices.

[0053] Parallel priority mode: the logic control unit, arbitrator combination master device request line and bus authorization line, when the device requests bus access, the device request signal is generated, the arbitration circuit of the arbitrator decides which device request to respond first, and sends the authorization signal to the device. Fast response time, less time to determine the priority of the device, no need to query one by one. In addition, the priority control is relatively flexible, which can be fixed or changed by software.

[0054] IO read operation is initiated by the bus master device. The master device that obtains bus control sends address, control signal, transmission direction (read or write), data width, etc. After passing through the logic control unit, router, etc., the effective address, IO read signal is formed in the address channel, control signal channel, and the selected slave device sends the effective data to the read data channel through the read data router. The slave device sets the data ready signal to low, indicating that the data is ready, and the master device can read the data on the read data channel. If the data ready signal is high, it means that the data is not ready, and the master device is in a waiting state.

[0055] IO write operation is initiated by the bus master device. The master device that obtains bus control sends address, control signal, transmission direction (read or write), data width, etc. After passing through the logic control unit, router, etc., the effective address, IO write signal is formed in the address channel, control signal channel, and the selected slave device sends the effective data to the write data channel through the write data router. After the slave device receives the write data, it sets the data ready signal to low, notifying the master device that the data has been received and the next transmission can be performed. If the slave device sets the data ready signal to high, it means that the data has not been received, and the master device is in a waiting state.

[0056] Memory read operation is initiated by the bus master device. The master device that obtains bus control sends address, control signal, transmission direction (read or write), data width, etc. After passing through the logic control unit, router, etc., the effective address, memory read signal is formed in the address channel, control signal channel, and the selected slave device sends the effective data to the read data channel through the read data router. The slave device sets the data ready signal to low, indicating that the data is ready, and the master device can read the data on the read data channel. If the data ready signal is high, it means that the data is not ready, and the master device is in a waiting state.

[0057] Memory write operation is initiated by bus master. The master that gets the bus control sends address, control signal, transmission direction (read or write), data width, etc. to the logic control unit, router, etc. After the logic control unit, router, etc., the effective address, memory write signal is formed in the address channel, control signal channel. The selected slave device sends the effective data to the write data channel through the write data router. After the slave device receives the write data, it sets the data ready signal to low, informing the master that the data has been received and the next transmission can be performed. If the data ready signal of the slave device is high, it indicates that the data has not been received, and the master is in a waiting state.

[0058] The master interface unit includes address, control signal, data signal buffers, which receive the address, data and control signal sent by the master, and are sent to the control logic and other routers, respectively. Among them, the data signal sent by the master is a tri-state interface.

[0059] The slave interface includes address, control signal, data signal buffers, which receive the address, data and control signal sent by the address channel, read data channel, write data channel, control signal channel and logic control unit, and are sent to the slave device. Among them, the data signal output to the slave device is a tri-state interface.

[0060] The function of the bus arbiter is to ensure that only one master controls the bus and initiates data transmission at a time, and to allow a certain master to control access to the bus at a certain time. The bus arbiter includes two priority modes: serial priority and parallel priority mode.

[0061] The logic control unit generates timing logic signals to control other units according to the master address, control signal, slave response signal and arbiter signal, including master-slave interface data gating control, address data multiplexing control, arbiter control and bus control signal, which determines which slave device to select through the unit.

[0062] Through the address router, the address signal of the master with the highest priority is selected and sent to the address channel.

[0063] Through the read data router, the corresponding slave data signal is selected and sent to the read data channel.

[0064] Through the write data router, the data signal of the master with the highest priority is selected and sent to the write data channel.

[0065] Through the control signal router, the control signal of the master with the highest priority is selected and sent to the control signal channel.

[0066] The address channel carries the address information of the on-chip bus.

[0067] The read data channel carries the data information from the slave device to the master device in the on-chip bus.

[0068] Write data channel carries data information from master to slave in the chip.

[0069] Control signal channel carries control signals such as IO read / write, memory read / write, bus ready, bus busy, etc.

[0070] Embodiment

[0071] This embodiment takes two masters and two slaves as an example, including two master interfaces 1 and 2, two slave interfaces 3 and 4, an address router 5, a write data router 6, a control logic 7, an arbiter 8, a control signal router 9, a read data router 10, an address channel 11, a read data channel 12, a write data channel 13, a control signal channel, etc.

[0072] Figure 2 The master interface principle diagram provided by the embodiment of the application is shown in Fig. 1. Figure 2 As shown in Fig. 1, the master interface 1, 2 performs the following steps:

[0073] Step 101: The master interface address latch receives the address MAx【0:31】 from the master, and the output MADDx【0:31】 signal of the address latch is sent to the address router 5 and the control logic 7, and the control logic 7 generates the enable signal LMAx of the address latch.

[0074] Step 102: The master interface data buffer receives the write data MDx【0:31】 from the master, and the output signal MWDx【0:31】 of the buffer is sent to the write data router 6, or receives the data MRDx【0:31】 from the slave sent by the read data router 10, and the data is sent to the master through the master interface data buffer. The control logic 7 generates the enable signal and the direction signal LMDx of the address buffer.

[0075] Step 103: The master interface control signal buffer buffers the control signals such as IO and memory read / write signal MMIO, data command control signal MDCx, address enable signal MALEx, clock signal MCLKx, reset signal MRESETx, etc., and then sends MCON to the control logic 7. The data ready signal MRDYx and the interrupt signal MINTRx are generated by the control logic 7 and sent to the master through the buffer.

[0076] Step 104: The address buffer, data buffer and control signal buffer of the master interface 2 are basically the same as those of the master interface 1, and are not described here.

[0077] Figure 3 The slave interface principle diagram provided by the embodiment of the application is shown in Fig. 2. Figure 3As shown, the slave interface 3, 4 performs the following steps:

[0078] Step 101: The slave interface 3, 4 receives the address CADDx【0:31】 sent from the address channel 11, and the address buffer outputs the SAx【0:31】 signal to the slave device. The control logic 7 generates the enable signal LSAx of the address buffer.

[0079] Step 102: The slave interface 3, 4 receives the write data CWDx【0:31】 sent from the write data channel 13, and the data buffer outputs the SDx【0:31】 signal to the slave device, or receives the data SDx【0:31】 sent from the slave device, and the data buffer outputs the SRDx【0:31】 signal to the read data router 10. The control logic 7 generates the direction and enable signal LSDx of the data buffer.

[0080] Step 103: The slave interface 3, 4 receives the control signals of the control signal channel 14, such as the io read / write signal, the memory read / write signal, the clock signal, the reset signal, the byte enable signal, etc. After buffering, the control signal buffer outputs the read / write signal SIORDx / SIOWRx, the memory read / write signal SMRDx / SMWRx, the clock signal SCLKx, the reset signal SRESETx, the byte enable signal SBEx to the slave device. The slave device's data ready signal SRDYx, the interrupt signal SINTx, etc. are outputted by the buffer and sent to the control signal channel 14.

[0081] Step 104: The address buffer, the data buffer, and the control signal buffer of the slave interface 4 are basically the same as those of the slave interface 3, and are not described here.

[0082] Figure 4 The principle schematic diagram of the address router provided by the embodiment of the present application is shown in Fig. 3. Figure 4 As shown, the address router 5 performs the following steps:

[0083] Step 101: The address router 5 receives the address signal MADD1【0:31】 of the master interface 1 and the address signal MADD2【0:31】 of the master interface 2.

[0084] Step 102: The address router 5 receives the control signal LA outputted by the control logic 7, and sends the address signal CADD【0:31】 with higher priority to the address channel 11.

[0085] Figure 5 The principle schematic diagram of the read data router provided by the embodiment of the present application is shown in Fig. 4. Figure 5 As shown, the read data router 10 performs the following steps:

[0086] Step 101: Read data router 10 receives read data SRD1【0:31】 from device interface 3, read data SRD2【0:31】 from device interface 31.

[0087] Step 102: Read data router 10 receives control signal LRD outputted by control logic 7, and sends slave read data signal CRD【0:31】 to read data channel 12.

[0088] Figure 6 The principle diagram of write data router provided by the embodiment of the present application is shown in Fig. 3. As shown in Fig. 3, write data router 6 performs the following steps: Figure 6

[0089] Step 101: Write data router 6 receives write data MWD1【0:31】 from master interface 1, and write data MWD2【0:31】 from master interface 2.

[0090] Step 102: Write data router 6 receives control signal LWD outputted by control logic 7, and sends master write data signal CWD【0:31】 to write data channel 13.

[0091] Figure 7 The principle diagram of logic control unit provided by the embodiment of the present application is shown in Fig. 4. As shown in Fig. 4, control signal 7 performs the following steps: Figure 7

[0092] Step 101: Control logic 7 receives address signal MADDx【0:31】 sent by master interface 1 and 2 respectively.

[0093] Step 102: Control logic 7 receives control signal MCONxx sent by master interface 1 and 2 respectively, including io, memory read / write signal MIO, data command control signal D / C, byte enable signal MBEx, global clock signal MCLK, reset signal MRESET and other signals.

[0094] Step 103: Control logic 7 receives bus busy signal CBUSY, data ready signal CRDY, interrupt signal CINT and other signals of control signal channel 14.

[0095] Step 104: Control logic 7 receives priority control signal CPBRNx, CBPROx and other signals sent by arbitrator 8.

[0096] Step 105: Control logic 7 selects master device with high priority according to priority mode, address signal, control signal and other signals, and generates corresponding control signal LMAx, LMDx, LMCx and sends to master interface 1 and 2, and the address, data and control signal of corresponding master device are valid.

[0097] ​​Step 106: The control logic 7 generates corresponding control signals LA, LRD, LWD, LCC according to the priority level and sends them to the address router 4, the read data router 10, the write data router 6 and the control signal router 9.

[0098] Step 107: The master control signals LMxIORD, LMxIOWR, LMxMRD, LMxMWR, LMxBEx, etc. of the master with high priority are selected and transmitted to the control signal router 9.

[0099] Step 108: The arbiter control signals LBPBRNx, LBSELx, LBREQx, LBPROx, LBRDYx, etc. are generated and transmitted to the arbiter 8.

[0100] Step 109: The control logic 7 selects the corresponding slave according to the read and write command and address signal of the master, enables the data and control signal of the corresponding slave and completes the read and write operation of the slave.

[0101] Figure 8 The principle diagram of the bus arbiter provided by the embodiment of the application is shown in Fig. 1. Figure 8 As shown in Fig. 1, the bus arbiter 8 performs the following steps:

[0102] Step 101: The bus arbiter 8 reads the external state and determines whether the priority mode is serial priority or parallel priority.

[0103] Step 102: If the priority mode is serial priority, the serial priority is realized by using the daisy chain technology. The bus priority output CBPRO of each master is connected with the bus priority input BPRN of the next lower priority master. When the master with the highest priority requires to control the bus, CBPRO is set to high and the BPRN of all the masters with lower priority is prohibited. The bus arbiter 8 receives the signals LBSELx, LBRDYx, etc. sent by the control logic 7, generates CBPROx output by the state machine and the combination logic of the bus arbiter 8, and the CBPROx signal is cascaded to the next master.

[0104] Step 103: If the priority mode is parallel priority, the bus arbiter 8 receives the signals CBREQ, CBUSY, LBPRNx, LBPROx, etc. sent by the control logic 7, generates BPRNx output by the state machine and the combination logic of the bus arbiter 8, and the bus arbiter is composed of the state machine and the combination logic. The priority logic determines the next master and it ensures that only the master with the highest priority is valid and supports the decision of the priority of multiple masters. CBREQ0-CBREQn corresponds to BPRN0-BPRNn. The order of the parallel priority is BREQn to BREQ0 in turn. BREQn is the highest and BREQ0 is the lowest.

[0105] Figure 9 The principle diagram of the control signal router is provided for the embodiment of the present application. As shown in the figure, the control signal router 9 performs the following steps: Figure 9

[0106] Step 101: The control signal router 9 receives the memory, IO signal read-write signals LMxIORD, LMxIOWR, LMxMRD, LMxMWR, bus busy signal LMxBUSY, byte enable signal LMBEx, clock signal LMxCLK, reset signal LMxRESET of the control logic 7 and other signals.

[0107] Step 102: The control signal router 9 receives the data ready LSxRDY and interrupt signal LSxINT of the slave device from the control signal channel 14.

[0108] Step 103: The control signal router 9 receives the control signals of the control logic 7 and sends the memory, IO signal read-write signals CIORD, CIOWR, CMRD, CMWR, CINT, CBUSY, CCLK, CRESET, CBEx of the master device with higher priority to the control signal channel 14.

[0109] Step 104: The control signal router 9 receives the bus busy signal LMxBUSY of the control logic 7 and outputs it to the control signal channel 14, indicating that the master device with higher priority occupies the bus. Meanwhile, the bus busy signal of the control signal channel 14 is fed back to the control logic 7, so that the master device with lower priority is in the waiting state.

[0110] Those skilled in the art will easily understand that the above description is only the preferred embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.​

Claims

1. A general-purpose multi-master parallel on-chip bus supporting X86 architecture, characterized in that, The in-chip bus is realized based on an IP core mode, supports multi-master device access, bus interface multiplexing and multiple priority arbitration strategies, and comprises a master device interface unit, a slave device interface unit, a bus arbitrator, a logic control unit, an address router, a read data router, a write data router, a control signal router, an address channel, a read data channel, a write data channel and a control signal channel. The master device interface unit is configured to receive address, data and control signals sent by a master device, and send the address, data and control signals to the logic control unit and corresponding routers respectively, and multiplex data transmission and reception in a same pin. The slave device interface unit is configured to receive address, data and control signals sent by the address channel, the read data channel, the write data channel, the control signal channel and the logic control unit, and send the address, data and control signals to a slave device, and multiplex data transmission and reception in a same pin. The bus arbitrator is configured to determine that a master device with high priority obtains control right of the bus, and ensure that only one bus master device initiates bus transmission each time. The logic control unit is configured to generate timing logic signals according to master device address, control signals, slave device response signals and bus arbitrator signals, to control other units. The address router is configured to select address signals of a master device with the highest priority to send to the address channel. The read data router is configured to select corresponding slave device data signals to send to the read data channel. The write data router is configured to select data signals of a master device with the highest priority to send to the write data channel. The control signal router is configured to select control signals of a master device with the highest priority to send to the control signal channel. The address channel is configured to carry in-chip bus address information. The read data channel is configured to carry data information of a slave device to a master device in the in-chip bus. The write data channel is configured to carry data information of a master device to a slave device in the in-chip bus. The control signal channel is configured to carry in-chip bus control signals, including IO read / write, memory read / write, bus ready and bus busy.

2. The on-chip bus of claim 1, wherein, The bus arbitrator comprises a serial priority, specifically, bus authorization signals are transmitted from one device to the next device in series, if the arrived device has no bus request, the next device is queried, if there is a bus request, the next device is not queried, and the device obtains control right of the bus.

3. The on-chip bus of claim 1, wherein, The bus arbitrator comprises a parallel priority mode, specifically, a logic control unit and an arbitrator combine a master device request line and a bus authorization line, when the device requests bus access, the request signal of the device is generated, and the arbitration circuit of the arbitrator determines which device request is responded first, and sends an authorization signal to the device.

4. The on-chip bus of claim 1, wherein, The logic control unit realizes control of an IO read operation in the following manner: A bus master device initiates an IO read operation; Address, data and control signals of the master device obtaining control right are sent to the address channel and the control signal channel after the logic control unit and corresponding routers, and effective address and IO read signals are formed in the address channel and the control signal channel. After address decoding, the selected slave device sends valid data to the read data channel through the read data router, and the data ready signal of the slave device is low, indicating that the data is ready, and the master device can read the data on the read data channel. If the data ready signal is high, it indicates that the data is not ready, and the master device is in a waiting state.

5. The on-chip bus of claim 1, wherein, The logic control unit realizes the control of IO write operation in the following way: The bus master initiates IO write operation; The logic control unit, the corresponding router, the address channel, and the control signal channel form valid address and IO write signal. After address decoding, the selected slave device sends valid data to the write data channel through the write data router. After receiving the write data, the slave device sets the data ready signal to low, notifying the master device that the data has been received and the next transmission can be performed. If the data ready signal is high, it indicates that the data has not been received, and the master device is in a waiting state.

6. The on-chip bus of claim 1, wherein, The logic control unit realizes the control of memory read operation in the following way: The bus master initiates memory read operation; The logic control unit, the corresponding router, the address channel, and the control signal channel form valid address and memory read signal. After address decoding, the selected slave device sends valid data to the read data channel through the read data router, and the data ready signal of the slave device is low, indicating that the data is ready, and the master device can read the data on the read data channel. If the data ready signal is high, it indicates that the data is not ready, and the master device is in a waiting state.

7. The on-chip bus of claim 1, wherein, The logic control unit realizes the control of memory write operation in the following way: The bus master initiates memory write operation; The logic control unit, the corresponding router, the address channel, and the control signal channel form valid address and memory write signal. After address decoding, the selected slave device sends valid data to the write data channel through the write data router. After receiving the write data, the slave device sets the data ready signal to low, notifying the master device that the data has been received and the next transmission can be performed. If the data ready signal is high, it indicates that the data has not been received, and the master device is in a waiting state.

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