stream engine with multi-dimensional cyclic addressing selectable in each dimension
By introducing streaming engine technology into digital signal processors, memory bandwidth and scheduling issues were resolved, memory access was optimized, and the efficiency and reliability of real-time data processing were improved.
Patent Information
- Application Number
- CN202211511073.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2016-12-20
- Filing Date
- 2017-12-20
- Publication Date
- 2026-05-12
- Estimated Expiration
- 2037-12-20
AI Technical Summary
Modern digital signal processors face memory bandwidth and scheduling issues when processing real-time data. In particular, they struggle to effectively process predictable but discontinuous input data patterns when memory access resources are limited, leading to increased system latency and potential errors.
Employing stream engine technology, it generates addresses of data elements by storing fixed data stream sequences and address generators in control registers, and provides data elements to functional units using stream head registers. It supports independent addressing modes and loop block sizes for multiple nested loops, optimizing memory access.
It increases the available bandwidth of functional units, reduces cache miss pauses, reduces the number of scalar operations required to maintain loops, and improves the efficiency and reliability of real-time data processing.