Semiconductor device, electronic device and manufacturing method

Abstract

The present disclosure discloses a semiconductor device, electronic device, and preparation method. Wordline trenches are first formed on a semiconductor substrate, followed by forming a wordline structure in the wordline trenches, and then forming an active area. This allows the wordline trenches to pass through the semiconductor substrate without requiring them to pass through other materials. Because the semiconductor substrate is made of uniform material, etching selectivity issues are eliminated, allowing the bottom surface of the formed wordline trenches to be flat. When forming the wordline structure in the wordline trenches, the wordline structure can be in direct contact with the semiconductor substrate without requiring it to contact other materials. This allows the bottom surface of the wordline structure to be flat, thereby improving the performance and reliability of the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to semiconductor devices, electronic devices, and preparation methods thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It is composed of many duplicate semiconductor devices. Each semiconductor device typically includes a capacitor and a transistor. The transistor's gate is connected to a word line, its drain is connected to a bit line, and its source is connected to a capacitor. The voltage signal on the word line controls the transistor's on and off state, allowing it to read data stored in the capacitor through the bit line or write data to the capacitor for storage.

[0003] Currently, a buried wordline approach can be used to address interference between wordlines. A typical method for preparing a buried wordline involves providing a semiconductor substrate, forming shallow trench isolation regions on the semiconductor substrate to define the active area, and filling the shallow trench isolation regions with silicon oxide. A wordline trench is then etched through the active area and the silicon oxide in the shallow trench isolation regions. A buried wordline is then formed in the wordline trench. However, due to the different etching selectivities between the semiconductor substrate and silicon oxide, the etch rates of the semiconductor substrate and silicon oxide differ, resulting in uneven bottom surfaces of the wordline trenches and, in turn, an uneven bottom surface of the buried wordline, impacting the performance and reliability of the semiconductor device. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor device, an electronic device, and a manufacturing method thereof, which are used to improve the problem of uneven bottom surfaces of word line grooves, improve the flatness of the bottom surfaces of buried word lines, and improve the performance and reliability of semiconductor devices.

[0005] According to some embodiments, a first aspect of the present disclosure provides a method for manufacturing a semiconductor device, which may include the following steps:

[0006] forming a plurality of word line trenches on a semiconductor substrate; wherein the word line trenches extend along a first direction;

[0007] forming a word line structure in each of the word line trenches; wherein a top surface of the word line structure is flush with a top surface of the semiconductor substrate;

[0008] forming a plurality of active area mask structures on the top surface of the semiconductor substrate; wherein the active area mask structures define active areas in the semiconductor substrate, and the orthographic projections of the active area mask structures on the bottom surface of the semiconductor substrate extend along a second direction and pass through the orthographic projections of the word line structures on the bottom surface of the semiconductor substrate;

[0009] The word line structure and the semiconductor substrate are etched using the active area mask structure as an etching mask to form an active area and a buried word line passing through the active area.

[0010] In some possible embodiments, forming a word line structure in each of the word line trenches may include: covering the sidewalls of the word line trench with a gate dielectric layer; filling a buried word line in the word line trench formed with the gate dielectric layer; wherein the top surface of the buried word line is lower than the top surface of the semiconductor substrate; and filling an insulating layer on the buried word line in the word line trench; wherein the top surface of the insulating layer is flush with the top surface of the semiconductor substrate.

[0011] In some possible embodiments, etching the word line structure and the semiconductor substrate to form an active area and a buried word line passing through the active area may include: etching the semiconductor substrate, the insulating layer, and the gate dielectric layer in the non-mask area to expose the buried word line in the non-mask area, and making the semiconductor substrate in the non-mask area flush with the bottom surface of the buried word line; wherein the non-mask area is the area excluding the area where the mask structure of the active area is located; etching the semiconductor substrate to a set depth in the non-mask area so that the plane where the semiconductor substrate in the non-mask area is located and the plane where the bottom surface of the buried word line is located have the set depth.

[0012] In some possible embodiments, the etching of the semiconductor substrate, the insulating layer and the gate dielectric layer in the non-mask area to expose the buried word line in the non-mask area and make the etched semiconductor substrate flush with the bottom surface of the buried word line may include: using the active area mask structure as an etching mask to etch the semiconductor substrate and the insulating layer in the non-mask area to make the top surface of the semiconductor substrate in the non-mask area flush with the top surface of the buried word line; using the active area mask structure as an etching mask to etch the semiconductor substrate and the gate dielectric layer in the non-mask area to expose the buried word line in the non-mask area and make the top surface of the semiconductor substrate in the non-mask area flush with the bottom surface of the buried word line.

[0013] In some possible embodiments, exposing the buried word line in the non-mask area may specifically include: using the active area mask structure as an etching mask to etch the semiconductor substrate and the gate dielectric layer in the non-mask area to expose the buried word line in the non-mask area, and making the height of the buried word line in the non-mask area equal to the height of the buried word line in the area where the active area mask structure is located.

[0014] In some possible embodiments, exposing the buried word line in the non-mask area may specifically include: using the active area mask structure as an etching mask to etch the semiconductor substrate and the gate dielectric layer in the non-mask area to expose the buried word line in the non-mask area, and making the top surface of the semiconductor substrate in the non-mask area flush with the bottom surface of the buried word line, and making the height of the buried word line in the non-mask area equal to the height of the buried word line in the area where the active area mask structure is located; using the active area mask structure as an etching mask to etch the buried word line in the non-mask area to make the height of the buried word line in the non-mask area less than the height of the buried word line in the area where the active area mask structure is located.

[0015] In some possible implementations, after making the etched semiconductor substrate flush with the bottom surface of the buried word line and before making the plane where the etched semiconductor substrate is located and the plane where the bottom surface of the buried word line is located have the set distance, it may also include: oxidizing the semiconductor substrate between the plane where the bottom surface of the active area mask structure is located and the plane where the bottom surface of the buried word line is located, so that an oxidation protection layer is formed on the surface of the semiconductor substrate.

[0016] In some possible embodiments, etching the semiconductor substrate to a set depth in the non-mask area so that the plane where the semiconductor substrate in the non-mask area is located and the plane where the bottom surface of the buried word line is located have the set depth may include: using the active area mask structure and the buried word line as etching masks, etching the semiconductor substrate to the set depth so that the plane where the etched semiconductor substrate is located and the plane where the bottom surface of the buried word line is located have the set depth; preferentially etching the semiconductor substrate at the set depth and in the area where the buried word line is located; and etching away the semiconductor substrate after the preferential etching treatment to form a shallow trench isolation groove.

[0017] In some possible embodiments, forming a plurality of word line trenches on a semiconductor substrate may include: forming a trench mask layer covering the semiconductor substrate on the semiconductor substrate; patterning the trench mask layer to form a plurality of strip-shaped trench mask structures; and removing the semiconductor substrate at a first set distance at a gap between adjacent trench mask structures to form the plurality of word line trenches.

[0018] In some possible implementations, after forming the active area and the buried word line passing through the active area, the method may further include: depositing an isolation layer on the semiconductor substrate so that the isolation layer is flush with the top surface of the semiconductor substrate.

[0019] According to some embodiments, a second aspect of the present disclosure provides a semiconductor device obtained by the above-mentioned preparation method; the semiconductor device includes:

[0020] A semiconductor substrate having an isolation region formed by a shallow trench isolation groove and a plurality of active regions defined by the isolation region;

[0021] A plurality of buried word lines are buried in word line trenches formed by etching the semiconductor substrate, and the buried word lines are arranged to intersect with corresponding active areas.

[0022] In some possible implementations, the remaining area except the area where the active area is located is used as the non-active area, and the height of the buried word line in the non-active area is less than or equal to the height of the buried word line in the active area.

[0023] In some possible implementations, an oxidation protection layer is formed on the surface of the semiconductor substrate between a plane where a top surface of the semiconductor substrate corresponding to the active area is located and a plane where a bottom surface of the buried word line is located.

[0024] In some possible implementations, the active regions are arranged into repeating units along the third direction, and the repeating units are arranged along the first direction; wherein the active regions in every two adjacent repeating units are staggered;

[0025] Each of the buried word lines alternately passes through active areas in odd-numbered repeating units and even-numbered repeating units.

[0026] According to some embodiments, a third aspect of the present disclosure provides an electronic device comprising the above-mentioned semiconductor device.

[0027] The embodiments of the present disclosure have at least the following beneficial effects:

[0028] The semiconductor device, electronic device, and preparation method provided by the embodiments of the present disclosure are achieved by first forming a wordline trench on a semiconductor substrate, then forming a wordline structure in the wordline trench, and then forming an active area. In this way, the wordline trench can pass through the semiconductor substrate without passing through other materials. Since the material of the semiconductor substrate is uniform, there is no problem of etching selectivity, and the bottom surface of the formed wordline trench can be flat. When forming the wordline structure in the wordline trench, the wordline structure can be directly in contact with the semiconductor substrate without the need for the wordline structure to contact other materials, so that the bottom surface of the wordline structure can be flat, thereby improving the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A It is a schematic diagram of a top view of a semiconductor device in the related art;

[0030] Figure 1B yes Figure 1A A cross-sectional structural diagram of the semiconductor device shown in the AA' direction;

[0031] Figure 1C yes Figure 1A A cross-sectional structural diagram of the semiconductor device shown in the BB' direction;

[0032] Figure 2 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0033] Figure 3A Some structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiment of the present disclosure;

[0034] Figure 3B for Figure 3A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0035] Figure 4A Other structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiment of the present disclosure;

[0036] Figure 4B for Figure 4A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0037] Figure 5A Some further structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiments of the present disclosure;

[0038] Figure 5B for Figure 5A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0039] Figure 6A Some further structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiments of the present disclosure;

[0040] Figure 6B for Figure 6A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0041] Figure 7A Some further structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiments of the present disclosure;

[0042] Figure 7B for Figure 7A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0043] Figure 8A Some further structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiments of the present disclosure;

[0044] Figure 8B for Figure 8AThe cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0045] Figure 9A Some further structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiments of the present disclosure;

[0046] Figure 9B for Figure 9A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0047] Figure 9C Some further schematic top views of structures during the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0048] Figure 9D Some further schematic top views of structures during the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0049] Figure 10A Some further structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiments of the present disclosure;

[0050] Figure 10B for Figure 10A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0051] Figure 10C Some further schematic top views of structures during the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0052] Figure 11A Some further structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiments of the present disclosure;

[0053] Figure 11B for Figure 11A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0054] Figure 12A Some further structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiments of the present disclosure;

[0055] Figure 12B for Figure 12A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0056] Figure 13A Some further structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiments of the present disclosure;

[0057] Figure 13B for Figure 13A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0058] Figure 14A Some structural schematic diagrams of semiconductor devices prepared according to the embodiments of the present disclosure;

[0059] Figure 14B for Figure 14A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0060] Figure 14C Some further schematic top views of the semiconductor devices prepared according to the embodiments of the present disclosure;

[0061] Figure 15A Some further structural schematic diagrams of the process of manufacturing a semiconductor device according to the embodiments of the present disclosure;

[0062] Figure 15B for Figure 15A The cross-sectional structural diagram corresponding to the structural schematic diagram shown;

[0063] Figure 16A Some further structural schematic diagrams of semiconductor devices prepared according to the embodiments of the present disclosure;

[0064] Figure 16B for Figure 16A The structural schematic diagram shown corresponds to the sectional structural diagram. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0066] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0067] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0068] To address the interference between word lines, a buried word line 132 method can be used. Figure 1A-Figure 1C . Figure 1A It is a schematic diagram of a top view structure of a semiconductor device in related technology. Figure 1B yes Figure 1A The cross-sectional structural diagram of the semiconductor device shown is along the AA' direction. Figure 1C yes Figure 1A The schematic diagram of the cross-sectional structure of the semiconductor device shown in the BB' direction. Currently, the common method for preparing a buried word line is to provide a semiconductor substrate 10, form a shallow trench isolation region on the semiconductor substrate 10 to define an active area 13, and fill the shallow trench isolation region with silicon oxide 11. Then, a word line trench is etched in the semiconductor substrate 10 to pass through the active area and the silicon oxide in the shallow trench isolation region. Then, a buried word line 12 is formed in the word line trench. Because the word line trench not only passes through the semiconductor substrate 10 but also passes through the silicon oxide 11 in the shallow trench isolation region, and the etching selectivity of the semiconductor substrate 10 and the silicon oxide 11 is different, the etching rates of the semiconductor substrate 10 and the silicon oxide 11 are different, resulting in an uneven bottom surface of the etched word line trench, which in turn causes an uneven bottom surface of the buried word line 12, affecting the performance and reliability of the semiconductor device.

[0069] Based on this, the embodiment of the present disclosure provides a method for preparing a semiconductor device, by first forming a wordline trench 101 on a semiconductor substrate 100, then forming a wordline structure 130 in the wordline trench 101, and then forming an active area. In this way, the wordline trench 101 can pass through the semiconductor substrate 100 without the need for the wordline trench 101 to pass through other materials. Since the material of the semiconductor substrate 100 is uniform, there is no problem of etching selectivity, and the bottom surface of the formed wordline trench 101 can be flat. When forming the wordline structure 130 in the wordline trench 101, the wordline structure 130 can be in direct contact with the semiconductor substrate 100 without the need for the wordline structure 130 to contact other materials, so that the bottom surface of the wordline structure 130 can be flat. In this way, the bottom surface of the formed buried word line can also be flush, thereby improving the performance and reliability of the semiconductor device.

[0070] See also Figure 2 、 Figures 3A-14C . Figure 2 A flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure. Figures 3A-14B The schematic diagram of the structure of the semiconductor device provided by the embodiment of the present disclosure after each step is performed. The method for preparing the semiconductor device provided by the present disclosure, specifically in this embodiment, includes the following steps:

[0071] S10 , forming a plurality of word line trenches 101 on the semiconductor substrate 100 .

[0072] In some examples, the material of semiconductor substrate 100 may include silicon, germanium, or a silicon-on-insulator (SOI) semiconductor, or may include a germanium-silicon compound, silicon carbide, or other known materials, such as Group III or V compounds such as gallium arsenide. Certain dopant ions may also be implanted into semiconductor substrate 100 to modify electrical parameters based on design requirements. For example, semiconductor substrate 100 may be a silicon substrate.

[0073] In some examples, step S10, forming a plurality of word line trenches 101 on the semiconductor substrate 100, can specifically include the following steps: first, forming a trench mask layer covering the semiconductor substrate 100 on the semiconductor substrate 100. The trench mask layer can be made of one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide / nitride / oxide materials. For example, a layer of silicon nitride is deposited at a set deposition rate as a trench mask layer. In terms of the choice of deposition method, those skilled in the art can choose from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes, and the present disclosure is not limited thereto. Similarly, in terms of the choice of deposition rate and the thickness of the trench mask layer, those skilled in the art can also choose other suitable rates and thicknesses according to actual needs. It should be noted that, in the selection of the following deposition methods, those skilled in the art can also choose from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes, which will not be elaborated here.

[0074] Afterwards, see Figure 3A-Figure 3B The trench mask layer is patterned to form a plurality of strip-shaped trench mask structures 200 extending along the first direction F1. For example, a vapor phase etching process can be used to remove the trench mask layer in the region where the wordline trenches 101 are to be formed, while retaining the trench mask layer in the remaining regions to form a plurality of strip-shaped trench mask structures 200 extending along the first direction F1. This allows the gaps between adjacent trench mask structures 200 to expose the semiconductor substrate 100 in the region where the wordline trenches 101 are to be formed. For example, the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar to achieve a certain etching selectivity, thereby enabling etching of the trench mask layer.

[0075] Afterwards, see Figure 4A-4BThe semiconductor substrate 100 at a predetermined distance between adjacent trench mask structures 200 is removed to form a plurality of word line trenches 101 extending along the first direction F1. For example, a vapor phase etching process is employed, and the etching gas may be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar, to achieve a certain etching selectivity, thereby etching the semiconductor substrate 100 exposed at the gaps between adjacent trench mask structures 200. Furthermore, the semiconductor substrate 100 at the predetermined distance is etched to form the word line trenches 101.

[0076] Among them, since the semiconductor substrate 100 is etched by a vapor phase etching process, each word line trench 101 can be formed in the semiconductor substrate 100 without passing through other materials, so that the depth H1 of each word line trench 101 can be basically equal, and the bottom surface S1 of the word line trench 101 can be made as flat as possible.

[0077] It should be noted that in actual processes, due to limitations of process conditions or other factors, the bottom surface S1 of the word line trench 101 may not be completely flat and may have some deviation. Therefore, as long as the flatness of the bottom surface S1 of the word line trench 101 substantially meets the above conditions, it falls within the scope of protection of this disclosure. For example, the flatness of the bottom surface S1 of the word line trench 101 can be within the allowable error range.

[0078] Afterwards, see Figure 5A-5B , and etching away the trench mask structure 200 .

[0079] S20: forming a word line structure 130 in each word line trench 101. This allows the bottom surface of the formed word line structure 130 to be as flat as possible.

[0080] For some examples, see Figures 6A-8B The top surface of the word line structure 130 is flush with the top surface of the semiconductor substrate 100, and the bottom surface of the word line structure 130 is formed on the bottom surface S1 of the word line trench 101. In this way, the bottom surface of the word line structure 130 can be in contact with the semiconductor substrate 100. In this way, the bottom surface of the word line structure 130 can be as flat as possible.

[0081] In some examples, the wordline structure 130 may include: a gate dielectric layer 131 formed on the sidewalls of the wordline trench 101, a buried wordline 132 filled in the wordline trench 101 having the gate dielectric layer 131, and an insulating layer 133 on the buried wordline 132 filled in the wordline trench 101. Since the bottom surface of the wordline trench 101 is as flat as possible, the bottom surface of the wordline trench 101 with the gate dielectric layer attached to the sidewall is also as flat as possible. This allows the bottom surface of the buried wordline 132 to be as flat as possible, thereby reducing interference and improving the performance and reliability of the semiconductor device.

[0082] In some examples, step S20, forming a word line structure 130 in each word line trench 101, may specifically include the following steps: First, referring to Figure 6A-Figure 6B , a gate dielectric layer 131 is formed on the sidewalls of the wordline trench 101. Exemplarily, the gate dielectric layer 131 may include one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide / nitride / oxide, and a high-K dielectric material. For example, atomic layer deposition may be used to form the gate dielectric layer 131 by covering the sidewalls of the wordline trench 101 with silicon oxide.

[0083] Afterwards, see Figure 7A-7B A buried word line 132 is filled in the word line trench 101 formed with the gate dielectric layer 131, and the top surface WS1 of the buried word line 132 is lower than the top surface BS1 of the semiconductor substrate 100. Exemplarily, the material of the buried word line 132 may include one or more of Ti, TiN, Ta, TaN, W, WN, TiSiN, and WSiN. For example, a deposition process may be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes to form TiN / W in the word line trench 101. The TiN / W formed in the word line trench 101 is then etched to a desired height through an etching process to form a buried word line 132 with a top surface WS1 lower than the top surface BS1 of the semiconductor substrate 100.

[0084] Afterwards, see Figure 8A-8B, an insulating layer 133 is filled on the buried word line 132 in the word line trench 101, and the top surface of the formed insulating layer 133 is flush with the top surface BS1 of the semiconductor substrate 100. Exemplarily, the material of the insulating layer 133 may include one or a combination of two or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxynitride. For example, a deposition process can be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition, or other suitable deposition processes to form silicon nitride as the insulating layer 133 on the word line trench 101 or the semiconductor substrate 100 where the buried word line 132 is formed. Furthermore, the insulating layer 133 is etched by an etching process so that the top surface of the insulating layer 133 is flush with the top surface BS1 of the semiconductor substrate 100. Alternatively, in order to make the top surfaces of the semiconductor substrate 100 and the insulating layer 133 flat, the insulating layer 133 and the semiconductor substrate 100 may be etched so that the overall top surface of the insulating layer 133 and the semiconductor substrate 100 after etching may be as flat as possible.

[0085] S30 , forming a plurality of active region mask structures 300 on the top surface of the semiconductor substrate 100 .

[0086] For some examples, see Figures 9A-10C The active area mask structure 300 defines an active area in the semiconductor substrate 100. That is, the orthographic projection of the active area mask structure 300 on the bottom surface of the semiconductor substrate 100 overlaps with the orthographic projection of the active area on the bottom surface of the semiconductor substrate 100. In this way, when the semiconductor substrate 100 in the non-mask area is etched later, the semiconductor substrate 100 under the active area mask structure 300 can be retained to be used as the active area.

[0087] For some examples, see Figures 10A-10C The orthographic projection of the active area mask structure 300 on the bottom surface of the semiconductor substrate 100 extends along the second direction F2 and passes through the orthographic projection of the wordline structure 130 on the bottom surface of the semiconductor substrate 100. This allows the resulting active area to be passed through by the buried wordline 132 to form a transistor. The angle between the second direction F2 and the first direction F1 is greater than 0° and less than 90°. This allows the active area and the buried wordline 132 to have an angle greater than 0° and less than 90°. The angle between the active area and the buried wordline 132 can be selected by those skilled in the art based on actual needs and is not limited here.

[0088] In some examples, step S30 forms a plurality of active area mask structures 300 on the top surface of the semiconductor substrate 100, specifically comprising the following steps: First, an etching mask layer and an etching stop layer covering the semiconductor substrate 100 are formed on the semiconductor substrate 100. The etching mask layer and the etching stop layer may be made of one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide / nitride / oxide materials. Furthermore, the materials of the etching mask layer and the etching stop layer may be different based on the etching selectivity. For example, a layer of silicon nitride is deposited at a set deposition rate as an etching mask layer. Also, a layer of silicon oxide is deposited at a set deposition rate as an etching stop layer. In terms of the choice of deposition method, those skilled in the art may select from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes, but the present disclosure is not limited thereto. Similarly, regarding the selection of the deposition rate and the thickness of the etching mask layer, those skilled in the art may also select other appropriate rates and thicknesses according to actual needs.

[0089] Afterwards, see Figure 9A-9B , the etch stop layer is patterned to form a plurality of strip-shaped etch stop isolation structures 310 extending along the second direction F2. For example, a vapor phase etching process can be used to remove a portion of the etch stop layer to form a plurality of strip-shaped etch stop isolation structures 310 extending along the second direction F2. These etch stop isolation structures 310 can shield the etch mask layer corresponding to the area where the active area is to be formed, so that the gaps between adjacent etch stop isolation structures 310 can expose the area of ​​the etch mask layer that needs to be etched and removed. For example, the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar to achieve a certain etching selectivity, thereby etching the etch mask layer.

[0090] Afterwards, see Figures 9A-9C , using the strip-shaped etch barrier isolation structure 310 as an etch mask, the etch mask layer is patterned to form a plurality of strip-shaped etch mask isolation structures 320 extending along the second direction F2. For example, a vapor phase etching process can be used to remove the etch mask layer in the gaps between the etch barrier isolation structures 310, while retaining the etch mask layer in the remaining areas to form a plurality of strip-shaped etch mask isolation structures 320 extending along the second direction F2, so that the gaps between adjacent etch mask isolation structures 320 can expose the area of ​​the semiconductor substrate 100 that needs to be etched and removed. For example, the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar to achieve a certain etching selectivity, thereby etching the etch mask layer.

[0091] Afterwards, the etch barrier isolation structure 310 is patterned again to divide the strip-shaped etch barrier isolation structure 310 into a plurality of etch barrier isolation structure segments. For example, a vapor phase etching process can be used to remove the middle portion of the etch barrier isolation structure 310 to divide the strip-shaped etch barrier isolation structure 310 into two or more etch barrier isolation structure segments. Each etch barrier isolation structure segment covers a plurality of active areas. Moreover, between the etch barrier isolation structure segments in the same etch barrier isolation structure 310, the area where the etch mask layer needs to be etched and removed is exposed. For example, the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2 and Ar to achieve a certain etching selectivity ratio, so that the etch mask layer can be etched.

[0092] Afterwards, see Figures 9A-9C , using the etch barrier isolation structure segments as etching masks, the etch mask isolation structure 320 is patterned, and the strip-shaped etch mask isolation structure 320 is divided into a plurality of etch mask isolation structure segments 321. Exemplarily, a vapor phase etching process can be used to remove the etch mask layer in the gaps between the etch barrier isolation structure segments 311 in the same etch barrier isolation structure 310, while retaining the etch mask layer in the remaining areas, so as to divide the one etch mask isolation structure 320 into a plurality of etch mask isolation structure segments 321, so that the gaps between the etch mask isolation structure segments 321 in the same etch mask isolation structure 320 can expose the area of ​​the semiconductor substrate 100 that needs to be etched and removed. Exemplarily, the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar, so as to achieve a certain etching selectivity, thereby etching the etch mask layer.

[0093] Afterwards, the etch barrier isolation structure segment is patterned again to divide each etch barrier isolation structure segment into two or more etch barrier isolation structure sub-segments. For example, a vapor phase etching process can be used to remove the middle portion of the etch barrier isolation structure segment to divide the etch barrier isolation structure segment into two etch barrier isolation structure sub-segments. Each etch barrier isolation structure sub-segment covers an active area. Moreover, between the etch barrier isolation structure sub-segments in the same etch barrier isolation structure segment, the area where the etch mask layer needs to be etched and removed is exposed. For example, the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2 and Ar to achieve a certain etching selectivity, so that the etch mask layer can be etched.

[0094] Afterwards, see Figures 10A-10C, using the etch barrier isolation structure sub-segments as etching masks, the etch mask layer is patterned to divide the etch mask isolation structure segment 321 into a plurality of active area mask structures 300. Exemplarily, a vapor phase etching process can be used to remove the etch mask layer in the gaps between the etch barrier isolation structure sub-segments in the same etch barrier isolation structure 310, while retaining the etch mask layer in the remaining areas, so as to divide one etch mask isolation structure segment 321 into two active area mask structures 300, thereby allowing the gaps between the active area mask structures 300 in the same etch mask isolation structure segment 321 to expose the area of ​​the semiconductor substrate 100 that needs to be etched and removed. One active area mask structure 300 covers one active area. Exemplarily, the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar to achieve a certain etching selectivity, thereby etching the etch mask layer.

[0095] S40 , using the active area mask structure 300 as an etching mask, etching the word line structure 130 and the semiconductor substrate 100 to form the active area 110 and the buried word line 132 passing through the active area 110 .

[0096] In some examples, step S40, etching the wordline structure 130 and the semiconductor substrate 100 to form an active area and a buried wordline 132 passing through the active area, may specifically include the following steps: first, etching the semiconductor substrate, the insulating layer, and the gate dielectric layer in the unmasked area to expose the buried wordline in the unmasked area, and ensuring that the semiconductor substrate in the unmasked area is flush with the bottom surface of the buried wordline; wherein the unmasked area is the area excluding the area where the mask structure of the active area is located. Then, etching the semiconductor substrate in the unmasked area to a predetermined depth, ensuring that the plane of the semiconductor substrate in the unmasked area and the plane of the bottom surface of the buried wordline have the predetermined depth. Exemplarily, etching the semiconductor substrate, insulating layer, and gate dielectric layer in the unmasked area to expose the buried word line in the unmasked area, and making the etched semiconductor substrate flush with the bottom surface of the buried word line, may specifically include: first, using the active area mask structure as an etching mask, etching the semiconductor substrate and insulating layer in the unmasked area to make the top surface of the semiconductor substrate in the unmasked area flush with the top surface of the buried word line. Then, using the active area mask structure as an etching mask, etching the semiconductor substrate and gate dielectric layer in the unmasked area to expose the buried word line in the unmasked area, and making the top surface of the semiconductor substrate in the unmasked area flush with the bottom surface of the buried word line. Among them, exposing the buried word line in the non-mask area can specifically include: using the active area mask structure as an etching mask to etch the semiconductor substrate and the gate dielectric layer in the non-mask area to expose the buried word line in the non-mask area, and making the height of the buried word line in the non-mask area equal to the height of the buried word line in the area where the active area mask structure is located.

[0097] Exemplarily, step S40 may be implemented as follows:

[0098] First, see Figures 11A-11B The area other than the area where the active area mask structure 300 is located is used as the unmasked area, and the semiconductor substrate 100, the insulating layer 133, and the gate dielectric layer 131 in the unmasked area are etched, while the semiconductor substrate 100, the insulating layer 133, and the gate dielectric layer 131 in the area where the active area mask structure 300 is located are retained. The top surface of the semiconductor substrate 100 in the unmasked area is flush with the top surface of the buried word line 132. For example, a vapor phase etching process can be used, using the active area mask structure 300 as an etching mask, to etch the semiconductor substrate 100 and the insulating layer 133 in the unmasked area, so that the top surface of the semiconductor substrate 100 in the unmasked area is flush with the top surface of the buried word line 132.

[0099] Afterwards, see Figures 12A-12B, using the active area mask structure 300 as an etching mask, the semiconductor substrate 100 and the gate dielectric layer 131 in the non-mask area are etched to expose the buried word line 132 in the non-mask area, and the top surface of the semiconductor substrate 100 in the non-mask area is flush with the bottom surface of the buried word line 132, and the height of the buried word line 132 in the non-mask area can be equal to the height of the buried word line 132 in the area where the active area mask structure 300 is located.

[0100] Afterwards, see Figures 12A-12B The semiconductor substrate 100 between the plane where the bottom surface of the active area mask structure 300 is located (i.e., the plane BS1 where the top surface of the semiconductor substrate is located) and the plane WS2 where the bottom surface of the buried word line 132 is located is oxidized, so that an oxidation protection layer is formed on the surface of the semiconductor substrate 100 between the plane BS1 where the bottom surface of the active area mask structure 300 is located and the plane WS2 where the bottom surface of the buried word line 132 is located. For example, a plasma oxidation process can be used to oxidize the surface of the semiconductor substrate 100 between the plane BS1 where the bottom surface of the active area mask structure 300 is located and the plane WS2 where the bottom surface of the buried word line 132 is located. Furthermore, in the plasma oxidation process, the plasma oxidation gas can be a mixture of O2 and N2, the temperature can be 600°C to 800°C, the plasma intensity can be 600W to 2000W, and the pressure can be 1Pa to 10Pa. Similarly, those skilled in the art can also select other appropriate parameters for the plasma oxidation process according to actual needs.

[0101] Afterwards, see Figures 13A-13B , the semiconductor substrate 100 is etched to a set depth in the non-mask region, so that the plane where the semiconductor substrate 100 in the non-mask region is located and the plane where the bottom surface of the buried word line 132 is located have a set depth HA1. For example, see Figures 13A-13B First, using the active area mask structure 300 and the buried word line 132 as etching masks, the semiconductor substrate 100 is etched to a set depth HA1, so that the plane of the etched semiconductor substrate 100 and the plane of the bottom surface of the buried word line 132 have the set depth HA1. Afterwards, the semiconductor substrate 100 within the set depth HA1 and located in the region where the buried word line 132 is located can be preferentially etched. When the semiconductor substrate 100 is subsequently etched, the semiconductor substrate 100 that has undergone the preferential etching treatment can be etched first without affecting the semiconductor substrate 100 below the active area mask structure 300. By etching away the semiconductor substrate 100 that has undergone the preferential etching treatment, a shallow trench isolation trench 120 can be formed, thereby defining the active area 110 through the shallow trench isolation trench.

[0102] For some examples, see Figures 14A-14BAfter forming the active area 110 and the buried word line 132 passing through the active area 110, the process may further include: depositing an isolation layer 400 on the semiconductor substrate 100 so that the isolation layer 400 is flush with the top surface of the semiconductor substrate 100. Furthermore, the isolation layer 400 is vapor-etched to expose the buried word line and the active area for subsequent electrical connection. The isolation layer may be made of one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, or oxide / nitride / oxide materials. For example, a layer of silicon oxide is deposited at a set deposition rate as the isolation layer. Regarding the selection of deposition methods, those skilled in the art may select from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition, or other suitable deposition processes, but the present disclosure is not limited thereto. Similarly, regarding the selection of the deposition rate and thickness of the isolation layer, those skilled in the art may also select other suitable rates and thicknesses according to actual needs. Exemplarily, the etching gas may be one or more of SF6, CF4, Cl2, CHF3, O2 and Ar, so as to achieve a certain etching selectivity ratio, thereby etching the isolation layer.

[0103] For example, a plurality of bit line structures intersecting with the corresponding active regions 110 may be formed on the semiconductor substrate 100 so that a source / drain region of the transistor (i.e., the portion between two adjacent word line structures 130 on the semiconductor substrate 100) is electrically connected to the corresponding bit line structure.

[0104] By applying the above-mentioned preparation method, the present disclosure provides a semiconductor device. For example, it can be a DRAM. Figures 14A to 14C. The semiconductor device provided by the present disclosure may include: a semiconductor substrate 100, a word line structure 130. The semiconductor substrate 100 has an isolation region 120 formed by a shallow trench isolation (STI) and a plurality of active regions 110 defined by the isolation region 120. A memory cell such as a DRAM may be formed in each active region 110. A word line structure 130 is formed in the semiconductor substrate 100, intersecting with the corresponding active region 110 and buried in the semiconductor substrate 100. The word line structure 130 is in contact with the semiconductor substrate 100. In addition, the word line structure 130 may include: a gate dielectric layer 131, a plurality of buried word lines 132, and an insulating layer 133. For example, when the word line structure 130 is formed in the word line trench 101, a gate dielectric layer 131, a buried word line 132, and an insulating layer 133 covering the buried word line 132 may be formed in sequence in the word line trench 101. The buried word line 132 extends along a first direction F1, and the orthographic projection of the active region on the bottom surface of the semiconductor substrate 100 extends along a second direction F2 and passes through the orthographic projection of the buried word line 132 on the bottom surface of the semiconductor substrate 100. The orthographic projections of the insulating layer 133 and the gate dielectric layer 131 on the bottom surface of the semiconductor substrate 100 are located within the orthographic projection of the active region on the bottom surface of the semiconductor substrate 100. Furthermore, the insulating layer 133 is located on the buried word line 132, and the orthographic projections of the insulating layer 133 and the buried word line 132 on the bottom surface of the semiconductor substrate 100 in the active region overlap. Furthermore, the orthographic projections of the gate dielectric layer 131 on the bottom surface of the semiconductor substrate 100 are located on both sides of the orthographic projection of the insulating layer 133 in the active region. For example, the buried word lines 132 in the word line structure 130 can serve as gates of transistors in the memory, and the source / drain regions of the transistors can be located in the active area 110 on both sides of the word line structure 130. For example, one of the source / drain regions, such as the source / drain region between two word line structures 130, can serve as the source of the corresponding transistor, and another source / drain region, such as the source / drain region between the word line structure 130 and the isolation region 120, can serve as the drain of the corresponding transistor.

[0105] For some examples, see Figures 13A-14CThe active regions are arranged into repeating units along the third direction F3, and the repeating units are arranged along the first direction F1. The active regions in every two adjacent repeating units are staggered. For example, the active regions in repeating units DZ1 and DZ2 are staggered, the active regions in repeating units DZ2 and DZ3 are staggered, the active regions in repeating units DZ3 and DZ4 are staggered, the active regions in repeating units DZ4 and DZ5 are staggered, and the active regions in repeating units DZ5 and DZ6 are staggered. For example, the repeating units in odd-numbered columns (e.g., DZ1, DZ3, and DZ5) are arranged in the same pattern along the first direction F1, and the repeating units in even-numbered columns (e.g., DZ2, DZ4, and DZ6) are arranged in the same pattern along the first direction F1.

[0106] For some examples, see Figures 13A-14C , one active area may be passed through by two buried word lines 132. For example, each active area may be passed through by two buried word lines 132. Exemplarily, each buried word line 132 may alternately pass through the active areas in odd-numbered repeating units and even-numbered repeating units.

[0107] For some examples, see Figures 13A-14B The rest of the area except the active area is used as the non-active area, and the height of the buried word lines 132 in the non-active area can be equal to the height of the buried word lines 132 in the active area. In this way, the buried word lines 132 in various locations can be evenly distributed.

[0108] The present disclosure also provides other methods for manufacturing semiconductor devices, which are modified from the above embodiments. The differences between this embodiment and the above embodiments are described below, and the similarities are not repeated here.

[0109] See also Figures 15A to 16B In the semiconductor device provided by the embodiments of the present disclosure, the height of the buried word lines 132 in the non-active region can be made smaller than the height of the buried word lines 132 in the active region 110. This can reduce the relative area between the buried word lines 132 in the non-active region, thereby reducing the coupling capacitance between the buried word lines 132 in the non-active region and further reducing signal interference. Exemplarily, the heights of the buried word lines 132 in the active region can be made equal. Exemplarily, the heights of the buried word lines 132 in the non-active region can be made equal. Exemplarily, using the active region mask structure 300 as an etching mask, the semiconductor substrate 100 and the gate dielectric layer 131 in the non-mask region are etched so that the top surface of the semiconductor substrate 100 in the non-mask region is flush with the bottom surface of the buried word lines 132, and the height of the buried word lines 132 in the non-mask region is made smaller than the height of the buried word lines 132 in the region where the active region mask structure 300 is located.

[0110] In some examples, step S40 may also be implemented as follows:

[0111] First, see Figures 11A-11B The area other than the area where the active area mask structure 300 is located is used as the unmasked area, and the semiconductor substrate 100, the insulating layer 133, and the gate dielectric layer 131 in the unmasked area are etched, while the semiconductor substrate 100, the insulating layer 133, and the gate dielectric layer 131 in the area where the active area mask structure 300 is located are retained. The top surface of the semiconductor substrate 100 in the unmasked area is flush with the top surface of the buried word line 132. For example, a vapor phase etching process can be used, using the active area mask structure 300 as an etching mask, to etch the semiconductor substrate 100 and the insulating layer 133 in the unmasked area, so that the top surface of the semiconductor substrate 100 in the unmasked area is flush with the top surface of the buried word line 132.

[0112] Afterwards, see Figures 12A-12B , using the active area mask structure 300 as an etching mask, the semiconductor substrate 100 and the gate dielectric layer 131 in the non-mask area are etched to expose the buried word line 132 in the non-mask area, and the top surface of the semiconductor substrate 100 in the non-mask area is flush with the bottom surface of the buried word line 132, and the height of the buried word line 132 in the non-mask area can be equal to the height of the buried word line 132 in the area where the active area mask structure 300 is located.

[0113] Afterwards, see Figures 15A-15B , using the active area mask structure 300 as an etching mask, the buried word lines 132 in the unmasked area are etched so that the height of the buried word lines 132 in the unmasked area is less than the height of the buried word lines 132 in the area where the active area mask structure 300 is located. Exemplarily, a vapor phase etching process can be used to remove part of the buried word lines 132 in the unmasked area so that the height of the buried word lines 132 in the unmasked area is less than the height of the buried word lines 132 in the area where the active area mask structure 300 is located. Exemplarily, the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar to achieve a certain etching selectivity, thereby etching the buried word lines. It should be noted that the height of the buried word lines 132 in the unmasked area can be set according to the actual application environment and is not limited here.

[0114] Then, referring to the above-described preparation method, the semiconductor substrate 100 between the plane where the bottom surface of the active area mask structure 300 is located and the plane where the bottom surface of the buried word line 132 is located is oxidized, so that an oxidation protection layer is formed on the surface of the semiconductor substrate 100 between the plane where the bottom surface of the active area mask structure 300 is located and the plane where the bottom surface of the buried word line 132 is located. For example, a plasma oxidation process can be used to oxidize the surface of the semiconductor substrate 100 between the plane where the bottom surface of the active area mask structure 300 is located and the plane where the bottom surface of the buried word line 132 is located. Furthermore, in the plasma oxidation process, the plasma oxidation gas can be a mixture of O2 and N2, the temperature can be 600°C to 800°C, the plasma intensity can be 600W to 2000W, and the pressure can be 1Pa to 10Pa. Similarly, those skilled in the art can also select other appropriate parameters for the plasma oxidation process according to actual needs.

[0115] Then, referring to the above-mentioned preparation method, the semiconductor substrate 100 is etched to a set depth in the non-mask area, so that the plane where the semiconductor substrate 100 in the non-mask area is located and the plane where the bottom surface of the buried word line 132 is located have a set depth HA1. For example, see Figures 13A-13B First, using the active area mask structure 300 and the buried word line 132 as etching masks, the semiconductor substrate 100 is etched to a set depth HA1, so that the plane of the etched semiconductor substrate 100 and the plane of the bottom surface of the buried word line 132 have the set depth HA1. Afterwards, the semiconductor substrate 100 within the set depth HA1 and located in the region where the buried word line 132 is located can be preferentially etched. When the semiconductor substrate 100 is subsequently etched, the semiconductor substrate 100 that has undergone the preferential etching treatment can be etched first without affecting the semiconductor substrate 100 below the active area mask structure 300. By etching away the semiconductor substrate 100 that has undergone the preferential etching treatment, a shallow trench isolation trench 120 can be formed, thereby defining the active area 110 through the shallow trench isolation trench.

[0116] For some examples, see Figures 16A-16BAn isolation layer is deposited on the semiconductor substrate 100 so that the isolation layer is flush with the top surface of the semiconductor substrate 100. Furthermore, the isolation layer 400 is vapor-etched to expose the buried word lines and active areas for subsequent electrical connection. The isolation layer can be made of one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, or oxide / nitride / oxide materials. Exemplarily, a layer of silicon oxide is deposited at a predetermined deposition rate as the isolation layer. Regarding the deposition method, those skilled in the art can select from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes, but the present disclosure is not limited thereto. Similarly, regarding the deposition rate and thickness of the isolation layer, those skilled in the art can also select other suitable rates and thicknesses based on actual needs. Exemplarily, the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar to achieve a certain etching selectivity, thereby etching the isolation layer.

[0117] The present disclosure also provides some electronic devices. These electronic devices may include the aforementioned semiconductor devices provided by the present disclosure. The principles of solving the problems of these electronic devices are similar to those of the aforementioned semiconductor devices. Therefore, the implementation of these electronic devices can refer to the implementation of the aforementioned semiconductor devices, and any repetitions will not be repeated here.

[0118] In specific implementations, in the disclosed embodiments, the electronic device may be any product or component with a storage function, such as a mobile phone or tablet computer. Other essential components of the electronic device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limiting the present invention.

[0119] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: forming a plurality of word line trenches on a semiconductor substrate; wherein the word line trenches extend along a first direction; forming a word line structure in each of the word line trenches; wherein a top surface of the word line structure is flush with a top surface of the semiconductor substrate; forming a plurality of active area mask structures on the top surface of the semiconductor substrate; wherein the active area mask structures define active areas in the semiconductor substrate, and the orthographic projections of the active area mask structures on the bottom surface of the semiconductor substrate extend along a second direction and pass through the orthographic projections of the word line structures on the bottom surface of the semiconductor substrate; The word line structure and the semiconductor substrate are etched using the active area mask structure as an etching mask to form an active area and a buried word line passing through the active area.

2. The method for preparing a semiconductor device according to claim 1, wherein: The forming of a word line structure in each of the word line trenches includes: covering the sidewalls of the word line trench with a gate dielectric layer; Filling a buried word line in the word line trench formed with the gate dielectric layer; wherein a top surface of the buried word line is lower than a top surface of the semiconductor substrate; An insulating layer is filled on the buried word line in the word line trench; wherein a top surface of the insulating layer is flush with a top surface of the semiconductor substrate.

3. The method for preparing a semiconductor device according to claim 2, wherein: The etching of the word line structure and the semiconductor substrate to form an active area and a buried word line passing through the active area includes: Etching the semiconductor substrate, the insulating layer, and the gate dielectric layer in the non-mask area to expose the buried word line in the non-mask area, and making the semiconductor substrate in the non-mask area flush with the bottom surface of the buried word line; wherein the non-mask area is the area excluding the area where the active area mask structure is located; The semiconductor substrate in the non-mask area is etched to a set depth, so that a top surface of the semiconductor substrate in the non-mask area and a bottom surface of the buried word line have the set depth.

4. The method for preparing a semiconductor device according to claim 3, wherein: The etching of the semiconductor substrate, the insulating layer, and the gate dielectric layer in the non-mask area to expose the buried word line in the non-mask area, and making the etched semiconductor substrate flush with the bottom surface of the buried word line, includes: Using the active area mask structure as an etching mask, etching the semiconductor substrate and the insulating layer in the non-mask area so that the top surface of the semiconductor substrate in the non-mask area is flush with the top surface of the buried word line; Using the active area mask structure as an etching mask, the semiconductor substrate and the gate dielectric layer in the non-mask area are etched to expose the buried word line in the non-mask area, and the top surface of the semiconductor substrate in the non-mask area is flush with the bottom surface of the buried word line.

5. The method for preparing a semiconductor device according to claim 4, wherein: Exposing the buried word line in the non-mask area includes: Using the active area mask structure as an etching mask, the semiconductor substrate and the gate dielectric layer in the non-mask area are etched to expose the buried word lines in the non-mask area, and the height of the buried word lines exposed in the non-mask area is made equal to the height of the buried word lines in the area where the active area mask structure is located.

6. The method for preparing a semiconductor device according to claim 4, wherein: Exposing the buried word line in the non-mask area includes: Using the active area mask structure as an etching mask, etching the semiconductor substrate and the gate dielectric layer in the non-mask area to expose the buried word line in the non-mask area, making the top surface of the semiconductor substrate in the non-mask area flush with the bottom surface of the buried word line, and making the height of the buried word line exposed in the non-mask area equal to the height of the buried word line in the area where the active area mask structure is located; The active area mask structure is used as an etching mask to etch the buried word lines in the non-mask area so that the height of the buried word lines in the non-mask area is smaller than the height of the buried word lines in the area where the active area mask structure is located.

7. The method for preparing a semiconductor device according to claim 3, wherein: After the etched semiconductor substrate is flush with the bottom surface of the buried word line, and before the top surface of the etched semiconductor substrate and the bottom surface of the buried word line have the set depth, the method further includes: The semiconductor substrate between the plane where the bottom surface of the active area mask structure is located and the plane where the bottom surface of the buried word line is located is oxidized to form an oxidation protection layer on the surface of the semiconductor substrate.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The etching of the semiconductor substrate to a set depth in the non-mask area so that the top surface of the semiconductor substrate in the non-mask area and the bottom surface of the buried word line have the set depth includes: Using the active area mask structure and the buried word line as etching masks, etching the semiconductor substrate to the set depth so that the top surface of the etched semiconductor substrate and the bottom surface of the buried word line have the set depth; performing an etching process on the semiconductor substrate located at the set depth and in the region where the buried word line is located; The semiconductor substrate after the etching process is removed by etching to form a shallow trench isolation groove.

9. The method for preparing a semiconductor device according to any one of claims 1 to 8, wherein: The step of forming a plurality of word line trenches on a semiconductor substrate comprises: forming a trench mask layer covering the semiconductor substrate on the semiconductor substrate; patterning the trench mask layer to form a plurality of strip-shaped trench mask structures; The semiconductor substrate having a set depth at the gaps between adjacent trench mask structures is removed to form the plurality of word line trenches.

10. The method for preparing a semiconductor device according to any one of claims 1 to 8, wherein: After forming the active area and the buried word line passing through the active area, the method further includes: An isolation layer is deposited on the semiconductor substrate so that the isolation layer is flush with a top surface of the semiconductor substrate.

11. A semiconductor device, characterized in that: Obtained by the preparation method according to any one of claims 1 to 10; The semiconductor device comprises: A semiconductor substrate having an isolation region formed by a shallow trench isolation groove and a plurality of active regions defined by the isolation region; A plurality of buried word lines are buried in word line trenches formed by etching the semiconductor substrate, and the buried word lines are arranged to intersect with corresponding active areas.

12. The semiconductor device according to claim 11, wherein The remaining area except the active area is used as a non-active area, and the height of the buried word line in the non-active area is less than or equal to the height of the buried word line in the active area.

13. The semiconductor device according to claim 11, wherein An oxidation protection layer is formed on the surface of the semiconductor substrate between the plane where the top surface of the semiconductor substrate corresponding to the active area is located and the plane where the bottom surface of the buried word line is located.

14. The semiconductor device according to claim 11, wherein The active regions are arranged into repeating units along the third direction, and the repeating units are arranged along the first direction; wherein the active regions in every two adjacent repeating units are staggered; Each of the buried word lines alternately passes through active areas in odd-numbered repeating units and even-numbered repeating units.

15. An electronic device, characterized in that: The semiconductor device comprises the semiconductor device according to any one of claims 11 to 14.

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