Method for manufacturing high-density server PCB board

Abstract

A kind of high-density server PCB board manufacturing method, comprising the following steps;Step S1, providing n layer circuit board;Step S2, n layer circuit board is formed respectively electric signal layer and ground layer;Step S3, through drilling, copper sinking, electroplating, ground hole and signal via hole that are formed in L1, L2, L3 ……Ln are passed through n layer circuit board;Step S4, between L1 and L2, Ln-1 and Ln layer by laser, electroplating makes L1 and L2, Ln-1 and Ln layer form blind hole;Step S5, between L1 to L3, Ln-2 to Ln layer by laser, electroplating is formed across L2 and Ln-1 cross layer blind hole, and cross layer blind hole is conducted between L1 and L3, Ln-2 and Ln layer.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of PCB manufacturing, in particular to a manufacturing method of a high-density interconnection server PCB. BACKGROUND

[0002] With the development of 5G communication, PCBs are advancing towards high density and high integration, and there are more and more demands for high layer number, high wiring density and low stub.

[0003] Server PCBs are developing towards high-density interconnection, and traditional PCB design interconnects through mechanical drilling, which occupies wiring space at the drilling position, and the inner layer wiring space and density are low, and cannot meet the demand of high-density interconnection of PCBs. SUMMARY

[0004] The application aims to provide a manufacturing method of a high-density server PCB.

[0005] The application adopts the following technical scheme to solve the technical problem:

[0006] The manufacturing method of the high-density server PCB comprises the following steps:

[0007] Step S1, providing n layers of circuit boards, n being an even number;

[0008] Step S2, forming a telecommunication signal layer and a ground layer in each of the n layers of circuit boards, wherein even layers in L1, L2, L3,..., Ln / 2-1 are arranged as ground layers, odd layers are arranged as high-speed signal lines and form telecommunication signal layers; L n / 2 and Ln / 2+1 are arranged as ground layers; odd layers in Ln / 2+2, Ln / 2+3,..., Ln are arranged as ground layers, and even layers are arranged as high-speed signal lines and form telecommunication signal layers;

[0009] Step S3, forming a ground hole and a signal via hole through drilling and electroplating in L1, L2, L3,..., Ln;

[0010] Step S4, forming a blind hole between L1 and L2 and between Ln-1 and Ln through laser and electroplating, so that L1 and L2 and Ln-1 and Ln form the blind hole;

[0011] Step S5, forming a cross-layer blind hole across L2 and Ln-1 between L1 and L3 and between Ln-2 and Ln through laser and electroplating, and the cross-layer blind hole connects L1 and L3 and Ln-2 and Ln.

[0012] Further, the thickness between the L1 layer of circuit board and the L2 layer of circuit board and the thickness between the Ln-1 layer of circuit board and the Ln layer of circuit board is 50-75 um, and the line width is 50-150 um.

[0013] Further, the line width of the electric signal layer is 50-150um.

[0014] Further, the metallized conducting channel is formed by drilling, copper sinking and electroplating in the ground hole and the signal via hole.

[0015] Further, the copper foil is arranged on the electric signal layer and the ground layer.

[0016] Further, the thickness of the copper foil on the electric signal layer is 0.5oz or 1oz, and the thickness of the copper foil on the ground layer is 1oz or 2oz.

[0017] Further, the shielding copper sheet is arranged above the L2 layer and below the Ln-1 layer in the blind hole, so that the blind hole is communicated with the shielding copper sheet.

[0018] Further, the ground hole comprises a ground hole I and a ground hole II; in the ground hole I, the shielding copper sheet is arranged on the ground layer of the L2……Ln / 2-1 layer; in the ground hole II, the shielding copper sheet is arranged below the ground layer of the Ln / 2+2……Ln-1 layer; the ground hole is connected with one or more shielding copper sheets in the L1……Ln layer.

[0019] Further, the signal via hole comprises the back drilling overlap of the metallized section and the demetallized section.

[0020] Further, the back drilling is drilled from the L1 surface or the Ln surface, and drilled to the signal line layer connected with the signal via hole, so as to ensure the minimum parasitic capacitance in signal transmission.

[0021] Compared with the prior art, the beneficial effects of the present application are as follows:

[0022] 1. By arranging the electric signal layer and the ground layer in a preset order, the high-level wiring and the high-speed signal line are arranged in different regions, the interference of high voltage on the high-speed signal line is reduced, the communication quality of the PCB board is improved, and high-density interconnection is realized.

[0023] 2. By controlling the thickness of L1 layer to L2 layer and Ln-1 layer to Ln layer to be 50-75um and the line width to be 50-150um, the line width can be limited under the premise of constant impedance, and high-density interconnection of the PCB board is further realized.

[0024] 3. By forming the cross-layer blind hole, the cross-layer blind hole only communicates L1 layer and L3 layer, and does not communicate L2, so as to avoid occupying the wiring space of L2, and realize high-density interconnection of L2 layer. Moreover, the formed cross-layer blind hole can avoid the stub generated by the connection of the via hole, and the parasitic capacitance generated by the influence of signal transmission.

[0025] 4. A rigidly supported stacked structure is formed by placing copper foil on both the electrical signal layer and the ground layer to meet the requirements of high-density interconnection.

[0026] 5. By setting the electrical signal layer and ground layer to be staggered in a preset order, high-level traces and high-speed signal lines are arranged in separate areas, reducing the interference of high voltage on high-speed signal lines, improving the communication quality of the PCB board, and achieving high-density interconnection. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the PCB board structure according to Embodiment 1 of the present invention.

[0028] In the diagram: 201-Blind via, 202-Blind via across layers, 203-Ground via, 204-Signal via, 215-Shielding copper foil, 213-Ground via ring, 301-Back drill hole. Detailed Implementation

[0029] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0030] Example 1

[0031] like Figure 1 As shown, this embodiment includes the following steps;

[0032] Step S1: Provide an n-layer circuit board, where n is an even number;

[0033] In step S2, the n-layer circuit board forms electrical signal layers and ground layers respectively. Among them, in the L1...Ln / 2-1 layer circuit board, the even-numbered layers are arranged as ground layers, and the odd-numbered layers are arranged as high-speed signal lines to form electrical signal layers; Ln / 2 and Ln / 2+1 layers are arranged as ground layers; in the Ln / 2+2...Ln layer circuit board, the odd-numbered layers are arranged as ground layers, and the even-numbered layers are arranged as high-speed signal lines to form electrical signal layers.

[0034] For example, when n=14, the circuit board consists of layers L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, and L14. Among these, L1, L3, L5, L10, L12, and L14 are electrical signal layers, while L2, L4, L6, L7, L8, L9, L11, and L13 are ground layers. This reduces interference from high voltage to high-speed signal lines, improves the communication quality of the PCB board, and enables high-density interconnection.

[0035] In this embodiment, the dielectric thickness between the L1 layer circuit board and the L2 layer circuit board, and between the Ln-1 layer circuit board and the Ln layer circuit board is 50-75um, and the line width is 50-150um; the line width of the electrical signal layer is 50-150um.

[0036] The copper foil on the electrical signal layer has a thickness of 0.5 oz or 1 oz, and the copper foil on the ground layer has a thickness of 1 oz or 2 oz;

[0037] In step S3, the through-hole 203 and the signal via 204 are formed in the L1, L2, L3, …, Ln by drilling and electroplating; specifically, the metallized conductive channel is formed in the through-hole 203 by drilling, copper plating, and electroplating to realize the conduction of each layer of the circuit board; in this embodiment, the through-hole 203 includes a through-hole I and a through-hole II; in the through-hole I, the ground layer of the L2, …, Ln / 2-1 layer is provided with the shielding copper sheet 215; in the through-hole II, the ground layer of the Ln / 2+2, …, Ln-1 layer is provided with the shielding copper sheet 215; thus, the through-hole 203 can be connected with one or more layers of the shielding copper sheet 215 in the L1, …, Ln.

[0038] The metallized conductive channel is formed in the signal via 204 by drilling, copper plating, and electroplating; the signal via 204 includes a via I and a via II; the signal via 204 includes the back-drilling hole 301 formed by the overlapping of the metallized section and the demetallized section; the back-drilling hole 301 can be drilled from the L1 surface or the Ln surface and drilled to the signal circuit layer connected with the signal via 204 to ensure the minimum parasitic capacitance in signal transmission.

[0039] In this embodiment, in the via I, the Ln / 2-1 layer, …, the Ln layer, the via I is the demetallized back-drilling hole 301;

[0040] In the via II, the L1, …, the Ln / 2+2 layer, the via II is the demetallized back-drilling hole 301;

[0041] In addition, in the through-hole I and the through-hole II, the ground layer and the electrical signal layer of the L1, L2, L3, …, Ln are provided with the through-hole ring 213;

[0042] In step S4, the blind hole 201 is formed between the L1 and the L2, and the Ln-1 and the Ln by laser and electroplating; thus, the circuit is conducted between the L1 and the L2, and the Ln-1 and the Ln; in this embodiment, the shielding copper sheet 211 is arranged above the L2 layer and below the Ln-1 layer in the blind hole 201, so that the blind hole 201 is located above or below the shielding copper sheet 211;

[0043] Step S5, forming a cross-layer blind hole 202 across L2 and Ln-1 by laser, electroplating between L1 to L3, Ln-2 to Ln layers, the cross-layer blind hole 202 conducts between L1 and L3, Ln-2 and Ln layers, and does not communicate L2, Ln-1 layer, avoids occupying the wiring space of L2, Ln-1 layer, to realize the high-density interconnection of L2, Ln-1 layer. Moreover, the formed cross-layer blind hole 202 can avoid the stub produced by the connection of the through hole, and the parasitic capacitance produced by the influence of signal transmission;

[0044] In addition, the L1 layer outer wall and the Ln outer wall, the blind hole 201, the cross-layer blind hole 202, the ground hole 203, and the signal via hole 204 are all provided with a solder pad.

[0045] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application, and not to limit them; although the technical solutions of the present application are described in detail with reference to the foregoing examples, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or equivalently replace some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for manufacturing a high-density server PCB board, characterized in that: The method comprises the following steps; Step S1, providing n layers of circuit boards, n being an even number; Step S2, forming electrical signal layers and ground layers in the n layers of circuit boards respectively, wherein even layers among L1……Ln / 2-1 layers of the circuit boards are arranged as ground layers, odd layers are arranged as high-speed signal lines and form electrical signal layers; L n / 2 and Ln / 2+1 layers are arranged as ground layers; odd layers among Ln / 2+2……Ln layers of the circuit boards are arranged as ground layers, even layers are arranged as high-speed signal lines and form electrical signal layers; Step S3, forming ground holes (203) and signal vias (204) through the n layers of circuit boards by drilling, electroplating in L1, L2, L3……Ln; The ground holes (203) comprise ground hole I and ground hole II; In the ground hole I, shielding copper sheets (215) are arranged on the ground layers of L2……Ln / 2-1 layers; In the ground hole II, shielding copper sheets (215) are arranged below the ground layers of Ln / 2+2……Ln-1 layers; The ground holes (203) are connected with one or more shielding copper sheets (215) in L1……Ln layers; The signal vias (204) comprise overlapping of back drilling holes (301) of the metalized sections and the demetalized sections; The back drilling holes (301) are drilled from the L1 surface or the Ln surface and drilled to the signal line layers connected with the signal vias (204) without damaging the signal line layers, so as to ensure the minimum parasitic capacitance in signal transmission; Step S4, forming blind holes (201) between L1 and L2, Ln-1 and Ln layers by laser and electroplating, shielding copper sheets (211) being arranged above the L2 layer and below the Ln-1 layer in the blind holes (201), so that the blind holes (201) are communicated with the shielding copper sheets (211); Step S5, forming cross-layer blind holes (202) across L2 and Ln-1 between L1 to L3, Ln-2 to Ln layers by laser and electroplating, the cross-layer blind holes (202) conducting between L1 and L3, Ln-2 and Ln layers.

2. The method of claim 1, wherein: The thickness of the intermediate layers between the L1 layer of circuit board to the L2 layer of circuit board and the Ln-1 layer of circuit board to the Ln layer of circuit board is 50-75 um, and the line width is 50-150 um.

3. The method of claim 2, wherein: The line width of the electrical signal layers is 50-150 um.

4. The method of claim 3, wherein: Metalized conducting channels are formed in the ground holes (203) and the signal vias (204) by drilling, copper deposition and electroplating.

5. The method of claim 4, wherein: Copper foils are arranged on the electrical signal layers and the ground layers.

6. The method of claim 5, wherein: The thickness of the copper foils on the electrical signal layers is 0.5 oz or 1 oz, and the thickness of the copper foils on the ground layers is 1 oz or 2 oz.

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